drivers/clk/tegra/clk-emc.c

   1 /*
   2  * drivers/clk/tegra/clk-emc.c
   3  *
   4  * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * Author:
   7  *      Mikko Perttunen <mperttunen@nvidia.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/clk-provider.h>
  20 #include <linux/clk.h>
  21 #include <linux/clkdev.h>
  22 #include <linux/delay.h>
  23 #include <linux/module.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/sort.h>
  28 #include <linux/string.h>
  29
  30 #include <soc/tegra/fuse.h>
  31 #include <soc/tegra/emc.h>
  32
  33 #include "clk.h"
  34
  35 #define CLK_SOURCE_EMC 0x19c
  36
  37 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0
  38 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff
  39 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK) << \
  40                                               CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT)
  41
  42 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT 29
  43 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7
  44 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK) << \
  45                                           CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
  46
  47 static const char * const emc_parent_clk_names[] = {
  48         "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud",
  49         "pll_c2", "pll_c3", "pll_c_ud"
  50 };
  51
  52 /*
  53  * List of clock sources for various parents the EMC clock can have.
  54  * When we change the timing to a timing with a parent that has the same
  55  * clock source as the current parent, we must first change to a backup
  56  * timing that has a different clock source.
  57  */
  58
  59 #define EMC_SRC_PLL_M 0
  60 #define EMC_SRC_PLL_C 1
  61 #define EMC_SRC_PLL_P 2
  62 #define EMC_SRC_CLK_M 3
  63 #define EMC_SRC_PLL_C2 4
  64 #define EMC_SRC_PLL_C3 5
  65
  66 static const char emc_parent_clk_sources[] = {
  67         EMC_SRC_PLL_M, EMC_SRC_PLL_C, EMC_SRC_PLL_P, EMC_SRC_CLK_M,
  68         EMC_SRC_PLL_M, EMC_SRC_PLL_C2, EMC_SRC_PLL_C3, EMC_SRC_PLL_C
  69 };
  70
  71 struct emc_timing {
  72         unsigned long rate, parent_rate;
  73         u8 parent_index;
  74         struct clk *parent;
  75         u32 ram_code;
  76 };
  77
  78 struct tegra_clk_emc {
  79         struct clk_hw hw;
  80         void __iomem *clk_regs;
  81         struct clk *prev_parent;
  82         bool changing_timing;
  83
  84         struct device_node *emc_node;
  85         struct tegra_emc *emc;
  86
  87         int num_timings;
  88         struct emc_timing *timings;
  89         spinlock_t *lock;
  90 };
  91
  92 /* Common clock framework callback implementations */
  93
  94 static unsigned long emc_recalc_rate(struct clk_hw *hw,
  95                                      unsigned long parent_rate)
  96 {
  97         struct tegra_clk_emc *tegra;
  98         u32 val, div;
  99
 100         tegra = container_of(hw, struct tegra_clk_emc, hw);
 101
 102         /*
 103          * CCF wrongly assumes that the parent won't change during set_rate,
 104          * so get the parent rate explicitly.
 105          */
 106         parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
 107
 108         val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
 109         div = val & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK;
 110
 111         return parent_rate / (div + 2) * 2;
 112 }
 113
 114 /*
 115  * Rounds up unless no higher rate exists, in which case down. This way is
 116  * safer since things have EMC rate floors. Also don't touch parent_rate
 117  * since we don't want the CCF to play with our parent clocks.
 118  */
 119 static int emc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
 120 {
 121         struct tegra_clk_emc *tegra;
 122         u8 ram_code = tegra_read_ram_code();
 123         struct emc_timing *timing = NULL;
 124         int i, k, t;
 125
 126         tegra = container_of(hw, struct tegra_clk_emc, hw);
 127
 128         for (k = 0; k < tegra->num_timings; k++) {
 129                 if (tegra->timings[k].ram_code == ram_code)
 130                         break;
 131         }
 132
 133         for (t = k; t < tegra->num_timings; t++) {
 134                 if (tegra->timings[t].ram_code != ram_code)
 135                         break;
 136         }
 137
 138         for (i = k; i < t; i++) {
 139                 timing = tegra->timings + i;
 140
 141                 if (timing->rate < req->rate && i != t - 1)
 142                         continue;
 143
 144                 if (timing->rate > req->max_rate) {
 145                         i = max(i, k + 1);
 146                         req->rate = tegra->timings[i - 1].rate;
 147                         return 0;
 148                 }
 149
 150                 if (timing->rate < req->min_rate)
 151                         continue;
 152
 153                 req->rate = timing->rate;
 154                 return 0;
 155         }
 156
 157         if (timing) {
 158                 req->rate = timing->rate;
 159                 return 0;
 160         }
 161
 162         req->rate = clk_hw_get_rate(hw);
 163         return 0;
 164 }
 165
 166 static u8 emc_get_parent(struct clk_hw *hw)
 167 {
 168         struct tegra_clk_emc *tegra;
 169         u32 val;
 170
 171         tegra = container_of(hw, struct tegra_clk_emc, hw);
 172
 173         val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
 174
 175         return (val >> CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
 176                 & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK;
 177 }
 178
 179 static struct tegra_emc *emc_ensure_emc_driver(struct tegra_clk_emc *tegra)
 180 {
 181         struct platform_device *pdev;
 182
 183         if (tegra->emc)
 184                 return tegra->emc;
 185
 186         if (!tegra->emc_node)
 187                 return NULL;
 188
 189         pdev = of_find_device_by_node(tegra->emc_node);
 190         if (!pdev) {
 191                 pr_err("%s: could not get external memory controller\n",
 192                        __func__);
 193                 return NULL;
 194         }
 195
 196         of_node_put(tegra->emc_node);
 197         tegra->emc_node = NULL;
 198
 199         tegra->emc = platform_get_drvdata(pdev);
 200         if (!tegra->emc) {
 201                 pr_err("%s: cannot find EMC driver\n", __func__);
 202                 return NULL;
 203         }
 204
 205         return tegra->emc;
 206 }
 207
 208 static int emc_set_timing(struct tegra_clk_emc *tegra,
 209                           struct emc_timing *timing)
 210 {
 211         int err;
 212         u8 div;
 213         u32 car_value;
 214         unsigned long flags = 0;
 215         struct tegra_emc *emc = emc_ensure_emc_driver(tegra);
 216
 217         if (!emc)
 218                 return -ENOENT;
 219
 220         pr_debug("going to rate %ld prate %ld p %s\n", timing->rate,
 221                  timing->parent_rate, __clk_get_name(timing->parent));
 222
 223         if (emc_get_parent(&tegra->hw) == timing->parent_index &&
 224             clk_get_rate(timing->parent) != timing->parent_rate) {
 225                 WARN_ONCE(1, "parent %s rate mismatch %lu %lu\n",
 226                           __clk_get_name(timing->parent),
 227                           clk_get_rate(timing->parent),
 228                           timing->parent_rate);
 229                 return -EINVAL;
 230         }
 231
 232         tegra->changing_timing = true;
 233
 234         err = clk_set_rate(timing->parent, timing->parent_rate);
 235         if (err) {
 236                 pr_err("cannot change parent %s rate to %ld: %d\n",
 237                        __clk_get_name(timing->parent), timing->parent_rate,
 238                        err);
 239
 240                 return err;
 241         }
 242
 243         err = clk_prepare_enable(timing->parent);
 244         if (err) {
 245                 pr_err("cannot enable parent clock: %d\n", err);
 246                 return err;
 247         }
 248
 249         div = timing->parent_rate / (timing->rate / 2) - 2;
 250
 251         err = tegra_emc_prepare_timing_change(emc, timing->rate);
 252         if (err)
 253                 return err;
 254
 255         spin_lock_irqsave(tegra->lock, flags);
 256
 257         car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC);
 258
 259         car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_SRC(~0);
 260         car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index);
 261
 262         car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(~0);
 263         car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(div);
 264
 265         writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC);
 266
 267         spin_unlock_irqrestore(tegra->lock, flags);
 268
 269         tegra_emc_complete_timing_change(emc, timing->rate);
 270
 271         clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));
 272         clk_disable_unprepare(tegra->prev_parent);
 273
 274         tegra->prev_parent = timing->parent;
 275         tegra->changing_timing = false;
 276
 277         return 0;
 278 }
 279
 280 /*
 281  * Get backup timing to use as an intermediate step when a change between
 282  * two timings with the same clock source has been requested. First try to
 283  * find a timing with a higher clock rate to avoid a rate below any set rate
 284  * floors. If that is not possible, find a lower rate.
 285  */
 286 static struct emc_timing *get_backup_timing(struct tegra_clk_emc *tegra,
 287                                             int timing_index)
 288 {
 289         int i;
 290         u32 ram_code = tegra_read_ram_code();
 291         struct emc_timing *timing;
 292
 293         for (i = timing_index+1; i < tegra->num_timings; i++) {
 294                 timing = tegra->timings + i;
 295                 if (timing->ram_code != ram_code)
 296                         break;
 297
 298                 if (emc_parent_clk_sources[timing->parent_index] !=
 299                     emc_parent_clk_sources[
 300                       tegra->timings[timing_index].parent_index])
 301                         return timing;
 302         }
 303
 304         for (i = timing_index-1; i >= 0; --i) {
 305                 timing = tegra->timings + i;
 306                 if (timing->ram_code != ram_code)
 307                         break;
 308
 309                 if (emc_parent_clk_sources[timing->parent_index] !=
 310                     emc_parent_clk_sources[
 311                       tegra->timings[timing_index].parent_index])
 312                         return timing;
 313         }
 314
 315         return NULL;
 316 }
 317
 318 static int emc_set_rate(struct clk_hw *hw, unsigned long rate,
 319                         unsigned long parent_rate)
 320 {
 321         struct tegra_clk_emc *tegra;
 322         struct emc_timing *timing = NULL;
 323         int i, err;
 324         u32 ram_code = tegra_read_ram_code();
 325
 326         tegra = container_of(hw, struct tegra_clk_emc, hw);
 327
 328         if (clk_hw_get_rate(hw) == rate)
 329                 return 0;
 330
 331         /*
 332          * When emc_set_timing changes the parent rate, CCF will propagate
 333          * that downward to us, so ignore any set_rate calls while a rate
 334          * change is already going on.
 335          */
 336         if (tegra->changing_timing)
 337                 return 0;
 338
 339         for (i = 0; i < tegra->num_timings; i++) {
 340                 if (tegra->timings[i].rate == rate &&
 341                     tegra->timings[i].ram_code == ram_code) {
 342                         timing = tegra->timings + i;
 343                         break;
 344                 }
 345         }
 346
 347         if (!timing) {
 348                 pr_err("cannot switch to rate %ld without emc table\n", rate);
 349                 return -EINVAL;
 350         }
 351
 352         if (emc_parent_clk_sources[emc_get_parent(hw)] ==
 353             emc_parent_clk_sources[timing->parent_index] &&
 354             clk_get_rate(timing->parent) != timing->parent_rate) {
 355                 /*
 356                  * Parent clock source not changed but parent rate has changed,
 357                  * need to temporarily switch to another parent
 358                  */
 359
 360                 struct emc_timing *backup_timing;
 361
 362                 backup_timing = get_backup_timing(tegra, i);
 363                 if (!backup_timing) {
 364                         pr_err("cannot find backup timing\n");
 365                         return -EINVAL;
 366                 }
 367
 368                 pr_debug("using %ld as backup rate when going to %ld\n",
 369                          backup_timing->rate, rate);
 370
 371                 err = emc_set_timing(tegra, backup_timing);
 372                 if (err) {
 373                         pr_err("cannot set backup timing: %d\n", err);
 374                         return err;
 375                 }
 376         }
 377
 378         return emc_set_timing(tegra, timing);
 379 }
 380
 381 /* Initialization and deinitialization */
 382
 383 static int load_one_timing_from_dt(struct tegra_clk_emc *tegra,
 384                                    struct emc_timing *timing,
 385                                    struct device_node *node)
 386 {
 387         int err, i;
 388         u32 tmp;
 389
 390         err = of_property_read_u32(node, "clock-frequency", &tmp);
 391         if (err) {
 392                 pr_err("timing %pOF: failed to read rate\n", node);
 393                 return err;
 394         }
 395
 396         timing->rate = tmp;
 397
 398         err = of_property_read_u32(node, "nvidia,parent-clock-frequency", &tmp);
 399         if (err) {
 400                 pr_err("timing %pOF: failed to read parent rate\n", node);
 401                 return err;
 402         }
 403
 404         timing->parent_rate = tmp;
 405
 406         timing->parent = of_clk_get_by_name(node, "emc-parent");
 407         if (IS_ERR(timing->parent)) {
 408                 pr_err("timing %pOF: failed to get parent clock\n", node);
 409                 return PTR_ERR(timing->parent);
 410         }
 411
 412         timing->parent_index = 0xff;
 413         for (i = 0; i < ARRAY_SIZE(emc_parent_clk_names); i++) {
 414                 if (!strcmp(emc_parent_clk_names[i],
 415                             __clk_get_name(timing->parent))) {
 416                         timing->parent_index = i;
 417                         break;
 418                 }
 419         }
 420         if (timing->parent_index == 0xff) {
 421                 pr_err("timing %pOF: %s is not a valid parent\n",
 422                        node, __clk_get_name(timing->parent));
 423                 clk_put(timing->parent);
 424                 return -EINVAL;
 425         }
 426
 427         return 0;
 428 }
 429
 430 static int cmp_timings(const void *_a, const void *_b)
 431 {
 432         const struct emc_timing *a = _a;
 433         const struct emc_timing *b = _b;
 434
 435         if (a->rate < b->rate)
 436                 return -1;
 437         else if (a->rate == b->rate)
 438                 return 0;
 439         else
 440                 return 1;
 441 }
 442
 443 static int load_timings_from_dt(struct tegra_clk_emc *tegra,
 444                                 struct device_node *node,
 445                                 u32 ram_code)
 446 {
 447         struct emc_timing *timings_ptr;
 448         struct device_node *child;
 449         int child_count = of_get_child_count(node);
 450         int i = 0, err;
 451         size_t size;
 452
 453         size = (tegra->num_timings + child_count) * sizeof(struct emc_timing);
 454
 455         tegra->timings = krealloc(tegra->timings, size, GFP_KERNEL);
 456         if (!tegra->timings)
 457                 return -ENOMEM;
 458
 459         timings_ptr = tegra->timings + tegra->num_timings;
 460         tegra->num_timings += child_count;
 461
 462         for_each_child_of_node(node, child) {
 463                 struct emc_timing *timing = timings_ptr + (i++);
 464
 465                 err = load_one_timing_from_dt(tegra, timing, child);
 466                 if (err) {
 467                         of_node_put(child);
 468                         return err;
 469                 }
 470
 471                 timing->ram_code = ram_code;
 472         }
 473
 474         sort(timings_ptr, child_count, sizeof(struct emc_timing),
 475              cmp_timings, NULL);
 476
 477         return 0;
 478 }
 479
 480 static const struct clk_ops tegra_clk_emc_ops = {
 481         .recalc_rate = emc_recalc_rate,
 482         .determine_rate = emc_determine_rate,
 483         .set_rate = emc_set_rate,
 484         .get_parent = emc_get_parent,
 485 };
 486
 487 struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
 488                                    spinlock_t *lock)
 489 {
 490         struct tegra_clk_emc *tegra;
 491         struct clk_init_data init;
 492         struct device_node *node;
 493         u32 node_ram_code;
 494         struct clk *clk;
 495         int err;
 496
 497         tegra = kcalloc(1, sizeof(*tegra), GFP_KERNEL);
 498         if (!tegra)
 499                 return ERR_PTR(-ENOMEM);
 500
 501         tegra->clk_regs = base;
 502         tegra->lock = lock;
 503
 504         tegra->num_timings = 0;
 505
 506         for_each_child_of_node(np, node) {
 507                 err = of_property_read_u32(node, "nvidia,ram-code",
 508                                            &node_ram_code);
 509                 if (err)
 510                         continue;
 511
 512                 /*
 513                  * Store timings for all ram codes as we cannot read the
 514                  * fuses until the apbmisc driver is loaded.
 515                  */
 516                 err = load_timings_from_dt(tegra, node, node_ram_code);
 517                 if (err) {
 518                         of_node_put(node);
 519                         return ERR_PTR(err);
 520                 }
 521         }
 522
 523         if (tegra->num_timings == 0)
 524                 pr_warn("%s: no memory timings registered\n", __func__);
 525
 526         tegra->emc_node = of_parse_phandle(np,
 527                         "nvidia,external-memory-controller", 0);
 528         if (!tegra->emc_node)
 529                 pr_warn("%s: couldn't find node for EMC driver\n", __func__);
 530
 531         init.name = "emc";
 532         init.ops = &tegra_clk_emc_ops;
 533         init.flags = CLK_IS_CRITICAL;
 534         init.parent_names = emc_parent_clk_names;
 535         init.num_parents = ARRAY_SIZE(emc_parent_clk_names);
 536
 537         tegra->hw.init = &init;
 538
 539         clk = clk_register(NULL, &tegra->hw);
 540         if (IS_ERR(clk))
 541                 return clk;
 542
 543         tegra->prev_parent = clk_hw_get_parent_by_index(
 544                 &tegra->hw, emc_get_parent(&tegra->hw))->clk;
 545         tegra->changing_timing = false;
 546
 547         /* Allow debugging tools to see the EMC clock */
 548         clk_register_clkdev(clk, "emc", "tegra-clk-debug");
 549
 550         return clk;
 551 };