1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
9 #include <linux/clk-provider.h>
11 #include "ccu_common.h"
15 * struct ccu_div_internal - Internal divider description
16 * @shift: Bit offset of the divider in its register
17 * @width: Width of the divider field in its register
18 * @max: Maximum value allowed for that divider. This is the
19 * arithmetic value, not the maximum value to be set in the
21 * @flags: clk_divider flags to apply on this divider
22 * @table: Divider table pointer (if applicable)
24 * That structure represents a single divider, and is meant to be
25 * embedded in other structures representing the various clock
28 * It is basically a wrapper around the clk_divider functions
31 struct ccu_div_internal {
40 struct clk_div_table *table;
43 #define _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, _flags) \
51 #define _SUNXI_CCU_DIV_TABLE(_shift, _width, _table) \
52 _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, 0)
54 #define _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, _off, _max, _flags) \
63 #define _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, _flags) \
64 _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, 1, _max, _flags)
66 #define _SUNXI_CCU_DIV_FLAGS(_shift, _width, _flags) \
67 _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, 0, _flags)
69 #define _SUNXI_CCU_DIV_MAX(_shift, _width, _max) \
70 _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, 0)
72 #define _SUNXI_CCU_DIV_OFFSET(_shift, _width, _offset) \
73 _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, _offset, 0, 0)
75 #define _SUNXI_CCU_DIV(_shift, _width) \
76 _SUNXI_CCU_DIV_FLAGS(_shift, _width, 0)
81 struct ccu_div_internal div;
82 struct ccu_mux_internal mux;
83 struct ccu_common common;
84 unsigned int fixed_post_div;
87 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
89 _table, _gate, _flags) \
90 struct ccu_div _struct = { \
91 .div = _SUNXI_CCU_DIV_TABLE(_shift, _width, \
96 .hw.init = CLK_HW_INIT(_name, \
104 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \
107 SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
108 _shift, _width, _table, 0, \
111 #define SUNXI_CCU_DIV_TABLE_HW(_struct, _name, _parent, _reg, \
114 struct ccu_div _struct = { \
115 .div = _SUNXI_CCU_DIV_TABLE(_shift, _width, \
119 .hw.init = CLK_HW_INIT_HW(_name, \
127 #define SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
131 _muxshift, _muxwidth, \
133 struct ccu_div _struct = { \
135 .div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
136 .mux = _SUNXI_CCU_MUX_TABLE(_muxshift, _muxwidth, _table), \
139 .hw.init = CLK_HW_INIT_PARENTS(_name, \
146 #define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
147 _mshift, _mwidth, _muxshift, _muxwidth, \
149 SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
151 _reg, _mshift, _mwidth, \
152 _muxshift, _muxwidth, \
155 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \
156 _mshift, _mwidth, _muxshift, _muxwidth, \
158 SUNXI_CCU_M_WITH_MUX_TABLE_GATE(_struct, _name, \
160 _reg, _mshift, _mwidth, \
161 _muxshift, _muxwidth, \
165 #define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \
166 _mshift, _mwidth, _gate, \
168 struct ccu_div _struct = { \
170 .div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
173 .hw.init = CLK_HW_INIT(_name, \
180 #define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \
182 SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \
183 _mshift, _mwidth, 0, _flags)
185 #define SUNXI_CCU_M_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
187 _muxshift, _muxwidth, \
189 struct ccu_div _struct = { \
191 .div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
192 .mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
195 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, \
202 #define SUNXI_CCU_M_DATA_WITH_MUX(_struct, _name, _parents, _reg, \
204 _muxshift, _muxwidth, \
206 SUNXI_CCU_M_DATA_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
208 _muxshift, _muxwidth, \
211 #define SUNXI_CCU_M_HW_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
212 _mshift, _mwidth, _muxshift, _muxwidth, \
214 struct ccu_div _struct = { \
216 .div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
217 .mux = _SUNXI_CCU_MUX(_muxshift, _muxwidth), \
220 .hw.init = CLK_HW_INIT_PARENTS_HW(_name, \
227 #define SUNXI_CCU_M_HWS_WITH_GATE(_struct, _name, _parent, _reg, \
228 _mshift, _mwidth, _gate, \
230 struct ccu_div _struct = { \
232 .div = _SUNXI_CCU_DIV(_mshift, _mwidth), \
235 .hw.init = CLK_HW_INIT_HWS(_name, \
242 #define SUNXI_CCU_M_HWS(_struct, _name, _parent, _reg, _mshift, \
244 SUNXI_CCU_M_HWS_WITH_GATE(_struct, _name, _parent, _reg, \
245 _mshift, _mwidth, 0, _flags)
247 static inline struct ccu_div *hw_to_ccu_div(struct clk_hw *hw)
249 struct ccu_common *common = hw_to_ccu_common(hw);
251 return container_of(common, struct ccu_div, common);
254 extern const struct clk_ops ccu_div_ops;
256 #endif /* _CCU_DIV_H_ */