1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
6 #include <linux/clk-provider.h>
7 #include <linux/of_address.h>
8 #include <linux/platform_device.h>
10 #include "ccu_common.h"
11 #include "ccu_reset.h"
18 #include "ccu-sun8i-r.h"
20 static const char * const ar100_parents[] = { "osc32k", "osc24M",
21 "pll-periph0", "iosc" };
22 static const char * const a83t_ar100_parents[] = { "osc16M-d512", "osc24M",
23 "pll-periph0", "iosc" };
24 static const struct ccu_mux_var_prediv ar100_predivs[] = {
25 { .index = 2, .shift = 8, .width = 5 },
28 static struct ccu_div ar100_clk = {
29 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
35 .var_predivs = ar100_predivs,
36 .n_var_predivs = ARRAY_SIZE(ar100_predivs),
41 .features = CCU_FEATURE_VARIABLE_PREDIV,
42 .hw.init = CLK_HW_INIT_PARENTS("ar100",
49 static struct ccu_div a83t_ar100_clk = {
50 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
56 .var_predivs = ar100_predivs,
57 .n_var_predivs = ARRAY_SIZE(ar100_predivs),
62 .features = CCU_FEATURE_VARIABLE_PREDIV,
63 .hw.init = CLK_HW_INIT_PARENTS("ar100",
70 static CLK_FIXED_FACTOR(ahb0_clk, "ahb0", "ar100", 1, 1, 0);
72 static struct ccu_div apb0_clk = {
73 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
77 .hw.init = CLK_HW_INIT("apb0",
84 static SUNXI_CCU_M(a83t_apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0);
86 static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0",
88 static SUNXI_CCU_GATE(apb0_ir_clk, "apb0-ir", "apb0",
90 static SUNXI_CCU_GATE(apb0_timer_clk, "apb0-timer", "apb0",
92 static SUNXI_CCU_GATE(apb0_rsb_clk, "apb0-rsb", "apb0",
94 static SUNXI_CCU_GATE(apb0_uart_clk, "apb0-uart", "apb0",
96 static SUNXI_CCU_GATE(apb0_i2c_clk, "apb0-i2c", "apb0",
98 static SUNXI_CCU_GATE(apb0_twd_clk, "apb0-twd", "apb0",
101 static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
102 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
103 r_mod0_default_parents, 0x54,
110 static const char *const a83t_r_mod0_parents[] = { "osc16M", "osc24M" };
111 static const struct ccu_mux_fixed_prediv a83t_ir_predivs[] = {
112 { .index = 0, .div = 16 },
114 static struct ccu_mp a83t_ir_clk = {
117 .m = _SUNXI_CCU_DIV(0, 4),
118 .p = _SUNXI_CCU_DIV(16, 2),
123 .fixed_predivs = a83t_ir_predivs,
124 .n_predivs = ARRAY_SIZE(a83t_ir_predivs),
129 .features = CCU_FEATURE_VARIABLE_PREDIV,
130 .hw.init = CLK_HW_INIT_PARENTS("ir",
137 static struct ccu_common *sun8i_a83t_r_ccu_clks[] = {
138 &a83t_ar100_clk.common,
139 &a83t_apb0_clk.common,
140 &apb0_pio_clk.common,
142 &apb0_timer_clk.common,
143 &apb0_rsb_clk.common,
144 &apb0_uart_clk.common,
145 &apb0_i2c_clk.common,
146 &apb0_twd_clk.common,
150 static struct ccu_common *sun8i_h3_r_ccu_clks[] = {
153 &apb0_pio_clk.common,
155 &apb0_timer_clk.common,
156 &apb0_uart_clk.common,
157 &apb0_i2c_clk.common,
158 &apb0_twd_clk.common,
162 static struct ccu_common *sun50i_a64_r_ccu_clks[] = {
165 &apb0_pio_clk.common,
167 &apb0_timer_clk.common,
168 &apb0_rsb_clk.common,
169 &apb0_uart_clk.common,
170 &apb0_i2c_clk.common,
171 &apb0_twd_clk.common,
175 static struct clk_hw_onecell_data sun8i_a83t_r_hw_clks = {
177 [CLK_AR100] = &a83t_ar100_clk.common.hw,
178 [CLK_AHB0] = &ahb0_clk.hw,
179 [CLK_APB0] = &a83t_apb0_clk.common.hw,
180 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
181 [CLK_APB0_IR] = &apb0_ir_clk.common.hw,
182 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw,
183 [CLK_APB0_RSB] = &apb0_rsb_clk.common.hw,
184 [CLK_APB0_UART] = &apb0_uart_clk.common.hw,
185 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw,
186 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw,
187 [CLK_IR] = &a83t_ir_clk.common.hw,
192 static struct clk_hw_onecell_data sun8i_h3_r_hw_clks = {
194 [CLK_AR100] = &ar100_clk.common.hw,
195 [CLK_AHB0] = &ahb0_clk.hw,
196 [CLK_APB0] = &apb0_clk.common.hw,
197 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
198 [CLK_APB0_IR] = &apb0_ir_clk.common.hw,
199 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw,
200 [CLK_APB0_UART] = &apb0_uart_clk.common.hw,
201 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw,
202 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw,
203 [CLK_IR] = &ir_clk.common.hw,
208 static struct clk_hw_onecell_data sun50i_a64_r_hw_clks = {
210 [CLK_AR100] = &ar100_clk.common.hw,
211 [CLK_AHB0] = &ahb0_clk.hw,
212 [CLK_APB0] = &apb0_clk.common.hw,
213 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
214 [CLK_APB0_IR] = &apb0_ir_clk.common.hw,
215 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw,
216 [CLK_APB0_RSB] = &apb0_rsb_clk.common.hw,
217 [CLK_APB0_UART] = &apb0_uart_clk.common.hw,
218 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw,
219 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw,
220 [CLK_IR] = &ir_clk.common.hw,
225 static struct ccu_reset_map sun8i_a83t_r_ccu_resets[] = {
226 [RST_APB0_IR] = { 0xb0, BIT(1) },
227 [RST_APB0_TIMER] = { 0xb0, BIT(2) },
228 [RST_APB0_RSB] = { 0xb0, BIT(3) },
229 [RST_APB0_UART] = { 0xb0, BIT(4) },
230 [RST_APB0_I2C] = { 0xb0, BIT(6) },
233 static struct ccu_reset_map sun8i_h3_r_ccu_resets[] = {
234 [RST_APB0_IR] = { 0xb0, BIT(1) },
235 [RST_APB0_TIMER] = { 0xb0, BIT(2) },
236 [RST_APB0_UART] = { 0xb0, BIT(4) },
237 [RST_APB0_I2C] = { 0xb0, BIT(6) },
240 static struct ccu_reset_map sun50i_a64_r_ccu_resets[] = {
241 [RST_APB0_IR] = { 0xb0, BIT(1) },
242 [RST_APB0_TIMER] = { 0xb0, BIT(2) },
243 [RST_APB0_RSB] = { 0xb0, BIT(3) },
244 [RST_APB0_UART] = { 0xb0, BIT(4) },
245 [RST_APB0_I2C] = { 0xb0, BIT(6) },
248 static const struct sunxi_ccu_desc sun8i_a83t_r_ccu_desc = {
249 .ccu_clks = sun8i_a83t_r_ccu_clks,
250 .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_r_ccu_clks),
252 .hw_clks = &sun8i_a83t_r_hw_clks,
254 .resets = sun8i_a83t_r_ccu_resets,
255 .num_resets = ARRAY_SIZE(sun8i_a83t_r_ccu_resets),
258 static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = {
259 .ccu_clks = sun8i_h3_r_ccu_clks,
260 .num_ccu_clks = ARRAY_SIZE(sun8i_h3_r_ccu_clks),
262 .hw_clks = &sun8i_h3_r_hw_clks,
264 .resets = sun8i_h3_r_ccu_resets,
265 .num_resets = ARRAY_SIZE(sun8i_h3_r_ccu_resets),
268 static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = {
269 .ccu_clks = sun50i_a64_r_ccu_clks,
270 .num_ccu_clks = ARRAY_SIZE(sun50i_a64_r_ccu_clks),
272 .hw_clks = &sun50i_a64_r_hw_clks,
274 .resets = sun50i_a64_r_ccu_resets,
275 .num_resets = ARRAY_SIZE(sun50i_a64_r_ccu_resets),
278 static void __init sunxi_r_ccu_init(struct device_node *node,
279 const struct sunxi_ccu_desc *desc)
283 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
285 pr_err("%pOF: Could not map the clock registers\n", node);
289 sunxi_ccu_probe(node, reg, desc);
292 static void __init sun8i_a83t_r_ccu_setup(struct device_node *node)
294 sunxi_r_ccu_init(node, &sun8i_a83t_r_ccu_desc);
296 CLK_OF_DECLARE(sun8i_a83t_r_ccu, "allwinner,sun8i-a83t-r-ccu",
297 sun8i_a83t_r_ccu_setup);
299 static void __init sun8i_h3_r_ccu_setup(struct device_node *node)
301 sunxi_r_ccu_init(node, &sun8i_h3_r_ccu_desc);
303 CLK_OF_DECLARE(sun8i_h3_r_ccu, "allwinner,sun8i-h3-r-ccu",
304 sun8i_h3_r_ccu_setup);
306 static void __init sun50i_a64_r_ccu_setup(struct device_node *node)
308 sunxi_r_ccu_init(node, &sun50i_a64_r_ccu_desc);
310 CLK_OF_DECLARE(sun50i_a64_r_ccu, "allwinner,sun50i-a64-r-ccu",
311 sun50i_a64_r_ccu_setup);