drivers/clk/sunxi-ng/ccu-sun8i-a33.c

   1 /*
   2  * Copyright (c) 2016 Maxime Ripard. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/clk-provider.h>
  15 #include <linux/io.h>
  16 #include <linux/of_address.h>
  17
  18 #include "ccu_common.h"
  19 #include "ccu_reset.h"
  20
  21 #include "ccu_div.h"
  22 #include "ccu_gate.h"
  23 #include "ccu_mp.h"
  24 #include "ccu_mult.h"
  25 #include "ccu_nk.h"
  26 #include "ccu_nkm.h"
  27 #include "ccu_nkmp.h"
  28 #include "ccu_nm.h"
  29 #include "ccu_phase.h"
  30
  31 #include "ccu-sun8i-a23-a33.h"
  32
  33 static struct ccu_nkmp pll_cpux_clk = {
  34         .enable = BIT(31),
  35         .lock   = BIT(28),
  36
  37         .n      = _SUNXI_CCU_MULT(8, 5),
  38         .k      = _SUNXI_CCU_MULT(4, 2),
  39         .m      = _SUNXI_CCU_DIV(0, 2),
  40         .p      = _SUNXI_CCU_DIV_MAX(16, 2, 4),
  41
  42         .common = {
  43                 .reg            = 0x000,
  44                 .hw.init        = CLK_HW_INIT("pll-cpux", "osc24M",
  45                                               &ccu_nkmp_ops,
  46                                               0),
  47         },
  48 };
  49
  50 /*
  51  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
  52  * the base (2x, 4x and 8x), and one variable divider (the one true
  53  * pll audio).
  54  *
  55  * With sigma-delta modulation for fractional-N on the audio PLL,
  56  * we have to use specific dividers. This means the variable divider
  57  * can no longer be used, as the audio codec requests the exact clock
  58  * rates we support through this mechanism. So we now hard code the
  59  * variable divider to 1. This means the clock rates will no longer
  60  * match the clock names.
  61  */
  62 #define SUN8I_A33_PLL_AUDIO_REG 0x008
  63
  64 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
  65         { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
  66         { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
  67 };
  68
  69 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
  70                                        "osc24M", 0x008,
  71                                        8, 7,    /* N */
  72                                        0, 5,    /* M */
  73                                        pll_audio_sdm_table, BIT(24),
  74                                        0x284, BIT(31),
  75                                        BIT(31), /* gate */
  76                                        BIT(28), /* lock */
  77                                        CLK_SET_RATE_UNGATE);
  78
  79 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
  80                                         "osc24M", 0x010,
  81                                         8, 7,           /* N */
  82                                         0, 4,           /* M */
  83                                         BIT(24),        /* frac enable */
  84                                         BIT(25),        /* frac select */
  85                                         270000000,      /* frac rate 0 */
  86                                         297000000,      /* frac rate 1 */
  87                                         BIT(31),        /* gate */
  88                                         BIT(28),        /* lock */
  89                                         CLK_SET_RATE_UNGATE);
  90
  91 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
  92                                         "osc24M", 0x018,
  93                                         8, 7,           /* N */
  94                                         0, 4,           /* M */
  95                                         BIT(24),        /* frac enable */
  96                                         BIT(25),        /* frac select */
  97                                         270000000,      /* frac rate 0 */
  98                                         297000000,      /* frac rate 1 */
  99                                         BIT(31),        /* gate */
 100                                         BIT(28),        /* lock */
 101                                         CLK_SET_RATE_UNGATE);
 102
 103 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
 104                                     "osc24M", 0x020,
 105                                     8, 5,               /* N */
 106                                     4, 2,               /* K */
 107                                     0, 2,               /* M */
 108                                     BIT(31),            /* gate */
 109                                     BIT(28),            /* lock */
 110                                     0);
 111
 112 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
 113                                            "osc24M", 0x028,
 114                                            8, 5,        /* N */
 115                                            4, 2,        /* K */
 116                                            BIT(31),     /* gate */
 117                                            BIT(28),     /* lock */
 118                                            2,           /* post-div */
 119                                            CLK_SET_RATE_UNGATE);
 120
 121 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
 122                                         "osc24M", 0x038,
 123                                         8, 7,           /* N */
 124                                         0, 4,           /* M */
 125                                         BIT(24),        /* frac enable */
 126                                         BIT(25),        /* frac select */
 127                                         270000000,      /* frac rate 0 */
 128                                         297000000,      /* frac rate 1 */
 129                                         BIT(31),        /* gate */
 130                                         BIT(28),        /* lock */
 131                                         CLK_SET_RATE_UNGATE);
 132
 133 /*
 134  * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
 135  *
 136  * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
 137  * integer / fractional clock with switchable multipliers and dividers.
 138  * This is not supported here. We hardcode the PLL to MIPI mode.
 139  */
 140 #define SUN8I_A33_PLL_MIPI_REG  0x040
 141 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
 142                                     "pll-video", 0x040,
 143                                     8, 4,               /* N */
 144                                     4, 2,               /* K */
 145                                     0, 4,               /* M */
 146                                     BIT(31) | BIT(23) | BIT(22), /* gate */
 147                                     BIT(28),            /* lock */
 148                                     CLK_SET_RATE_UNGATE);
 149
 150 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
 151                                         "osc24M", 0x044,
 152                                         8, 7,           /* N */
 153                                         0, 4,           /* M */
 154                                         BIT(24),        /* frac enable */
 155                                         BIT(25),        /* frac select */
 156                                         270000000,      /* frac rate 0 */
 157                                         297000000,      /* frac rate 1 */
 158                                         BIT(31),        /* gate */
 159                                         BIT(28),        /* lock */
 160                                         CLK_SET_RATE_UNGATE);
 161
 162 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
 163                                         "osc24M", 0x048,
 164                                         8, 7,           /* N */
 165                                         0, 4,           /* M */
 166                                         BIT(24),        /* frac enable */
 167                                         BIT(25),        /* frac select */
 168                                         270000000,      /* frac rate 0 */
 169                                         297000000,      /* frac rate 1 */
 170                                         BIT(31),        /* gate */
 171                                         BIT(28),        /* lock */
 172                                         CLK_SET_RATE_UNGATE);
 173
 174 static struct ccu_mult pll_ddr1_clk = {
 175         .enable = BIT(31),
 176         .lock   = BIT(28),
 177         .mult   = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 6, 0, 12, 0),
 178         .common = {
 179                 .reg            = 0x04c,
 180                 .hw.init        = CLK_HW_INIT("pll-ddr1", "osc24M",
 181                                               &ccu_mult_ops,
 182                                               CLK_SET_RATE_UNGATE),
 183         },
 184 };
 185
 186 static const char * const cpux_parents[] = { "osc32k", "osc24M",
 187                                              "pll-cpux" , "pll-cpux" };
 188 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
 189                      0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
 190
 191 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
 192
 193 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
 194                                              "axi" , "pll-periph" };
 195 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
 196         { .index = 3, .shift = 6, .width = 2 },
 197 };
 198 static struct ccu_div ahb1_clk = {
 199         .div            = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
 200
 201         .mux            = {
 202                 .shift  = 12,
 203                 .width  = 2,
 204
 205                 .var_predivs    = ahb1_predivs,
 206                 .n_var_predivs  = ARRAY_SIZE(ahb1_predivs),
 207         },
 208
 209         .common         = {
 210                 .reg            = 0x054,
 211                 .features       = CCU_FEATURE_VARIABLE_PREDIV,
 212                 .hw.init        = CLK_HW_INIT_PARENTS("ahb1",
 213                                                       ahb1_parents,
 214                                                       &ccu_div_ops,
 215                                                       0),
 216         },
 217 };
 218
 219 static struct clk_div_table apb1_div_table[] = {
 220         { .val = 0, .div = 2 },
 221         { .val = 1, .div = 2 },
 222         { .val = 2, .div = 4 },
 223         { .val = 3, .div = 8 },
 224         { /* Sentinel */ },
 225 };
 226 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
 227                            0x054, 8, 2, apb1_div_table, 0);
 228
 229 static const char * const apb2_parents[] = { "osc32k", "osc24M",
 230                                              "pll-periph" , "pll-periph" };
 231 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
 232                              0, 5,      /* M */
 233                              16, 2,     /* P */
 234                              24, 2,     /* mux */
 235                              0);
 236
 237 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
 238                       0x060, BIT(1), 0);
 239 static SUNXI_CCU_GATE(bus_ss_clk,       "bus-ss",       "ahb1",
 240                       0x060, BIT(5), 0);
 241 static SUNXI_CCU_GATE(bus_dma_clk,      "bus-dma",      "ahb1",
 242                       0x060, BIT(6), 0);
 243 static SUNXI_CCU_GATE(bus_mmc0_clk,     "bus-mmc0",     "ahb1",
 244                       0x060, BIT(8), 0);
 245 static SUNXI_CCU_GATE(bus_mmc1_clk,     "bus-mmc1",     "ahb1",
 246                       0x060, BIT(9), 0);
 247 static SUNXI_CCU_GATE(bus_mmc2_clk,     "bus-mmc2",     "ahb1",
 248                       0x060, BIT(10), 0);
 249 static SUNXI_CCU_GATE(bus_nand_clk,     "bus-nand",     "ahb1",
 250                       0x060, BIT(13), 0);
 251 static SUNXI_CCU_GATE(bus_dram_clk,     "bus-dram",     "ahb1",
 252                       0x060, BIT(14), 0);
 253 static SUNXI_CCU_GATE(bus_hstimer_clk,  "bus-hstimer",  "ahb1",
 254                       0x060, BIT(19), 0);
 255 static SUNXI_CCU_GATE(bus_spi0_clk,     "bus-spi0",     "ahb1",
 256                       0x060, BIT(20), 0);
 257 static SUNXI_CCU_GATE(bus_spi1_clk,     "bus-spi1",     "ahb1",
 258                       0x060, BIT(21), 0);
 259 static SUNXI_CCU_GATE(bus_otg_clk,      "bus-otg",      "ahb1",
 260                       0x060, BIT(24), 0);
 261 static SUNXI_CCU_GATE(bus_ehci_clk,     "bus-ehci",     "ahb1",
 262                       0x060, BIT(26), 0);
 263 static SUNXI_CCU_GATE(bus_ohci_clk,     "bus-ohci",     "ahb1",
 264                       0x060, BIT(29), 0);
 265
 266 static SUNXI_CCU_GATE(bus_ve_clk,       "bus-ve",       "ahb1",
 267                       0x064, BIT(0), 0);
 268 static SUNXI_CCU_GATE(bus_lcd_clk,      "bus-lcd",      "ahb1",
 269                       0x064, BIT(4), 0);
 270 static SUNXI_CCU_GATE(bus_csi_clk,      "bus-csi",      "ahb1",
 271                       0x064, BIT(8), 0);
 272 static SUNXI_CCU_GATE(bus_de_be_clk,    "bus-de-be",    "ahb1",
 273                       0x064, BIT(12), 0);
 274 static SUNXI_CCU_GATE(bus_de_fe_clk,    "bus-de-fe",    "ahb1",
 275                       0x064, BIT(14), 0);
 276 static SUNXI_CCU_GATE(bus_gpu_clk,      "bus-gpu",      "ahb1",
 277                       0x064, BIT(20), 0);
 278 static SUNXI_CCU_GATE(bus_msgbox_clk,   "bus-msgbox",   "ahb1",
 279                       0x064, BIT(21), 0);
 280 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
 281                       0x064, BIT(22), 0);
 282 static SUNXI_CCU_GATE(bus_drc_clk,      "bus-drc",      "ahb1",
 283                       0x064, BIT(25), 0);
 284 static SUNXI_CCU_GATE(bus_sat_clk,      "bus-sat",      "ahb1",
 285                       0x064, BIT(26), 0);
 286
 287 static SUNXI_CCU_GATE(bus_codec_clk,    "bus-codec",    "apb1",
 288                       0x068, BIT(0), 0);
 289 static SUNXI_CCU_GATE(bus_pio_clk,      "bus-pio",      "apb1",
 290                       0x068, BIT(5), 0);
 291 static SUNXI_CCU_GATE(bus_i2s0_clk,     "bus-i2s0",     "apb1",
 292                       0x068, BIT(12), 0);
 293 static SUNXI_CCU_GATE(bus_i2s1_clk,     "bus-i2s1",     "apb1",
 294                       0x068, BIT(13), 0);
 295
 296 static SUNXI_CCU_GATE(bus_i2c0_clk,     "bus-i2c0",     "apb2",
 297                       0x06c, BIT(0), 0);
 298 static SUNXI_CCU_GATE(bus_i2c1_clk,     "bus-i2c1",     "apb2",
 299                       0x06c, BIT(1), 0);
 300 static SUNXI_CCU_GATE(bus_i2c2_clk,     "bus-i2c2",     "apb2",
 301                       0x06c, BIT(2), 0);
 302 static SUNXI_CCU_GATE(bus_uart0_clk,    "bus-uart0",    "apb2",
 303                       0x06c, BIT(16), 0);
 304 static SUNXI_CCU_GATE(bus_uart1_clk,    "bus-uart1",    "apb2",
 305                       0x06c, BIT(17), 0);
 306 static SUNXI_CCU_GATE(bus_uart2_clk,    "bus-uart2",    "apb2",
 307                       0x06c, BIT(18), 0);
 308 static SUNXI_CCU_GATE(bus_uart3_clk,    "bus-uart3",    "apb2",
 309                       0x06c, BIT(19), 0);
 310 static SUNXI_CCU_GATE(bus_uart4_clk,    "bus-uart4",    "apb2",
 311                       0x06c, BIT(20), 0);
 312
 313 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
 314 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
 315                                   0, 4,         /* M */
 316                                   16, 2,        /* P */
 317                                   24, 2,        /* mux */
 318                                   BIT(31),      /* gate */
 319                                   0);
 320
 321 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
 322                                   0, 4,         /* M */
 323                                   16, 2,        /* P */
 324                                   24, 2,        /* mux */
 325                                   BIT(31),      /* gate */
 326                                   0);
 327
 328 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
 329                        0x088, 20, 3, 0);
 330 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
 331                        0x088, 8, 3, 0);
 332
 333 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
 334                                   0, 4,         /* M */
 335                                   16, 2,        /* P */
 336                                   24, 2,        /* mux */
 337                                   BIT(31),      /* gate */
 338                                   0);
 339
 340 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
 341                        0x08c, 20, 3, 0);
 342 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
 343                        0x08c, 8, 3, 0);
 344
 345 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
 346                                   0, 4,         /* M */
 347                                   16, 2,        /* P */
 348                                   24, 2,        /* mux */
 349                                   BIT(31),      /* gate */
 350                                   0);
 351
 352 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
 353                        0x090, 20, 3, 0);
 354 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
 355                        0x090, 8, 3, 0);
 356
 357 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
 358                                   0, 4,         /* M */
 359                                   16, 2,        /* P */
 360                                   24, 2,        /* mux */
 361                                   BIT(31),      /* gate */
 362                                   0);
 363
 364 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
 365                                   0, 4,         /* M */
 366                                   16, 2,        /* P */
 367                                   24, 2,        /* mux */
 368                                   BIT(31),      /* gate */
 369                                   0);
 370
 371 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
 372                                   0, 4,         /* M */
 373                                   16, 2,        /* P */
 374                                   24, 2,        /* mux */
 375                                   BIT(31),      /* gate */
 376                                   0);
 377
 378 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
 379                                             "pll-audio-2x", "pll-audio" };
 380 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
 381                                0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
 382
 383 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
 384                                0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
 385
 386 /* TODO: the parent for most of the USB clocks is not known */
 387 static SUNXI_CCU_GATE(usb_phy0_clk,     "usb-phy0",     "osc24M",
 388                       0x0cc, BIT(8), 0);
 389 static SUNXI_CCU_GATE(usb_phy1_clk,     "usb-phy1",     "osc24M",
 390                       0x0cc, BIT(9), 0);
 391 static SUNXI_CCU_GATE(usb_hsic_clk,     "usb-hsic",     "pll-hsic",
 392                       0x0cc, BIT(10), 0);
 393 static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M",
 394                       0x0cc, BIT(11), 0);
 395 static SUNXI_CCU_GATE(usb_ohci_clk,     "usb-ohci",     "osc24M",
 396                       0x0cc, BIT(16), 0);
 397
 398 static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr",
 399                    0x0f4, 0, 4, CLK_IS_CRITICAL);
 400
 401 static const char * const pll_ddr_parents[] = { "pll-ddr0", "pll-ddr1" };
 402 static SUNXI_CCU_MUX(pll_ddr_clk, "pll-ddr", pll_ddr_parents,
 403                      0x0f8, 16, 1, 0);
 404
 405 static SUNXI_CCU_GATE(dram_ve_clk,      "dram-ve",      "dram",
 406                       0x100, BIT(0), 0);
 407 static SUNXI_CCU_GATE(dram_csi_clk,     "dram-csi",     "dram",
 408                       0x100, BIT(1), 0);
 409 static SUNXI_CCU_GATE(dram_drc_clk,     "dram-drc",     "dram",
 410                       0x100, BIT(16), 0);
 411 static SUNXI_CCU_GATE(dram_de_fe_clk,   "dram-de-fe",   "dram",
 412                       0x100, BIT(24), 0);
 413 static SUNXI_CCU_GATE(dram_de_be_clk,   "dram-de-be",   "dram",
 414                       0x100, BIT(26), 0);
 415
 416 static const char * const de_parents[] = { "pll-video", "pll-periph-2x",
 417                                            "pll-gpu", "pll-de" };
 418 static const u8 de_table[] = { 0, 2, 3, 5 };
 419 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
 420                                        de_parents, de_table,
 421                                        0x104, 0, 4, 24, 3, BIT(31), 0);
 422
 423 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
 424                                        de_parents, de_table,
 425                                        0x10c, 0, 4, 24, 3, BIT(31), 0);
 426
 427 static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x",
 428                                                 "pll-mipi" };
 429 static const u8 lcd_ch0_table[] = { 0, 2, 4 };
 430 static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0",
 431                                      lcd_ch0_parents, lcd_ch0_table,
 432                                      0x118, 24, 3, BIT(31),
 433                                      CLK_SET_RATE_PARENT);
 434
 435 static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" };
 436 static const u8 lcd_ch1_table[] = { 0, 2 };
 437 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1",
 438                                        lcd_ch1_parents, lcd_ch1_table,
 439                                        0x12c, 0, 4, 24, 2, BIT(31), 0);
 440
 441 static const char * const csi_sclk_parents[] = { "pll-video", "pll-de",
 442                                                  "pll-mipi", "pll-ve" };
 443 static const u8 csi_sclk_table[] = { 0, 3, 4, 5 };
 444 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
 445                                        csi_sclk_parents, csi_sclk_table,
 446                                        0x134, 16, 4, 24, 3, BIT(31), 0);
 447
 448 static const char * const csi_mclk_parents[] = { "pll-video", "pll-de",
 449                                                  "osc24M" };
 450 static const u8 csi_mclk_table[] = { 0, 3, 5 };
 451 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
 452                                        csi_mclk_parents, csi_mclk_table,
 453                                        0x134, 0, 5, 8, 3, BIT(15), 0);
 454
 455 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
 456                              0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
 457
 458 static SUNXI_CCU_GATE(ac_dig_clk,       "ac-dig",       "pll-audio",
 459                       0x140, BIT(31), CLK_SET_RATE_PARENT);
 460 static SUNXI_CCU_GATE(ac_dig_4x_clk,    "ac-dig-4x",    "pll-audio-4x",
 461                       0x140, BIT(30), CLK_SET_RATE_PARENT);
 462 static SUNXI_CCU_GATE(avs_clk,          "avs",          "osc24M",
 463                       0x144, BIT(31), 0);
 464
 465 static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x",
 466                                              "pll-ddr0", "pll-ddr1" };
 467 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
 468                                  0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
 469
 470 static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" };
 471 static const u8 dsi_sclk_table[] = { 0, 2 };
 472 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk",
 473                                        dsi_sclk_parents, dsi_sclk_table,
 474                                        0x168, 16, 4, 24, 2, BIT(31), 0);
 475
 476 static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" };
 477 static const u8 dsi_dphy_table[] = { 0, 2 };
 478 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
 479                                        dsi_dphy_parents, dsi_dphy_table,
 480                                        0x168, 0, 4, 8, 2, BIT(15), 0);
 481
 482 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc",
 483                                        de_parents, de_table,
 484                                        0x180, 0, 4, 24, 3, BIT(31), 0);
 485
 486 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
 487                              0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
 488
 489 static const char * const ats_parents[] = { "osc24M", "pll-periph" };
 490 static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents,
 491                                  0x1b0, 0, 3, 24, 2, BIT(31), 0);
 492
 493 static struct ccu_common *sun8i_a33_ccu_clks[] = {
 494         &pll_cpux_clk.common,
 495         &pll_audio_base_clk.common,
 496         &pll_video_clk.common,
 497         &pll_ve_clk.common,
 498         &pll_ddr0_clk.common,
 499         &pll_periph_clk.common,
 500         &pll_gpu_clk.common,
 501         &pll_mipi_clk.common,
 502         &pll_hsic_clk.common,
 503         &pll_de_clk.common,
 504         &pll_ddr1_clk.common,
 505         &pll_ddr_clk.common,
 506         &cpux_clk.common,
 507         &axi_clk.common,
 508         &ahb1_clk.common,
 509         &apb1_clk.common,
 510         &apb2_clk.common,
 511         &bus_mipi_dsi_clk.common,
 512         &bus_ss_clk.common,
 513         &bus_dma_clk.common,
 514         &bus_mmc0_clk.common,
 515         &bus_mmc1_clk.common,
 516         &bus_mmc2_clk.common,
 517         &bus_nand_clk.common,
 518         &bus_dram_clk.common,
 519         &bus_hstimer_clk.common,
 520         &bus_spi0_clk.common,
 521         &bus_spi1_clk.common,
 522         &bus_otg_clk.common,
 523         &bus_ehci_clk.common,
 524         &bus_ohci_clk.common,
 525         &bus_ve_clk.common,
 526         &bus_lcd_clk.common,
 527         &bus_csi_clk.common,
 528         &bus_de_fe_clk.common,
 529         &bus_de_be_clk.common,
 530         &bus_gpu_clk.common,
 531         &bus_msgbox_clk.common,
 532         &bus_spinlock_clk.common,
 533         &bus_drc_clk.common,
 534         &bus_sat_clk.common,
 535         &bus_codec_clk.common,
 536         &bus_pio_clk.common,
 537         &bus_i2s0_clk.common,
 538         &bus_i2s1_clk.common,
 539         &bus_i2c0_clk.common,
 540         &bus_i2c1_clk.common,
 541         &bus_i2c2_clk.common,
 542         &bus_uart0_clk.common,
 543         &bus_uart1_clk.common,
 544         &bus_uart2_clk.common,
 545         &bus_uart3_clk.common,
 546         &bus_uart4_clk.common,
 547         &nand_clk.common,
 548         &mmc0_clk.common,
 549         &mmc0_sample_clk.common,
 550         &mmc0_output_clk.common,
 551         &mmc1_clk.common,
 552         &mmc1_sample_clk.common,
 553         &mmc1_output_clk.common,
 554         &mmc2_clk.common,
 555         &mmc2_sample_clk.common,
 556         &mmc2_output_clk.common,
 557         &ss_clk.common,
 558         &spi0_clk.common,
 559         &spi1_clk.common,
 560         &i2s0_clk.common,
 561         &i2s1_clk.common,
 562         &usb_phy0_clk.common,
 563         &usb_phy1_clk.common,
 564         &usb_hsic_clk.common,
 565         &usb_hsic_12M_clk.common,
 566         &usb_ohci_clk.common,
 567         &dram_clk.common,
 568         &dram_ve_clk.common,
 569         &dram_csi_clk.common,
 570         &dram_drc_clk.common,
 571         &dram_de_fe_clk.common,
 572         &dram_de_be_clk.common,
 573         &de_be_clk.common,
 574         &de_fe_clk.common,
 575         &lcd_ch0_clk.common,
 576         &lcd_ch1_clk.common,
 577         &csi_sclk_clk.common,
 578         &csi_mclk_clk.common,
 579         &ve_clk.common,
 580         &ac_dig_clk.common,
 581         &ac_dig_4x_clk.common,
 582         &avs_clk.common,
 583         &mbus_clk.common,
 584         &dsi_sclk_clk.common,
 585         &dsi_dphy_clk.common,
 586         &drc_clk.common,
 587         &gpu_clk.common,
 588         &ats_clk.common,
 589 };
 590
 591 /* We hardcode the divider to 1 for now */
 592 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
 593                         "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
 594 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
 595                         "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
 596 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
 597                         "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
 598 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
 599                         "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
 600 static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x",
 601                         "pll-periph", 1, 2, 0);
 602 static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x",
 603                         "pll-video", 1, 2, 0);
 604
 605 static struct clk_hw_onecell_data sun8i_a33_hw_clks = {
 606         .hws    = {
 607                 [CLK_PLL_CPUX]          = &pll_cpux_clk.common.hw,
 608                 [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
 609                 [CLK_PLL_AUDIO]         = &pll_audio_clk.hw,
 610                 [CLK_PLL_AUDIO_2X]      = &pll_audio_2x_clk.hw,
 611                 [CLK_PLL_AUDIO_4X]      = &pll_audio_4x_clk.hw,
 612                 [CLK_PLL_AUDIO_8X]      = &pll_audio_8x_clk.hw,
 613                 [CLK_PLL_VIDEO]         = &pll_video_clk.common.hw,
 614                 [CLK_PLL_VIDEO_2X]      = &pll_video_2x_clk.hw,
 615                 [CLK_PLL_VE]            = &pll_ve_clk.common.hw,
 616                 [CLK_PLL_DDR0]          = &pll_ddr0_clk.common.hw,
 617                 [CLK_PLL_PERIPH]        = &pll_periph_clk.common.hw,
 618                 [CLK_PLL_PERIPH_2X]     = &pll_periph_2x_clk.hw,
 619                 [CLK_PLL_GPU]           = &pll_gpu_clk.common.hw,
 620                 [CLK_PLL_MIPI]          = &pll_mipi_clk.common.hw,
 621                 [CLK_PLL_HSIC]          = &pll_hsic_clk.common.hw,
 622                 [CLK_PLL_DE]            = &pll_de_clk.common.hw,
 623                 [CLK_PLL_DDR1]          = &pll_ddr1_clk.common.hw,
 624                 [CLK_PLL_DDR]           = &pll_ddr_clk.common.hw,
 625                 [CLK_CPUX]              = &cpux_clk.common.hw,
 626                 [CLK_AXI]               = &axi_clk.common.hw,
 627                 [CLK_AHB1]              = &ahb1_clk.common.hw,
 628                 [CLK_APB1]              = &apb1_clk.common.hw,
 629                 [CLK_APB2]              = &apb2_clk.common.hw,
 630                 [CLK_BUS_MIPI_DSI]      = &bus_mipi_dsi_clk.common.hw,
 631                 [CLK_BUS_SS]            = &bus_ss_clk.common.hw,
 632                 [CLK_BUS_DMA]           = &bus_dma_clk.common.hw,
 633                 [CLK_BUS_MMC0]          = &bus_mmc0_clk.common.hw,
 634                 [CLK_BUS_MMC1]          = &bus_mmc1_clk.common.hw,
 635                 [CLK_BUS_MMC2]          = &bus_mmc2_clk.common.hw,
 636                 [CLK_BUS_NAND]          = &bus_nand_clk.common.hw,
 637                 [CLK_BUS_DRAM]          = &bus_dram_clk.common.hw,
 638                 [CLK_BUS_HSTIMER]       = &bus_hstimer_clk.common.hw,
 639                 [CLK_BUS_SPI0]          = &bus_spi0_clk.common.hw,
 640                 [CLK_BUS_SPI1]          = &bus_spi1_clk.common.hw,
 641                 [CLK_BUS_OTG]           = &bus_otg_clk.common.hw,
 642                 [CLK_BUS_EHCI]          = &bus_ehci_clk.common.hw,
 643                 [CLK_BUS_OHCI]          = &bus_ohci_clk.common.hw,
 644                 [CLK_BUS_VE]            = &bus_ve_clk.common.hw,
 645                 [CLK_BUS_LCD]           = &bus_lcd_clk.common.hw,
 646                 [CLK_BUS_CSI]           = &bus_csi_clk.common.hw,
 647                 [CLK_BUS_DE_BE]         = &bus_de_be_clk.common.hw,
 648                 [CLK_BUS_DE_FE]         = &bus_de_fe_clk.common.hw,
 649                 [CLK_BUS_GPU]           = &bus_gpu_clk.common.hw,
 650                 [CLK_BUS_MSGBOX]        = &bus_msgbox_clk.common.hw,
 651                 [CLK_BUS_SPINLOCK]      = &bus_spinlock_clk.common.hw,
 652                 [CLK_BUS_DRC]           = &bus_drc_clk.common.hw,
 653                 [CLK_BUS_SAT]           = &bus_sat_clk.common.hw,
 654                 [CLK_BUS_CODEC]         = &bus_codec_clk.common.hw,
 655                 [CLK_BUS_PIO]           = &bus_pio_clk.common.hw,
 656                 [CLK_BUS_I2S0]          = &bus_i2s0_clk.common.hw,
 657                 [CLK_BUS_I2S1]          = &bus_i2s1_clk.common.hw,
 658                 [CLK_BUS_I2C0]          = &bus_i2c0_clk.common.hw,
 659                 [CLK_BUS_I2C1]          = &bus_i2c1_clk.common.hw,
 660                 [CLK_BUS_I2C2]          = &bus_i2c2_clk.common.hw,
 661                 [CLK_BUS_UART0]         = &bus_uart0_clk.common.hw,
 662                 [CLK_BUS_UART1]         = &bus_uart1_clk.common.hw,
 663                 [CLK_BUS_UART2]         = &bus_uart2_clk.common.hw,
 664                 [CLK_BUS_UART3]         = &bus_uart3_clk.common.hw,
 665                 [CLK_BUS_UART4]         = &bus_uart4_clk.common.hw,
 666                 [CLK_NAND]              = &nand_clk.common.hw,
 667                 [CLK_MMC0]              = &mmc0_clk.common.hw,
 668                 [CLK_MMC0_SAMPLE]       = &mmc0_sample_clk.common.hw,
 669                 [CLK_MMC0_OUTPUT]       = &mmc0_output_clk.common.hw,
 670                 [CLK_MMC1]              = &mmc1_clk.common.hw,
 671                 [CLK_MMC1_SAMPLE]       = &mmc1_sample_clk.common.hw,
 672                 [CLK_MMC1_OUTPUT]       = &mmc1_output_clk.common.hw,
 673                 [CLK_MMC2]              = &mmc2_clk.common.hw,
 674                 [CLK_MMC2_SAMPLE]       = &mmc2_sample_clk.common.hw,
 675                 [CLK_MMC2_OUTPUT]       = &mmc2_output_clk.common.hw,
 676                 [CLK_SS]                = &ss_clk.common.hw,
 677                 [CLK_SPI0]              = &spi0_clk.common.hw,
 678                 [CLK_SPI1]              = &spi1_clk.common.hw,
 679                 [CLK_I2S0]              = &i2s0_clk.common.hw,
 680                 [CLK_I2S1]              = &i2s1_clk.common.hw,
 681                 [CLK_USB_PHY0]          = &usb_phy0_clk.common.hw,
 682                 [CLK_USB_PHY1]          = &usb_phy1_clk.common.hw,
 683                 [CLK_USB_HSIC]          = &usb_hsic_clk.common.hw,
 684                 [CLK_USB_HSIC_12M]      = &usb_hsic_12M_clk.common.hw,
 685                 [CLK_USB_OHCI]          = &usb_ohci_clk.common.hw,
 686                 [CLK_DRAM]              = &dram_clk.common.hw,
 687                 [CLK_DRAM_VE]           = &dram_ve_clk.common.hw,
 688                 [CLK_DRAM_CSI]          = &dram_csi_clk.common.hw,
 689                 [CLK_DRAM_DRC]          = &dram_drc_clk.common.hw,
 690                 [CLK_DRAM_DE_FE]        = &dram_de_fe_clk.common.hw,
 691                 [CLK_DRAM_DE_BE]        = &dram_de_be_clk.common.hw,
 692                 [CLK_DE_BE]             = &de_be_clk.common.hw,
 693                 [CLK_DE_FE]             = &de_fe_clk.common.hw,
 694                 [CLK_LCD_CH0]           = &lcd_ch0_clk.common.hw,
 695                 [CLK_LCD_CH1]           = &lcd_ch1_clk.common.hw,
 696                 [CLK_CSI_SCLK]          = &csi_sclk_clk.common.hw,
 697                 [CLK_CSI_MCLK]          = &csi_mclk_clk.common.hw,
 698                 [CLK_VE]                = &ve_clk.common.hw,
 699                 [CLK_AC_DIG]            = &ac_dig_clk.common.hw,
 700                 [CLK_AC_DIG_4X]         = &ac_dig_4x_clk.common.hw,
 701                 [CLK_AVS]               = &avs_clk.common.hw,
 702                 [CLK_MBUS]              = &mbus_clk.common.hw,
 703                 [CLK_DSI_SCLK]          = &dsi_sclk_clk.common.hw,
 704                 [CLK_DSI_DPHY]          = &dsi_dphy_clk.common.hw,
 705                 [CLK_DRC]               = &drc_clk.common.hw,
 706                 [CLK_GPU]               = &gpu_clk.common.hw,
 707                 [CLK_ATS]               = &ats_clk.common.hw,
 708         },
 709         .num    = CLK_NUMBER,
 710 };
 711
 712 static struct ccu_reset_map sun8i_a33_ccu_resets[] = {
 713         [RST_USB_PHY0]          =  { 0x0cc, BIT(0) },
 714         [RST_USB_PHY1]          =  { 0x0cc, BIT(1) },
 715         [RST_USB_HSIC]          =  { 0x0cc, BIT(2) },
 716
 717         [RST_MBUS]              =  { 0x0fc, BIT(31) },
 718
 719         [RST_BUS_MIPI_DSI]      =  { 0x2c0, BIT(1) },
 720         [RST_BUS_SS]            =  { 0x2c0, BIT(5) },
 721         [RST_BUS_DMA]           =  { 0x2c0, BIT(6) },
 722         [RST_BUS_MMC0]          =  { 0x2c0, BIT(8) },
 723         [RST_BUS_MMC1]          =  { 0x2c0, BIT(9) },
 724         [RST_BUS_MMC2]          =  { 0x2c0, BIT(10) },
 725         [RST_BUS_NAND]          =  { 0x2c0, BIT(13) },
 726         [RST_BUS_DRAM]          =  { 0x2c0, BIT(14) },
 727         [RST_BUS_HSTIMER]       =  { 0x2c0, BIT(19) },
 728         [RST_BUS_SPI0]          =  { 0x2c0, BIT(20) },
 729         [RST_BUS_SPI1]          =  { 0x2c0, BIT(21) },
 730         [RST_BUS_OTG]           =  { 0x2c0, BIT(24) },
 731         [RST_BUS_EHCI]          =  { 0x2c0, BIT(26) },
 732         [RST_BUS_OHCI]          =  { 0x2c0, BIT(29) },
 733
 734         [RST_BUS_VE]            =  { 0x2c4, BIT(0) },
 735         [RST_BUS_LCD]           =  { 0x2c4, BIT(4) },
 736         [RST_BUS_CSI]           =  { 0x2c4, BIT(8) },
 737         [RST_BUS_DE_BE]         =  { 0x2c4, BIT(12) },
 738         [RST_BUS_DE_FE]         =  { 0x2c4, BIT(14) },
 739         [RST_BUS_GPU]           =  { 0x2c4, BIT(20) },
 740         [RST_BUS_MSGBOX]        =  { 0x2c4, BIT(21) },
 741         [RST_BUS_SPINLOCK]      =  { 0x2c4, BIT(22) },
 742         [RST_BUS_DRC]           =  { 0x2c4, BIT(25) },
 743         [RST_BUS_SAT]           =  { 0x2c4, BIT(26) },
 744
 745         [RST_BUS_LVDS]          =  { 0x2c8, BIT(0) },
 746
 747         [RST_BUS_CODEC]         =  { 0x2d0, BIT(0) },
 748         [RST_BUS_I2S0]          =  { 0x2d0, BIT(12) },
 749         [RST_BUS_I2S1]          =  { 0x2d0, BIT(13) },
 750
 751         [RST_BUS_I2C0]          =  { 0x2d8, BIT(0) },
 752         [RST_BUS_I2C1]          =  { 0x2d8, BIT(1) },
 753         [RST_BUS_I2C2]          =  { 0x2d8, BIT(2) },
 754         [RST_BUS_UART0]         =  { 0x2d8, BIT(16) },
 755         [RST_BUS_UART1]         =  { 0x2d8, BIT(17) },
 756         [RST_BUS_UART2]         =  { 0x2d8, BIT(18) },
 757         [RST_BUS_UART3]         =  { 0x2d8, BIT(19) },
 758         [RST_BUS_UART4]         =  { 0x2d8, BIT(20) },
 759 };
 760
 761 static const struct sunxi_ccu_desc sun8i_a33_ccu_desc = {
 762         .ccu_clks       = sun8i_a33_ccu_clks,
 763         .num_ccu_clks   = ARRAY_SIZE(sun8i_a33_ccu_clks),
 764
 765         .hw_clks        = &sun8i_a33_hw_clks,
 766
 767         .resets         = sun8i_a33_ccu_resets,
 768         .num_resets     = ARRAY_SIZE(sun8i_a33_ccu_resets),
 769 };
 770
 771 static struct ccu_pll_nb sun8i_a33_pll_cpu_nb = {
 772         .common = &pll_cpux_clk.common,
 773         /* copy from pll_cpux_clk */
 774         .enable = BIT(31),
 775         .lock   = BIT(28),
 776 };
 777
 778 static struct ccu_mux_nb sun8i_a33_cpu_nb = {
 779         .common         = &cpux_clk.common,
 780         .cm             = &cpux_clk.mux,
 781         .delay_us       = 1, /* > 8 clock cycles at 24 MHz */
 782         .bypass_index   = 1, /* index of 24 MHz oscillator */
 783 };
 784
 785 static void __init sun8i_a33_ccu_setup(struct device_node *node)
 786 {
 787         void __iomem *reg;
 788         u32 val;
 789
 790         reg = of_io_request_and_map(node, 0, of_node_full_name(node));
 791         if (IS_ERR(reg)) {
 792                 pr_err("%pOF: Could not map the clock registers\n", node);
 793                 return;
 794         }
 795
 796         /* Force the PLL-Audio-1x divider to 1 */
 797         val = readl(reg + SUN8I_A33_PLL_AUDIO_REG);
 798         val &= ~GENMASK(19, 16);
 799         writel(val | (0 << 16), reg + SUN8I_A33_PLL_AUDIO_REG);
 800
 801         /* Force PLL-MIPI to MIPI mode */
 802         val = readl(reg + SUN8I_A33_PLL_MIPI_REG);
 803         val &= ~BIT(16);
 804         writel(val, reg + SUN8I_A33_PLL_MIPI_REG);
 805
 806         sunxi_ccu_probe(node, reg, &sun8i_a33_ccu_desc);
 807
 808         /* Gate then ungate PLL CPU after any rate changes */
 809         ccu_pll_notifier_register(&sun8i_a33_pll_cpu_nb);
 810
 811         /* Reparent CPU during PLL CPU rate changes */
 812         ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
 813                                   &sun8i_a33_cpu_nb);
 814 }
 815 CLK_OF_DECLARE(sun8i_a33_ccu, "allwinner,sun8i-a33-ccu",
 816                sun8i_a33_ccu_setup);