1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/of_device.h>
9 #include <linux/platform_device.h>
11 #include "ccu_common.h"
12 #include "ccu_reset.h"
19 #include "ccu-sun50i-h6-r.h"
22 * Information about AR100 and AHB/APB clocks in R_CCU are gathered from
23 * clock definitions in the BSP source code.
26 static const char * const ar100_r_apb2_parents[] = { "osc24M", "osc32k",
27 "iosc", "pll-periph0" };
28 static const struct ccu_mux_var_prediv ar100_r_apb2_predivs[] = {
29 { .index = 3, .shift = 0, .width = 5 },
32 static struct ccu_div ar100_clk = {
33 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
39 .var_predivs = ar100_r_apb2_predivs,
40 .n_var_predivs = ARRAY_SIZE(ar100_r_apb2_predivs),
45 .features = CCU_FEATURE_VARIABLE_PREDIV,
46 .hw.init = CLK_HW_INIT_PARENTS("ar100",
53 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0);
55 static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0);
57 static struct ccu_div r_apb2_clk = {
58 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
64 .var_predivs = ar100_r_apb2_predivs,
65 .n_var_predivs = ARRAY_SIZE(ar100_r_apb2_predivs),
70 .features = CCU_FEATURE_VARIABLE_PREDIV,
71 .hw.init = CLK_HW_INIT_PARENTS("r-apb2",
79 * Information about the gate/resets are gathered from the clock header file
80 * in the BSP source code, although most of them are unused. The existence
81 * of the hardware block is verified with "3.1 Memory Mapping" chapter in
82 * "Allwinner H6 V200 User Manual V1.1"; and the parent APB buses are verified
83 * with "3.3.2.1 System Bus Tree" chapter inthe same document.
85 static SUNXI_CCU_GATE(r_apb1_timer_clk, "r-apb1-timer", "r-apb1",
87 static SUNXI_CCU_GATE(r_apb1_twd_clk, "r-apb1-twd", "r-apb1",
89 static SUNXI_CCU_GATE(r_apb1_pwm_clk, "r-apb1-pwm", "r-apb1",
91 static SUNXI_CCU_GATE(r_apb2_uart_clk, "r-apb2-uart", "r-apb2",
93 static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
95 static SUNXI_CCU_GATE(r_apb2_rsb_clk, "r-apb2-rsb", "r-apb2",
97 static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1",
99 static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
101 static SUNXI_CCU_GATE(r_apb1_rtc_clk, "r-apb1-rtc", "r-apb1",
102 0x20c, BIT(0), CLK_IGNORE_UNUSED);
104 /* Information of IR(RX) mod clock is gathered from BSP source code */
105 static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
106 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
107 r_mod0_default_parents, 0x1c0,
115 * BSP didn't use the 1-wire function at all now, and the information about
116 * this mod clock is guessed from the IR mod clock above. The existence of
117 * this mod clock is proven by BSP clock header, and the dividers are verified
118 * by contents in the 1-wire related chapter of the User Manual.
121 static SUNXI_CCU_MP_WITH_MUX_GATE(w1_clk, "w1",
122 r_mod0_default_parents, 0x1e0,
129 static struct ccu_common *sun50i_h6_r_ccu_clks[] = {
133 &r_apb1_timer_clk.common,
134 &r_apb1_twd_clk.common,
135 &r_apb1_pwm_clk.common,
136 &r_apb2_uart_clk.common,
137 &r_apb2_i2c_clk.common,
138 &r_apb2_rsb_clk.common,
139 &r_apb1_ir_clk.common,
140 &r_apb1_w1_clk.common,
141 &r_apb1_rtc_clk.common,
146 static struct ccu_common *sun50i_h616_r_ccu_clks[] = {
149 &r_apb1_twd_clk.common,
150 &r_apb2_i2c_clk.common,
151 &r_apb2_rsb_clk.common,
152 &r_apb1_ir_clk.common,
153 &r_apb1_rtc_clk.common,
157 static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
159 [CLK_AR100] = &ar100_clk.common.hw,
160 [CLK_R_AHB] = &r_ahb_clk.hw,
161 [CLK_R_APB1] = &r_apb1_clk.common.hw,
162 [CLK_R_APB2] = &r_apb2_clk.common.hw,
163 [CLK_R_APB1_TIMER] = &r_apb1_timer_clk.common.hw,
164 [CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw,
165 [CLK_R_APB1_PWM] = &r_apb1_pwm_clk.common.hw,
166 [CLK_R_APB2_UART] = &r_apb2_uart_clk.common.hw,
167 [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw,
168 [CLK_R_APB2_RSB] = &r_apb2_rsb_clk.common.hw,
169 [CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw,
170 [CLK_R_APB1_W1] = &r_apb1_w1_clk.common.hw,
171 [CLK_R_APB1_RTC] = &r_apb1_rtc_clk.common.hw,
172 [CLK_IR] = &ir_clk.common.hw,
173 [CLK_W1] = &w1_clk.common.hw,
178 static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = {
180 [CLK_R_AHB] = &r_ahb_clk.hw,
181 [CLK_R_APB1] = &r_apb1_clk.common.hw,
182 [CLK_R_APB2] = &r_apb2_clk.common.hw,
183 [CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw,
184 [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw,
185 [CLK_R_APB2_RSB] = &r_apb2_rsb_clk.common.hw,
186 [CLK_R_APB1_IR] = &r_apb1_ir_clk.common.hw,
187 [CLK_R_APB1_RTC] = &r_apb1_rtc_clk.common.hw,
188 [CLK_IR] = &ir_clk.common.hw,
193 static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
194 [RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
195 [RST_R_APB1_TWD] = { 0x12c, BIT(16) },
196 [RST_R_APB1_PWM] = { 0x13c, BIT(16) },
197 [RST_R_APB2_UART] = { 0x18c, BIT(16) },
198 [RST_R_APB2_I2C] = { 0x19c, BIT(16) },
199 [RST_R_APB2_RSB] = { 0x1bc, BIT(16) },
200 [RST_R_APB1_IR] = { 0x1cc, BIT(16) },
201 [RST_R_APB1_W1] = { 0x1ec, BIT(16) },
204 static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = {
205 [RST_R_APB1_TWD] = { 0x12c, BIT(16) },
206 [RST_R_APB2_I2C] = { 0x19c, BIT(16) },
207 [RST_R_APB2_RSB] = { 0x1bc, BIT(16) },
208 [RST_R_APB1_IR] = { 0x1cc, BIT(16) },
211 static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
212 .ccu_clks = sun50i_h6_r_ccu_clks,
213 .num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks),
215 .hw_clks = &sun50i_h6_r_hw_clks,
217 .resets = sun50i_h6_r_ccu_resets,
218 .num_resets = ARRAY_SIZE(sun50i_h6_r_ccu_resets),
221 static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = {
222 .ccu_clks = sun50i_h616_r_ccu_clks,
223 .num_ccu_clks = ARRAY_SIZE(sun50i_h616_r_ccu_clks),
225 .hw_clks = &sun50i_h616_r_hw_clks,
227 .resets = sun50i_h616_r_ccu_resets,
228 .num_resets = ARRAY_SIZE(sun50i_h616_r_ccu_resets),
231 static int sun50i_h6_r_ccu_probe(struct platform_device *pdev)
233 const struct sunxi_ccu_desc *desc;
236 desc = of_device_get_match_data(&pdev->dev);
240 reg = devm_platform_ioremap_resource(pdev, 0);
244 return devm_sunxi_ccu_probe(&pdev->dev, reg, desc);
247 static const struct of_device_id sun50i_h6_r_ccu_ids[] = {
249 .compatible = "allwinner,sun50i-h6-r-ccu",
250 .data = &sun50i_h6_r_ccu_desc,
253 .compatible = "allwinner,sun50i-h616-r-ccu",
254 .data = &sun50i_h616_r_ccu_desc,
259 static struct platform_driver sun50i_h6_r_ccu_driver = {
260 .probe = sun50i_h6_r_ccu_probe,
262 .name = "sun50i-h6-r-ccu",
263 .suppress_bind_attrs = true,
264 .of_match_table = sun50i_h6_r_ccu_ids,
267 module_platform_driver(sun50i_h6_r_ccu_driver);
269 MODULE_IMPORT_NS(SUNXI_CCU);
270 MODULE_LICENSE("GPL");