drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
   4  */
   5
   6 #include <linux/clk-provider.h>
   7 #include <linux/of_address.h>
   8 #include <linux/platform_device.h>
   9
  10 #include "ccu_common.h"
  11 #include "ccu_reset.h"
  12
  13 #include "ccu_div.h"
  14 #include "ccu_gate.h"
  15 #include "ccu_mp.h"
  16 #include "ccu_nm.h"
  17
  18 #include "ccu-sun50i-h6-r.h"
  19
  20 /*
  21  * Information about AR100 and AHB/APB clocks in R_CCU are gathered from
  22  * clock definitions in the BSP source code.
  23  */
  24
  25 static const char * const ar100_r_apb2_parents[] = { "osc24M", "osc32k",
  26                                                      "iosc", "pll-periph0" };
  27 static const struct ccu_mux_var_prediv ar100_r_apb2_predivs[] = {
  28         { .index = 3, .shift = 0, .width = 5 },
  29 };
  30
  31 static struct ccu_div ar100_clk = {
  32         .div            = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
  33
  34         .mux            = {
  35                 .shift  = 24,
  36                 .width  = 2,
  37
  38                 .var_predivs    = ar100_r_apb2_predivs,
  39                 .n_var_predivs  = ARRAY_SIZE(ar100_r_apb2_predivs),
  40         },
  41
  42         .common         = {
  43                 .reg            = 0x000,
  44                 .features       = CCU_FEATURE_VARIABLE_PREDIV,
  45                 .hw.init        = CLK_HW_INIT_PARENTS("ar100",
  46                                                       ar100_r_apb2_parents,
  47                                                       &ccu_div_ops,
  48                                                       0),
  49         },
  50 };
  51
  52 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0);
  53
  54 static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0);
  55
  56 static struct ccu_div r_apb2_clk = {
  57         .div            = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
  58
  59         .mux            = {
  60                 .shift  = 24,
  61                 .width  = 2,
  62
  63                 .var_predivs    = ar100_r_apb2_predivs,
  64                 .n_var_predivs  = ARRAY_SIZE(ar100_r_apb2_predivs),
  65         },
  66
  67         .common         = {
  68                 .reg            = 0x010,
  69                 .features       = CCU_FEATURE_VARIABLE_PREDIV,
  70                 .hw.init        = CLK_HW_INIT_PARENTS("r-apb2",
  71                                                       ar100_r_apb2_parents,
  72                                                       &ccu_div_ops,
  73                                                       0),
  74         },
  75 };
  76
  77 /*
  78  * Information about the gate/resets are gathered from the clock header file
  79  * in the BSP source code, although most of them are unused. The existence
  80  * of the hardware block is verified with "3.1 Memory Mapping" chapter in
  81  * "Allwinner H6 V200 User Manual V1.1"; and the parent APB buses are verified
  82  * with "3.3.2.1 System Bus Tree" chapter inthe same document.
  83  */
  84 static SUNXI_CCU_GATE(r_apb1_timer_clk, "r-apb1-timer", "r-apb1",
  85                       0x11c, BIT(0), 0);
  86 static SUNXI_CCU_GATE(r_apb1_twd_clk,   "r-apb1-twd",   "r-apb1",
  87                       0x12c, BIT(0), 0);
  88 static SUNXI_CCU_GATE(r_apb1_pwm_clk,   "r-apb1-pwm",   "r-apb1",
  89                       0x13c, BIT(0), 0);
  90 static SUNXI_CCU_GATE(r_apb2_uart_clk,  "r-apb2-uart",  "r-apb2",
  91                       0x18c, BIT(0), 0);
  92 static SUNXI_CCU_GATE(r_apb2_i2c_clk,   "r-apb2-i2c",   "r-apb2",
  93                       0x19c, BIT(0), 0);
  94 static SUNXI_CCU_GATE(r_apb1_ir_clk,    "r-apb1-ir",    "r-apb1",
  95                       0x1cc, BIT(0), 0);
  96 static SUNXI_CCU_GATE(r_apb1_w1_clk,    "r-apb1-w1",    "r-apb1",
  97                       0x1ec, BIT(0), 0);
  98
  99 /* Information of IR(RX) mod clock is gathered from BSP source code */
 100 static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
 101 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
 102                                   r_mod0_default_parents, 0x1c0,
 103                                   0, 5,         /* M */
 104                                   8, 2,         /* P */
 105                                   24, 1,        /* mux */
 106                                   BIT(31),      /* gate */
 107                                   0);
 108
 109 /*
 110  * BSP didn't use the 1-wire function at all now, and the information about
 111  * this mod clock is guessed from the IR mod clock above. The existence of
 112  * this mod clock is proven by BSP clock header, and the dividers are verified
 113  * by contents in the 1-wire related chapter of the User Manual.
 114  */
 115
 116 static SUNXI_CCU_MP_WITH_MUX_GATE(w1_clk, "w1",
 117                                   r_mod0_default_parents, 0x1e0,
 118                                   0, 5,         /* M */
 119                                   8, 2,         /* P */
 120                                   24, 1,        /* mux */
 121                                   BIT(31),      /* gate */
 122                                   0);
 123
 124 static struct ccu_common *sun50i_h6_r_ccu_clks[] = {
 125         &ar100_clk.common,
 126         &r_apb1_clk.common,
 127         &r_apb2_clk.common,
 128         &r_apb1_timer_clk.common,
 129         &r_apb1_twd_clk.common,
 130         &r_apb1_pwm_clk.common,
 131         &r_apb2_uart_clk.common,
 132         &r_apb2_i2c_clk.common,
 133         &r_apb1_ir_clk.common,
 134         &r_apb1_w1_clk.common,
 135         &ir_clk.common,
 136         &w1_clk.common,
 137 };
 138
 139 static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
 140         .hws    = {
 141                 [CLK_AR100]             = &ar100_clk.common.hw,
 142                 [CLK_R_AHB]             = &r_ahb_clk.hw,
 143                 [CLK_R_APB1]            = &r_apb1_clk.common.hw,
 144                 [CLK_R_APB2]            = &r_apb2_clk.common.hw,
 145                 [CLK_R_APB1_TIMER]      = &r_apb1_timer_clk.common.hw,
 146                 [CLK_R_APB1_TWD]        = &r_apb1_twd_clk.common.hw,
 147                 [CLK_R_APB1_PWM]        = &r_apb1_pwm_clk.common.hw,
 148                 [CLK_R_APB2_UART]       = &r_apb2_uart_clk.common.hw,
 149                 [CLK_R_APB2_I2C]        = &r_apb2_i2c_clk.common.hw,
 150                 [CLK_R_APB1_IR]         = &r_apb1_ir_clk.common.hw,
 151                 [CLK_R_APB1_W1]         = &r_apb1_w1_clk.common.hw,
 152                 [CLK_IR]                = &ir_clk.common.hw,
 153                 [CLK_W1]                = &w1_clk.common.hw,
 154         },
 155         .num    = CLK_NUMBER,
 156 };
 157
 158 static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
 159         [RST_R_APB1_TIMER]      =  { 0x11c, BIT(16) },
 160         [RST_R_APB1_TWD]        =  { 0x12c, BIT(16) },
 161         [RST_R_APB1_PWM]        =  { 0x13c, BIT(16) },
 162         [RST_R_APB2_UART]       =  { 0x18c, BIT(16) },
 163         [RST_R_APB2_I2C]        =  { 0x19c, BIT(16) },
 164         [RST_R_APB1_IR]         =  { 0x1cc, BIT(16) },
 165         [RST_R_APB1_W1]         =  { 0x1ec, BIT(16) },
 166 };
 167
 168 static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
 169         .ccu_clks       = sun50i_h6_r_ccu_clks,
 170         .num_ccu_clks   = ARRAY_SIZE(sun50i_h6_r_ccu_clks),
 171
 172         .hw_clks        = &sun50i_h6_r_hw_clks,
 173
 174         .resets         = sun50i_h6_r_ccu_resets,
 175         .num_resets     = ARRAY_SIZE(sun50i_h6_r_ccu_resets),
 176 };
 177
 178 static void __init sunxi_r_ccu_init(struct device_node *node,
 179                                     const struct sunxi_ccu_desc *desc)
 180 {
 181         void __iomem *reg;
 182
 183         reg = of_io_request_and_map(node, 0, of_node_full_name(node));
 184         if (IS_ERR(reg)) {
 185                 pr_err("%pOF: Could not map the clock registers\n", node);
 186                 return;
 187         }
 188
 189         sunxi_ccu_probe(node, reg, desc);
 190 }
 191
 192 static void __init sun50i_h6_r_ccu_setup(struct device_node *node)
 193 {
 194         sunxi_r_ccu_init(node, &sun50i_h6_r_ccu_desc);
 195 }
 196 CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu",
 197                sun50i_h6_r_ccu_setup);