drivers/clk/sunxi-ng/ccu-sun4i-a10.c

   1 /*
   2  * Copyright (c) 2017 Priit Laes <plaes@plaes.org>.
   3  * Copyright (c) 2017 Maxime Ripard.
   4  * Copyright (c) 2017 Jonathan Liu.
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/clk-provider.h>
  17 #include <linux/io.h>
  18 #include <linux/of_address.h>
  19
  20 #include "ccu_common.h"
  21 #include "ccu_reset.h"
  22
  23 #include "ccu_div.h"
  24 #include "ccu_gate.h"
  25 #include "ccu_mp.h"
  26 #include "ccu_mult.h"
  27 #include "ccu_nk.h"
  28 #include "ccu_nkm.h"
  29 #include "ccu_nkmp.h"
  30 #include "ccu_nm.h"
  31 #include "ccu_phase.h"
  32 #include "ccu_sdm.h"
  33
  34 #include "ccu-sun4i-a10.h"
  35
  36 static struct ccu_nkmp pll_core_clk = {
  37         .enable         = BIT(31),
  38         .n              = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
  39         .k              = _SUNXI_CCU_MULT(4, 2),
  40         .m              = _SUNXI_CCU_DIV(0, 2),
  41         .p              = _SUNXI_CCU_DIV(16, 2),
  42         .common         = {
  43                 .reg            = 0x000,
  44                 .hw.init        = CLK_HW_INIT("pll-core",
  45                                               "hosc",
  46                                               &ccu_nkmp_ops,
  47                                               0),
  48         },
  49 };
  50
  51 /*
  52  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
  53  * the base (2x, 4x and 8x), and one variable divider (the one true
  54  * pll audio).
  55  *
  56  * With sigma-delta modulation for fractional-N on the audio PLL,
  57  * we have to use specific dividers. This means the variable divider
  58  * can no longer be used, as the audio codec requests the exact clock
  59  * rates we support through this mechanism. So we now hard code the
  60  * variable divider to 1. This means the clock rates will no longer
  61  * match the clock names.
  62  */
  63 #define SUN4I_PLL_AUDIO_REG     0x008
  64
  65 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
  66         { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
  67         { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
  68 };
  69
  70 static struct ccu_nm pll_audio_base_clk = {
  71         .enable         = BIT(31),
  72         .n              = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
  73         .m              = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
  74         .sdm            = _SUNXI_CCU_SDM(pll_audio_sdm_table, 0,
  75                                          0x00c, BIT(31)),
  76         .common         = {
  77                 .reg            = 0x008,
  78                 .features       = CCU_FEATURE_SIGMA_DELTA_MOD,
  79                 .hw.init        = CLK_HW_INIT("pll-audio-base",
  80                                               "hosc",
  81                                               &ccu_nm_ops,
  82                                               0),
  83         },
  84
  85 };
  86
  87 static struct ccu_mult pll_video0_clk = {
  88         .enable         = BIT(31),
  89         .mult           = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
  90         .frac           = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
  91                                           270000000, 297000000),
  92         .common         = {
  93                 .reg            = 0x010,
  94                 .features       = (CCU_FEATURE_FRACTIONAL |
  95                                    CCU_FEATURE_ALL_PREDIV),
  96                 .prediv         = 8,
  97                 .hw.init        = CLK_HW_INIT("pll-video0",
  98                                               "hosc",
  99                                               &ccu_mult_ops,
 100                                               0),
 101         },
 102 };
 103
 104 static struct ccu_nkmp pll_ve_sun4i_clk = {
 105         .enable         = BIT(31),
 106         .n              = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
 107         .k              = _SUNXI_CCU_MULT(4, 2),
 108         .m              = _SUNXI_CCU_DIV(0, 2),
 109         .p              = _SUNXI_CCU_DIV(16, 2),
 110         .common         = {
 111                 .reg            = 0x018,
 112                 .hw.init        = CLK_HW_INIT("pll-ve",
 113                                               "hosc",
 114                                               &ccu_nkmp_ops,
 115                                               0),
 116         },
 117 };
 118
 119 static struct ccu_nk pll_ve_sun7i_clk = {
 120         .enable         = BIT(31),
 121         .n              = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
 122         .k              = _SUNXI_CCU_MULT(4, 2),
 123         .common         = {
 124                 .reg            = 0x018,
 125                 .hw.init        = CLK_HW_INIT("pll-ve",
 126                                               "hosc",
 127                                               &ccu_nk_ops,
 128                                               0),
 129         },
 130 };
 131
 132 static struct ccu_nk pll_ddr_base_clk = {
 133         .enable         = BIT(31),
 134         .n              = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
 135         .k              = _SUNXI_CCU_MULT(4, 2),
 136         .common         = {
 137                 .reg            = 0x020,
 138                 .hw.init        = CLK_HW_INIT("pll-ddr-base",
 139                                               "hosc",
 140                                               &ccu_nk_ops,
 141                                               0),
 142         },
 143 };
 144
 145 static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,
 146                    CLK_IS_CRITICAL);
 147
 148 static struct ccu_div pll_ddr_other_clk = {
 149         .div            = _SUNXI_CCU_DIV_FLAGS(16, 2, CLK_DIVIDER_POWER_OF_TWO),
 150         .common         = {
 151                 .reg            = 0x020,
 152                 .hw.init        = CLK_HW_INIT("pll-ddr-other", "pll-ddr-base",
 153                                               &ccu_div_ops,
 154                                               0),
 155         },
 156 };
 157
 158 static struct ccu_nk pll_periph_base_clk = {
 159         .enable         = BIT(31),
 160         .n              = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
 161         .k              = _SUNXI_CCU_MULT(4, 2),
 162         .common         = {
 163                 .reg            = 0x028,
 164                 .hw.init        = CLK_HW_INIT("pll-periph-base",
 165                                               "hosc",
 166                                               &ccu_nk_ops,
 167                                               0),
 168         },
 169 };
 170
 171 static CLK_FIXED_FACTOR(pll_periph_clk, "pll-periph", "pll-periph-base",
 172                         2, 1, CLK_SET_RATE_PARENT);
 173
 174 /* Not documented on A10 */
 175 static struct ccu_div pll_periph_sata_clk = {
 176         .enable         = BIT(14),
 177         .div            = _SUNXI_CCU_DIV(0, 2),
 178         .fixed_post_div = 6,
 179         .common         = {
 180                 .reg            = 0x028,
 181                 .features       = CCU_FEATURE_FIXED_POSTDIV,
 182                 .hw.init        = CLK_HW_INIT("pll-periph-sata",
 183                                               "pll-periph-base",
 184                                               &ccu_div_ops, 0),
 185         },
 186 };
 187
 188 static struct ccu_mult pll_video1_clk = {
 189         .enable         = BIT(31),
 190         .mult           = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
 191         .frac           = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
 192                                   270000000, 297000000),
 193         .common         = {
 194                 .reg            = 0x030,
 195                 .features       = (CCU_FEATURE_FRACTIONAL |
 196                                    CCU_FEATURE_ALL_PREDIV),
 197                 .prediv         = 8,
 198                 .hw.init        = CLK_HW_INIT("pll-video1",
 199                                               "hosc",
 200                                               &ccu_mult_ops,
 201                                               0),
 202         },
 203 };
 204
 205 /* Not present on A10 */
 206 static struct ccu_nk pll_gpu_clk = {
 207         .enable         = BIT(31),
 208         .n              = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
 209         .k              = _SUNXI_CCU_MULT(4, 2),
 210         .common         = {
 211                 .reg            = 0x040,
 212                 .hw.init        = CLK_HW_INIT("pll-gpu",
 213                                               "hosc",
 214                                               &ccu_nk_ops,
 215                                               0),
 216         },
 217 };
 218
 219 static SUNXI_CCU_GATE(hosc_clk, "hosc", "osc24M", 0x050, BIT(0), 0);
 220
 221 static const char *const cpu_parents[] = { "osc32k", "hosc",
 222                                            "pll-core", "pll-periph" };
 223 static const struct ccu_mux_fixed_prediv cpu_predivs[] = {
 224         { .index = 3, .div = 3, },
 225 };
 226
 227 #define SUN4I_AHB_REG           0x054
 228 static struct ccu_mux cpu_clk = {
 229         .mux            = {
 230                 .shift          = 16,
 231                 .width          = 2,
 232                 .fixed_predivs  = cpu_predivs,
 233                 .n_predivs      = ARRAY_SIZE(cpu_predivs),
 234         },
 235         .common         = {
 236                 .reg            = 0x054,
 237                 .features       = CCU_FEATURE_FIXED_PREDIV,
 238                 .hw.init        = CLK_HW_INIT_PARENTS("cpu",
 239                                                       cpu_parents,
 240                                                       &ccu_mux_ops,
 241                                                       CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
 242         }
 243 };
 244
 245 static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x054, 0, 2, 0);
 246
 247 static struct ccu_div ahb_sun4i_clk = {
 248         .div            = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
 249         .common         = {
 250                 .reg            = 0x054,
 251                 .hw.init        = CLK_HW_INIT("ahb", "axi", &ccu_div_ops, 0),
 252         },
 253 };
 254
 255 static const char *const ahb_sun7i_parents[] = { "axi", "pll-periph",
 256                                                  "pll-periph" };
 257 static const struct ccu_mux_fixed_prediv ahb_sun7i_predivs[] = {
 258         { .index = 1, .div = 2, },
 259         { /* Sentinel */ },
 260 };
 261 static struct ccu_div ahb_sun7i_clk = {
 262         .div            = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
 263         .mux            = {
 264                 .shift          = 6,
 265                 .width          = 2,
 266                 .fixed_predivs  = ahb_sun7i_predivs,
 267                 .n_predivs      = ARRAY_SIZE(ahb_sun7i_predivs),
 268         },
 269
 270         .common         = {
 271                 .reg            = 0x054,
 272                 .hw.init        = CLK_HW_INIT_PARENTS("ahb",
 273                                                       ahb_sun7i_parents,
 274                                                       &ccu_div_ops,
 275                                                       0),
 276         },
 277 };
 278
 279 static struct clk_div_table apb0_div_table[] = {
 280         { .val = 0, .div = 2 },
 281         { .val = 1, .div = 2 },
 282         { .val = 2, .div = 4 },
 283         { .val = 3, .div = 8 },
 284         { /* Sentinel */ },
 285 };
 286 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
 287                            0x054, 8, 2, apb0_div_table, 0);
 288
 289 static const char *const apb1_parents[] = { "hosc", "pll-periph", "osc32k" };
 290 static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x058,
 291                              0, 5,      /* M */
 292                              16, 2,     /* P */
 293                              24, 2,     /* mux */
 294                              0);
 295
 296 /* Not present on A20 */
 297 static SUNXI_CCU_GATE(axi_dram_clk,     "axi-dram",     "ahb",
 298                       0x05c, BIT(31), 0);
 299
 300 static SUNXI_CCU_GATE(ahb_otg_clk,      "ahb-otg",      "ahb",
 301                       0x060, BIT(0), 0);
 302 static SUNXI_CCU_GATE(ahb_ehci0_clk,    "ahb-ehci0",    "ahb",
 303                       0x060, BIT(1), 0);
 304 static SUNXI_CCU_GATE(ahb_ohci0_clk,    "ahb-ohci0",    "ahb",
 305                       0x060, BIT(2), 0);
 306 static SUNXI_CCU_GATE(ahb_ehci1_clk,    "ahb-ehci1",    "ahb",
 307                       0x060, BIT(3), 0);
 308 static SUNXI_CCU_GATE(ahb_ohci1_clk,    "ahb-ohci1",    "ahb",
 309                       0x060, BIT(4), 0);
 310 static SUNXI_CCU_GATE(ahb_ss_clk,       "ahb-ss",       "ahb",
 311                       0x060, BIT(5), 0);
 312 static SUNXI_CCU_GATE(ahb_dma_clk,      "ahb-dma",      "ahb",
 313                       0x060, BIT(6), 0);
 314 static SUNXI_CCU_GATE(ahb_bist_clk,     "ahb-bist",     "ahb",
 315                       0x060, BIT(7), 0);
 316 static SUNXI_CCU_GATE(ahb_mmc0_clk,     "ahb-mmc0",     "ahb",
 317                       0x060, BIT(8), 0);
 318 static SUNXI_CCU_GATE(ahb_mmc1_clk,     "ahb-mmc1",     "ahb",
 319                       0x060, BIT(9), 0);
 320 static SUNXI_CCU_GATE(ahb_mmc2_clk,     "ahb-mmc2",     "ahb",
 321                       0x060, BIT(10), 0);
 322 static SUNXI_CCU_GATE(ahb_mmc3_clk,     "ahb-mmc3",     "ahb",
 323                       0x060, BIT(11), 0);
 324 static SUNXI_CCU_GATE(ahb_ms_clk,       "ahb-ms",       "ahb",
 325                       0x060, BIT(12), 0);
 326 static SUNXI_CCU_GATE(ahb_nand_clk,     "ahb-nand",     "ahb",
 327                       0x060, BIT(13), 0);
 328 static SUNXI_CCU_GATE(ahb_sdram_clk,    "ahb-sdram",    "ahb",
 329                       0x060, BIT(14), CLK_IS_CRITICAL);
 330
 331 static SUNXI_CCU_GATE(ahb_ace_clk,      "ahb-ace",      "ahb",
 332                       0x060, BIT(16), 0);
 333 static SUNXI_CCU_GATE(ahb_emac_clk,     "ahb-emac",     "ahb",
 334                       0x060, BIT(17), 0);
 335 static SUNXI_CCU_GATE(ahb_ts_clk,       "ahb-ts",       "ahb",
 336                       0x060, BIT(18), 0);
 337 static SUNXI_CCU_GATE(ahb_spi0_clk,     "ahb-spi0",     "ahb",
 338                       0x060, BIT(20), 0);
 339 static SUNXI_CCU_GATE(ahb_spi1_clk,     "ahb-spi1",     "ahb",
 340                       0x060, BIT(21), 0);
 341 static SUNXI_CCU_GATE(ahb_spi2_clk,     "ahb-spi2",     "ahb",
 342                       0x060, BIT(22), 0);
 343 static SUNXI_CCU_GATE(ahb_spi3_clk,     "ahb-spi3",     "ahb",
 344                       0x060, BIT(23), 0);
 345 static SUNXI_CCU_GATE(ahb_pata_clk,     "ahb-pata",     "ahb",
 346                       0x060, BIT(24), 0);
 347 /* Not documented on A20 */
 348 static SUNXI_CCU_GATE(ahb_sata_clk,     "ahb-sata",     "ahb",
 349                       0x060, BIT(25), 0);
 350 /* Not present on A20 */
 351 static SUNXI_CCU_GATE(ahb_gps_clk,      "ahb-gps",      "ahb",
 352                       0x060, BIT(26), 0);
 353 /* Not present on A10 */
 354 static SUNXI_CCU_GATE(ahb_hstimer_clk,  "ahb-hstimer",  "ahb",
 355                       0x060, BIT(28), 0);
 356
 357 static SUNXI_CCU_GATE(ahb_ve_clk,       "ahb-ve",       "ahb",
 358                       0x064, BIT(0), 0);
 359 static SUNXI_CCU_GATE(ahb_tvd_clk,      "ahb-tvd",      "ahb",
 360                       0x064, BIT(1), 0);
 361 static SUNXI_CCU_GATE(ahb_tve0_clk,     "ahb-tve0",     "ahb",
 362                       0x064, BIT(2), 0);
 363 static SUNXI_CCU_GATE(ahb_tve1_clk,     "ahb-tve1",     "ahb",
 364                       0x064, BIT(3), 0);
 365 static SUNXI_CCU_GATE(ahb_lcd0_clk,     "ahb-lcd0",     "ahb",
 366                       0x064, BIT(4), 0);
 367 static SUNXI_CCU_GATE(ahb_lcd1_clk,     "ahb-lcd1",     "ahb",
 368                       0x064, BIT(5), 0);
 369 static SUNXI_CCU_GATE(ahb_csi0_clk,     "ahb-csi0",     "ahb",
 370                       0x064, BIT(8), 0);
 371 static SUNXI_CCU_GATE(ahb_csi1_clk,     "ahb-csi1",     "ahb",
 372                       0x064, BIT(9), 0);
 373 /* Not present on A10 */
 374 static SUNXI_CCU_GATE(ahb_hdmi1_clk,    "ahb-hdmi1",    "ahb",
 375                       0x064, BIT(10), 0);
 376 static SUNXI_CCU_GATE(ahb_hdmi0_clk,    "ahb-hdmi0",    "ahb",
 377                       0x064, BIT(11), 0);
 378 static SUNXI_CCU_GATE(ahb_de_be0_clk,   "ahb-de-be0",   "ahb",
 379                       0x064, BIT(12), 0);
 380 static SUNXI_CCU_GATE(ahb_de_be1_clk,   "ahb-de-be1",   "ahb",
 381                       0x064, BIT(13), 0);
 382 static SUNXI_CCU_GATE(ahb_de_fe0_clk,   "ahb-de-fe0",   "ahb",
 383                       0x064, BIT(14), 0);
 384 static SUNXI_CCU_GATE(ahb_de_fe1_clk,   "ahb-de-fe1",   "ahb",
 385                       0x064, BIT(15), 0);
 386 /* Not present on A10 */
 387 static SUNXI_CCU_GATE(ahb_gmac_clk,     "ahb-gmac",     "ahb",
 388                       0x064, BIT(17), 0);
 389 static SUNXI_CCU_GATE(ahb_mp_clk,       "ahb-mp",       "ahb",
 390                       0x064, BIT(18), 0);
 391 static SUNXI_CCU_GATE(ahb_gpu_clk,      "ahb-gpu",      "ahb",
 392                       0x064, BIT(20), 0);
 393
 394 static SUNXI_CCU_GATE(apb0_codec_clk,   "apb0-codec",   "apb0",
 395                       0x068, BIT(0), 0);
 396 static SUNXI_CCU_GATE(apb0_spdif_clk,   "apb0-spdif",   "apb0",
 397                       0x068, BIT(1), 0);
 398 static SUNXI_CCU_GATE(apb0_ac97_clk,    "apb0-ac97",    "apb0",
 399                       0x068, BIT(2), 0);
 400 static SUNXI_CCU_GATE(apb0_i2s0_clk,    "apb0-i2s0",    "apb0",
 401                       0x068, BIT(3), 0);
 402 /* Not present on A10 */
 403 static SUNXI_CCU_GATE(apb0_i2s1_clk,    "apb0-i2s1",    "apb0",
 404                       0x068, BIT(4), 0);
 405 static SUNXI_CCU_GATE(apb0_pio_clk,     "apb0-pio",     "apb0",
 406                       0x068, BIT(5), 0);
 407 static SUNXI_CCU_GATE(apb0_ir0_clk,     "apb0-ir0",     "apb0",
 408                       0x068, BIT(6), 0);
 409 static SUNXI_CCU_GATE(apb0_ir1_clk,     "apb0-ir1",     "apb0",
 410                       0x068, BIT(7), 0);
 411 /* Not present on A10 */
 412 static SUNXI_CCU_GATE(apb0_i2s2_clk,    "apb0-i2s2",    "apb0",
 413                       0x068, BIT(8), 0);
 414 static SUNXI_CCU_GATE(apb0_keypad_clk,  "apb0-keypad",  "apb0",
 415                       0x068, BIT(10), 0);
 416
 417 static SUNXI_CCU_GATE(apb1_i2c0_clk,    "apb1-i2c0",    "apb1",
 418                       0x06c, BIT(0), 0);
 419 static SUNXI_CCU_GATE(apb1_i2c1_clk,    "apb1-i2c1",    "apb1",
 420                       0x06c, BIT(1), 0);
 421 static SUNXI_CCU_GATE(apb1_i2c2_clk,    "apb1-i2c2",    "apb1",
 422                       0x06c, BIT(2), 0);
 423 /* Not present on A10 */
 424 static SUNXI_CCU_GATE(apb1_i2c3_clk,    "apb1-i2c3",    "apb1",
 425                       0x06c, BIT(3), 0);
 426 static SUNXI_CCU_GATE(apb1_can_clk,     "apb1-can",     "apb1",
 427                       0x06c, BIT(4), 0);
 428 static SUNXI_CCU_GATE(apb1_scr_clk,     "apb1-scr",     "apb1",
 429                       0x06c, BIT(5), 0);
 430 static SUNXI_CCU_GATE(apb1_ps20_clk,    "apb1-ps20",    "apb1",
 431                       0x06c, BIT(6), 0);
 432 static SUNXI_CCU_GATE(apb1_ps21_clk,    "apb1-ps21",    "apb1",
 433                       0x06c, BIT(7), 0);
 434 /* Not present on A10 */
 435 static SUNXI_CCU_GATE(apb1_i2c4_clk,    "apb1-i2c4",    "apb1",
 436                       0x06c, BIT(15), 0);
 437 static SUNXI_CCU_GATE(apb1_uart0_clk,   "apb1-uart0",   "apb1",
 438                       0x06c, BIT(16), 0);
 439 static SUNXI_CCU_GATE(apb1_uart1_clk,   "apb1-uart1",   "apb1",
 440                       0x06c, BIT(17), 0);
 441 static SUNXI_CCU_GATE(apb1_uart2_clk,   "apb1-uart2",   "apb1",
 442                       0x06c, BIT(18), 0);
 443 static SUNXI_CCU_GATE(apb1_uart3_clk,   "apb1-uart3",   "apb1",
 444                       0x06c, BIT(19), 0);
 445 static SUNXI_CCU_GATE(apb1_uart4_clk,   "apb1-uart4",   "apb1",
 446                       0x06c, BIT(20), 0);
 447 static SUNXI_CCU_GATE(apb1_uart5_clk,   "apb1-uart5",   "apb1",
 448                       0x06c, BIT(21), 0);
 449 static SUNXI_CCU_GATE(apb1_uart6_clk,   "apb1-uart6",   "apb1",
 450                       0x06c, BIT(22), 0);
 451 static SUNXI_CCU_GATE(apb1_uart7_clk,   "apb1-uart7",   "apb1",
 452                       0x06c, BIT(23), 0);
 453
 454 static const char *const mod0_default_parents[] = { "hosc", "pll-periph",
 455                                                      "pll-ddr-other" };
 456 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
 457                                   0, 4,         /* M */
 458                                   16, 2,        /* P */
 459                                   24, 2,        /* mux */
 460                                   BIT(31),      /* gate */
 461                                   0);
 462
 463 /* Undocumented on A10 */
 464 static SUNXI_CCU_MP_WITH_MUX_GATE(ms_clk, "ms", mod0_default_parents, 0x084,
 465                                   0, 4,         /* M */
 466                                   16, 2,        /* P */
 467                                   24, 2,        /* mux */
 468                                   BIT(31),      /* gate */
 469                                   0);
 470
 471 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
 472                                   0, 4,         /* M */
 473                                   16, 2,        /* P */
 474                                   24, 2,        /* mux */
 475                                   BIT(31),      /* gate */
 476                                   0);
 477
 478 /* MMC output and sample clocks are not present on A10 */
 479 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
 480                        0x088, 8, 3, 0);
 481 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
 482                        0x088, 20, 3, 0);
 483
 484 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
 485                                   0, 4,         /* M */
 486                                   16, 2,        /* P */
 487                                   24, 2,        /* mux */
 488                                   BIT(31),      /* gate */
 489                                   0);
 490
 491 /* MMC output and sample clocks are not present on A10 */
 492 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
 493                        0x08c, 8, 3, 0);
 494 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
 495                        0x08c, 20, 3, 0);
 496
 497 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
 498                                   0, 4,         /* M */
 499                                   16, 2,        /* P */
 500                                   24, 2,        /* mux */
 501                                   BIT(31),      /* gate */
 502                                   0);
 503
 504 /* MMC output and sample clocks are not present on A10 */
 505 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
 506                        0x090, 8, 3, 0);
 507 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
 508                        0x090, 20, 3, 0);
 509
 510 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094,
 511                                   0, 4,         /* M */
 512                                   16, 2,        /* P */
 513                                   24, 2,        /* mux */
 514                                   BIT(31),      /* gate */
 515                                   0);
 516
 517 /* MMC output and sample clocks are not present on A10 */
 518 static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3_output", "mmc3",
 519                        0x094, 8, 3, 0);
 520 static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3_sample", "mmc3",
 521                        0x094, 20, 3, 0);
 522
 523 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
 524                                   0, 4,         /* M */
 525                                   16, 2,        /* P */
 526                                   24, 2,        /* mux */
 527                                   BIT(31),      /* gate */
 528                                   0);
 529
 530 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
 531                                   0, 4,         /* M */
 532                                   16, 2,        /* P */
 533                                   24, 2,        /* mux */
 534                                   BIT(31),      /* gate */
 535                                   0);
 536
 537 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
 538                                   0, 4,         /* M */
 539                                   16, 2,        /* P */
 540                                   24, 2,        /* mux */
 541                                   BIT(31),      /* gate */
 542                                   0);
 543
 544 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
 545                                   0, 4,         /* M */
 546                                   16, 2,        /* P */
 547                                   24, 2,        /* mux */
 548                                   BIT(31),      /* gate */
 549                                   0);
 550
 551 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
 552                                   0, 4,         /* M */
 553                                   16, 2,        /* P */
 554                                   24, 2,        /* mux */
 555                                   BIT(31),      /* gate */
 556                                   0);
 557
 558 /* Undocumented on A10 */
 559 static SUNXI_CCU_MP_WITH_MUX_GATE(pata_clk, "pata", mod0_default_parents, 0x0ac,
 560                                   0, 4,         /* M */
 561                                   16, 2,        /* P */
 562                                   24, 2,        /* mux */
 563                                   BIT(31),      /* gate */
 564                                   0);
 565
 566 /* TODO: Check whether A10 actually supports osc32k as 4th parent? */
 567 static const char *const ir_parents_sun4i[] = { "hosc", "pll-periph",
 568                                                 "pll-ddr-other" };
 569 static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_sun4i_clk, "ir0", ir_parents_sun4i, 0x0b0,
 570                                   0, 4,         /* M */
 571                                   16, 2,        /* P */
 572                                   24, 2,        /* mux */
 573                                   BIT(31),      /* gate */
 574                                   0);
 575
 576 static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_sun4i_clk, "ir1", ir_parents_sun4i, 0x0b4,
 577                                   0, 4,         /* M */
 578                                   16, 2,        /* P */
 579                                   24, 2,        /* mux */
 580                                   BIT(31),      /* gate */
 581                                   0);
 582 static const char *const ir_parents_sun7i[] = { "hosc", "pll-periph",
 583                                                 "pll-ddr-other", "osc32k" };
 584 static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_sun7i_clk, "ir0", ir_parents_sun7i, 0x0b0,
 585                                   0, 4,         /* M */
 586                                   16, 2,        /* P */
 587                                   24, 2,        /* mux */
 588                                   BIT(31),      /* gate */
 589                                   0);
 590
 591 static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_sun7i_clk, "ir1", ir_parents_sun7i, 0x0b4,
 592                                   0, 4,         /* M */
 593                                   16, 2,        /* P */
 594                                   24, 2,        /* mux */
 595                                   BIT(31),      /* gate */
 596                                   0);
 597
 598 static const char *const audio_parents[] = { "pll-audio-8x", "pll-audio-4x",
 599                                               "pll-audio-2x", "pll-audio" };
 600 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", audio_parents,
 601                                0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
 602
 603 static SUNXI_CCU_MUX_WITH_GATE(ac97_clk, "ac97", audio_parents,
 604                                0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
 605
 606 /* Undocumented on A10 */
 607 static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", audio_parents,
 608                                0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
 609
 610 static const char *const keypad_parents[] = { "hosc", "losc"};
 611 static const u8 keypad_table[] = { 0, 2 };
 612 static struct ccu_mp keypad_clk = {
 613         .enable         = BIT(31),
 614         .m              = _SUNXI_CCU_DIV(0, 5),
 615         .p              = _SUNXI_CCU_DIV(16, 2),
 616         .mux            = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
 617         .common         = {
 618                 .reg            = 0x0c4,
 619                 .hw.init        = CLK_HW_INIT_PARENTS("keypad",
 620                                                       keypad_parents,
 621                                                       &ccu_mp_ops,
 622                                                       0),
 623         },
 624 };
 625
 626 /*
 627  * SATA supports external clock as parent via BIT(24) and is probably an
 628  * optional crystal or oscillator that can be connected to the
 629  * SATA-CLKM / SATA-CLKP pins.
 630  */
 631 static const char *const sata_parents[] = {"pll-periph-sata", "sata-ext"};
 632 static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents,
 633                                0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);
 634
 635
 636 static SUNXI_CCU_GATE(usb_ohci0_clk,    "usb-ohci0",    "pll-periph",
 637                       0x0cc, BIT(6), 0);
 638 static SUNXI_CCU_GATE(usb_ohci1_clk,    "usb-ohci1",    "pll-periph",
 639                       0x0cc, BIT(7), 0);
 640 static SUNXI_CCU_GATE(usb_phy_clk,      "usb-phy",      "pll-periph",
 641                       0x0cc, BIT(8), 0);
 642
 643 /* TODO: GPS CLK 0x0d0 */
 644
 645 static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0d4,
 646                                   0, 4,         /* M */
 647                                   16, 2,        /* P */
 648                                   24, 2,        /* mux */
 649                                   BIT(31),      /* gate */
 650                                   0);
 651
 652 /* Not present on A10 */
 653 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", audio_parents,
 654                                0x0d8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
 655
 656 /* Not present on A10 */
 657 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", audio_parents,
 658                                0x0dc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
 659
 660 static SUNXI_CCU_GATE(dram_ve_clk,      "dram-ve",      "pll-ddr",
 661                       0x100, BIT(0), 0);
 662 static SUNXI_CCU_GATE(dram_csi0_clk,    "dram-csi0",    "pll-ddr",
 663                       0x100, BIT(1), 0);
 664 static SUNXI_CCU_GATE(dram_csi1_clk,    "dram-csi1",    "pll-ddr",
 665                       0x100, BIT(2), 0);
 666 static SUNXI_CCU_GATE(dram_ts_clk,      "dram-ts",      "pll-ddr",
 667                       0x100, BIT(3), 0);
 668 static SUNXI_CCU_GATE(dram_tvd_clk,     "dram-tvd",     "pll-ddr",
 669                       0x100, BIT(4), 0);
 670 static SUNXI_CCU_GATE(dram_tve0_clk,    "dram-tve0",    "pll-ddr",
 671                       0x100, BIT(5), 0);
 672 static SUNXI_CCU_GATE(dram_tve1_clk,    "dram-tve1",    "pll-ddr",
 673                       0x100, BIT(6), 0);
 674
 675 /* Clock seems to be critical only on sun4i */
 676 static SUNXI_CCU_GATE(dram_out_clk,     "dram-out",     "pll-ddr",
 677                       0x100, BIT(15), CLK_IS_CRITICAL);
 678 static SUNXI_CCU_GATE(dram_de_fe1_clk,  "dram-de-fe1",  "pll-ddr",
 679                       0x100, BIT(24), 0);
 680 static SUNXI_CCU_GATE(dram_de_fe0_clk,  "dram-de-fe0",  "pll-ddr",
 681                       0x100, BIT(25), 0);
 682 static SUNXI_CCU_GATE(dram_de_be0_clk,  "dram-de-be0",  "pll-ddr",
 683                       0x100, BIT(26), 0);
 684 static SUNXI_CCU_GATE(dram_de_be1_clk,  "dram-de-be1",  "pll-ddr",
 685                       0x100, BIT(27), 0);
 686 static SUNXI_CCU_GATE(dram_mp_clk,      "dram-mp",      "pll-ddr",
 687                       0x100, BIT(28), 0);
 688 static SUNXI_CCU_GATE(dram_ace_clk,     "dram-ace",     "pll-ddr",
 689                       0x100, BIT(29), 0);
 690
 691 static const char *const de_parents[] = { "pll-video0", "pll-video1",
 692                                            "pll-ddr-other" };
 693 static SUNXI_CCU_M_WITH_MUX_GATE(de_be0_clk, "de-be0", de_parents,
 694                                  0x104, 0, 4, 24, 2, BIT(31), 0);
 695
 696 static SUNXI_CCU_M_WITH_MUX_GATE(de_be1_clk, "de-be1", de_parents,
 697                                  0x108, 0, 4, 24, 2, BIT(31), 0);
 698
 699 static SUNXI_CCU_M_WITH_MUX_GATE(de_fe0_clk, "de-fe0", de_parents,
 700                                  0x10c, 0, 4, 24, 2, BIT(31), 0);
 701
 702 static SUNXI_CCU_M_WITH_MUX_GATE(de_fe1_clk, "de-fe1", de_parents,
 703                                  0x110, 0, 4, 24, 2, BIT(31), 0);
 704
 705 /* Undocumented on A10 */
 706 static SUNXI_CCU_M_WITH_MUX_GATE(de_mp_clk, "de-mp", de_parents,
 707                                  0x114, 0, 4, 24, 2, BIT(31), 0);
 708
 709 static const char *const disp_parents[] = { "pll-video0", "pll-video1",
 710                                             "pll-video0-2x", "pll-video1-2x" };
 711 static SUNXI_CCU_MUX_WITH_GATE(tcon0_ch0_clk, "tcon0-ch0-sclk", disp_parents,
 712                                0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
 713 static SUNXI_CCU_MUX_WITH_GATE(tcon1_ch0_clk, "tcon1-ch0-sclk", disp_parents,
 714                                0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
 715
 716 static const char *const csi_sclk_parents[] = { "pll-video0", "pll-ve",
 717                                                 "pll-ddr-other", "pll-periph" };
 718
 719 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk",
 720                                  csi_sclk_parents,
 721                                  0x120, 0, 4, 24, 2, BIT(31), 0);
 722
 723 /* TVD clock setup for A10 */
 724 static const char *const tvd_parents[] = { "pll-video0", "pll-video1" };
 725 static SUNXI_CCU_MUX_WITH_GATE(tvd_sun4i_clk, "tvd", tvd_parents,
 726                                0x128, 24, 1, BIT(31), 0);
 727
 728 /* TVD clock setup for A20 */
 729 static SUNXI_CCU_MP_WITH_MUX_GATE(tvd_sclk2_sun7i_clk,
 730                                   "tvd-sclk2", tvd_parents,
 731                                   0x128,
 732                                   0, 4,         /* M */
 733                                   16, 4,        /* P */
 734                                   8, 1,         /* mux */
 735                                   BIT(15),      /* gate */
 736                                   0);
 737
 738 static SUNXI_CCU_M_WITH_GATE(tvd_sclk1_sun7i_clk, "tvd-sclk1", "tvd-sclk2",
 739                              0x128, 0, 4, BIT(31), 0);
 740
 741 static SUNXI_CCU_M_WITH_MUX_GATE(tcon0_ch1_sclk2_clk, "tcon0-ch1-sclk2",
 742                                  disp_parents,
 743                                  0x12c, 0, 4, 24, 2, BIT(31),
 744                                  CLK_SET_RATE_PARENT);
 745
 746 static SUNXI_CCU_M_WITH_GATE(tcon0_ch1_clk,
 747                              "tcon0-ch1-sclk1", "tcon0-ch1-sclk2",
 748                              0x12c, 11, 1, BIT(15),
 749                              CLK_SET_RATE_PARENT);
 750
 751 static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_ch1_sclk2_clk, "tcon1-ch1-sclk2",
 752                                  disp_parents,
 753                                  0x130, 0, 4, 24, 2, BIT(31),
 754                                  CLK_SET_RATE_PARENT);
 755
 756 static SUNXI_CCU_M_WITH_GATE(tcon1_ch1_clk,
 757                              "tcon1-ch1-sclk1", "tcon1-ch1-sclk2",
 758                              0x130, 11, 1, BIT(15),
 759                              CLK_SET_RATE_PARENT);
 760
 761 static const char *const csi_parents[] = { "hosc", "pll-video0", "pll-video1",
 762                                            "pll-video0-2x", "pll-video1-2x"};
 763 static const u8 csi_table[] = { 0, 1, 2, 5, 6};
 764 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi0_clk, "csi0",
 765                                        csi_parents, csi_table,
 766                                        0x134, 0, 5, 24, 3, BIT(31), 0);
 767
 768 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi1_clk, "csi1",
 769                                        csi_parents, csi_table,
 770                                        0x138, 0, 5, 24, 3, BIT(31), 0);
 771
 772 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c, 16, 8, BIT(31), 0);
 773
 774 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
 775                       0x140, BIT(31), CLK_SET_RATE_PARENT);
 776
 777 static SUNXI_CCU_GATE(avs_clk, "avs", "hosc", 0x144, BIT(31), 0);
 778
 779 static const char *const ace_parents[] = { "pll-ve", "pll-ddr-other" };
 780 static SUNXI_CCU_M_WITH_MUX_GATE(ace_clk, "ace", ace_parents,
 781                                  0x148, 0, 4, 24, 1, BIT(31), 0);
 782
 783 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", disp_parents,
 784                                  0x150, 0, 4, 24, 2, BIT(31),
 785                                  CLK_SET_RATE_PARENT);
 786
 787 static const char *const gpu_parents_sun4i[] = { "pll-video0", "pll-ve",
 788                                                  "pll-ddr-other",
 789                                                  "pll-video1" };
 790 static SUNXI_CCU_M_WITH_MUX_GATE(gpu_sun4i_clk, "gpu", gpu_parents_sun4i,
 791                                  0x154, 0, 4, 24, 2, BIT(31),
 792                                  CLK_SET_RATE_PARENT);
 793
 794 static const char *const gpu_parents_sun7i[] = { "pll-video0", "pll-ve",
 795                                                  "pll-ddr-other", "pll-video1",
 796                                                  "pll-gpu" };
 797 static const u8 gpu_table_sun7i[] = { 0, 1, 2, 3, 4 };
 798 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(gpu_sun7i_clk, "gpu",
 799                                        gpu_parents_sun7i, gpu_table_sun7i,
 800                                        0x154, 0, 4, 24, 3, BIT(31),
 801                                        CLK_SET_RATE_PARENT);
 802
 803 static const char *const mbus_sun4i_parents[] = { "hosc", "pll-periph",
 804                                                   "pll-ddr-other" };
 805 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_sun4i_clk, "mbus", mbus_sun4i_parents,
 806                                   0x15c, 0, 4, 16, 2, 24, 2, BIT(31),
 807                                   0);
 808 static const char *const mbus_sun7i_parents[] = { "hosc", "pll-periph-base",
 809                                                   "pll-ddr-other" };
 810 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_sun7i_clk, "mbus", mbus_sun7i_parents,
 811                                   0x15c, 0, 4, 16, 2, 24, 2, BIT(31),
 812                                   CLK_IS_CRITICAL);
 813
 814 static SUNXI_CCU_GATE(hdmi1_slow_clk, "hdmi1-slow", "hosc", 0x178, BIT(31), 0);
 815
 816 static const char *const hdmi1_parents[] = { "pll-video0", "pll-video1" };
 817 static const u8 hdmi1_table[] = { 0, 1};
 818 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(hdmi1_clk, "hdmi1",
 819                                        hdmi1_parents, hdmi1_table,
 820                                        0x17c, 0, 4, 24, 2, BIT(31),
 821                                        CLK_SET_RATE_PARENT);
 822
 823 static const char *const out_parents[] = { "hosc", "osc32k", "hosc" };
 824 static const struct ccu_mux_fixed_prediv clk_out_predivs[] = {
 825         { .index = 0, .div = 750, },
 826 };
 827
 828 static struct ccu_mp out_a_clk = {
 829         .enable         = BIT(31),
 830         .m              = _SUNXI_CCU_DIV(8, 5),
 831         .p              = _SUNXI_CCU_DIV(20, 2),
 832         .mux            = {
 833                 .shift          = 24,
 834                 .width          = 2,
 835                 .fixed_predivs  = clk_out_predivs,
 836                 .n_predivs      = ARRAY_SIZE(clk_out_predivs),
 837         },
 838         .common         = {
 839                 .reg            = 0x1f0,
 840                 .features       = CCU_FEATURE_FIXED_PREDIV,
 841                 .hw.init        = CLK_HW_INIT_PARENTS("out-a",
 842                                                       out_parents,
 843                                                       &ccu_mp_ops,
 844                                                       0),
 845         },
 846 };
 847 static struct ccu_mp out_b_clk = {
 848         .enable         = BIT(31),
 849         .m              = _SUNXI_CCU_DIV(8, 5),
 850         .p              = _SUNXI_CCU_DIV(20, 2),
 851         .mux            = {
 852                 .shift          = 24,
 853                 .width          = 2,
 854                 .fixed_predivs  = clk_out_predivs,
 855                 .n_predivs      = ARRAY_SIZE(clk_out_predivs),
 856         },
 857         .common         = {
 858                 .reg            = 0x1f4,
 859                 .features       = CCU_FEATURE_FIXED_PREDIV,
 860                 .hw.init        = CLK_HW_INIT_PARENTS("out-b",
 861                                                       out_parents,
 862                                                       &ccu_mp_ops,
 863                                                       0),
 864         },
 865 };
 866
 867 static struct ccu_common *sun4i_sun7i_ccu_clks[] = {
 868         &hosc_clk.common,
 869         &pll_core_clk.common,
 870         &pll_audio_base_clk.common,
 871         &pll_video0_clk.common,
 872         &pll_ve_sun4i_clk.common,
 873         &pll_ve_sun7i_clk.common,
 874         &pll_ddr_base_clk.common,
 875         &pll_ddr_clk.common,
 876         &pll_ddr_other_clk.common,
 877         &pll_periph_base_clk.common,
 878         &pll_periph_sata_clk.common,
 879         &pll_video1_clk.common,
 880         &pll_gpu_clk.common,
 881         &cpu_clk.common,
 882         &axi_clk.common,
 883         &axi_dram_clk.common,
 884         &ahb_sun4i_clk.common,
 885         &ahb_sun7i_clk.common,
 886         &apb0_clk.common,
 887         &apb1_clk.common,
 888         &ahb_otg_clk.common,
 889         &ahb_ehci0_clk.common,
 890         &ahb_ohci0_clk.common,
 891         &ahb_ehci1_clk.common,
 892         &ahb_ohci1_clk.common,
 893         &ahb_ss_clk.common,
 894         &ahb_dma_clk.common,
 895         &ahb_bist_clk.common,
 896         &ahb_mmc0_clk.common,
 897         &ahb_mmc1_clk.common,
 898         &ahb_mmc2_clk.common,
 899         &ahb_mmc3_clk.common,
 900         &ahb_ms_clk.common,
 901         &ahb_nand_clk.common,
 902         &ahb_sdram_clk.common,
 903         &ahb_ace_clk.common,
 904         &ahb_emac_clk.common,
 905         &ahb_ts_clk.common,
 906         &ahb_spi0_clk.common,
 907         &ahb_spi1_clk.common,
 908         &ahb_spi2_clk.common,
 909         &ahb_spi3_clk.common,
 910         &ahb_pata_clk.common,
 911         &ahb_sata_clk.common,
 912         &ahb_gps_clk.common,
 913         &ahb_hstimer_clk.common,
 914         &ahb_ve_clk.common,
 915         &ahb_tvd_clk.common,
 916         &ahb_tve0_clk.common,
 917         &ahb_tve1_clk.common,
 918         &ahb_lcd0_clk.common,
 919         &ahb_lcd1_clk.common,
 920         &ahb_csi0_clk.common,
 921         &ahb_csi1_clk.common,
 922         &ahb_hdmi1_clk.common,
 923         &ahb_hdmi0_clk.common,
 924         &ahb_de_be0_clk.common,
 925         &ahb_de_be1_clk.common,
 926         &ahb_de_fe0_clk.common,
 927         &ahb_de_fe1_clk.common,
 928         &ahb_gmac_clk.common,
 929         &ahb_mp_clk.common,
 930         &ahb_gpu_clk.common,
 931         &apb0_codec_clk.common,
 932         &apb0_spdif_clk.common,
 933         &apb0_ac97_clk.common,
 934         &apb0_i2s0_clk.common,
 935         &apb0_i2s1_clk.common,
 936         &apb0_pio_clk.common,
 937         &apb0_ir0_clk.common,
 938         &apb0_ir1_clk.common,
 939         &apb0_i2s2_clk.common,
 940         &apb0_keypad_clk.common,
 941         &apb1_i2c0_clk.common,
 942         &apb1_i2c1_clk.common,
 943         &apb1_i2c2_clk.common,
 944         &apb1_i2c3_clk.common,
 945         &apb1_can_clk.common,
 946         &apb1_scr_clk.common,
 947         &apb1_ps20_clk.common,
 948         &apb1_ps21_clk.common,
 949         &apb1_i2c4_clk.common,
 950         &apb1_uart0_clk.common,
 951         &apb1_uart1_clk.common,
 952         &apb1_uart2_clk.common,
 953         &apb1_uart3_clk.common,
 954         &apb1_uart4_clk.common,
 955         &apb1_uart5_clk.common,
 956         &apb1_uart6_clk.common,
 957         &apb1_uart7_clk.common,
 958         &nand_clk.common,
 959         &ms_clk.common,
 960         &mmc0_clk.common,
 961         &mmc0_output_clk.common,
 962         &mmc0_sample_clk.common,
 963         &mmc1_clk.common,
 964         &mmc1_output_clk.common,
 965         &mmc1_sample_clk.common,
 966         &mmc2_clk.common,
 967         &mmc2_output_clk.common,
 968         &mmc2_sample_clk.common,
 969         &mmc3_clk.common,
 970         &mmc3_output_clk.common,
 971         &mmc3_sample_clk.common,
 972         &ts_clk.common,
 973         &ss_clk.common,
 974         &spi0_clk.common,
 975         &spi1_clk.common,
 976         &spi2_clk.common,
 977         &pata_clk.common,
 978         &ir0_sun4i_clk.common,
 979         &ir1_sun4i_clk.common,
 980         &ir0_sun7i_clk.common,
 981         &ir1_sun7i_clk.common,
 982         &i2s0_clk.common,
 983         &ac97_clk.common,
 984         &spdif_clk.common,
 985         &keypad_clk.common,
 986         &sata_clk.common,
 987         &usb_ohci0_clk.common,
 988         &usb_ohci1_clk.common,
 989         &usb_phy_clk.common,
 990         &spi3_clk.common,
 991         &i2s1_clk.common,
 992         &i2s2_clk.common,
 993         &dram_ve_clk.common,
 994         &dram_csi0_clk.common,
 995         &dram_csi1_clk.common,
 996         &dram_ts_clk.common,
 997         &dram_tvd_clk.common,
 998         &dram_tve0_clk.common,
 999         &dram_tve1_clk.common,
1000         &dram_out_clk.common,
1001         &dram_de_fe1_clk.common,
1002         &dram_de_fe0_clk.common,
1003         &dram_de_be0_clk.common,
1004         &dram_de_be1_clk.common,
1005         &dram_mp_clk.common,
1006         &dram_ace_clk.common,
1007         &de_be0_clk.common,
1008         &de_be1_clk.common,
1009         &de_fe0_clk.common,
1010         &de_fe1_clk.common,
1011         &de_mp_clk.common,
1012         &tcon0_ch0_clk.common,
1013         &tcon1_ch0_clk.common,
1014         &csi_sclk_clk.common,
1015         &tvd_sun4i_clk.common,
1016         &tvd_sclk1_sun7i_clk.common,
1017         &tvd_sclk2_sun7i_clk.common,
1018         &tcon0_ch1_sclk2_clk.common,
1019         &tcon0_ch1_clk.common,
1020         &tcon1_ch1_sclk2_clk.common,
1021         &tcon1_ch1_clk.common,
1022         &csi0_clk.common,
1023         &csi1_clk.common,
1024         &ve_clk.common,
1025         &codec_clk.common,
1026         &avs_clk.common,
1027         &ace_clk.common,
1028         &hdmi_clk.common,
1029         &gpu_sun4i_clk.common,
1030         &gpu_sun7i_clk.common,
1031         &mbus_sun4i_clk.common,
1032         &mbus_sun7i_clk.common,
1033         &hdmi1_slow_clk.common,
1034         &hdmi1_clk.common,
1035         &out_a_clk.common,
1036         &out_b_clk.common
1037 };
1038
1039 /* Post-divider for pll-audio is hardcoded to 1 */
1040 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
1041                         "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
1042 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
1043                         "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
1044 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
1045                         "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
1046 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
1047                         "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
1048 static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
1049                         "pll-video0", 1, 2, CLK_SET_RATE_PARENT);
1050 static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
1051                         "pll-video1", 1, 2, CLK_SET_RATE_PARENT);
1052
1053
1054 static struct clk_hw_onecell_data sun4i_a10_hw_clks = {
1055         .hws    = {
1056                 [CLK_HOSC]              = &hosc_clk.common.hw,
1057                 [CLK_PLL_CORE]          = &pll_core_clk.common.hw,
1058                 [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
1059                 [CLK_PLL_AUDIO]         = &pll_audio_clk.hw,
1060                 [CLK_PLL_AUDIO_2X]      = &pll_audio_2x_clk.hw,
1061                 [CLK_PLL_AUDIO_4X]      = &pll_audio_4x_clk.hw,
1062                 [CLK_PLL_AUDIO_8X]      = &pll_audio_8x_clk.hw,
1063                 [CLK_PLL_VIDEO0]        = &pll_video0_clk.common.hw,
1064                 [CLK_PLL_VIDEO0_2X]     = &pll_video0_2x_clk.hw,
1065                 [CLK_PLL_VE]            = &pll_ve_sun4i_clk.common.hw,
1066                 [CLK_PLL_DDR_BASE]      = &pll_ddr_base_clk.common.hw,
1067                 [CLK_PLL_DDR]           = &pll_ddr_clk.common.hw,
1068                 [CLK_PLL_DDR_OTHER]     = &pll_ddr_other_clk.common.hw,
1069                 [CLK_PLL_PERIPH_BASE]   = &pll_periph_base_clk.common.hw,
1070                 [CLK_PLL_PERIPH]        = &pll_periph_clk.hw,
1071                 [CLK_PLL_PERIPH_SATA]   = &pll_periph_sata_clk.common.hw,
1072                 [CLK_PLL_VIDEO1]        = &pll_video1_clk.common.hw,
1073                 [CLK_PLL_VIDEO1_2X]     = &pll_video1_2x_clk.hw,
1074                 [CLK_CPU]               = &cpu_clk.common.hw,
1075                 [CLK_AXI]               = &axi_clk.common.hw,
1076                 [CLK_AXI_DRAM]          = &axi_dram_clk.common.hw,
1077                 [CLK_AHB]               = &ahb_sun4i_clk.common.hw,
1078                 [CLK_APB0]              = &apb0_clk.common.hw,
1079                 [CLK_APB1]              = &apb1_clk.common.hw,
1080                 [CLK_AHB_OTG]           = &ahb_otg_clk.common.hw,
1081                 [CLK_AHB_EHCI0]         = &ahb_ehci0_clk.common.hw,
1082                 [CLK_AHB_OHCI0]         = &ahb_ohci0_clk.common.hw,
1083                 [CLK_AHB_EHCI1]         = &ahb_ehci1_clk.common.hw,
1084                 [CLK_AHB_OHCI1]         = &ahb_ohci1_clk.common.hw,
1085                 [CLK_AHB_SS]            = &ahb_ss_clk.common.hw,
1086                 [CLK_AHB_DMA]           = &ahb_dma_clk.common.hw,
1087                 [CLK_AHB_BIST]          = &ahb_bist_clk.common.hw,
1088                 [CLK_AHB_MMC0]          = &ahb_mmc0_clk.common.hw,
1089                 [CLK_AHB_MMC1]          = &ahb_mmc1_clk.common.hw,
1090                 [CLK_AHB_MMC2]          = &ahb_mmc2_clk.common.hw,
1091                 [CLK_AHB_MMC3]          = &ahb_mmc3_clk.common.hw,
1092                 [CLK_AHB_MS]            = &ahb_ms_clk.common.hw,
1093                 [CLK_AHB_NAND]          = &ahb_nand_clk.common.hw,
1094                 [CLK_AHB_SDRAM]         = &ahb_sdram_clk.common.hw,
1095                 [CLK_AHB_ACE]           = &ahb_ace_clk.common.hw,
1096                 [CLK_AHB_EMAC]          = &ahb_emac_clk.common.hw,
1097                 [CLK_AHB_TS]            = &ahb_ts_clk.common.hw,
1098                 [CLK_AHB_SPI0]          = &ahb_spi0_clk.common.hw,
1099                 [CLK_AHB_SPI1]          = &ahb_spi1_clk.common.hw,
1100                 [CLK_AHB_SPI2]          = &ahb_spi2_clk.common.hw,
1101                 [CLK_AHB_SPI3]          = &ahb_spi3_clk.common.hw,
1102                 [CLK_AHB_PATA]          = &ahb_pata_clk.common.hw,
1103                 [CLK_AHB_SATA]          = &ahb_sata_clk.common.hw,
1104                 [CLK_AHB_GPS]           = &ahb_gps_clk.common.hw,
1105                 [CLK_AHB_VE]            = &ahb_ve_clk.common.hw,
1106                 [CLK_AHB_TVD]           = &ahb_tvd_clk.common.hw,
1107                 [CLK_AHB_TVE0]          = &ahb_tve0_clk.common.hw,
1108                 [CLK_AHB_TVE1]          = &ahb_tve1_clk.common.hw,
1109                 [CLK_AHB_LCD0]          = &ahb_lcd0_clk.common.hw,
1110                 [CLK_AHB_LCD1]          = &ahb_lcd1_clk.common.hw,
1111                 [CLK_AHB_CSI0]          = &ahb_csi0_clk.common.hw,
1112                 [CLK_AHB_CSI1]          = &ahb_csi1_clk.common.hw,
1113                 [CLK_AHB_HDMI0]         = &ahb_hdmi0_clk.common.hw,
1114                 [CLK_AHB_DE_BE0]        = &ahb_de_be0_clk.common.hw,
1115                 [CLK_AHB_DE_BE1]        = &ahb_de_be1_clk.common.hw,
1116                 [CLK_AHB_DE_FE0]        = &ahb_de_fe0_clk.common.hw,
1117                 [CLK_AHB_DE_FE1]        = &ahb_de_fe1_clk.common.hw,
1118                 [CLK_AHB_MP]            = &ahb_mp_clk.common.hw,
1119                 [CLK_AHB_GPU]           = &ahb_gpu_clk.common.hw,
1120                 [CLK_APB0_CODEC]        = &apb0_codec_clk.common.hw,
1121                 [CLK_APB0_SPDIF]        = &apb0_spdif_clk.common.hw,
1122                 [CLK_APB0_AC97]         = &apb0_ac97_clk.common.hw,
1123                 [CLK_APB0_I2S0]         = &apb0_i2s0_clk.common.hw,
1124                 [CLK_APB0_PIO]          = &apb0_pio_clk.common.hw,
1125                 [CLK_APB0_IR0]          = &apb0_ir0_clk.common.hw,
1126                 [CLK_APB0_IR1]          = &apb0_ir1_clk.common.hw,
1127                 [CLK_APB0_KEYPAD]       = &apb0_keypad_clk.common.hw,
1128                 [CLK_APB1_I2C0]         = &apb1_i2c0_clk.common.hw,
1129                 [CLK_APB1_I2C1]         = &apb1_i2c1_clk.common.hw,
1130                 [CLK_APB1_I2C2]         = &apb1_i2c2_clk.common.hw,
1131                 [CLK_APB1_CAN]          = &apb1_can_clk.common.hw,
1132                 [CLK_APB1_SCR]          = &apb1_scr_clk.common.hw,
1133                 [CLK_APB1_PS20]         = &apb1_ps20_clk.common.hw,
1134                 [CLK_APB1_PS21]         = &apb1_ps21_clk.common.hw,
1135                 [CLK_APB1_UART0]        = &apb1_uart0_clk.common.hw,
1136                 [CLK_APB1_UART1]        = &apb1_uart1_clk.common.hw,
1137                 [CLK_APB1_UART2]        = &apb1_uart2_clk.common.hw,
1138                 [CLK_APB1_UART3]        = &apb1_uart3_clk.common.hw,
1139                 [CLK_APB1_UART4]        = &apb1_uart4_clk.common.hw,
1140                 [CLK_APB1_UART5]        = &apb1_uart5_clk.common.hw,
1141                 [CLK_APB1_UART6]        = &apb1_uart6_clk.common.hw,
1142                 [CLK_APB1_UART7]        = &apb1_uart7_clk.common.hw,
1143                 [CLK_NAND]              = &nand_clk.common.hw,
1144                 [CLK_MS]                = &ms_clk.common.hw,
1145                 [CLK_MMC0]              = &mmc0_clk.common.hw,
1146                 [CLK_MMC1]              = &mmc1_clk.common.hw,
1147                 [CLK_MMC2]              = &mmc2_clk.common.hw,
1148                 [CLK_MMC3]              = &mmc3_clk.common.hw,
1149                 [CLK_TS]                = &ts_clk.common.hw,
1150                 [CLK_SS]                = &ss_clk.common.hw,
1151                 [CLK_SPI0]              = &spi0_clk.common.hw,
1152                 [CLK_SPI1]              = &spi1_clk.common.hw,
1153                 [CLK_SPI2]              = &spi2_clk.common.hw,
1154                 [CLK_PATA]              = &pata_clk.common.hw,
1155                 [CLK_IR0]               = &ir0_sun4i_clk.common.hw,
1156                 [CLK_IR1]               = &ir1_sun4i_clk.common.hw,
1157                 [CLK_I2S0]              = &i2s0_clk.common.hw,
1158                 [CLK_AC97]              = &ac97_clk.common.hw,
1159                 [CLK_SPDIF]             = &spdif_clk.common.hw,
1160                 [CLK_KEYPAD]            = &keypad_clk.common.hw,
1161                 [CLK_SATA]              = &sata_clk.common.hw,
1162                 [CLK_USB_OHCI0]         = &usb_ohci0_clk.common.hw,
1163                 [CLK_USB_OHCI1]         = &usb_ohci1_clk.common.hw,
1164                 [CLK_USB_PHY]           = &usb_phy_clk.common.hw,
1165                 /* CLK_GPS is unimplemented */
1166                 [CLK_SPI3]              = &spi3_clk.common.hw,
1167                 [CLK_DRAM_VE]           = &dram_ve_clk.common.hw,
1168                 [CLK_DRAM_CSI0]         = &dram_csi0_clk.common.hw,
1169                 [CLK_DRAM_CSI1]         = &dram_csi1_clk.common.hw,
1170                 [CLK_DRAM_TS]           = &dram_ts_clk.common.hw,
1171                 [CLK_DRAM_TVD]          = &dram_tvd_clk.common.hw,
1172                 [CLK_DRAM_TVE0]         = &dram_tve0_clk.common.hw,
1173                 [CLK_DRAM_TVE1]         = &dram_tve1_clk.common.hw,
1174                 [CLK_DRAM_OUT]          = &dram_out_clk.common.hw,
1175                 [CLK_DRAM_DE_FE1]       = &dram_de_fe1_clk.common.hw,
1176                 [CLK_DRAM_DE_FE0]       = &dram_de_fe0_clk.common.hw,
1177                 [CLK_DRAM_DE_BE0]       = &dram_de_be0_clk.common.hw,
1178                 [CLK_DRAM_DE_BE1]       = &dram_de_be1_clk.common.hw,
1179                 [CLK_DRAM_MP]           = &dram_mp_clk.common.hw,
1180                 [CLK_DRAM_ACE]          = &dram_ace_clk.common.hw,
1181                 [CLK_DE_BE0]            = &de_be0_clk.common.hw,
1182                 [CLK_DE_BE1]            = &de_be1_clk.common.hw,
1183                 [CLK_DE_FE0]            = &de_fe0_clk.common.hw,
1184                 [CLK_DE_FE1]            = &de_fe1_clk.common.hw,
1185                 [CLK_DE_MP]             = &de_mp_clk.common.hw,
1186                 [CLK_TCON0_CH0]         = &tcon0_ch0_clk.common.hw,
1187                 [CLK_TCON1_CH0]         = &tcon1_ch0_clk.common.hw,
1188                 [CLK_CSI_SCLK]          = &csi_sclk_clk.common.hw,
1189                 [CLK_TVD]               = &tvd_sun4i_clk.common.hw,
1190                 [CLK_TCON0_CH1_SCLK2]   = &tcon0_ch1_sclk2_clk.common.hw,
1191                 [CLK_TCON0_CH1]         = &tcon0_ch1_clk.common.hw,
1192                 [CLK_TCON1_CH1_SCLK2]   = &tcon1_ch1_sclk2_clk.common.hw,
1193                 [CLK_TCON1_CH1]         = &tcon1_ch1_clk.common.hw,
1194                 [CLK_CSI0]              = &csi0_clk.common.hw,
1195                 [CLK_CSI1]              = &csi1_clk.common.hw,
1196                 [CLK_VE]                = &ve_clk.common.hw,
1197                 [CLK_CODEC]             = &codec_clk.common.hw,
1198                 [CLK_AVS]               = &avs_clk.common.hw,
1199                 [CLK_ACE]               = &ace_clk.common.hw,
1200                 [CLK_HDMI]              = &hdmi_clk.common.hw,
1201                 [CLK_GPU]               = &gpu_sun7i_clk.common.hw,
1202                 [CLK_MBUS]              = &mbus_sun4i_clk.common.hw,
1203         },
1204         .num    = CLK_NUMBER_SUN4I,
1205 };
1206 static struct clk_hw_onecell_data sun7i_a20_hw_clks = {
1207         .hws    = {
1208                 [CLK_HOSC]              = &hosc_clk.common.hw,
1209                 [CLK_PLL_CORE]          = &pll_core_clk.common.hw,
1210                 [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
1211                 [CLK_PLL_AUDIO]         = &pll_audio_clk.hw,
1212                 [CLK_PLL_AUDIO_2X]      = &pll_audio_2x_clk.hw,
1213                 [CLK_PLL_AUDIO_4X]      = &pll_audio_4x_clk.hw,
1214                 [CLK_PLL_AUDIO_8X]      = &pll_audio_8x_clk.hw,
1215                 [CLK_PLL_VIDEO0]        = &pll_video0_clk.common.hw,
1216                 [CLK_PLL_VIDEO0_2X]     = &pll_video0_2x_clk.hw,
1217                 [CLK_PLL_VE]            = &pll_ve_sun7i_clk.common.hw,
1218                 [CLK_PLL_DDR_BASE]      = &pll_ddr_base_clk.common.hw,
1219                 [CLK_PLL_DDR]           = &pll_ddr_clk.common.hw,
1220                 [CLK_PLL_DDR_OTHER]     = &pll_ddr_other_clk.common.hw,
1221                 [CLK_PLL_PERIPH_BASE]   = &pll_periph_base_clk.common.hw,
1222                 [CLK_PLL_PERIPH]        = &pll_periph_clk.hw,
1223                 [CLK_PLL_PERIPH_SATA]   = &pll_periph_sata_clk.common.hw,
1224                 [CLK_PLL_VIDEO1]        = &pll_video1_clk.common.hw,
1225                 [CLK_PLL_VIDEO1_2X]     = &pll_video1_2x_clk.hw,
1226                 [CLK_PLL_GPU]           = &pll_gpu_clk.common.hw,
1227                 [CLK_CPU]               = &cpu_clk.common.hw,
1228                 [CLK_AXI]               = &axi_clk.common.hw,
1229                 [CLK_AHB]               = &ahb_sun7i_clk.common.hw,
1230                 [CLK_APB0]              = &apb0_clk.common.hw,
1231                 [CLK_APB1]              = &apb1_clk.common.hw,
1232                 [CLK_AHB_OTG]           = &ahb_otg_clk.common.hw,
1233                 [CLK_AHB_EHCI0]         = &ahb_ehci0_clk.common.hw,
1234                 [CLK_AHB_OHCI0]         = &ahb_ohci0_clk.common.hw,
1235                 [CLK_AHB_EHCI1]         = &ahb_ehci1_clk.common.hw,
1236                 [CLK_AHB_OHCI1]         = &ahb_ohci1_clk.common.hw,
1237                 [CLK_AHB_SS]            = &ahb_ss_clk.common.hw,
1238                 [CLK_AHB_DMA]           = &ahb_dma_clk.common.hw,
1239                 [CLK_AHB_BIST]          = &ahb_bist_clk.common.hw,
1240                 [CLK_AHB_MMC0]          = &ahb_mmc0_clk.common.hw,
1241                 [CLK_AHB_MMC1]          = &ahb_mmc1_clk.common.hw,
1242                 [CLK_AHB_MMC2]          = &ahb_mmc2_clk.common.hw,
1243                 [CLK_AHB_MMC3]          = &ahb_mmc3_clk.common.hw,
1244                 [CLK_AHB_MS]            = &ahb_ms_clk.common.hw,
1245                 [CLK_AHB_NAND]          = &ahb_nand_clk.common.hw,
1246                 [CLK_AHB_SDRAM]         = &ahb_sdram_clk.common.hw,
1247                 [CLK_AHB_ACE]           = &ahb_ace_clk.common.hw,
1248                 [CLK_AHB_EMAC]          = &ahb_emac_clk.common.hw,
1249                 [CLK_AHB_TS]            = &ahb_ts_clk.common.hw,
1250                 [CLK_AHB_SPI0]          = &ahb_spi0_clk.common.hw,
1251                 [CLK_AHB_SPI1]          = &ahb_spi1_clk.common.hw,
1252                 [CLK_AHB_SPI2]          = &ahb_spi2_clk.common.hw,
1253                 [CLK_AHB_SPI3]          = &ahb_spi3_clk.common.hw,
1254                 [CLK_AHB_PATA]          = &ahb_pata_clk.common.hw,
1255                 [CLK_AHB_SATA]          = &ahb_sata_clk.common.hw,
1256                 [CLK_AHB_HSTIMER]       = &ahb_hstimer_clk.common.hw,
1257                 [CLK_AHB_VE]            = &ahb_ve_clk.common.hw,
1258                 [CLK_AHB_TVD]           = &ahb_tvd_clk.common.hw,
1259                 [CLK_AHB_TVE0]          = &ahb_tve0_clk.common.hw,
1260                 [CLK_AHB_TVE1]          = &ahb_tve1_clk.common.hw,
1261                 [CLK_AHB_LCD0]          = &ahb_lcd0_clk.common.hw,
1262                 [CLK_AHB_LCD1]          = &ahb_lcd1_clk.common.hw,
1263                 [CLK_AHB_CSI0]          = &ahb_csi0_clk.common.hw,
1264                 [CLK_AHB_CSI1]          = &ahb_csi1_clk.common.hw,
1265                 [CLK_AHB_HDMI1]         = &ahb_hdmi1_clk.common.hw,
1266                 [CLK_AHB_HDMI0]         = &ahb_hdmi0_clk.common.hw,
1267                 [CLK_AHB_DE_BE0]        = &ahb_de_be0_clk.common.hw,
1268                 [CLK_AHB_DE_BE1]        = &ahb_de_be1_clk.common.hw,
1269                 [CLK_AHB_DE_FE0]        = &ahb_de_fe0_clk.common.hw,
1270                 [CLK_AHB_DE_FE1]        = &ahb_de_fe1_clk.common.hw,
1271                 [CLK_AHB_GMAC]          = &ahb_gmac_clk.common.hw,
1272                 [CLK_AHB_MP]            = &ahb_mp_clk.common.hw,
1273                 [CLK_AHB_GPU]           = &ahb_gpu_clk.common.hw,
1274                 [CLK_APB0_CODEC]        = &apb0_codec_clk.common.hw,
1275                 [CLK_APB0_SPDIF]        = &apb0_spdif_clk.common.hw,
1276                 [CLK_APB0_AC97]         = &apb0_ac97_clk.common.hw,
1277                 [CLK_APB0_I2S0]         = &apb0_i2s0_clk.common.hw,
1278                 [CLK_APB0_I2S1]         = &apb0_i2s1_clk.common.hw,
1279                 [CLK_APB0_PIO]          = &apb0_pio_clk.common.hw,
1280                 [CLK_APB0_IR0]          = &apb0_ir0_clk.common.hw,
1281                 [CLK_APB0_IR1]          = &apb0_ir1_clk.common.hw,
1282                 [CLK_APB0_I2S2]         = &apb0_i2s2_clk.common.hw,
1283                 [CLK_APB0_KEYPAD]       = &apb0_keypad_clk.common.hw,
1284                 [CLK_APB1_I2C0]         = &apb1_i2c0_clk.common.hw,
1285                 [CLK_APB1_I2C1]         = &apb1_i2c1_clk.common.hw,
1286                 [CLK_APB1_I2C2]         = &apb1_i2c2_clk.common.hw,
1287                 [CLK_APB1_I2C3]         = &apb1_i2c3_clk.common.hw,
1288                 [CLK_APB1_CAN]          = &apb1_can_clk.common.hw,
1289                 [CLK_APB1_SCR]          = &apb1_scr_clk.common.hw,
1290                 [CLK_APB1_PS20]         = &apb1_ps20_clk.common.hw,
1291                 [CLK_APB1_PS21]         = &apb1_ps21_clk.common.hw,
1292                 [CLK_APB1_I2C4]         = &apb1_i2c4_clk.common.hw,
1293                 [CLK_APB1_UART0]        = &apb1_uart0_clk.common.hw,
1294                 [CLK_APB1_UART1]        = &apb1_uart1_clk.common.hw,
1295                 [CLK_APB1_UART2]        = &apb1_uart2_clk.common.hw,
1296                 [CLK_APB1_UART3]        = &apb1_uart3_clk.common.hw,
1297                 [CLK_APB1_UART4]        = &apb1_uart4_clk.common.hw,
1298                 [CLK_APB1_UART5]        = &apb1_uart5_clk.common.hw,
1299                 [CLK_APB1_UART6]        = &apb1_uart6_clk.common.hw,
1300                 [CLK_APB1_UART7]        = &apb1_uart7_clk.common.hw,
1301                 [CLK_NAND]              = &nand_clk.common.hw,
1302                 [CLK_MS]                = &ms_clk.common.hw,
1303                 [CLK_MMC0]              = &mmc0_clk.common.hw,
1304                 [CLK_MMC0_OUTPUT]       = &mmc0_output_clk.common.hw,
1305                 [CLK_MMC0_SAMPLE]       = &mmc0_sample_clk.common.hw,
1306                 [CLK_MMC1]              = &mmc1_clk.common.hw,
1307                 [CLK_MMC1_OUTPUT]       = &mmc1_output_clk.common.hw,
1308                 [CLK_MMC1_SAMPLE]       = &mmc1_sample_clk.common.hw,
1309                 [CLK_MMC2]              = &mmc2_clk.common.hw,
1310                 [CLK_MMC2_OUTPUT]       = &mmc2_output_clk.common.hw,
1311                 [CLK_MMC2_SAMPLE]       = &mmc2_sample_clk.common.hw,
1312                 [CLK_MMC3]              = &mmc3_clk.common.hw,
1313                 [CLK_MMC3_OUTPUT]       = &mmc3_output_clk.common.hw,
1314                 [CLK_MMC3_SAMPLE]       = &mmc3_sample_clk.common.hw,
1315                 [CLK_TS]                = &ts_clk.common.hw,
1316                 [CLK_SS]                = &ss_clk.common.hw,
1317                 [CLK_SPI0]              = &spi0_clk.common.hw,
1318                 [CLK_SPI1]              = &spi1_clk.common.hw,
1319                 [CLK_SPI2]              = &spi2_clk.common.hw,
1320                 [CLK_PATA]              = &pata_clk.common.hw,
1321                 [CLK_IR0]               = &ir0_sun7i_clk.common.hw,
1322                 [CLK_IR1]               = &ir1_sun7i_clk.common.hw,
1323                 [CLK_I2S0]              = &i2s0_clk.common.hw,
1324                 [CLK_AC97]              = &ac97_clk.common.hw,
1325                 [CLK_SPDIF]             = &spdif_clk.common.hw,
1326                 [CLK_KEYPAD]            = &keypad_clk.common.hw,
1327                 [CLK_SATA]              = &sata_clk.common.hw,
1328                 [CLK_USB_OHCI0]         = &usb_ohci0_clk.common.hw,
1329                 [CLK_USB_OHCI1]         = &usb_ohci1_clk.common.hw,
1330                 [CLK_USB_PHY]           = &usb_phy_clk.common.hw,
1331                 /* CLK_GPS is unimplemented */
1332                 [CLK_SPI3]              = &spi3_clk.common.hw,
1333                 [CLK_I2S1]              = &i2s1_clk.common.hw,
1334                 [CLK_I2S2]              = &i2s2_clk.common.hw,
1335                 [CLK_DRAM_VE]           = &dram_ve_clk.common.hw,
1336                 [CLK_DRAM_CSI0]         = &dram_csi0_clk.common.hw,
1337                 [CLK_DRAM_CSI1]         = &dram_csi1_clk.common.hw,
1338                 [CLK_DRAM_TS]           = &dram_ts_clk.common.hw,
1339                 [CLK_DRAM_TVD]          = &dram_tvd_clk.common.hw,
1340                 [CLK_DRAM_TVE0]         = &dram_tve0_clk.common.hw,
1341                 [CLK_DRAM_TVE1]         = &dram_tve1_clk.common.hw,
1342                 [CLK_DRAM_OUT]          = &dram_out_clk.common.hw,
1343                 [CLK_DRAM_DE_FE1]       = &dram_de_fe1_clk.common.hw,
1344                 [CLK_DRAM_DE_FE0]       = &dram_de_fe0_clk.common.hw,
1345                 [CLK_DRAM_DE_BE0]       = &dram_de_be0_clk.common.hw,
1346                 [CLK_DRAM_DE_BE1]       = &dram_de_be1_clk.common.hw,
1347                 [CLK_DRAM_MP]           = &dram_mp_clk.common.hw,
1348                 [CLK_DRAM_ACE]          = &dram_ace_clk.common.hw,
1349                 [CLK_DE_BE0]            = &de_be0_clk.common.hw,
1350                 [CLK_DE_BE1]            = &de_be1_clk.common.hw,
1351                 [CLK_DE_FE0]            = &de_fe0_clk.common.hw,
1352                 [CLK_DE_FE1]            = &de_fe1_clk.common.hw,
1353                 [CLK_DE_MP]             = &de_mp_clk.common.hw,
1354                 [CLK_TCON0_CH0]         = &tcon0_ch0_clk.common.hw,
1355                 [CLK_TCON1_CH0]         = &tcon1_ch0_clk.common.hw,
1356                 [CLK_CSI_SCLK]          = &csi_sclk_clk.common.hw,
1357                 [CLK_TVD_SCLK2]         = &tvd_sclk2_sun7i_clk.common.hw,
1358                 [CLK_TVD]               = &tvd_sclk1_sun7i_clk.common.hw,
1359                 [CLK_TCON0_CH1_SCLK2]   = &tcon0_ch1_sclk2_clk.common.hw,
1360                 [CLK_TCON0_CH1]         = &tcon0_ch1_clk.common.hw,
1361                 [CLK_TCON1_CH1_SCLK2]   = &tcon1_ch1_sclk2_clk.common.hw,
1362                 [CLK_TCON1_CH1]         = &tcon1_ch1_clk.common.hw,
1363                 [CLK_CSI0]              = &csi0_clk.common.hw,
1364                 [CLK_CSI1]              = &csi1_clk.common.hw,
1365                 [CLK_VE]                = &ve_clk.common.hw,
1366                 [CLK_CODEC]             = &codec_clk.common.hw,
1367                 [CLK_AVS]               = &avs_clk.common.hw,
1368                 [CLK_ACE]               = &ace_clk.common.hw,
1369                 [CLK_HDMI]              = &hdmi_clk.common.hw,
1370                 [CLK_GPU]               = &gpu_sun7i_clk.common.hw,
1371                 [CLK_MBUS]              = &mbus_sun7i_clk.common.hw,
1372                 [CLK_HDMI1_SLOW]        = &hdmi1_slow_clk.common.hw,
1373                 [CLK_HDMI1]             = &hdmi1_clk.common.hw,
1374                 [CLK_OUT_A]             = &out_a_clk.common.hw,
1375                 [CLK_OUT_B]             = &out_b_clk.common.hw,
1376         },
1377         .num    = CLK_NUMBER_SUN7I,
1378 };
1379
1380 static struct ccu_reset_map sunxi_a10_a20_ccu_resets[] = {
1381         [RST_USB_PHY0]          = { 0x0cc, BIT(0) },
1382         [RST_USB_PHY1]          = { 0x0cc, BIT(1) },
1383         [RST_USB_PHY2]          = { 0x0cc, BIT(2) },
1384         [RST_GPS]               = { 0x0d0, BIT(0) },
1385         [RST_DE_BE0]            = { 0x104, BIT(30) },
1386         [RST_DE_BE1]            = { 0x108, BIT(30) },
1387         [RST_DE_FE0]            = { 0x10c, BIT(30) },
1388         [RST_DE_FE1]            = { 0x110, BIT(30) },
1389         [RST_DE_MP]             = { 0x114, BIT(30) },
1390         [RST_TVE0]              = { 0x118, BIT(29) },
1391         [RST_TCON0]             = { 0x118, BIT(30) },
1392         [RST_TVE1]              = { 0x11c, BIT(29) },
1393         [RST_TCON1]             = { 0x11c, BIT(30) },
1394         [RST_CSI0]              = { 0x134, BIT(30) },
1395         [RST_CSI1]              = { 0x138, BIT(30) },
1396         [RST_VE]                = { 0x13c, BIT(0) },
1397         [RST_ACE]               = { 0x148, BIT(16) },
1398         [RST_LVDS]              = { 0x14c, BIT(0) },
1399         [RST_GPU]               = { 0x154, BIT(30) },
1400         [RST_HDMI_H]            = { 0x170, BIT(0) },
1401         [RST_HDMI_SYS]          = { 0x170, BIT(1) },
1402         [RST_HDMI_AUDIO_DMA]    = { 0x170, BIT(2) },
1403 };
1404
1405 static const struct sunxi_ccu_desc sun4i_a10_ccu_desc = {
1406         .ccu_clks       = sun4i_sun7i_ccu_clks,
1407         .num_ccu_clks   = ARRAY_SIZE(sun4i_sun7i_ccu_clks),
1408
1409         .hw_clks        = &sun4i_a10_hw_clks,
1410
1411         .resets         = sunxi_a10_a20_ccu_resets,
1412         .num_resets     = ARRAY_SIZE(sunxi_a10_a20_ccu_resets),
1413 };
1414
1415 static const struct sunxi_ccu_desc sun7i_a20_ccu_desc = {
1416         .ccu_clks       = sun4i_sun7i_ccu_clks,
1417         .num_ccu_clks   = ARRAY_SIZE(sun4i_sun7i_ccu_clks),
1418
1419         .hw_clks        = &sun7i_a20_hw_clks,
1420
1421         .resets         = sunxi_a10_a20_ccu_resets,
1422         .num_resets     = ARRAY_SIZE(sunxi_a10_a20_ccu_resets),
1423 };
1424
1425 static void __init sun4i_ccu_init(struct device_node *node,
1426                                   const struct sunxi_ccu_desc *desc)
1427 {
1428         void __iomem *reg;
1429         u32 val;
1430
1431         reg = of_io_request_and_map(node, 0, of_node_full_name(node));
1432         if (IS_ERR(reg)) {
1433                 pr_err("%s: Could not map the clock registers\n",
1434                        of_node_full_name(node));
1435                 return;
1436         }
1437
1438         val = readl(reg + SUN4I_PLL_AUDIO_REG);
1439
1440         /*
1441          * Force VCO and PLL bias current to lowest setting. Higher
1442          * settings interfere with sigma-delta modulation and result
1443          * in audible noise and distortions when using SPDIF or I2S.
1444          */
1445         val &= ~GENMASK(25, 16);
1446
1447         /* Force the PLL-Audio-1x divider to 1 */
1448         val &= ~GENMASK(29, 26);
1449         writel(val | (1 << 26), reg + SUN4I_PLL_AUDIO_REG);
1450
1451         /*
1452          * Use the peripheral PLL6 as the AHB parent, instead of CPU /
1453          * AXI which have rate changes due to cpufreq.
1454          *
1455          * This is especially a big deal for the HS timer whose parent
1456          * clock is AHB.
1457          *
1458          * NB! These bits are undocumented in A10 manual.
1459          */
1460         val = readl(reg + SUN4I_AHB_REG);
1461         val &= ~GENMASK(7, 6);
1462         writel(val | (2 << 6), reg + SUN4I_AHB_REG);
1463
1464         sunxi_ccu_probe(node, reg, desc);
1465 }
1466
1467 static void __init sun4i_a10_ccu_setup(struct device_node *node)
1468 {
1469         sun4i_ccu_init(node, &sun4i_a10_ccu_desc);
1470 }
1471 CLK_OF_DECLARE(sun4i_a10_ccu, "allwinner,sun4i-a10-ccu",
1472                sun4i_a10_ccu_setup);
1473
1474 static void __init sun7i_a20_ccu_setup(struct device_node *node)
1475 {
1476         sun4i_ccu_init(node, &sun7i_a20_ccu_desc);
1477 }
1478 CLK_OF_DECLARE(sun7i_a20_ccu, "allwinner,sun7i-a20-ccu",
1479                sun7i_a20_ccu_setup);