1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017, Intel Corporation
6 #ifndef __STRATIX10_CLK_H
7 #define __STRATIX10_CLK_H
9 struct stratix10_clock_data {
10 struct clk_onecell_data clk_data;
14 struct stratix10_pll_clock {
17 const struct clk_parent_data *parent_data;
23 struct stratix10_perip_c_clock {
26 const char *parent_name;
27 const struct clk_parent_data *parent_data;
33 struct n5x_perip_c_clock {
36 const char *parent_name;
37 const char *const *parent_names;
44 struct stratix10_perip_cnt_clock {
47 const char *parent_name;
48 const struct clk_parent_data *parent_data;
53 unsigned long bypass_reg;
54 unsigned long bypass_shift;
57 struct stratix10_gate_clock {
60 const char *parent_name;
61 const struct clk_parent_data *parent_data;
64 unsigned long gate_reg;
66 unsigned long div_reg;
69 unsigned long bypass_reg;
74 struct clk *s10_register_pll(const struct stratix10_pll_clock *,
76 struct clk *agilex_register_pll(const struct stratix10_pll_clock *,
78 struct clk *n5x_register_pll(const struct stratix10_pll_clock *clks,
80 struct clk *s10_register_periph(const struct stratix10_perip_c_clock *,
82 struct clk *n5x_register_periph(const struct n5x_perip_c_clock *clks,
84 struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *,
86 struct clk *s10_register_gate(const struct stratix10_gate_clock *,
88 #endif /* __STRATIX10_CLK_H */