1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017, Intel Corporation
6 #ifndef __STRATIX10_CLK_H
7 #define __STRATIX10_CLK_H
9 struct stratix10_clock_data {
10 struct clk_onecell_data clk_data;
14 struct stratix10_pll_clock {
17 const struct clk_parent_data *parent_data;
23 struct stratix10_perip_c_clock {
26 const char *parent_name;
27 const struct clk_parent_data *parent_data;
33 struct stratix10_perip_cnt_clock {
36 const char *parent_name;
37 const struct clk_parent_data *parent_data;
42 unsigned long bypass_reg;
43 unsigned long bypass_shift;
46 struct stratix10_gate_clock {
49 const char *parent_name;
50 const struct clk_parent_data *parent_data;
53 unsigned long gate_reg;
55 unsigned long div_reg;
58 unsigned long bypass_reg;
63 struct clk *s10_register_pll(const struct stratix10_pll_clock *,
65 struct clk *agilex_register_pll(const struct stratix10_pll_clock *,
67 struct clk *s10_register_periph(const struct stratix10_perip_c_clock *,
69 struct clk *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *,
71 struct clk *s10_register_gate(const struct stratix10_gate_clock *,
73 #endif /* __STRATIX10_CLK_H */