2 * Copyright 2011-2012 Calxeda, Inc.
3 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * Based from clk-highbank.c
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/clk.h>
21 #include <linux/clkdev.h>
22 #include <linux/clk-provider.h>
26 /* Clock Manager offsets */
27 #define CLKMGR_CTRL 0x0
28 #define CLKMGR_BYPASS 0x4
29 #define CLKMGR_L4SRC 0x70
30 #define CLKMGR_PERPLL_SRC 0xAC
32 /* Clock bypass bits */
33 #define MAINPLL_BYPASS (1<<0)
34 #define SDRAMPLL_BYPASS (1<<1)
35 #define SDRAMPLL_SRC_BYPASS (1<<2)
36 #define PERPLL_BYPASS (1<<3)
37 #define PERPLL_SRC_BYPASS (1<<4)
39 #define SOCFPGA_PLL_BG_PWRDWN 0
40 #define SOCFPGA_PLL_EXT_ENA 1
41 #define SOCFPGA_PLL_PWR_DOWN 2
42 #define SOCFPGA_PLL_DIVF_MASK 0x0000FFF8
43 #define SOCFPGA_PLL_DIVF_SHIFT 3
44 #define SOCFPGA_PLL_DIVQ_MASK 0x003F0000
45 #define SOCFPGA_PLL_DIVQ_SHIFT 16
46 #define SOCFGPA_MAX_PARENTS 3
48 #define SOCFPGA_L4_MP_CLK "l4_mp_clk"
49 #define SOCFPGA_L4_SP_CLK "l4_sp_clk"
50 #define SOCFPGA_NAND_CLK "nand_clk"
51 #define SOCFPGA_NAND_X_CLK "nand_x_clk"
52 #define SOCFPGA_MMC_CLK "sdmmc_clk"
53 #define SOCFPGA_DB_CLK "gpio_db_clk"
55 #define div_mask(width) ((1 << (width)) - 1)
56 #define streq(a, b) (strcmp((a), (b)) == 0)
58 extern void __iomem *clk_mgr_base_addr;
65 void __iomem *div_reg;
66 u32 width; /* only valid if div_reg != 0 */
67 u32 shift; /* only valid if div_reg != 0 */
69 #define to_socfpga_clk(p) container_of(p, struct socfpga_clk, hw.hw)
71 static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
72 unsigned long parent_rate)
74 struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
75 unsigned long divf, divq, vco_freq, reg;
78 reg = readl(socfpgaclk->hw.reg);
79 bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS);
80 if (bypass & MAINPLL_BYPASS)
83 divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
84 divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
85 vco_freq = parent_rate * (divf + 1);
86 return vco_freq / (1 + divq);
90 static struct clk_ops clk_pll_ops = {
91 .recalc_rate = clk_pll_recalc_rate,
94 static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
95 unsigned long parent_rate)
97 struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
100 if (socfpgaclk->fixed_div)
101 div = socfpgaclk->fixed_div;
103 div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);
105 return parent_rate / div;
108 static const struct clk_ops periclk_ops = {
109 .recalc_rate = clk_periclk_recalc_rate,
112 static __init struct clk *socfpga_clk_init(struct device_node *node,
113 const struct clk_ops *ops)
117 struct socfpga_clk *socfpga_clk;
118 const char *clk_name = node->name;
119 const char *parent_name;
120 struct clk_init_data init;
124 of_property_read_u32(node, "reg", ®);
126 socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
127 if (WARN_ON(!socfpga_clk))
130 socfpga_clk->hw.reg = clk_mgr_base_addr + reg;
132 rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
134 socfpga_clk->fixed_div = 0;
136 socfpga_clk->fixed_div = fixed_div;
138 of_property_read_string(node, "clock-output-names", &clk_name);
140 init.name = clk_name;
143 parent_name = of_clk_get_parent_name(node, 0);
144 init.parent_names = &parent_name;
145 init.num_parents = 1;
147 socfpga_clk->hw.hw.init = &init;
149 if (streq(clk_name, "main_pll") ||
150 streq(clk_name, "periph_pll") ||
151 streq(clk_name, "sdram_pll")) {
152 socfpga_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
153 clk_pll_ops.enable = clk_gate_ops.enable;
154 clk_pll_ops.disable = clk_gate_ops.disable;
157 clk = clk_register(NULL, &socfpga_clk->hw.hw);
158 if (WARN_ON(IS_ERR(clk))) {
162 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
166 static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
171 if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
172 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
173 return l4_src &= 0x1;
175 if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
176 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
177 return !!(l4_src & 2);
180 perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
181 if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
182 return perpll_src &= 0x3;
183 if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
184 streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
185 return (perpll_src >> 2) & 3;
188 return (perpll_src >> 4) & 3;
192 static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
196 if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
197 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
200 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
201 } else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
202 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
204 src_reg |= (parent << 1);
205 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
207 src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
208 if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {
211 } else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
212 streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {
214 src_reg |= (parent << 2);
215 } else {/* QSPI clock */
217 src_reg |= (parent << 4);
219 writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
225 static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
226 unsigned long parent_rate)
228 struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
231 if (socfpgaclk->fixed_div)
232 div = socfpgaclk->fixed_div;
233 else if (socfpgaclk->div_reg) {
234 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
235 val &= div_mask(socfpgaclk->width);
236 if (streq(hwclk->init->name, SOCFPGA_DB_CLK))
242 return parent_rate / div;
245 static struct clk_ops gateclk_ops = {
246 .recalc_rate = socfpga_clk_recalc_rate,
247 .get_parent = socfpga_clk_get_parent,
248 .set_parent = socfpga_clk_set_parent,
251 static void __init socfpga_gate_clk_init(struct device_node *node,
252 const struct clk_ops *ops)
258 struct socfpga_clk *socfpga_clk;
259 const char *clk_name = node->name;
260 const char *parent_name[SOCFGPA_MAX_PARENTS];
261 struct clk_init_data init;
265 socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
266 if (WARN_ON(!socfpga_clk))
269 rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
274 socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
275 socfpga_clk->hw.bit_idx = clk_gate[1];
277 gateclk_ops.enable = clk_gate_ops.enable;
278 gateclk_ops.disable = clk_gate_ops.disable;
281 rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
283 socfpga_clk->fixed_div = 0;
285 socfpga_clk->fixed_div = fixed_div;
287 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
289 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
290 socfpga_clk->shift = div_reg[1];
291 socfpga_clk->width = div_reg[2];
293 socfpga_clk->div_reg = NULL;
296 of_property_read_string(node, "clock-output-names", &clk_name);
298 init.name = clk_name;
301 while (i < SOCFGPA_MAX_PARENTS && (parent_name[i] =
302 of_clk_get_parent_name(node, i)) != NULL)
305 init.parent_names = parent_name;
306 init.num_parents = i;
307 socfpga_clk->hw.hw.init = &init;
309 clk = clk_register(NULL, &socfpga_clk->hw.hw);
310 if (WARN_ON(IS_ERR(clk))) {
314 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
319 static void __init socfpga_pll_init(struct device_node *node)
321 socfpga_clk_init(node, &clk_pll_ops);
323 CLK_OF_DECLARE(socfpga_pll, "altr,socfpga-pll-clock", socfpga_pll_init);
325 static void __init socfpga_periph_init(struct device_node *node)
327 socfpga_clk_init(node, &periclk_ops);
329 CLK_OF_DECLARE(socfpga_periph, "altr,socfpga-perip-clk", socfpga_periph_init);
331 static void __init socfpga_gate_init(struct device_node *node)
333 socfpga_gate_clk_init(node, &gateclk_ops);
335 CLK_OF_DECLARE(socfpga_gate, "altr,socfpga-gate-clk", socfpga_gate_init);
337 void __init socfpga_init_clocks(void)
342 clk = clk_register_fixed_factor(NULL, "smp_twd", "mpuclk", 0, 1, 4);
343 ret = clk_register_clkdev(clk, NULL, "smp_twd");
345 pr_err("smp_twd alias not registered\n");