drivers/clk/sifive/fu740-prci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2020 SiFive, Inc.
   4  * Copyright (C) 2020 Zong Li
   5  */
   6
   7 #include <linux/module.h>
   8
   9 #include <dt-bindings/clock/sifive-fu740-prci.h>
  10
  11 #include "fu540-prci.h"
  12 #include "sifive-prci.h"
  13
  14 /* PRCI integration data for each WRPLL instance */
  15
  16 static struct __prci_wrpll_data __prci_corepll_data = {
  17         .cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
  18         .cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
  19         .enable_bypass = sifive_prci_coreclksel_use_hfclk,
  20         .disable_bypass = sifive_prci_coreclksel_use_final_corepll,
  21 };
  22
  23 static struct __prci_wrpll_data __prci_ddrpll_data = {
  24         .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
  25         .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
  26 };
  27
  28 static struct __prci_wrpll_data __prci_gemgxlpll_data = {
  29         .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
  30         .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
  31 };
  32
  33 static struct __prci_wrpll_data __prci_dvfscorepll_data = {
  34         .cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET,
  35         .cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET,
  36         .enable_bypass = sifive_prci_corepllsel_use_corepll,
  37         .disable_bypass = sifive_prci_corepllsel_use_dvfscorepll,
  38 };
  39
  40 static struct __prci_wrpll_data __prci_hfpclkpll_data = {
  41         .cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET,
  42         .cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET,
  43         .enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk,
  44         .disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll,
  45 };
  46
  47 static struct __prci_wrpll_data __prci_cltxpll_data = {
  48         .cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET,
  49         .cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET,
  50 };
  51
  52 /* Linux clock framework integration */
  53
  54 static const struct clk_ops sifive_fu740_prci_wrpll_clk_ops = {
  55         .set_rate = sifive_prci_wrpll_set_rate,
  56         .round_rate = sifive_prci_wrpll_round_rate,
  57         .recalc_rate = sifive_prci_wrpll_recalc_rate,
  58         .enable = sifive_prci_clock_enable,
  59         .disable = sifive_prci_clock_disable,
  60         .is_enabled = sifive_clk_is_enabled,
  61 };
  62
  63 static const struct clk_ops sifive_fu740_prci_wrpll_ro_clk_ops = {
  64         .recalc_rate = sifive_prci_wrpll_recalc_rate,
  65 };
  66
  67 static const struct clk_ops sifive_fu740_prci_tlclksel_clk_ops = {
  68         .recalc_rate = sifive_prci_tlclksel_recalc_rate,
  69 };
  70
  71 static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = {
  72         .recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate,
  73 };
  74
  75 static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops = {
  76         .enable = sifive_prci_pcie_aux_clock_enable,
  77         .disable = sifive_prci_pcie_aux_clock_disable,
  78         .is_enabled = sifive_prci_pcie_aux_clock_is_enabled,
  79 };
  80
  81 /* List of clock controls provided by the PRCI */
  82 struct __prci_clock __prci_init_clocks_fu740[] = {
  83         [PRCI_CLK_COREPLL] = {
  84                 .name = "corepll",
  85                 .parent_name = "hfclk",
  86                 .ops = &sifive_fu740_prci_wrpll_clk_ops,
  87                 .pwd = &__prci_corepll_data,
  88         },
  89         [PRCI_CLK_DDRPLL] = {
  90                 .name = "ddrpll",
  91                 .parent_name = "hfclk",
  92                 .ops = &sifive_fu740_prci_wrpll_ro_clk_ops,
  93                 .pwd = &__prci_ddrpll_data,
  94         },
  95         [PRCI_CLK_GEMGXLPLL] = {
  96                 .name = "gemgxlpll",
  97                 .parent_name = "hfclk",
  98                 .ops = &sifive_fu740_prci_wrpll_clk_ops,
  99                 .pwd = &__prci_gemgxlpll_data,
 100         },
 101         [PRCI_CLK_DVFSCOREPLL] = {
 102                 .name = "dvfscorepll",
 103                 .parent_name = "hfclk",
 104                 .ops = &sifive_fu740_prci_wrpll_clk_ops,
 105                 .pwd = &__prci_dvfscorepll_data,
 106         },
 107         [PRCI_CLK_HFPCLKPLL] = {
 108                 .name = "hfpclkpll",
 109                 .parent_name = "hfclk",
 110                 .ops = &sifive_fu740_prci_wrpll_clk_ops,
 111                 .pwd = &__prci_hfpclkpll_data,
 112         },
 113         [PRCI_CLK_CLTXPLL] = {
 114                 .name = "cltxpll",
 115                 .parent_name = "hfclk",
 116                 .ops = &sifive_fu740_prci_wrpll_clk_ops,
 117                 .pwd = &__prci_cltxpll_data,
 118         },
 119         [PRCI_CLK_TLCLK] = {
 120                 .name = "tlclk",
 121                 .parent_name = "corepll",
 122                 .ops = &sifive_fu740_prci_tlclksel_clk_ops,
 123         },
 124         [PRCI_CLK_PCLK] = {
 125                 .name = "pclk",
 126                 .parent_name = "hfpclkpll",
 127                 .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
 128         },
 129         [PRCI_CLK_PCIE_AUX] = {
 130                 .name = "pcie_aux",
 131                 .parent_name = "hfclk",
 132                 .ops = &sifive_fu740_prci_pcie_aux_clk_ops,
 133         },
 134 };