2 * r8a7790 Common Clock Framework support
4 * Copyright (C) 2013 Renesas Solutions Corp.
6 * Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
13 #include <linux/clk-provider.h>
14 #include <linux/clkdev.h>
15 #include <linux/init.h>
17 #include <linux/kernel.h>
19 #include <linux/of_address.h>
21 #define CPG_DIV6_CKSTP BIT(8)
22 #define CPG_DIV6_DIV(d) ((d) & 0x3f)
23 #define CPG_DIV6_DIV_MASK 0x3f
26 * struct div6_clock - CPG 6 bit divider clock
27 * @hw: handle between common and hardware-specific interfaces
28 * @reg: IO-remapped register
29 * @div: divisor value (1-64)
40 #define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw)
42 static int cpg_div6_clock_enable(struct clk_hw *hw)
44 struct div6_clock *clock = to_div6_clock(hw);
47 val = (clk_readl(clock->reg) & ~(CPG_DIV6_DIV_MASK | CPG_DIV6_CKSTP))
48 | CPG_DIV6_DIV(clock->div - 1);
49 clk_writel(val, clock->reg);
54 static void cpg_div6_clock_disable(struct clk_hw *hw)
56 struct div6_clock *clock = to_div6_clock(hw);
59 val = clk_readl(clock->reg);
60 val |= CPG_DIV6_CKSTP;
62 * DIV6 clocks require the divisor field to be non-zero when stopping
63 * the clock. However, some clocks (e.g. ZB on sh73a0) fail to be
64 * re-enabled later if the divisor field is changed when stopping the
67 if (!(val & CPG_DIV6_DIV_MASK))
68 val |= CPG_DIV6_DIV_MASK;
69 clk_writel(val, clock->reg);
72 static int cpg_div6_clock_is_enabled(struct clk_hw *hw)
74 struct div6_clock *clock = to_div6_clock(hw);
76 return !(clk_readl(clock->reg) & CPG_DIV6_CKSTP);
79 static unsigned long cpg_div6_clock_recalc_rate(struct clk_hw *hw,
80 unsigned long parent_rate)
82 struct div6_clock *clock = to_div6_clock(hw);
83 unsigned int div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
85 return parent_rate / div;
88 static unsigned int cpg_div6_clock_calc_div(unsigned long rate,
89 unsigned long parent_rate)
93 div = DIV_ROUND_CLOSEST(parent_rate, rate);
94 return clamp_t(unsigned int, div, 1, 64);
97 static long cpg_div6_clock_round_rate(struct clk_hw *hw, unsigned long rate,
98 unsigned long *parent_rate)
100 unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate);
102 return *parent_rate / div;
105 static int cpg_div6_clock_set_rate(struct clk_hw *hw, unsigned long rate,
106 unsigned long parent_rate)
108 struct div6_clock *clock = to_div6_clock(hw);
109 unsigned int div = cpg_div6_clock_calc_div(rate, parent_rate);
114 val = clk_readl(clock->reg) & ~CPG_DIV6_DIV_MASK;
115 /* Only program the new divisor if the clock isn't stopped. */
116 if (!(val & CPG_DIV6_CKSTP))
117 clk_writel(val | CPG_DIV6_DIV(clock->div - 1), clock->reg);
122 static u8 cpg_div6_clock_get_parent(struct clk_hw *hw)
124 struct div6_clock *clock = to_div6_clock(hw);
128 if (clock->src_width == 0)
131 hw_index = (clk_readl(clock->reg) >> clock->src_shift) &
132 (BIT(clock->src_width) - 1);
133 for (i = 0; i < __clk_get_num_parents(hw->clk); i++) {
134 if (clock->parents[i] == hw_index)
138 pr_err("%s: %s DIV6 clock set to invalid parent %u\n",
139 __func__, __clk_get_name(hw->clk), hw_index);
143 static int cpg_div6_clock_set_parent(struct clk_hw *hw, u8 index)
145 struct div6_clock *clock = to_div6_clock(hw);
149 if (index >= __clk_get_num_parents(hw->clk))
152 mask = ~((BIT(clock->src_width) - 1) << clock->src_shift);
153 hw_index = clock->parents[index];
155 clk_writel((clk_readl(clock->reg) & mask) |
156 (hw_index << clock->src_shift), clock->reg);
161 static const struct clk_ops cpg_div6_clock_ops = {
162 .enable = cpg_div6_clock_enable,
163 .disable = cpg_div6_clock_disable,
164 .is_enabled = cpg_div6_clock_is_enabled,
165 .get_parent = cpg_div6_clock_get_parent,
166 .set_parent = cpg_div6_clock_set_parent,
167 .recalc_rate = cpg_div6_clock_recalc_rate,
168 .round_rate = cpg_div6_clock_round_rate,
169 .set_rate = cpg_div6_clock_set_rate,
172 static void __init cpg_div6_clock_init(struct device_node *np)
174 unsigned int num_parents, valid_parents;
175 const char **parent_names;
176 struct clk_init_data init;
177 struct div6_clock *clock;
183 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
187 num_parents = of_clk_get_parent_count(np);
188 if (num_parents < 1) {
189 pr_err("%s: no parent found for %s DIV6 clock\n",
194 clock->parents = kmalloc_array(num_parents, sizeof(*clock->parents),
196 parent_names = kmalloc_array(num_parents, sizeof(*parent_names),
201 /* Remap the clock register and read the divisor. Disabling the
202 * clock overwrites the divisor, so we need to cache its value for the
205 clock->reg = of_iomap(np, 0);
206 if (clock->reg == NULL) {
207 pr_err("%s: failed to map %s DIV6 clock register\n",
212 clock->div = (clk_readl(clock->reg) & CPG_DIV6_DIV_MASK) + 1;
214 /* Parse the DT properties. */
215 ret = of_property_read_string(np, "clock-output-names", &name);
217 pr_err("%s: failed to get %s DIV6 clock output name\n",
223 for (i = 0, valid_parents = 0; i < num_parents; i++) {
224 const char *name = of_clk_get_parent_name(np, i);
227 parent_names[valid_parents] = name;
228 clock->parents[valid_parents] = i;
233 switch (num_parents) {
235 /* fixed parent clock */
236 clock->src_shift = clock->src_width = 0;
239 /* clock with EXSRC bits 6-7 */
240 clock->src_shift = 6;
241 clock->src_width = 2;
244 /* VCLK with EXSRC bits 12-14 */
245 clock->src_shift = 12;
246 clock->src_width = 3;
249 pr_err("%s: invalid number of parents for DIV6 clock %s\n",
254 /* Register the clock. */
256 init.ops = &cpg_div6_clock_ops;
257 init.flags = CLK_IS_BASIC;
258 init.parent_names = parent_names;
259 init.num_parents = valid_parents;
261 clock->hw.init = &init;
263 clk = clk_register(NULL, &clock->hw);
265 pr_err("%s: failed to register %s DIV6 clock (%ld)\n",
266 __func__, np->name, PTR_ERR(clk));
270 of_clk_add_provider(np, of_clk_src_simple_get, clk);
281 CLK_OF_DECLARE(cpg_div6_clk, "renesas,cpg-div6-clock", cpg_div6_clock_init);