2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2013 Linaro Ltd.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This file contains the utility functions to register the pll clocks.
12 #include <linux/errno.h>
13 #include <linux/hrtimer.h>
17 #define PLL_TIMEOUT_MS 10
19 struct samsung_clk_pll {
21 void __iomem *lock_reg;
22 void __iomem *con_reg;
23 enum samsung_pll_type type;
24 unsigned int rate_count;
25 const struct samsung_pll_rate_table *rate_table;
28 #define to_clk_pll(_hw) container_of(_hw, struct samsung_clk_pll, hw)
30 static const struct samsung_pll_rate_table *samsung_get_pll_settings(
31 struct samsung_clk_pll *pll, unsigned long rate)
33 const struct samsung_pll_rate_table *rate_table = pll->rate_table;
36 for (i = 0; i < pll->rate_count; i++) {
37 if (rate == rate_table[i].rate)
38 return &rate_table[i];
44 static long samsung_pll_round_rate(struct clk_hw *hw,
45 unsigned long drate, unsigned long *prate)
47 struct samsung_clk_pll *pll = to_clk_pll(hw);
48 const struct samsung_pll_rate_table *rate_table = pll->rate_table;
51 /* Assumming rate_table is in descending order */
52 for (i = 0; i < pll->rate_count; i++) {
53 if (drate >= rate_table[i].rate)
54 return rate_table[i].rate;
57 /* return minimum supported value */
58 return rate_table[i - 1].rate;
64 /* Maximum lock time can be 270 * PDIV cycles */
65 #define PLL35XX_LOCK_FACTOR (270)
67 #define PLL35XX_MDIV_MASK (0x3FF)
68 #define PLL35XX_PDIV_MASK (0x3F)
69 #define PLL35XX_SDIV_MASK (0x7)
70 #define PLL35XX_LOCK_STAT_MASK (0x1)
71 #define PLL35XX_MDIV_SHIFT (16)
72 #define PLL35XX_PDIV_SHIFT (8)
73 #define PLL35XX_SDIV_SHIFT (0)
74 #define PLL35XX_LOCK_STAT_SHIFT (29)
76 static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
77 unsigned long parent_rate)
79 struct samsung_clk_pll *pll = to_clk_pll(hw);
80 u32 mdiv, pdiv, sdiv, pll_con;
81 u64 fvco = parent_rate;
83 pll_con = __raw_readl(pll->con_reg);
84 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
85 pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
86 sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
89 do_div(fvco, (pdiv << sdiv));
91 return (unsigned long)fvco;
94 static inline bool samsung_pll35xx_mp_change(
95 const struct samsung_pll_rate_table *rate, u32 pll_con)
97 u32 old_mdiv, old_pdiv;
99 old_mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
100 old_pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
102 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv);
105 static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate,
108 struct samsung_clk_pll *pll = to_clk_pll(hw);
109 const struct samsung_pll_rate_table *rate;
112 /* Get required rate settings from table */
113 rate = samsung_get_pll_settings(pll, drate);
115 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
116 drate, __clk_get_name(hw->clk));
120 tmp = __raw_readl(pll->con_reg);
122 if (!(samsung_pll35xx_mp_change(rate, tmp))) {
123 /* If only s change, change just s value only*/
124 tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT);
125 tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT;
126 __raw_writel(tmp, pll->con_reg);
131 /* Set PLL lock time. */
132 __raw_writel(rate->pdiv * PLL35XX_LOCK_FACTOR,
135 /* Change PLL PMS values */
136 tmp &= ~((PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT) |
137 (PLL35XX_PDIV_MASK << PLL35XX_PDIV_SHIFT) |
138 (PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT));
139 tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) |
140 (rate->pdiv << PLL35XX_PDIV_SHIFT) |
141 (rate->sdiv << PLL35XX_SDIV_SHIFT);
142 __raw_writel(tmp, pll->con_reg);
147 tmp = __raw_readl(pll->con_reg);
148 } while (!(tmp & (PLL35XX_LOCK_STAT_MASK
149 << PLL35XX_LOCK_STAT_SHIFT)));
153 static const struct clk_ops samsung_pll35xx_clk_ops = {
154 .recalc_rate = samsung_pll35xx_recalc_rate,
155 .round_rate = samsung_pll_round_rate,
156 .set_rate = samsung_pll35xx_set_rate,
159 static const struct clk_ops samsung_pll35xx_clk_min_ops = {
160 .recalc_rate = samsung_pll35xx_recalc_rate,
166 /* Maximum lock time can be 3000 * PDIV cycles */
167 #define PLL36XX_LOCK_FACTOR (3000)
169 #define PLL36XX_KDIV_MASK (0xFFFF)
170 #define PLL36XX_MDIV_MASK (0x1FF)
171 #define PLL36XX_PDIV_MASK (0x3F)
172 #define PLL36XX_SDIV_MASK (0x7)
173 #define PLL36XX_MDIV_SHIFT (16)
174 #define PLL36XX_PDIV_SHIFT (8)
175 #define PLL36XX_SDIV_SHIFT (0)
176 #define PLL36XX_KDIV_SHIFT (0)
177 #define PLL36XX_LOCK_STAT_SHIFT (29)
179 static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw,
180 unsigned long parent_rate)
182 struct samsung_clk_pll *pll = to_clk_pll(hw);
183 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1;
185 u64 fvco = parent_rate;
187 pll_con0 = __raw_readl(pll->con_reg);
188 pll_con1 = __raw_readl(pll->con_reg + 4);
189 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
190 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
191 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
192 kdiv = (s16)(pll_con1 & PLL36XX_KDIV_MASK);
194 fvco *= (mdiv << 16) + kdiv;
195 do_div(fvco, (pdiv << sdiv));
198 return (unsigned long)fvco;
201 static inline bool samsung_pll36xx_mpk_change(
202 const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1)
204 u32 old_mdiv, old_pdiv, old_kdiv;
206 old_mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
207 old_pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
208 old_kdiv = (pll_con1 >> PLL36XX_KDIV_SHIFT) & PLL36XX_KDIV_MASK;
210 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
211 rate->kdiv != old_kdiv);
214 static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate,
215 unsigned long parent_rate)
217 struct samsung_clk_pll *pll = to_clk_pll(hw);
218 u32 tmp, pll_con0, pll_con1;
219 const struct samsung_pll_rate_table *rate;
221 rate = samsung_get_pll_settings(pll, drate);
223 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
224 drate, __clk_get_name(hw->clk));
228 pll_con0 = __raw_readl(pll->con_reg);
229 pll_con1 = __raw_readl(pll->con_reg + 4);
231 if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) {
232 /* If only s change, change just s value only*/
233 pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT);
234 pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT);
235 __raw_writel(pll_con0, pll->con_reg);
240 /* Set PLL lock time. */
241 __raw_writel(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg);
243 /* Change PLL PMS values */
244 pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) |
245 (PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT) |
246 (PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT));
247 pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) |
248 (rate->pdiv << PLL36XX_PDIV_SHIFT) |
249 (rate->sdiv << PLL36XX_SDIV_SHIFT);
250 __raw_writel(pll_con0, pll->con_reg);
252 pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT);
253 pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT;
254 __raw_writel(pll_con1, pll->con_reg + 4);
259 tmp = __raw_readl(pll->con_reg);
260 } while (!(tmp & (1 << PLL36XX_LOCK_STAT_SHIFT)));
265 static const struct clk_ops samsung_pll36xx_clk_ops = {
266 .recalc_rate = samsung_pll36xx_recalc_rate,
267 .set_rate = samsung_pll36xx_set_rate,
268 .round_rate = samsung_pll_round_rate,
271 static const struct clk_ops samsung_pll36xx_clk_min_ops = {
272 .recalc_rate = samsung_pll36xx_recalc_rate,
278 #define PLL4502_LOCK_FACTOR 400
279 #define PLL4508_LOCK_FACTOR 240
281 #define PLL45XX_MDIV_MASK (0x3FF)
282 #define PLL45XX_PDIV_MASK (0x3F)
283 #define PLL45XX_SDIV_MASK (0x7)
284 #define PLL45XX_AFC_MASK (0x1F)
285 #define PLL45XX_MDIV_SHIFT (16)
286 #define PLL45XX_PDIV_SHIFT (8)
287 #define PLL45XX_SDIV_SHIFT (0)
288 #define PLL45XX_AFC_SHIFT (0)
290 #define PLL45XX_ENABLE BIT(31)
291 #define PLL45XX_LOCKED BIT(29)
293 static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
294 unsigned long parent_rate)
296 struct samsung_clk_pll *pll = to_clk_pll(hw);
297 u32 mdiv, pdiv, sdiv, pll_con;
298 u64 fvco = parent_rate;
300 pll_con = __raw_readl(pll->con_reg);
301 mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
302 pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
303 sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
305 if (pll->type == pll_4508)
309 do_div(fvco, (pdiv << sdiv));
311 return (unsigned long)fvco;
314 static bool samsung_pll45xx_mp_change(u32 pll_con0, u32 pll_con1,
315 const struct samsung_pll_rate_table *rate)
317 u32 old_mdiv, old_pdiv, old_afc;
319 old_mdiv = (pll_con0 >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
320 old_pdiv = (pll_con0 >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
321 old_afc = (pll_con1 >> PLL45XX_AFC_SHIFT) & PLL45XX_AFC_MASK;
323 return (old_mdiv != rate->mdiv || old_pdiv != rate->pdiv
324 || old_afc != rate->afc);
327 static int samsung_pll45xx_set_rate(struct clk_hw *hw, unsigned long drate,
330 struct samsung_clk_pll *pll = to_clk_pll(hw);
331 const struct samsung_pll_rate_table *rate;
335 /* Get required rate settings from table */
336 rate = samsung_get_pll_settings(pll, drate);
338 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
339 drate, __clk_get_name(hw->clk));
343 con0 = __raw_readl(pll->con_reg);
344 con1 = __raw_readl(pll->con_reg + 0x4);
346 if (!(samsung_pll45xx_mp_change(con0, con1, rate))) {
347 /* If only s change, change just s value only*/
348 con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT);
349 con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT;
350 __raw_writel(con0, pll->con_reg);
355 /* Set PLL PMS values. */
356 con0 &= ~((PLL45XX_MDIV_MASK << PLL45XX_MDIV_SHIFT) |
357 (PLL45XX_PDIV_MASK << PLL45XX_PDIV_SHIFT) |
358 (PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT));
359 con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) |
360 (rate->pdiv << PLL45XX_PDIV_SHIFT) |
361 (rate->sdiv << PLL45XX_SDIV_SHIFT);
363 /* Set PLL AFC value. */
364 con1 = __raw_readl(pll->con_reg + 0x4);
365 con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT);
366 con1 |= (rate->afc << PLL45XX_AFC_SHIFT);
368 /* Set PLL lock time. */
371 __raw_writel(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg);
374 __raw_writel(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg);
380 /* Set new configuration. */
381 __raw_writel(con1, pll->con_reg + 0x4);
382 __raw_writel(con0, pll->con_reg);
384 /* Wait for locking. */
386 while (!(__raw_readl(pll->con_reg) & PLL45XX_LOCKED)) {
387 ktime_t delta = ktime_sub(ktime_get(), start);
389 if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) {
390 pr_err("%s: could not lock PLL %s\n",
391 __func__, __clk_get_name(hw->clk));
401 static const struct clk_ops samsung_pll45xx_clk_ops = {
402 .recalc_rate = samsung_pll45xx_recalc_rate,
403 .round_rate = samsung_pll_round_rate,
404 .set_rate = samsung_pll45xx_set_rate,
407 static const struct clk_ops samsung_pll45xx_clk_min_ops = {
408 .recalc_rate = samsung_pll45xx_recalc_rate,
415 #define PLL46XX_MDIV_MASK (0x1FF)
416 #define PLL46XX_PDIV_MASK (0x3F)
417 #define PLL46XX_SDIV_MASK (0x7)
418 #define PLL46XX_MDIV_SHIFT (16)
419 #define PLL46XX_PDIV_SHIFT (8)
420 #define PLL46XX_SDIV_SHIFT (0)
422 #define PLL46XX_KDIV_MASK (0xFFFF)
423 #define PLL4650C_KDIV_MASK (0xFFF)
424 #define PLL46XX_KDIV_SHIFT (0)
426 static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
427 unsigned long parent_rate)
429 struct samsung_clk_pll *pll = to_clk_pll(hw);
430 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift;
431 u64 fvco = parent_rate;
433 pll_con0 = __raw_readl(pll->con_reg);
434 pll_con1 = __raw_readl(pll->con_reg + 4);
435 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
436 pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
437 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
438 kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
439 pll_con1 & PLL46XX_KDIV_MASK;
441 shift = pll->type == pll_4600 ? 16 : 10;
442 fvco *= (mdiv << shift) + kdiv;
443 do_div(fvco, (pdiv << sdiv));
446 return (unsigned long)fvco;
449 static const struct clk_ops samsung_pll46xx_clk_ops = {
450 .recalc_rate = samsung_pll46xx_recalc_rate,
457 #define PLL6552_MDIV_MASK 0x3ff
458 #define PLL6552_PDIV_MASK 0x3f
459 #define PLL6552_SDIV_MASK 0x7
460 #define PLL6552_MDIV_SHIFT 16
461 #define PLL6552_PDIV_SHIFT 8
462 #define PLL6552_SDIV_SHIFT 0
464 static unsigned long samsung_pll6552_recalc_rate(struct clk_hw *hw,
465 unsigned long parent_rate)
467 struct samsung_clk_pll *pll = to_clk_pll(hw);
468 u32 mdiv, pdiv, sdiv, pll_con;
469 u64 fvco = parent_rate;
471 pll_con = __raw_readl(pll->con_reg);
472 mdiv = (pll_con >> PLL6552_MDIV_SHIFT) & PLL6552_MDIV_MASK;
473 pdiv = (pll_con >> PLL6552_PDIV_SHIFT) & PLL6552_PDIV_MASK;
474 sdiv = (pll_con >> PLL6552_SDIV_SHIFT) & PLL6552_SDIV_MASK;
477 do_div(fvco, (pdiv << sdiv));
479 return (unsigned long)fvco;
482 static const struct clk_ops samsung_pll6552_clk_ops = {
483 .recalc_rate = samsung_pll6552_recalc_rate,
490 #define PLL6553_MDIV_MASK 0xff
491 #define PLL6553_PDIV_MASK 0x3f
492 #define PLL6553_SDIV_MASK 0x7
493 #define PLL6553_KDIV_MASK 0xffff
494 #define PLL6553_MDIV_SHIFT 16
495 #define PLL6553_PDIV_SHIFT 8
496 #define PLL6553_SDIV_SHIFT 0
497 #define PLL6553_KDIV_SHIFT 0
499 static unsigned long samsung_pll6553_recalc_rate(struct clk_hw *hw,
500 unsigned long parent_rate)
502 struct samsung_clk_pll *pll = to_clk_pll(hw);
503 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
504 u64 fvco = parent_rate;
506 pll_con0 = __raw_readl(pll->con_reg);
507 pll_con1 = __raw_readl(pll->con_reg + 0x4);
508 mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK;
509 pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK;
510 sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK;
511 kdiv = (pll_con1 >> PLL6553_KDIV_SHIFT) & PLL6553_KDIV_MASK;
513 fvco *= (mdiv << 16) + kdiv;
514 do_div(fvco, (pdiv << sdiv));
517 return (unsigned long)fvco;
520 static const struct clk_ops samsung_pll6553_clk_ops = {
521 .recalc_rate = samsung_pll6553_recalc_rate,
525 * PLL2550x Clock Type
528 #define PLL2550X_R_MASK (0x1)
529 #define PLL2550X_P_MASK (0x3F)
530 #define PLL2550X_M_MASK (0x3FF)
531 #define PLL2550X_S_MASK (0x7)
532 #define PLL2550X_R_SHIFT (20)
533 #define PLL2550X_P_SHIFT (14)
534 #define PLL2550X_M_SHIFT (4)
535 #define PLL2550X_S_SHIFT (0)
537 struct samsung_clk_pll2550x {
539 const void __iomem *reg_base;
540 unsigned long offset;
543 #define to_clk_pll2550x(_hw) container_of(_hw, struct samsung_clk_pll2550x, hw)
545 static unsigned long samsung_pll2550x_recalc_rate(struct clk_hw *hw,
546 unsigned long parent_rate)
548 struct samsung_clk_pll2550x *pll = to_clk_pll2550x(hw);
549 u32 r, p, m, s, pll_stat;
550 u64 fvco = parent_rate;
552 pll_stat = __raw_readl(pll->reg_base + pll->offset * 3);
553 r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK;
556 p = (pll_stat >> PLL2550X_P_SHIFT) & PLL2550X_P_MASK;
557 m = (pll_stat >> PLL2550X_M_SHIFT) & PLL2550X_M_MASK;
558 s = (pll_stat >> PLL2550X_S_SHIFT) & PLL2550X_S_MASK;
561 do_div(fvco, (p << s));
563 return (unsigned long)fvco;
566 static const struct clk_ops samsung_pll2550x_clk_ops = {
567 .recalc_rate = samsung_pll2550x_recalc_rate,
570 struct clk * __init samsung_clk_register_pll2550x(const char *name,
571 const char *pname, const void __iomem *reg_base,
572 const unsigned long offset)
574 struct samsung_clk_pll2550x *pll;
576 struct clk_init_data init;
578 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
580 pr_err("%s: could not allocate pll clk %s\n", __func__, name);
585 init.ops = &samsung_pll2550x_clk_ops;
586 init.flags = CLK_GET_RATE_NOCACHE;
587 init.parent_names = &pname;
588 init.num_parents = 1;
590 pll->hw.init = &init;
591 pll->reg_base = reg_base;
592 pll->offset = offset;
594 clk = clk_register(NULL, &pll->hw);
596 pr_err("%s: failed to register pll clock %s\n", __func__,
601 if (clk_register_clkdev(clk, name, NULL))
602 pr_err("%s: failed to register lookup for %s", __func__, name);
607 static void __init _samsung_clk_register_pll(struct samsung_pll_clock *pll_clk,
610 struct samsung_clk_pll *pll;
612 struct clk_init_data init;
615 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
617 pr_err("%s: could not allocate pll clk %s\n",
618 __func__, pll_clk->name);
622 init.name = pll_clk->name;
623 init.flags = pll_clk->flags;
624 init.parent_names = &pll_clk->parent_name;
625 init.num_parents = 1;
627 if (pll_clk->rate_table) {
628 /* find count of rates in rate_table */
629 for (len = 0; pll_clk->rate_table[len].rate != 0; )
632 pll->rate_count = len;
633 pll->rate_table = kmemdup(pll_clk->rate_table,
635 sizeof(struct samsung_pll_rate_table),
637 WARN(!pll->rate_table,
638 "%s: could not allocate rate table for %s\n",
639 __func__, pll_clk->name);
642 switch (pll_clk->type) {
643 /* clk_ops for 35xx and 2550 are similar */
646 if (!pll->rate_table)
647 init.ops = &samsung_pll35xx_clk_min_ops;
649 init.ops = &samsung_pll35xx_clk_ops;
652 init.ops = &samsung_pll45xx_clk_min_ops;
656 if (!pll->rate_table)
657 init.ops = &samsung_pll45xx_clk_min_ops;
659 init.ops = &samsung_pll45xx_clk_ops;
661 /* clk_ops for 36xx and 2650 are similar */
664 if (!pll->rate_table)
665 init.ops = &samsung_pll36xx_clk_min_ops;
667 init.ops = &samsung_pll36xx_clk_ops;
670 init.ops = &samsung_pll6552_clk_ops;
673 init.ops = &samsung_pll6553_clk_ops;
678 init.ops = &samsung_pll46xx_clk_ops;
681 pr_warn("%s: Unknown pll type for pll clk %s\n",
682 __func__, pll_clk->name);
685 pll->hw.init = &init;
686 pll->type = pll_clk->type;
687 pll->lock_reg = base + pll_clk->lock_offset;
688 pll->con_reg = base + pll_clk->con_offset;
690 clk = clk_register(NULL, &pll->hw);
692 pr_err("%s: failed to register pll clock %s : %ld\n",
693 __func__, pll_clk->name, PTR_ERR(clk));
698 samsung_clk_add_lookup(clk, pll_clk->id);
703 ret = clk_register_clkdev(clk, pll_clk->alias, pll_clk->dev_name);
705 pr_err("%s: failed to register lookup for %s : %d",
706 __func__, pll_clk->name, ret);
709 void __init samsung_clk_register_pll(struct samsung_pll_clock *pll_list,
710 unsigned int nr_pll, void __iomem *base)
714 for (cnt = 0; cnt < nr_pll; cnt++)
715 _samsung_clk_register_pll(&pll_list[cnt], base);