1 // SPDX-License-Identifier: GPL-2.0
3 * RZ/G2L Clock Pulse Generator
5 * Copyright (C) 2021 Renesas Electronics Corp.
7 * Based on renesas-cpg-mssr.c
9 * Copyright (C) 2015 Glider bvba
10 * Copyright (C) 2013 Ideas On Board SPRL
11 * Copyright (C) 2015 Renesas Electronics Corp.
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16 #include <linux/clk/renesas.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/init.h>
20 #include <linux/mod_devicetable.h>
21 #include <linux/module.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_clock.h>
26 #include <linux/pm_domain.h>
27 #include <linux/reset-controller.h>
28 #include <linux/slab.h>
30 #include <dt-bindings/clock/renesas-cpg-mssr.h>
32 #include "rzg2l-cpg.h"
35 #define WARN_DEBUG(x) WARN_ON(x)
37 #define WARN_DEBUG(x) do { } while (0)
40 #define DIV_RSMASK(v, s, m) ((v >> s) & m)
41 #define GET_SHIFT(val) ((val >> 12) & 0xff)
42 #define GET_WIDTH(val) ((val >> 8) & 0xf)
44 #define KDIV(val) DIV_RSMASK(val, 16, 0xffff)
45 #define MDIV(val) DIV_RSMASK(val, 6, 0x3ff)
46 #define PDIV(val) DIV_RSMASK(val, 0, 0x3f)
47 #define SDIV(val) DIV_RSMASK(val, 0, 0x7)
49 #define CLK_ON_R(reg) (reg)
50 #define CLK_MON_R(reg) (0x180 + (reg))
51 #define CLK_RST_R(reg) (reg)
52 #define CLK_MRST_R(reg) (0x180 + (reg))
54 #define GET_REG_OFFSET(val) ((val >> 20) & 0xfff)
55 #define GET_REG_SAMPLL_CLK1(val) ((val >> 22) & 0xfff)
56 #define GET_REG_SAMPLL_CLK2(val) ((val >> 12) & 0xfff)
59 * struct rzg2l_cpg_priv - Clock Pulse Generator Private Data
61 * @rcdev: Reset controller entity
63 * @base: CPG register block base address
64 * @rmw_lock: protects register accesses
65 * @clks: Array containing all Core and Module Clocks
66 * @num_core_clks: Number of Core Clocks in clks[]
67 * @num_mod_clks: Number of Module Clocks in clks[]
68 * @last_dt_core_clk: ID of the last Core Clock exported to DT
69 * @notifiers: Notifier chain to save/restore clock state for system resume
70 * @info: Pointer to platform data
72 struct rzg2l_cpg_priv {
73 struct reset_controller_dev rcdev;
79 unsigned int num_core_clks;
80 unsigned int num_mod_clks;
81 unsigned int num_resets;
82 unsigned int last_dt_core_clk;
84 struct raw_notifier_head notifiers;
85 const struct rzg2l_cpg_info *info;
88 static void rzg2l_cpg_del_clk_provider(void *data)
90 of_clk_del_provider(data);
93 static struct clk * __init
94 rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core,
97 struct rzg2l_cpg_priv *priv)
99 struct device *dev = priv->dev;
100 const struct clk *parent;
101 const char *parent_name;
102 struct clk_hw *clk_hw;
104 parent = clks[core->parent & 0xffff];
106 return ERR_CAST(parent);
108 parent_name = __clk_get_name(parent);
111 clk_hw = clk_hw_register_divider_table(dev, core->name,
113 base + GET_REG_OFFSET(core->conf),
114 GET_SHIFT(core->conf),
115 GET_WIDTH(core->conf),
120 clk_hw = clk_hw_register_divider(dev, core->name,
122 base + GET_REG_OFFSET(core->conf),
123 GET_SHIFT(core->conf),
124 GET_WIDTH(core->conf),
125 core->flag, &priv->rmw_lock);
128 return ERR_CAST(clk_hw);
138 struct rzg2l_cpg_priv *priv;
141 #define to_pll(_hw) container_of(_hw, struct pll_clk, hw)
143 static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
144 unsigned long parent_rate)
146 struct pll_clk *pll_clk = to_pll(hw);
147 struct rzg2l_cpg_priv *priv = pll_clk->priv;
148 unsigned int val1, val2;
149 unsigned int mult = 1;
150 unsigned int div = 1;
152 if (pll_clk->type != CLK_TYPE_SAM_PLL)
155 val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));
156 val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf));
157 mult = MDIV(val1) + KDIV(val1) / 65536;
158 div = PDIV(val1) * (1 << SDIV(val2));
160 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, div);
163 static const struct clk_ops rzg2l_cpg_pll_ops = {
164 .recalc_rate = rzg2l_cpg_pll_clk_recalc_rate,
167 static struct clk * __init
168 rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
171 struct rzg2l_cpg_priv *priv)
173 struct device *dev = priv->dev;
174 const struct clk *parent;
175 struct clk_init_data init;
176 const char *parent_name;
177 struct pll_clk *pll_clk;
179 parent = clks[core->parent & 0xffff];
181 return ERR_CAST(parent);
183 pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
185 return ERR_PTR(-ENOMEM);
187 parent_name = __clk_get_name(parent);
188 init.name = core->name;
189 init.ops = &rzg2l_cpg_pll_ops;
191 init.parent_names = &parent_name;
192 init.num_parents = 1;
194 pll_clk->hw.init = &init;
195 pll_clk->conf = core->conf;
196 pll_clk->base = base;
197 pll_clk->priv = priv;
198 pll_clk->type = core->type;
200 return clk_register(NULL, &pll_clk->hw);
204 *rzg2l_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
207 unsigned int clkidx = clkspec->args[1];
208 struct rzg2l_cpg_priv *priv = data;
209 struct device *dev = priv->dev;
213 switch (clkspec->args[0]) {
216 if (clkidx > priv->last_dt_core_clk) {
217 dev_err(dev, "Invalid %s clock index %u\n", type, clkidx);
218 return ERR_PTR(-EINVAL);
220 clk = priv->clks[clkidx];
225 if (clkidx >= priv->num_mod_clks) {
226 dev_err(dev, "Invalid %s clock index %u\n", type,
228 return ERR_PTR(-EINVAL);
230 clk = priv->clks[priv->num_core_clks + clkidx];
234 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
235 return ERR_PTR(-EINVAL);
239 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
242 dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
243 clkspec->args[0], clkspec->args[1], clk,
249 rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
250 const struct rzg2l_cpg_info *info,
251 struct rzg2l_cpg_priv *priv)
253 struct clk *clk = ERR_PTR(-EOPNOTSUPP), *parent;
254 struct device *dev = priv->dev;
255 unsigned int id = core->id, div = core->div;
256 const char *parent_name;
258 WARN_DEBUG(id >= priv->num_core_clks);
259 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
262 /* Skip NULLified clock */
266 switch (core->type) {
268 clk = of_clk_get_by_name(priv->dev->of_node, core->name);
271 WARN_DEBUG(core->parent >= priv->num_core_clks);
272 parent = priv->clks[core->parent];
273 if (IS_ERR(parent)) {
278 parent_name = __clk_get_name(parent);
279 clk = clk_register_fixed_factor(NULL, core->name,
280 parent_name, CLK_SET_RATE_PARENT,
283 case CLK_TYPE_SAM_PLL:
284 clk = rzg2l_cpg_pll_clk_register(core, priv->clks,
288 clk = rzg2l_cpg_div_clk_register(core, priv->clks,
295 if (IS_ERR_OR_NULL(clk))
298 dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
299 priv->clks[id] = clk;
303 dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
304 core->name, PTR_ERR(clk));
308 * struct mstp_clock - MSTP gating clock
310 * @hw: handle between common and hardware-specific interfaces
311 * @off: register offset
313 * @priv: CPG/MSTP private data
319 struct rzg2l_cpg_priv *priv;
322 #define to_mod_clock(_hw) container_of(_hw, struct mstp_clock, hw)
324 static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
326 struct mstp_clock *clock = to_mod_clock(hw);
327 struct rzg2l_cpg_priv *priv = clock->priv;
328 unsigned int reg = clock->off;
329 struct device *dev = priv->dev;
332 u32 bitmask = BIT(clock->bit);
336 dev_dbg(dev, "%pC does not support ON/OFF\n", hw->clk);
340 dev_dbg(dev, "CLK_ON %u/%pC %s\n", CLK_ON_R(reg), hw->clk,
341 enable ? "ON" : "OFF");
342 spin_lock_irqsave(&priv->rmw_lock, flags);
345 value = (bitmask << 16) | bitmask;
347 value = bitmask << 16;
348 writel(value, priv->base + CLK_ON_R(reg));
350 spin_unlock_irqrestore(&priv->rmw_lock, flags);
355 for (i = 1000; i > 0; --i) {
356 if (((readl(priv->base + CLK_MON_R(reg))) & bitmask))
362 dev_err(dev, "Failed to enable CLK_ON %p\n",
363 priv->base + CLK_ON_R(reg));
370 static int rzg2l_mod_clock_enable(struct clk_hw *hw)
372 return rzg2l_mod_clock_endisable(hw, true);
375 static void rzg2l_mod_clock_disable(struct clk_hw *hw)
377 rzg2l_mod_clock_endisable(hw, false);
380 static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
382 struct mstp_clock *clock = to_mod_clock(hw);
383 struct rzg2l_cpg_priv *priv = clock->priv;
384 u32 bitmask = BIT(clock->bit);
388 dev_dbg(priv->dev, "%pC does not support ON/OFF\n", hw->clk);
392 value = readl(priv->base + CLK_MON_R(clock->off));
394 return value & bitmask;
397 static const struct clk_ops rzg2l_mod_clock_ops = {
398 .enable = rzg2l_mod_clock_enable,
399 .disable = rzg2l_mod_clock_disable,
400 .is_enabled = rzg2l_mod_clock_is_enabled,
404 rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
405 const struct rzg2l_cpg_info *info,
406 struct rzg2l_cpg_priv *priv)
408 struct mstp_clock *clock = NULL;
409 struct device *dev = priv->dev;
410 unsigned int id = mod->id;
411 struct clk_init_data init;
412 struct clk *parent, *clk;
413 const char *parent_name;
416 WARN_DEBUG(id < priv->num_core_clks);
417 WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
418 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
419 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
422 /* Skip NULLified clock */
426 parent = priv->clks[mod->parent];
427 if (IS_ERR(parent)) {
432 clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL);
434 clk = ERR_PTR(-ENOMEM);
438 init.name = mod->name;
439 init.ops = &rzg2l_mod_clock_ops;
440 init.flags = CLK_SET_RATE_PARENT;
441 for (i = 0; i < info->num_crit_mod_clks; i++)
442 if (id == info->crit_mod_clks[i]) {
443 dev_dbg(dev, "CPG %s setting CLK_IS_CRITICAL\n",
445 init.flags |= CLK_IS_CRITICAL;
449 parent_name = __clk_get_name(parent);
450 init.parent_names = &parent_name;
451 init.num_parents = 1;
453 clock->off = mod->off;
454 clock->bit = mod->bit;
456 clock->hw.init = &init;
458 clk = clk_register(NULL, &clock->hw);
462 dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
463 priv->clks[id] = clk;
467 dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
468 mod->name, PTR_ERR(clk));
471 #define rcdev_to_priv(x) container_of(x, struct rzg2l_cpg_priv, rcdev)
473 static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
476 struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
477 const struct rzg2l_cpg_info *info = priv->info;
478 unsigned int reg = info->resets[id].off;
479 u32 dis = BIT(info->resets[id].bit);
482 dev_dbg(rcdev->dev, "reset id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
485 writel(we, priv->base + CLK_RST_R(reg));
487 /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
490 /* Release module from reset state */
491 writel(we | dis, priv->base + CLK_RST_R(reg));
496 static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
499 struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
500 const struct rzg2l_cpg_info *info = priv->info;
501 unsigned int reg = info->resets[id].off;
502 u32 value = BIT(info->resets[id].bit) << 16;
504 dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
506 writel(value, priv->base + CLK_RST_R(reg));
510 static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,
513 struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
514 const struct rzg2l_cpg_info *info = priv->info;
515 unsigned int reg = info->resets[id].off;
516 u32 dis = BIT(info->resets[id].bit);
517 u32 value = (dis << 16) | dis;
519 dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id,
522 writel(value, priv->base + CLK_RST_R(reg));
526 static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
529 struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
530 const struct rzg2l_cpg_info *info = priv->info;
531 unsigned int reg = info->resets[id].off;
532 u32 bitmask = BIT(info->resets[id].bit);
534 return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
537 static const struct reset_control_ops rzg2l_cpg_reset_ops = {
538 .reset = rzg2l_cpg_reset,
539 .assert = rzg2l_cpg_assert,
540 .deassert = rzg2l_cpg_deassert,
541 .status = rzg2l_cpg_status,
544 static int rzg2l_cpg_reset_xlate(struct reset_controller_dev *rcdev,
545 const struct of_phandle_args *reset_spec)
547 struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
548 const struct rzg2l_cpg_info *info = priv->info;
549 unsigned int id = reset_spec->args[0];
551 if (id >= rcdev->nr_resets || !info->resets[id].off) {
552 dev_err(rcdev->dev, "Invalid reset index %u\n", id);
559 static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv)
561 priv->rcdev.ops = &rzg2l_cpg_reset_ops;
562 priv->rcdev.of_node = priv->dev->of_node;
563 priv->rcdev.dev = priv->dev;
564 priv->rcdev.of_reset_n_cells = 1;
565 priv->rcdev.of_xlate = rzg2l_cpg_reset_xlate;
566 priv->rcdev.nr_resets = priv->num_resets;
568 return devm_reset_controller_register(priv->dev, &priv->rcdev);
571 static bool rzg2l_cpg_is_pm_clk(const struct of_phandle_args *clkspec)
573 if (clkspec->args_count != 2)
576 switch (clkspec->args[0]) {
585 static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device *dev)
587 struct device_node *np = dev->of_node;
588 struct of_phandle_args clkspec;
594 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
596 if (rzg2l_cpg_is_pm_clk(&clkspec)) {
599 error = pm_clk_create(dev);
601 of_node_put(clkspec.np);
605 clk = of_clk_get_from_provider(&clkspec);
606 of_node_put(clkspec.np);
608 error = PTR_ERR(clk);
612 error = pm_clk_add_clk(dev, clk);
614 dev_err(dev, "pm_clk_add_clk failed %d\n",
619 of_node_put(clkspec.np);
635 static void rzg2l_cpg_detach_dev(struct generic_pm_domain *unused, struct device *dev)
637 if (!pm_clk_no_clocks(dev))
641 static int __init rzg2l_cpg_add_clk_domain(struct device *dev)
643 struct device_node *np = dev->of_node;
644 struct generic_pm_domain *genpd;
646 genpd = devm_kzalloc(dev, sizeof(*genpd), GFP_KERNEL);
650 genpd->name = np->name;
651 genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
652 GENPD_FLAG_ACTIVE_WAKEUP;
653 genpd->attach_dev = rzg2l_cpg_attach_dev;
654 genpd->detach_dev = rzg2l_cpg_detach_dev;
655 pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
657 of_genpd_add_provider_simple(np, genpd);
661 static int __init rzg2l_cpg_probe(struct platform_device *pdev)
663 struct device *dev = &pdev->dev;
664 struct device_node *np = dev->of_node;
665 const struct rzg2l_cpg_info *info;
666 struct rzg2l_cpg_priv *priv;
667 unsigned int nclks, i;
671 info = of_device_get_match_data(dev);
673 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
679 spin_lock_init(&priv->rmw_lock);
681 priv->base = devm_platform_ioremap_resource(pdev, 0);
682 if (IS_ERR(priv->base))
683 return PTR_ERR(priv->base);
685 nclks = info->num_total_core_clks + info->num_hw_mod_clks;
686 clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
690 dev_set_drvdata(dev, priv);
692 priv->num_core_clks = info->num_total_core_clks;
693 priv->num_mod_clks = info->num_hw_mod_clks;
694 priv->num_resets = info->num_resets;
695 priv->last_dt_core_clk = info->last_dt_core_clk;
697 for (i = 0; i < nclks; i++)
698 clks[i] = ERR_PTR(-ENOENT);
700 for (i = 0; i < info->num_core_clks; i++)
701 rzg2l_cpg_register_core_clk(&info->core_clks[i], info, priv);
703 for (i = 0; i < info->num_mod_clks; i++)
704 rzg2l_cpg_register_mod_clk(&info->mod_clks[i], info, priv);
706 error = of_clk_add_provider(np, rzg2l_cpg_clk_src_twocell_get, priv);
710 error = devm_add_action_or_reset(dev, rzg2l_cpg_del_clk_provider, np);
714 error = rzg2l_cpg_add_clk_domain(dev);
718 error = rzg2l_cpg_reset_controller_register(priv);
725 static const struct of_device_id rzg2l_cpg_match[] = {
726 #ifdef CONFIG_CLK_R9A07G044
728 .compatible = "renesas,r9a07g044-cpg",
729 .data = &r9a07g044_cpg_info,
735 static struct platform_driver rzg2l_cpg_driver = {
738 .of_match_table = rzg2l_cpg_match,
742 static int __init rzg2l_cpg_init(void)
744 return platform_driver_probe(&rzg2l_cpg_driver, rzg2l_cpg_probe);
747 subsys_initcall(rzg2l_cpg_init);
749 MODULE_DESCRIPTION("Renesas RZ/G2L CPG Driver");
750 MODULE_LICENSE("GPL v2");