drivers/clk/renesas/rzg2l-cpg.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * RZ/G2L Clock Pulse Generator
   4  *
   5  * Copyright (C) 2021 Renesas Electronics Corp.
   6  *
   7  * Based on renesas-cpg-mssr.c
   8  *
   9  * Copyright (C) 2015 Glider bvba
  10  * Copyright (C) 2013 Ideas On Board SPRL
  11  * Copyright (C) 2015 Renesas Electronics Corp.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/clk-provider.h>
  16 #include <linux/clk/renesas.h>
  17 #include <linux/delay.h>
  18 #include <linux/device.h>
  19 #include <linux/init.h>
  20 #include <linux/mod_devicetable.h>
  21 #include <linux/module.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_device.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/pm_clock.h>
  26 #include <linux/pm_domain.h>
  27 #include <linux/reset-controller.h>
  28 #include <linux/slab.h>
  29
  30 #include <dt-bindings/clock/renesas-cpg-mssr.h>
  31
  32 #include "rzg2l-cpg.h"
  33
  34 #ifdef DEBUG
  35 #define WARN_DEBUG(x)   WARN_ON(x)
  36 #else
  37 #define WARN_DEBUG(x)   do { } while (0)
  38 #endif
  39
  40 #define DIV_RSMASK(v, s, m)     ((v >> s) & m)
  41 #define GET_SHIFT(val)          ((val >> 12) & 0xff)
  42 #define GET_WIDTH(val)          ((val >> 8) & 0xf)
  43
  44 #define KDIV(val)               DIV_RSMASK(val, 16, 0xffff)
  45 #define MDIV(val)               DIV_RSMASK(val, 6, 0x3ff)
  46 #define PDIV(val)               DIV_RSMASK(val, 0, 0x3f)
  47 #define SDIV(val)               DIV_RSMASK(val, 0, 0x7)
  48
  49 #define CLK_ON_R(reg)           (reg)
  50 #define CLK_MON_R(reg)          (0x180 + (reg))
  51 #define CLK_RST_R(reg)          (reg)
  52 #define CLK_MRST_R(reg)         (0x180 + (reg))
  53
  54 #define GET_REG_OFFSET(val)             ((val >> 20) & 0xfff)
  55 #define GET_REG_SAMPLL_CLK1(val)        ((val >> 22) & 0xfff)
  56 #define GET_REG_SAMPLL_CLK2(val)        ((val >> 12) & 0xfff)
  57
  58 /**
  59  * struct rzg2l_cpg_priv - Clock Pulse Generator Private Data
  60  *
  61  * @rcdev: Reset controller entity
  62  * @dev: CPG device
  63  * @base: CPG register block base address
  64  * @rmw_lock: protects register accesses
  65  * @clks: Array containing all Core and Module Clocks
  66  * @num_core_clks: Number of Core Clocks in clks[]
  67  * @num_mod_clks: Number of Module Clocks in clks[]
  68  * @last_dt_core_clk: ID of the last Core Clock exported to DT
  69  * @notifiers: Notifier chain to save/restore clock state for system resume
  70  * @info: Pointer to platform data
  71  */
  72 struct rzg2l_cpg_priv {
  73         struct reset_controller_dev rcdev;
  74         struct device *dev;
  75         void __iomem *base;
  76         spinlock_t rmw_lock;
  77
  78         struct clk **clks;
  79         unsigned int num_core_clks;
  80         unsigned int num_mod_clks;
  81         unsigned int num_resets;
  82         unsigned int last_dt_core_clk;
  83
  84         struct raw_notifier_head notifiers;
  85         const struct rzg2l_cpg_info *info;
  86 };
  87
  88 static void rzg2l_cpg_del_clk_provider(void *data)
  89 {
  90         of_clk_del_provider(data);
  91 }
  92
  93 static struct clk * __init
  94 rzg2l_cpg_div_clk_register(const struct cpg_core_clk *core,
  95                            struct clk **clks,
  96                            void __iomem *base,
  97                            struct rzg2l_cpg_priv *priv)
  98 {
  99         struct device *dev = priv->dev;
 100         const struct clk *parent;
 101         const char *parent_name;
 102         struct clk_hw *clk_hw;
 103
 104         parent = clks[core->parent & 0xffff];
 105         if (IS_ERR(parent))
 106                 return ERR_CAST(parent);
 107
 108         parent_name = __clk_get_name(parent);
 109
 110         if (core->dtable)
 111                 clk_hw = clk_hw_register_divider_table(dev, core->name,
 112                                                        parent_name, 0,
 113                                                        base + GET_REG_OFFSET(core->conf),
 114                                                        GET_SHIFT(core->conf),
 115                                                        GET_WIDTH(core->conf),
 116                                                        core->flag,
 117                                                        core->dtable,
 118                                                        &priv->rmw_lock);
 119         else
 120                 clk_hw = clk_hw_register_divider(dev, core->name,
 121                                                  parent_name, 0,
 122                                                  base + GET_REG_OFFSET(core->conf),
 123                                                  GET_SHIFT(core->conf),
 124                                                  GET_WIDTH(core->conf),
 125                                                  core->flag, &priv->rmw_lock);
 126
 127         if (IS_ERR(clk_hw))
 128                 return ERR_CAST(clk_hw);
 129
 130         return clk_hw->clk;
 131 }
 132
 133 struct pll_clk {
 134         struct clk_hw hw;
 135         unsigned int conf;
 136         unsigned int type;
 137         void __iomem *base;
 138         struct rzg2l_cpg_priv *priv;
 139 };
 140
 141 #define to_pll(_hw)     container_of(_hw, struct pll_clk, hw)
 142
 143 static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
 144                                                    unsigned long parent_rate)
 145 {
 146         struct pll_clk *pll_clk = to_pll(hw);
 147         struct rzg2l_cpg_priv *priv = pll_clk->priv;
 148         unsigned int val1, val2;
 149         unsigned int mult = 1;
 150         unsigned int div = 1;
 151
 152         if (pll_clk->type != CLK_TYPE_SAM_PLL)
 153                 return parent_rate;
 154
 155         val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));
 156         val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf));
 157         mult = MDIV(val1) + KDIV(val1) / 65536;
 158         div = PDIV(val1) * (1 << SDIV(val2));
 159
 160         return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, div);
 161 }
 162
 163 static const struct clk_ops rzg2l_cpg_pll_ops = {
 164         .recalc_rate = rzg2l_cpg_pll_clk_recalc_rate,
 165 };
 166
 167 static struct clk * __init
 168 rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
 169                            struct clk **clks,
 170                            void __iomem *base,
 171                            struct rzg2l_cpg_priv *priv)
 172 {
 173         struct device *dev = priv->dev;
 174         const struct clk *parent;
 175         struct clk_init_data init;
 176         const char *parent_name;
 177         struct pll_clk *pll_clk;
 178
 179         parent = clks[core->parent & 0xffff];
 180         if (IS_ERR(parent))
 181                 return ERR_CAST(parent);
 182
 183         pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
 184         if (!pll_clk)
 185                 return ERR_PTR(-ENOMEM);
 186
 187         parent_name = __clk_get_name(parent);
 188         init.name = core->name;
 189         init.ops = &rzg2l_cpg_pll_ops;
 190         init.flags = 0;
 191         init.parent_names = &parent_name;
 192         init.num_parents = 1;
 193
 194         pll_clk->hw.init = &init;
 195         pll_clk->conf = core->conf;
 196         pll_clk->base = base;
 197         pll_clk->priv = priv;
 198         pll_clk->type = core->type;
 199
 200         return clk_register(NULL, &pll_clk->hw);
 201 }
 202
 203 static struct clk
 204 *rzg2l_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
 205                                void *data)
 206 {
 207         unsigned int clkidx = clkspec->args[1];
 208         struct rzg2l_cpg_priv *priv = data;
 209         struct device *dev = priv->dev;
 210         const char *type;
 211         struct clk *clk;
 212
 213         switch (clkspec->args[0]) {
 214         case CPG_CORE:
 215                 type = "core";
 216                 if (clkidx > priv->last_dt_core_clk) {
 217                         dev_err(dev, "Invalid %s clock index %u\n", type, clkidx);
 218                         return ERR_PTR(-EINVAL);
 219                 }
 220                 clk = priv->clks[clkidx];
 221                 break;
 222
 223         case CPG_MOD:
 224                 type = "module";
 225                 if (clkidx >= priv->num_mod_clks) {
 226                         dev_err(dev, "Invalid %s clock index %u\n", type,
 227                                 clkidx);
 228                         return ERR_PTR(-EINVAL);
 229                 }
 230                 clk = priv->clks[priv->num_core_clks + clkidx];
 231                 break;
 232
 233         default:
 234                 dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
 235                 return ERR_PTR(-EINVAL);
 236         }
 237
 238         if (IS_ERR(clk))
 239                 dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
 240                         PTR_ERR(clk));
 241         else
 242                 dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
 243                         clkspec->args[0], clkspec->args[1], clk,
 244                         clk_get_rate(clk));
 245         return clk;
 246 }
 247
 248 static void __init
 249 rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
 250                             const struct rzg2l_cpg_info *info,
 251                             struct rzg2l_cpg_priv *priv)
 252 {
 253         struct clk *clk = ERR_PTR(-EOPNOTSUPP), *parent;
 254         struct device *dev = priv->dev;
 255         unsigned int id = core->id, div = core->div;
 256         const char *parent_name;
 257
 258         WARN_DEBUG(id >= priv->num_core_clks);
 259         WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
 260
 261         if (!core->name) {
 262                 /* Skip NULLified clock */
 263                 return;
 264         }
 265
 266         switch (core->type) {
 267         case CLK_TYPE_IN:
 268                 clk = of_clk_get_by_name(priv->dev->of_node, core->name);
 269                 break;
 270         case CLK_TYPE_FF:
 271                 WARN_DEBUG(core->parent >= priv->num_core_clks);
 272                 parent = priv->clks[core->parent];
 273                 if (IS_ERR(parent)) {
 274                         clk = parent;
 275                         goto fail;
 276                 }
 277
 278                 parent_name = __clk_get_name(parent);
 279                 clk = clk_register_fixed_factor(NULL, core->name,
 280                                                 parent_name, CLK_SET_RATE_PARENT,
 281                                                 core->mult, div);
 282                 break;
 283         case CLK_TYPE_SAM_PLL:
 284                 clk = rzg2l_cpg_pll_clk_register(core, priv->clks,
 285                                                  priv->base, priv);
 286                 break;
 287         case CLK_TYPE_DIV:
 288                 clk = rzg2l_cpg_div_clk_register(core, priv->clks,
 289                                                  priv->base, priv);
 290                 break;
 291         default:
 292                 goto fail;
 293         }
 294
 295         if (IS_ERR_OR_NULL(clk))
 296                 goto fail;
 297
 298         dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
 299         priv->clks[id] = clk;
 300         return;
 301
 302 fail:
 303         dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
 304                 core->name, PTR_ERR(clk));
 305 }
 306
 307 /**
 308  * struct mstp_clock - MSTP gating clock
 309  *
 310  * @hw: handle between common and hardware-specific interfaces
 311  * @off: register offset
 312  * @bit: ON/MON bit
 313  * @priv: CPG/MSTP private data
 314  */
 315 struct mstp_clock {
 316         struct clk_hw hw;
 317         u16 off;
 318         u8 bit;
 319         struct rzg2l_cpg_priv *priv;
 320 };
 321
 322 #define to_mod_clock(_hw) container_of(_hw, struct mstp_clock, hw)
 323
 324 static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
 325 {
 326         struct mstp_clock *clock = to_mod_clock(hw);
 327         struct rzg2l_cpg_priv *priv = clock->priv;
 328         unsigned int reg = clock->off;
 329         struct device *dev = priv->dev;
 330         unsigned long flags;
 331         unsigned int i;
 332         u32 bitmask = BIT(clock->bit);
 333         u32 value;
 334
 335         if (!clock->off) {
 336                 dev_dbg(dev, "%pC does not support ON/OFF\n",  hw->clk);
 337                 return 0;
 338         }
 339
 340         dev_dbg(dev, "CLK_ON %u/%pC %s\n", CLK_ON_R(reg), hw->clk,
 341                 enable ? "ON" : "OFF");
 342         spin_lock_irqsave(&priv->rmw_lock, flags);
 343
 344         if (enable)
 345                 value = (bitmask << 16) | bitmask;
 346         else
 347                 value = bitmask << 16;
 348         writel(value, priv->base + CLK_ON_R(reg));
 349
 350         spin_unlock_irqrestore(&priv->rmw_lock, flags);
 351
 352         if (!enable)
 353                 return 0;
 354
 355         for (i = 1000; i > 0; --i) {
 356                 if (((readl(priv->base + CLK_MON_R(reg))) & bitmask))
 357                         break;
 358                 cpu_relax();
 359         }
 360
 361         if (!i) {
 362                 dev_err(dev, "Failed to enable CLK_ON %p\n",
 363                         priv->base + CLK_ON_R(reg));
 364                 return -ETIMEDOUT;
 365         }
 366
 367         return 0;
 368 }
 369
 370 static int rzg2l_mod_clock_enable(struct clk_hw *hw)
 371 {
 372         return rzg2l_mod_clock_endisable(hw, true);
 373 }
 374
 375 static void rzg2l_mod_clock_disable(struct clk_hw *hw)
 376 {
 377         rzg2l_mod_clock_endisable(hw, false);
 378 }
 379
 380 static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
 381 {
 382         struct mstp_clock *clock = to_mod_clock(hw);
 383         struct rzg2l_cpg_priv *priv = clock->priv;
 384         u32 bitmask = BIT(clock->bit);
 385         u32 value;
 386
 387         if (!clock->off) {
 388                 dev_dbg(priv->dev, "%pC does not support ON/OFF\n",  hw->clk);
 389                 return 1;
 390         }
 391
 392         value = readl(priv->base + CLK_MON_R(clock->off));
 393
 394         return value & bitmask;
 395 }
 396
 397 static const struct clk_ops rzg2l_mod_clock_ops = {
 398         .enable = rzg2l_mod_clock_enable,
 399         .disable = rzg2l_mod_clock_disable,
 400         .is_enabled = rzg2l_mod_clock_is_enabled,
 401 };
 402
 403 static void __init
 404 rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod,
 405                            const struct rzg2l_cpg_info *info,
 406                            struct rzg2l_cpg_priv *priv)
 407 {
 408         struct mstp_clock *clock = NULL;
 409         struct device *dev = priv->dev;
 410         unsigned int id = mod->id;
 411         struct clk_init_data init;
 412         struct clk *parent, *clk;
 413         const char *parent_name;
 414         unsigned int i;
 415
 416         WARN_DEBUG(id < priv->num_core_clks);
 417         WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
 418         WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
 419         WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
 420
 421         if (!mod->name) {
 422                 /* Skip NULLified clock */
 423                 return;
 424         }
 425
 426         parent = priv->clks[mod->parent];
 427         if (IS_ERR(parent)) {
 428                 clk = parent;
 429                 goto fail;
 430         }
 431
 432         clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL);
 433         if (!clock) {
 434                 clk = ERR_PTR(-ENOMEM);
 435                 goto fail;
 436         }
 437
 438         init.name = mod->name;
 439         init.ops = &rzg2l_mod_clock_ops;
 440         init.flags = CLK_SET_RATE_PARENT;
 441         for (i = 0; i < info->num_crit_mod_clks; i++)
 442                 if (id == info->crit_mod_clks[i]) {
 443                         dev_dbg(dev, "CPG %s setting CLK_IS_CRITICAL\n",
 444                                 mod->name);
 445                         init.flags |= CLK_IS_CRITICAL;
 446                         break;
 447                 }
 448
 449         parent_name = __clk_get_name(parent);
 450         init.parent_names = &parent_name;
 451         init.num_parents = 1;
 452
 453         clock->off = mod->off;
 454         clock->bit = mod->bit;
 455         clock->priv = priv;
 456         clock->hw.init = &init;
 457
 458         clk = clk_register(NULL, &clock->hw);
 459         if (IS_ERR(clk))
 460                 goto fail;
 461
 462         dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
 463         priv->clks[id] = clk;
 464         return;
 465
 466 fail:
 467         dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
 468                 mod->name, PTR_ERR(clk));
 469 }
 470
 471 #define rcdev_to_priv(x)        container_of(x, struct rzg2l_cpg_priv, rcdev)
 472
 473 static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
 474                            unsigned long id)
 475 {
 476         struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
 477         const struct rzg2l_cpg_info *info = priv->info;
 478         unsigned int reg = info->resets[id].off;
 479         u32 dis = BIT(info->resets[id].bit);
 480         u32 we = dis << 16;
 481
 482         dev_dbg(rcdev->dev, "reset id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
 483
 484         /* Reset module */
 485         writel(we, priv->base + CLK_RST_R(reg));
 486
 487         /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
 488         udelay(35);
 489
 490         /* Release module from reset state */
 491         writel(we | dis, priv->base + CLK_RST_R(reg));
 492
 493         return 0;
 494 }
 495
 496 static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
 497                             unsigned long id)
 498 {
 499         struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
 500         const struct rzg2l_cpg_info *info = priv->info;
 501         unsigned int reg = info->resets[id].off;
 502         u32 value = BIT(info->resets[id].bit) << 16;
 503
 504         dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
 505
 506         writel(value, priv->base + CLK_RST_R(reg));
 507         return 0;
 508 }
 509
 510 static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,
 511                               unsigned long id)
 512 {
 513         struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
 514         const struct rzg2l_cpg_info *info = priv->info;
 515         unsigned int reg = info->resets[id].off;
 516         u32 dis = BIT(info->resets[id].bit);
 517         u32 value = (dis << 16) | dis;
 518
 519         dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id,
 520                 CLK_RST_R(reg));
 521
 522         writel(value, priv->base + CLK_RST_R(reg));
 523         return 0;
 524 }
 525
 526 static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
 527                             unsigned long id)
 528 {
 529         struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
 530         const struct rzg2l_cpg_info *info = priv->info;
 531         unsigned int reg = info->resets[id].off;
 532         u32 bitmask = BIT(info->resets[id].bit);
 533
 534         return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
 535 }
 536
 537 static const struct reset_control_ops rzg2l_cpg_reset_ops = {
 538         .reset = rzg2l_cpg_reset,
 539         .assert = rzg2l_cpg_assert,
 540         .deassert = rzg2l_cpg_deassert,
 541         .status = rzg2l_cpg_status,
 542 };
 543
 544 static int rzg2l_cpg_reset_xlate(struct reset_controller_dev *rcdev,
 545                                  const struct of_phandle_args *reset_spec)
 546 {
 547         struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
 548         const struct rzg2l_cpg_info *info = priv->info;
 549         unsigned int id = reset_spec->args[0];
 550
 551         if (id >= rcdev->nr_resets || !info->resets[id].off) {
 552                 dev_err(rcdev->dev, "Invalid reset index %u\n", id);
 553                 return -EINVAL;
 554         }
 555
 556         return id;
 557 }
 558
 559 static int rzg2l_cpg_reset_controller_register(struct rzg2l_cpg_priv *priv)
 560 {
 561         priv->rcdev.ops = &rzg2l_cpg_reset_ops;
 562         priv->rcdev.of_node = priv->dev->of_node;
 563         priv->rcdev.dev = priv->dev;
 564         priv->rcdev.of_reset_n_cells = 1;
 565         priv->rcdev.of_xlate = rzg2l_cpg_reset_xlate;
 566         priv->rcdev.nr_resets = priv->num_resets;
 567
 568         return devm_reset_controller_register(priv->dev, &priv->rcdev);
 569 }
 570
 571 static bool rzg2l_cpg_is_pm_clk(const struct of_phandle_args *clkspec)
 572 {
 573         if (clkspec->args_count != 2)
 574                 return false;
 575
 576         switch (clkspec->args[0]) {
 577         case CPG_MOD:
 578                 return true;
 579
 580         default:
 581                 return false;
 582         }
 583 }
 584
 585 static int rzg2l_cpg_attach_dev(struct generic_pm_domain *unused, struct device *dev)
 586 {
 587         struct device_node *np = dev->of_node;
 588         struct of_phandle_args clkspec;
 589         bool once = true;
 590         struct clk *clk;
 591         int error;
 592         int i = 0;
 593
 594         while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
 595                                            &clkspec)) {
 596                 if (rzg2l_cpg_is_pm_clk(&clkspec)) {
 597                         if (once) {
 598                                 once = false;
 599                                 error = pm_clk_create(dev);
 600                                 if (error) {
 601                                         of_node_put(clkspec.np);
 602                                         goto err;
 603                                 }
 604                         }
 605                         clk = of_clk_get_from_provider(&clkspec);
 606                         of_node_put(clkspec.np);
 607                         if (IS_ERR(clk)) {
 608                                 error = PTR_ERR(clk);
 609                                 goto fail_destroy;
 610                         }
 611
 612                         error = pm_clk_add_clk(dev, clk);
 613                         if (error) {
 614                                 dev_err(dev, "pm_clk_add_clk failed %d\n",
 615                                         error);
 616                                 goto fail_put;
 617                         }
 618                 } else {
 619                         of_node_put(clkspec.np);
 620                 }
 621                 i++;
 622         }
 623
 624         return 0;
 625
 626 fail_put:
 627         clk_put(clk);
 628
 629 fail_destroy:
 630         pm_clk_destroy(dev);
 631 err:
 632         return error;
 633 }
 634
 635 static void rzg2l_cpg_detach_dev(struct generic_pm_domain *unused, struct device *dev)
 636 {
 637         if (!pm_clk_no_clocks(dev))
 638                 pm_clk_destroy(dev);
 639 }
 640
 641 static int __init rzg2l_cpg_add_clk_domain(struct device *dev)
 642 {
 643         struct device_node *np = dev->of_node;
 644         struct generic_pm_domain *genpd;
 645
 646         genpd = devm_kzalloc(dev, sizeof(*genpd), GFP_KERNEL);
 647         if (!genpd)
 648                 return -ENOMEM;
 649
 650         genpd->name = np->name;
 651         genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
 652                        GENPD_FLAG_ACTIVE_WAKEUP;
 653         genpd->attach_dev = rzg2l_cpg_attach_dev;
 654         genpd->detach_dev = rzg2l_cpg_detach_dev;
 655         pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
 656
 657         of_genpd_add_provider_simple(np, genpd);
 658         return 0;
 659 }
 660
 661 static int __init rzg2l_cpg_probe(struct platform_device *pdev)
 662 {
 663         struct device *dev = &pdev->dev;
 664         struct device_node *np = dev->of_node;
 665         const struct rzg2l_cpg_info *info;
 666         struct rzg2l_cpg_priv *priv;
 667         unsigned int nclks, i;
 668         struct clk **clks;
 669         int error;
 670
 671         info = of_device_get_match_data(dev);
 672
 673         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 674         if (!priv)
 675                 return -ENOMEM;
 676
 677         priv->dev = dev;
 678         priv->info = info;
 679         spin_lock_init(&priv->rmw_lock);
 680
 681         priv->base = devm_platform_ioremap_resource(pdev, 0);
 682         if (IS_ERR(priv->base))
 683                 return PTR_ERR(priv->base);
 684
 685         nclks = info->num_total_core_clks + info->num_hw_mod_clks;
 686         clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
 687         if (!clks)
 688                 return -ENOMEM;
 689
 690         dev_set_drvdata(dev, priv);
 691         priv->clks = clks;
 692         priv->num_core_clks = info->num_total_core_clks;
 693         priv->num_mod_clks = info->num_hw_mod_clks;
 694         priv->num_resets = info->num_resets;
 695         priv->last_dt_core_clk = info->last_dt_core_clk;
 696
 697         for (i = 0; i < nclks; i++)
 698                 clks[i] = ERR_PTR(-ENOENT);
 699
 700         for (i = 0; i < info->num_core_clks; i++)
 701                 rzg2l_cpg_register_core_clk(&info->core_clks[i], info, priv);
 702
 703         for (i = 0; i < info->num_mod_clks; i++)
 704                 rzg2l_cpg_register_mod_clk(&info->mod_clks[i], info, priv);
 705
 706         error = of_clk_add_provider(np, rzg2l_cpg_clk_src_twocell_get, priv);
 707         if (error)
 708                 return error;
 709
 710         error = devm_add_action_or_reset(dev, rzg2l_cpg_del_clk_provider, np);
 711         if (error)
 712                 return error;
 713
 714         error = rzg2l_cpg_add_clk_domain(dev);
 715         if (error)
 716                 return error;
 717
 718         error = rzg2l_cpg_reset_controller_register(priv);
 719         if (error)
 720                 return error;
 721
 722         return 0;
 723 }
 724
 725 static const struct of_device_id rzg2l_cpg_match[] = {
 726 #ifdef CONFIG_CLK_R9A07G044
 727         {
 728                 .compatible = "renesas,r9a07g044-cpg",
 729                 .data = &r9a07g044_cpg_info,
 730         },
 731 #endif
 732         { /* sentinel */ }
 733 };
 734
 735 static struct platform_driver rzg2l_cpg_driver = {
 736         .driver         = {
 737                 .name   = "rzg2l-cpg",
 738                 .of_match_table = rzg2l_cpg_match,
 739         },
 740 };
 741
 742 static int __init rzg2l_cpg_init(void)
 743 {
 744         return platform_driver_probe(&rzg2l_cpg_driver, rzg2l_cpg_probe);
 745 }
 746
 747 subsys_initcall(rzg2l_cpg_init);
 748
 749 MODULE_DESCRIPTION("Renesas RZ/G2L CPG Driver");
 750 MODULE_LICENSE("GPL v2");