1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Renesas Clock Pulse Generator / Module Standby and Software Reset
5 * Copyright (C) 2015 Glider bvba
8 #ifndef __CLK_RENESAS_CPG_MSSR_H__
9 #define __CLK_RENESAS_CPG_MSSR_H__
12 * Definitions of CPG Core Clocks
15 * - Clock outputs exported to DT
16 * - External input clocks
17 * - Internal CPG clocks
25 /* Depending on type */
26 unsigned int parent; /* Core Clocks only */
34 CLK_TYPE_IN, /* External Clock Input */
35 CLK_TYPE_FF, /* Fixed Factor Clock */
36 CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
37 CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
39 /* Custom definitions start here */
43 #define DEF_TYPE(_name, _id, _type...) \
44 { .name = _name, .id = _id, .type = _type }
45 #define DEF_BASE(_name, _id, _type, _parent...) \
46 DEF_TYPE(_name, _id, _type, .parent = _parent)
48 #define DEF_INPUT(_name, _id) \
49 DEF_TYPE(_name, _id, CLK_TYPE_IN)
50 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \
51 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
52 #define DEF_DIV6P1(_name, _id, _parent, _offset) \
53 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
54 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
55 DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
58 * Definitions of Module Clocks
64 unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */
67 /* Convert from sparse base-100 to packed index space */
68 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
70 #define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))
72 #define DEF_MOD(_name, _mod, _parent...) \
73 { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
79 * SoC-specific CPG/MSSR Description
81 * @core_clks: Array of Core Clock definitions
82 * @num_core_clks: Number of entries in core_clks[]
83 * @last_dt_core_clk: ID of the last Core Clock exported to DT
84 * @num_total_core_clks: Total number of Core Clocks (exported + internal)
86 * @mod_clks: Array of Module Clock definitions
87 * @num_mod_clks: Number of entries in mod_clks[]
88 * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
90 * @crit_mod_clks: Array with Module Clock IDs of critical clocks that
91 * should not be disabled without a knowledgeable driver
92 * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
94 * @core_pm_clks: Array with IDs of Core Clocks that are suitable for Power
95 * Management, in addition to Module Clocks
96 * @num_core_pm_clks: Number of entries in core_pm_clks[]
98 * @init: Optional callback to perform SoC-specific initialization
99 * @cpg_clk_register: Optional callback to handle special Core Clock types
102 struct cpg_mssr_info {
104 const struct cpg_core_clk *core_clks;
105 unsigned int num_core_clks;
106 unsigned int last_dt_core_clk;
107 unsigned int num_total_core_clks;
110 const struct mssr_mod_clk *mod_clks;
111 unsigned int num_mod_clks;
112 unsigned int num_hw_mod_clks;
114 /* Critical Module Clocks that should not be disabled */
115 const unsigned int *crit_mod_clks;
116 unsigned int num_crit_mod_clks;
118 /* Core Clocks suitable for PM, in addition to the Module Clocks */
119 const unsigned int *core_pm_clks;
120 unsigned int num_core_pm_clks;
123 int (*init)(struct device *dev);
124 struct clk *(*cpg_clk_register)(struct device *dev,
125 const struct cpg_core_clk *core,
126 const struct cpg_mssr_info *info,
127 struct clk **clks, void __iomem *base,
128 struct raw_notifier_head *notifiers);
131 extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
132 extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
133 extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;
134 extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
135 extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;
136 extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
137 extern const struct cpg_mssr_info r8a7794_cpg_mssr_info;
138 extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
139 extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
140 extern const struct cpg_mssr_info r8a77965_cpg_mssr_info;
141 extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
142 extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
143 extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
144 extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
148 * Helpers for fixing up clock tables depending on SoC revision
151 struct mssr_mod_reparent {
152 unsigned int clk, parent;
156 extern void cpg_core_nullify_range(struct cpg_core_clk *core_clks,
157 unsigned int num_core_clks,
158 unsigned int first_clk,
159 unsigned int last_clk);
160 extern void mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
161 unsigned int num_mod_clks,
162 const unsigned int *clks, unsigned int n);
163 extern void mssr_mod_reparent(struct mssr_mod_clk *mod_clks,
164 unsigned int num_mod_clks,
165 const struct mssr_mod_reparent *clks,