1 /* SPDX-License-Identifier: GPL-2.0 */
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
6 * Copyright (C) 2018 Renesas Electronics Corp.
10 #ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
11 #define __CLK_RENESAS_RCAR_GEN3_CPG_H__
13 enum rcar_gen3_clk_types {
14 CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
22 CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
24 CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
25 CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
27 CLK_TYPE_GEN3_E3_RPCSRC,
31 /* SoC specific definitions start here */
32 CLK_TYPE_GEN3_SOC_BASE,
35 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \
36 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
38 #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
39 DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
40 (_parent0) << 16 | (_parent1), \
41 .div = (_div0) << 16 | (_div1), .offset = _md)
43 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
45 DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
46 _parent_clean, _div_clean)
48 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \
49 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
51 #define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
52 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
53 (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
55 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \
56 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
58 #define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \
59 DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \
60 (_parent0) << 16 | (_parent1), .div = 8)
62 struct rcar_gen3_cpg_pll_config {
71 #define CPG_RPCCKCR 0x238
72 #define CPG_RCKCR 0x240
74 struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
75 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
76 struct clk **clks, void __iomem *base,
77 struct raw_notifier_head *notifiers);
78 int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
79 unsigned int clk_extalr, u32 mode);