1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
7 * Based on clk-rcar-gen3.c
9 * Copyright (C) 2015 Renesas Electronics Corp.
12 #include <linux/bug.h>
13 #include <linux/bitfield.h>
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16 #include <linux/device.h>
17 #include <linux/err.h>
18 #include <linux/init.h>
21 #include <linux/slab.h>
22 #include <linux/sys_soc.h>
24 #include "renesas-cpg-mssr.h"
25 #include "rcar-gen3-cpg.h"
27 #define CPG_PLL0CR 0x00d8
28 #define CPG_PLL2CR 0x002c
29 #define CPG_PLL4CR 0x01f4
31 #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
33 struct cpg_simple_notifier {
34 struct notifier_block nb;
39 static int cpg_simple_notifier_call(struct notifier_block *nb,
40 unsigned long action, void *data)
42 struct cpg_simple_notifier *csn =
43 container_of(nb, struct cpg_simple_notifier, nb);
46 case PM_EVENT_SUSPEND:
47 csn->saved = readl(csn->reg);
51 writel(csn->saved, csn->reg);
57 static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
58 struct cpg_simple_notifier *csn)
60 csn->nb.notifier_call = cpg_simple_notifier_call;
61 raw_notifier_chain_register(notifiers, &csn->nb);
67 * Traits of this clock:
68 * prepare - clk_prepare only ensures that parents are prepared
69 * enable - clk_enable only ensures that parents are enabled
70 * rate - rate is adjustable. clk->rate = (parent->rate * mult / 32 ) / 2
71 * parent - fixed parent. No clk_set_parent support
73 #define CPG_FRQCRB 0x00000004
74 #define CPG_FRQCRB_KICK BIT(31)
75 #define CPG_FRQCRC 0x000000e0
76 #define CPG_FRQCRC_ZFC_MASK GENMASK(12, 8)
77 #define CPG_FRQCRC_Z2FC_MASK GENMASK(4, 0)
82 void __iomem *kick_reg;
86 #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
88 static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
89 unsigned long parent_rate)
91 struct cpg_z_clk *zclk = to_z_clk(hw);
95 val = readl(zclk->reg) & zclk->mask;
96 mult = 32 - (val >> __ffs(zclk->mask));
98 /* Factor of 2 is for fixed divider */
99 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * 2);
102 static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
103 unsigned long *parent_rate)
105 /* Factor of 2 is for fixed divider */
106 unsigned long prate = *parent_rate / 2;
109 mult = div_u64(rate * 32ULL, prate);
110 mult = clamp(mult, 1U, 32U);
112 return (u64)prate * mult / 32;
115 static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
116 unsigned long parent_rate)
118 struct cpg_z_clk *zclk = to_z_clk(hw);
123 /* Factor of 2 is for fixed divider */
124 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate);
125 mult = clamp(mult, 1U, 32U);
127 if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
130 val = readl(zclk->reg) & ~zclk->mask;
131 val |= ((32 - mult) << __ffs(zclk->mask)) & zclk->mask;
132 writel(val, zclk->reg);
135 * Set KICK bit in FRQCRB to update hardware setting and wait for
136 * clock change completion.
138 kick = readl(zclk->kick_reg);
139 kick |= CPG_FRQCRB_KICK;
140 writel(kick, zclk->kick_reg);
143 * Note: There is no HW information about the worst case latency.
145 * Using experimental measurements, it seems that no more than
146 * ~10 iterations are needed, independently of the CPU rate.
147 * Since this value might be dependent of external xtal rate, pll1
148 * rate or even the other emulation clocks rate, use 1000 as a
149 * "super" safe value.
151 for (i = 1000; i; i--) {
152 if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
161 static const struct clk_ops cpg_z_clk_ops = {
162 .recalc_rate = cpg_z_clk_recalc_rate,
163 .round_rate = cpg_z_clk_round_rate,
164 .set_rate = cpg_z_clk_set_rate,
167 static struct clk * __init cpg_z_clk_register(const char *name,
168 const char *parent_name,
172 struct clk_init_data init;
173 struct cpg_z_clk *zclk;
176 zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
178 return ERR_PTR(-ENOMEM);
181 init.ops = &cpg_z_clk_ops;
183 init.parent_names = &parent_name;
184 init.num_parents = 1;
186 zclk->reg = reg + CPG_FRQCRC;
187 zclk->kick_reg = reg + CPG_FRQCRB;
188 zclk->hw.init = &init;
191 clk = clk_register(NULL, &zclk->hw);
201 #define CPG_SD_STP_HCK BIT(9)
202 #define CPG_SD_STP_CK BIT(8)
204 #define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
205 #define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
207 #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
209 .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
210 ((stp_ck) ? CPG_SD_STP_CK : 0) | \
211 ((sd_srcfc) << 2) | \
216 struct sd_div_table {
223 const struct sd_div_table *div_table;
224 struct cpg_simple_notifier csn;
225 unsigned int div_num;
226 unsigned int div_min;
227 unsigned int div_max;
228 unsigned int cur_div_idx;
233 * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
234 *-------------------------------------------------------------------
235 * 0 0 0 (1) 1 (4) 4 : SDR104 / HS200 / HS400 (8 TAP)
236 * 0 0 1 (2) 1 (4) 8 : SDR50
237 * 1 0 2 (4) 1 (4) 16 : HS / SDR25
238 * 1 0 3 (8) 1 (4) 32 : NS / SDR12
239 * 1 0 4 (16) 1 (4) 64
241 * 0 0 1 (2) 0 (2) 4 : SDR104 / HS200 / HS400 (4 TAP)
244 * 1 0 4 (16) 0 (2) 32
246 * NOTE: There is a quirk option to ignore the first row of the dividers
247 * table when searching for suitable settings. This is because HS400 on
248 * early ES versions of H3 and M3-W requires a specific setting to work.
250 static const struct sd_div_table cpg_sd_div_table[] = {
251 /* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
252 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
253 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
254 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
255 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
256 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
257 CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
258 CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
259 CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
260 CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
261 CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
264 #define to_sd_clock(_hw) container_of(_hw, struct sd_clock, hw)
266 static int cpg_sd_clock_enable(struct clk_hw *hw)
268 struct sd_clock *clock = to_sd_clock(hw);
269 u32 val = readl(clock->csn.reg);
271 val &= ~(CPG_SD_STP_MASK);
272 val |= clock->div_table[clock->cur_div_idx].val & CPG_SD_STP_MASK;
274 writel(val, clock->csn.reg);
279 static void cpg_sd_clock_disable(struct clk_hw *hw)
281 struct sd_clock *clock = to_sd_clock(hw);
283 writel(readl(clock->csn.reg) | CPG_SD_STP_MASK, clock->csn.reg);
286 static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
288 struct sd_clock *clock = to_sd_clock(hw);
290 return !(readl(clock->csn.reg) & CPG_SD_STP_MASK);
293 static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
294 unsigned long parent_rate)
296 struct sd_clock *clock = to_sd_clock(hw);
298 return DIV_ROUND_CLOSEST(parent_rate,
299 clock->div_table[clock->cur_div_idx].div);
302 static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock,
304 unsigned long parent_rate)
311 div = DIV_ROUND_CLOSEST(parent_rate, rate);
313 return clamp_t(unsigned int, div, clock->div_min, clock->div_max);
316 static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
317 unsigned long *parent_rate)
319 struct sd_clock *clock = to_sd_clock(hw);
320 unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate);
322 return DIV_ROUND_CLOSEST(*parent_rate, div);
325 static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
326 unsigned long parent_rate)
328 struct sd_clock *clock = to_sd_clock(hw);
329 unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
333 for (i = 0; i < clock->div_num; i++)
334 if (div == clock->div_table[i].div)
337 if (i >= clock->div_num)
340 clock->cur_div_idx = i;
342 val = readl(clock->csn.reg);
343 val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK);
344 val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK);
345 writel(val, clock->csn.reg);
350 static const struct clk_ops cpg_sd_clock_ops = {
351 .enable = cpg_sd_clock_enable,
352 .disable = cpg_sd_clock_disable,
353 .is_enabled = cpg_sd_clock_is_enabled,
354 .recalc_rate = cpg_sd_clock_recalc_rate,
355 .round_rate = cpg_sd_clock_round_rate,
356 .set_rate = cpg_sd_clock_set_rate,
359 static u32 cpg_quirks __initdata;
361 #define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */
362 #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
363 #define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */
365 static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
366 void __iomem *base, const char *parent_name,
367 struct raw_notifier_head *notifiers)
369 struct clk_init_data init;
370 struct sd_clock *clock;
375 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
377 return ERR_PTR(-ENOMEM);
379 init.name = core->name;
380 init.ops = &cpg_sd_clock_ops;
381 init.flags = CLK_SET_RATE_PARENT;
382 init.parent_names = &parent_name;
383 init.num_parents = 1;
385 clock->csn.reg = base + core->offset;
386 clock->hw.init = &init;
387 clock->div_table = cpg_sd_div_table;
388 clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
390 if (cpg_quirks & SD_SKIP_FIRST) {
395 val = readl(clock->csn.reg) & ~CPG_SD_FC_MASK;
396 val |= CPG_SD_STP_MASK | (clock->div_table[0].val & CPG_SD_FC_MASK);
397 writel(val, clock->csn.reg);
399 clock->div_max = clock->div_table[0].div;
400 clock->div_min = clock->div_max;
401 for (i = 1; i < clock->div_num; i++) {
402 clock->div_max = max(clock->div_max, clock->div_table[i].div);
403 clock->div_min = min(clock->div_min, clock->div_table[i].div);
406 clk = clk_register(NULL, &clock->hw);
410 cpg_simple_notifier_register(notifiers, &clock->csn);
419 static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
420 static unsigned int cpg_clk_extalr __initdata;
421 static u32 cpg_mode __initdata;
423 static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
425 .soc_id = "r8a7795", .revision = "ES1.0",
426 .data = (void *)(PLL_ERRATA | RCKCR_CKSEL | SD_SKIP_FIRST),
429 .soc_id = "r8a7795", .revision = "ES1.*",
430 .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST),
433 .soc_id = "r8a7795", .revision = "ES2.0",
434 .data = (void *)SD_SKIP_FIRST,
437 .soc_id = "r8a7796", .revision = "ES1.0",
438 .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST),
441 .soc_id = "r8a7796", .revision = "ES1.1",
442 .data = (void *)SD_SKIP_FIRST,
447 struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
448 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
449 struct clk **clks, void __iomem *base,
450 struct raw_notifier_head *notifiers)
452 const struct clk *parent;
453 unsigned int mult = 1;
454 unsigned int div = 1;
457 parent = clks[core->parent & 0xffff]; /* some types use high bits */
459 return ERR_CAST(parent);
461 switch (core->type) {
462 case CLK_TYPE_GEN3_MAIN:
463 div = cpg_pll_config->extal_div;
466 case CLK_TYPE_GEN3_PLL0:
468 * PLL0 is a configurable multiplier clock. Register it as a
469 * fixed factor clock for now as there's no generic multiplier
470 * clock implementation and we currently have no need to change
471 * the multiplier value.
473 value = readl(base + CPG_PLL0CR);
474 mult = (((value >> 24) & 0x7f) + 1) * 2;
475 if (cpg_quirks & PLL_ERRATA)
479 case CLK_TYPE_GEN3_PLL1:
480 mult = cpg_pll_config->pll1_mult;
481 div = cpg_pll_config->pll1_div;
484 case CLK_TYPE_GEN3_PLL2:
486 * PLL2 is a configurable multiplier clock. Register it as a
487 * fixed factor clock for now as there's no generic multiplier
488 * clock implementation and we currently have no need to change
489 * the multiplier value.
491 value = readl(base + CPG_PLL2CR);
492 mult = (((value >> 24) & 0x7f) + 1) * 2;
493 if (cpg_quirks & PLL_ERRATA)
497 case CLK_TYPE_GEN3_PLL3:
498 mult = cpg_pll_config->pll3_mult;
499 div = cpg_pll_config->pll3_div;
502 case CLK_TYPE_GEN3_PLL4:
504 * PLL4 is a configurable multiplier clock. Register it as a
505 * fixed factor clock for now as there's no generic multiplier
506 * clock implementation and we currently have no need to change
507 * the multiplier value.
509 value = readl(base + CPG_PLL4CR);
510 mult = (((value >> 24) & 0x7f) + 1) * 2;
511 if (cpg_quirks & PLL_ERRATA)
515 case CLK_TYPE_GEN3_SD:
516 return cpg_sd_clk_register(core, base, __clk_get_name(parent),
519 case CLK_TYPE_GEN3_R:
520 if (cpg_quirks & RCKCR_CKSEL) {
521 struct cpg_simple_notifier *csn;
523 csn = kzalloc(sizeof(*csn), GFP_KERNEL);
525 return ERR_PTR(-ENOMEM);
527 csn->reg = base + CPG_RCKCR;
531 * Only if EXTALR is populated, we switch to it.
533 value = readl(csn->reg) & 0x3f;
535 if (clk_get_rate(clks[cpg_clk_extalr])) {
536 parent = clks[cpg_clk_extalr];
537 value |= CPG_RCKCR_CKSEL;
540 writel(value, csn->reg);
541 cpg_simple_notifier_register(notifiers, csn);
545 /* Select parent clock of RCLK by MD28 */
546 if (cpg_mode & BIT(28))
547 parent = clks[cpg_clk_extalr];
550 case CLK_TYPE_GEN3_MDSEL:
552 * Clock selectable between two parents and two fixed dividers
555 if (cpg_mode & BIT(core->offset)) {
556 div = core->div & 0xffff;
558 parent = clks[core->parent >> 16];
560 return ERR_CAST(parent);
561 div = core->div >> 16;
566 case CLK_TYPE_GEN3_Z:
567 return cpg_z_clk_register(core->name, __clk_get_name(parent),
568 base, CPG_FRQCRC_ZFC_MASK);
570 case CLK_TYPE_GEN3_Z2:
571 return cpg_z_clk_register(core->name, __clk_get_name(parent),
572 base, CPG_FRQCRC_Z2FC_MASK);
574 case CLK_TYPE_GEN3_OSC:
576 * Clock combining OSC EXTAL predivider and a fixed divider
578 div = cpg_pll_config->osc_prediv * core->div;
581 case CLK_TYPE_GEN3_RCKSEL:
583 * Clock selectable between two parents and two fixed dividers
586 if (readl(base + CPG_RCKCR) & CPG_RCKCR_CKSEL) {
587 div = core->div & 0xffff;
589 parent = clks[core->parent >> 16];
591 return ERR_CAST(parent);
592 div = core->div >> 16;
597 return ERR_PTR(-EINVAL);
600 return clk_register_fixed_factor(NULL, core->name,
601 __clk_get_name(parent), 0, mult, div);
604 int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
605 unsigned int clk_extalr, u32 mode)
607 const struct soc_device_attribute *attr;
609 cpg_pll_config = config;
610 cpg_clk_extalr = clk_extalr;
612 attr = soc_device_match(cpg_quirks_match);
614 cpg_quirks = (uintptr_t)attr->data;
615 pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);