1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
6 * Copyright (C) 2019 Renesas Electronics Corp.
8 * Based on clk-rcar-gen3.c
10 * Copyright (C) 2015 Renesas Electronics Corp.
13 #include <linux/bug.h>
14 #include <linux/bitfield.h>
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/device.h>
18 #include <linux/err.h>
19 #include <linux/init.h>
22 #include <linux/slab.h>
23 #include <linux/sys_soc.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-cpg-lib.h"
27 #include "rcar-gen3-cpg.h"
29 #define CPG_PLLECR 0x00d0 /* PLL Enable Control Register */
31 #define CPG_PLLECR_PLLST(n) BIT(8 + (n)) /* PLLn Circuit Status */
33 #define CPG_PLL0CR 0x00d8 /* PLLn Control Registers */
34 #define CPG_PLL2CR 0x002c
35 #define CPG_PLL4CR 0x01f4
37 #define CPG_PLLnCR_STC_MASK GENMASK(30, 24) /* PLL Circuit Mult. Ratio */
39 #define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
44 void __iomem *pllcr_reg;
45 void __iomem *pllecr_reg;
46 unsigned int fixed_mult;
47 u32 pllecr_pllst_mask;
50 #define to_pll_clk(_hw) container_of(_hw, struct cpg_pll_clk, hw)
52 static unsigned long cpg_pll_clk_recalc_rate(struct clk_hw *hw,
53 unsigned long parent_rate)
55 struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
59 val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK;
60 mult = (val >> __ffs(CPG_PLLnCR_STC_MASK)) + 1;
62 return parent_rate * mult * pll_clk->fixed_mult;
65 static int cpg_pll_clk_determine_rate(struct clk_hw *hw,
66 struct clk_rate_request *req)
68 struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
69 unsigned int min_mult, max_mult, mult;
72 prate = req->best_parent_rate * pll_clk->fixed_mult;
73 min_mult = max(div64_ul(req->min_rate, prate), 1ULL);
74 max_mult = min(div64_ul(req->max_rate, prate), 128ULL);
75 if (max_mult < min_mult)
78 mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate);
79 mult = clamp(mult, min_mult, max_mult);
81 req->rate = prate * mult;
85 static int cpg_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
86 unsigned long parent_rate)
88 struct cpg_pll_clk *pll_clk = to_pll_clk(hw);
92 mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult);
93 mult = clamp(mult, 1U, 128U);
95 val = readl(pll_clk->pllcr_reg);
96 val &= ~CPG_PLLnCR_STC_MASK;
97 val |= (mult - 1) << __ffs(CPG_PLLnCR_STC_MASK);
98 writel(val, pll_clk->pllcr_reg);
100 for (i = 1000; i; i--) {
101 if (readl(pll_clk->pllecr_reg) & pll_clk->pllecr_pllst_mask)
110 static const struct clk_ops cpg_pll_clk_ops = {
111 .recalc_rate = cpg_pll_clk_recalc_rate,
112 .determine_rate = cpg_pll_clk_determine_rate,
113 .set_rate = cpg_pll_clk_set_rate,
116 static struct clk * __init cpg_pll_clk_register(const char *name,
117 const char *parent_name,
124 struct cpg_pll_clk *pll_clk;
125 struct clk_init_data init = {};
128 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
130 return ERR_PTR(-ENOMEM);
133 init.ops = &cpg_pll_clk_ops;
134 init.parent_names = &parent_name;
135 init.num_parents = 1;
137 pll_clk->hw.init = &init;
138 pll_clk->pllcr_reg = base + offset;
139 pll_clk->pllecr_reg = base + CPG_PLLECR;
140 pll_clk->fixed_mult = mult; /* PLL refclk x (setting + 1) x mult */
141 pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index);
143 clk = clk_register(NULL, &pll_clk->hw);
153 * Traits of this clock:
154 * prepare - clk_prepare only ensures that parents are prepared
155 * enable - clk_enable only ensures that parents are enabled
156 * rate - rate is adjustable.
157 * clk->rate = (parent->rate * mult / 32 ) / fixed_div
158 * parent - fixed parent. No clk_set_parent support
160 #define CPG_FRQCRB 0x00000004
161 #define CPG_FRQCRB_KICK BIT(31)
162 #define CPG_FRQCRC 0x000000e0
167 void __iomem *kick_reg;
168 unsigned long max_rate; /* Maximum rate for normal mode */
169 unsigned int fixed_div;
173 #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
175 static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
176 unsigned long parent_rate)
178 struct cpg_z_clk *zclk = to_z_clk(hw);
182 val = readl(zclk->reg) & zclk->mask;
183 mult = 32 - (val >> __ffs(zclk->mask));
185 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult,
186 32 * zclk->fixed_div);
189 static int cpg_z_clk_determine_rate(struct clk_hw *hw,
190 struct clk_rate_request *req)
192 struct cpg_z_clk *zclk = to_z_clk(hw);
193 unsigned int min_mult, max_mult, mult;
194 unsigned long rate, prate;
196 rate = min(req->rate, req->max_rate);
197 if (rate <= zclk->max_rate) {
198 /* Set parent rate to initial value for normal modes */
199 prate = zclk->max_rate;
201 /* Set increased parent rate for boost modes */
204 req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
205 prate * zclk->fixed_div);
207 prate = req->best_parent_rate / zclk->fixed_div;
208 min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
209 max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);
210 if (max_mult < min_mult)
213 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate);
214 mult = clamp(mult, min_mult, max_mult);
216 req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32);
220 static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
221 unsigned long parent_rate)
223 struct cpg_z_clk *zclk = to_z_clk(hw);
227 mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div,
229 mult = clamp(mult, 1U, 32U);
231 if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
234 cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask));
237 * Set KICK bit in FRQCRB to update hardware setting and wait for
238 * clock change completion.
240 cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK);
243 * Note: There is no HW information about the worst case latency.
245 * Using experimental measurements, it seems that no more than
246 * ~10 iterations are needed, independently of the CPU rate.
247 * Since this value might be dependent on external xtal rate, pll1
248 * rate or even the other emulation clocks rate, use 1000 as a
249 * "super" safe value.
251 for (i = 1000; i; i--) {
252 if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
261 static const struct clk_ops cpg_z_clk_ops = {
262 .recalc_rate = cpg_z_clk_recalc_rate,
263 .determine_rate = cpg_z_clk_determine_rate,
264 .set_rate = cpg_z_clk_set_rate,
267 static struct clk * __init cpg_z_clk_register(const char *name,
268 const char *parent_name,
273 struct clk_init_data init = {};
274 struct cpg_z_clk *zclk;
277 zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
279 return ERR_PTR(-ENOMEM);
282 init.ops = &cpg_z_clk_ops;
283 init.flags = CLK_SET_RATE_PARENT;
284 init.parent_names = &parent_name;
285 init.num_parents = 1;
287 zclk->reg = reg + CPG_FRQCRC;
288 zclk->kick_reg = reg + CPG_FRQCRB;
289 zclk->hw.init = &init;
290 zclk->mask = GENMASK(offset + 4, offset);
291 zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */
293 clk = clk_register(NULL, &zclk->hw);
299 zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) /
305 struct clk_divider div;
306 struct clk_gate gate;
308 * One notifier covers both RPC and RPCD2 clocks as they are both
309 * controlled by the same RPCCKCR register...
311 struct cpg_simple_notifier csn;
314 static const struct clk_div_table cpg_rpcsrc_div_table[] = {
315 { 2, 5 }, { 3, 6 }, { 0, 0 },
318 static const struct clk_div_table cpg_rpc_div_table[] = {
319 { 1, 2 }, { 3, 4 }, { 5, 6 }, { 7, 8 }, { 0, 0 },
322 static struct clk * __init cpg_rpc_clk_register(const char *name,
323 void __iomem *base, const char *parent_name,
324 struct raw_notifier_head *notifiers)
326 struct rpc_clock *rpc;
329 rpc = kzalloc(sizeof(*rpc), GFP_KERNEL);
331 return ERR_PTR(-ENOMEM);
333 rpc->div.reg = base + CPG_RPCCKCR;
335 rpc->div.table = cpg_rpc_div_table;
336 rpc->div.lock = &cpg_lock;
338 rpc->gate.reg = base + CPG_RPCCKCR;
339 rpc->gate.bit_idx = 8;
340 rpc->gate.flags = CLK_GATE_SET_TO_DISABLE;
341 rpc->gate.lock = &cpg_lock;
343 rpc->csn.reg = base + CPG_RPCCKCR;
345 clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
346 &rpc->div.hw, &clk_divider_ops,
347 &rpc->gate.hw, &clk_gate_ops,
348 CLK_SET_RATE_PARENT);
354 cpg_simple_notifier_register(notifiers, &rpc->csn);
359 struct clk_fixed_factor fixed;
360 struct clk_gate gate;
363 static struct clk * __init cpg_rpcd2_clk_register(const char *name,
365 const char *parent_name)
367 struct rpcd2_clock *rpcd2;
370 rpcd2 = kzalloc(sizeof(*rpcd2), GFP_KERNEL);
372 return ERR_PTR(-ENOMEM);
374 rpcd2->fixed.mult = 1;
375 rpcd2->fixed.div = 2;
377 rpcd2->gate.reg = base + CPG_RPCCKCR;
378 rpcd2->gate.bit_idx = 9;
379 rpcd2->gate.flags = CLK_GATE_SET_TO_DISABLE;
380 rpcd2->gate.lock = &cpg_lock;
382 clk = clk_register_composite(NULL, name, &parent_name, 1, NULL, NULL,
383 &rpcd2->fixed.hw, &clk_fixed_factor_ops,
384 &rpcd2->gate.hw, &clk_gate_ops,
385 CLK_SET_RATE_PARENT);
393 static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
394 static unsigned int cpg_clk_extalr __initdata;
395 static u32 cpg_mode __initdata;
396 static u32 cpg_quirks __initdata;
398 #define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */
399 #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
400 #define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */
403 static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
405 .soc_id = "r8a7795", .revision = "ES1.0",
406 .data = (void *)(PLL_ERRATA | RCKCR_CKSEL | SD_SKIP_FIRST),
409 .soc_id = "r8a7795", .revision = "ES1.*",
410 .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST),
413 .soc_id = "r8a7795", .revision = "ES2.0",
414 .data = (void *)SD_SKIP_FIRST,
417 .soc_id = "r8a7796", .revision = "ES1.0",
418 .data = (void *)(RCKCR_CKSEL | SD_SKIP_FIRST),
421 .soc_id = "r8a7796", .revision = "ES1.1",
422 .data = (void *)SD_SKIP_FIRST,
427 struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
428 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
429 struct clk **clks, void __iomem *base,
430 struct raw_notifier_head *notifiers)
432 const struct clk *parent;
433 unsigned int mult = 1;
434 unsigned int div = 1;
437 parent = clks[core->parent & 0xffff]; /* some types use high bits */
439 return ERR_CAST(parent);
441 switch (core->type) {
442 case CLK_TYPE_GEN3_MAIN:
443 div = cpg_pll_config->extal_div;
446 case CLK_TYPE_GEN3_PLL0:
448 * PLL0 is implemented as a custom clock, to change the
449 * multiplier when cpufreq changes between normal and boost
452 mult = (cpg_quirks & PLL_ERRATA) ? 4 : 2;
453 return cpg_pll_clk_register(core->name, __clk_get_name(parent),
454 base, mult, CPG_PLL0CR, 0);
456 case CLK_TYPE_GEN3_PLL1:
457 mult = cpg_pll_config->pll1_mult;
458 div = cpg_pll_config->pll1_div;
461 case CLK_TYPE_GEN3_PLL2:
463 * PLL2 is implemented as a custom clock, to change the
464 * multiplier when cpufreq changes between normal and boost
467 mult = (cpg_quirks & PLL_ERRATA) ? 4 : 2;
468 return cpg_pll_clk_register(core->name, __clk_get_name(parent),
469 base, mult, CPG_PLL2CR, 2);
471 case CLK_TYPE_GEN3_PLL3:
472 mult = cpg_pll_config->pll3_mult;
473 div = cpg_pll_config->pll3_div;
476 case CLK_TYPE_GEN3_PLL4:
478 * PLL4 is a configurable multiplier clock. Register it as a
479 * fixed factor clock for now as there's no generic multiplier
480 * clock implementation and we currently have no need to change
481 * the multiplier value.
483 value = readl(base + CPG_PLL4CR);
484 mult = (((value >> 24) & 0x7f) + 1) * 2;
485 if (cpg_quirks & PLL_ERRATA)
489 case CLK_TYPE_GEN3_SD:
490 return cpg_sd_clk_register(core->name, base, core->offset,
491 __clk_get_name(parent), notifiers,
492 cpg_quirks & SD_SKIP_FIRST);
494 case CLK_TYPE_GEN3_R:
495 if (cpg_quirks & RCKCR_CKSEL) {
496 struct cpg_simple_notifier *csn;
498 csn = kzalloc(sizeof(*csn), GFP_KERNEL);
500 return ERR_PTR(-ENOMEM);
502 csn->reg = base + CPG_RCKCR;
506 * Only if EXTALR is populated, we switch to it.
508 value = readl(csn->reg) & 0x3f;
510 if (clk_get_rate(clks[cpg_clk_extalr])) {
511 parent = clks[cpg_clk_extalr];
512 value |= CPG_RCKCR_CKSEL;
515 writel(value, csn->reg);
516 cpg_simple_notifier_register(notifiers, csn);
520 /* Select parent clock of RCLK by MD28 */
521 if (cpg_mode & BIT(28))
522 parent = clks[cpg_clk_extalr];
525 case CLK_TYPE_GEN3_MDSEL:
527 * Clock selectable between two parents and two fixed dividers
530 if (cpg_mode & BIT(core->offset)) {
531 div = core->div & 0xffff;
533 parent = clks[core->parent >> 16];
535 return ERR_CAST(parent);
536 div = core->div >> 16;
541 case CLK_TYPE_GEN3_Z:
542 return cpg_z_clk_register(core->name, __clk_get_name(parent),
543 base, core->div, core->offset);
545 case CLK_TYPE_GEN3_OSC:
547 * Clock combining OSC EXTAL predivider and a fixed divider
549 div = cpg_pll_config->osc_prediv * core->div;
552 case CLK_TYPE_GEN3_RCKSEL:
554 * Clock selectable between two parents and two fixed dividers
557 if (readl(base + CPG_RCKCR) & CPG_RCKCR_CKSEL) {
558 div = core->div & 0xffff;
560 parent = clks[core->parent >> 16];
562 return ERR_CAST(parent);
563 div = core->div >> 16;
567 case CLK_TYPE_GEN3_RPCSRC:
568 return clk_register_divider_table(NULL, core->name,
569 __clk_get_name(parent), 0,
570 base + CPG_RPCCKCR, 3, 2, 0,
571 cpg_rpcsrc_div_table,
574 case CLK_TYPE_GEN3_E3_RPCSRC:
576 * Register RPCSRC as fixed factor clock based on the
577 * MD[4:1] pins and CPG_RPCCKCR[4:3] register value for
578 * which has been set prior to booting the kernel.
580 value = (readl(base + CPG_RPCCKCR) & GENMASK(4, 3)) >> 3;
590 parent = clks[core->parent >> 16];
592 return ERR_CAST(parent);
602 case CLK_TYPE_GEN3_RPC:
603 return cpg_rpc_clk_register(core->name, base,
604 __clk_get_name(parent), notifiers);
606 case CLK_TYPE_GEN3_RPCD2:
607 return cpg_rpcd2_clk_register(core->name, base,
608 __clk_get_name(parent));
611 return ERR_PTR(-EINVAL);
614 return clk_register_fixed_factor(NULL, core->name,
615 __clk_get_name(parent), 0, mult, div);
618 int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
619 unsigned int clk_extalr, u32 mode)
621 const struct soc_device_attribute *attr;
623 cpg_pll_config = config;
624 cpg_clk_extalr = clk_extalr;
626 attr = soc_device_match(cpg_quirks_match);
628 cpg_quirks = (uintptr_t)attr->data;
629 pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
631 spin_lock_init(&cpg_lock);