drivers/clk/renesas/r9a07g044-cpg.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * RZ/G2L CPG driver
   4  *
   5  * Copyright (C) 2021 Renesas Electronics Corp.
   6  */
   7
   8 #include <linux/clk-provider.h>
   9 #include <linux/device.h>
  10 #include <linux/init.h>
  11 #include <linux/kernel.h>
  12
  13 #include <dt-bindings/clock/r9a07g044-cpg.h>
  14
  15 #include "renesas-rzg2l-cpg.h"
  16
  17 enum clk_ids {
  18         /* Core Clock Outputs exported to DT */
  19         LAST_DT_CORE_CLK = R9A07G044_OSCCLK,
  20
  21         /* External Input Clocks */
  22         CLK_EXTAL,
  23
  24         /* Internal Core Clocks */
  25         CLK_OSC_DIV1000,
  26         CLK_PLL1,
  27         CLK_PLL2,
  28         CLK_PLL2_DIV2,
  29         CLK_PLL2_DIV16,
  30         CLK_PLL2_DIV20,
  31         CLK_PLL3,
  32         CLK_PLL3_DIV2,
  33         CLK_PLL3_DIV2_4,
  34         CLK_PLL3_DIV2_4_2,
  35         CLK_PLL3_DIV4,
  36         CLK_PLL4,
  37         CLK_PLL5,
  38         CLK_PLL5_DIV2,
  39         CLK_PLL6,
  40
  41         /* Module Clocks */
  42         MOD_CLK_BASE,
  43 };
  44
  45 /* Divider tables */
  46 static const struct clk_div_table dtable_1_32[] = {
  47         {0, 1},
  48         {1, 2},
  49         {2, 4},
  50         {3, 8},
  51         {4, 32},
  52         {0, 0},
  53 };
  54
  55 static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = {
  56         /* External Clock Inputs */
  57         DEF_INPUT("extal", CLK_EXTAL),
  58
  59         /* Internal Core Clocks */
  60         DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
  61         DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
  62         DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
  63         DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2),
  64         DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2),
  65
  66         DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
  67         DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16),
  68         DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20),
  69
  70         DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
  71         DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
  72         DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
  73         DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4),
  74
  75         /* Core output clk */
  76         DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1),
  77         DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A,
  78                 dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
  79         DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1),
  80         DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
  81                 DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
  82         DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
  83                 DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
  84 };
  85
  86 static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
  87         DEF_MOD("gic",          R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1,
  88                                 0x514, 0),
  89         DEF_MOD("ia55_pclk",    R9A07G044_IA55_PCLK, R9A07G044_CLK_P2,
  90                                 0x518, 0),
  91         DEF_MOD("ia55_clk",     R9A07G044_IA55_CLK, R9A07G044_CLK_P1,
  92                                 0x518, 1),
  93         DEF_MOD("scif0",        R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0,
  94                                 0x584, 0),
  95         DEF_MOD("scif1",        R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0,
  96                                 0x584, 1),
  97         DEF_MOD("scif2",        R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0,
  98                                 0x584, 2),
  99         DEF_MOD("scif3",        R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0,
 100                                 0x584, 3),
 101         DEF_MOD("scif4",        R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0,
 102                                 0x584, 4),
 103         DEF_MOD("sci0",         R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
 104                                 0x588, 0),
 105 };
 106
 107 static struct rzg2l_reset r9a07g044_resets[] = {
 108         DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),
 109         DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),
 110         DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),
 111         DEF_RST(R9A07G044_SCIF0_RST_SYSTEM_N, 0x884, 0),
 112         DEF_RST(R9A07G044_SCIF1_RST_SYSTEM_N, 0x884, 1),
 113         DEF_RST(R9A07G044_SCIF2_RST_SYSTEM_N, 0x884, 2),
 114         DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
 115         DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
 116         DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
 117 };
 118
 119 static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
 120         MOD_CLK_BASE + R9A07G044_GIC600_GICCLK,
 121 };
 122
 123 const struct rzg2l_cpg_info r9a07g044_cpg_info = {
 124         /* Core Clocks */
 125         .core_clks = r9a07g044_core_clks,
 126         .num_core_clks = ARRAY_SIZE(r9a07g044_core_clks),
 127         .last_dt_core_clk = LAST_DT_CORE_CLK,
 128         .num_total_core_clks = MOD_CLK_BASE,
 129
 130         /* Critical Module Clocks */
 131         .crit_mod_clks = r9a07g044_crit_mod_clks,
 132         .num_crit_mod_clks = ARRAY_SIZE(r9a07g044_crit_mod_clks),
 133
 134         /* Module Clocks */
 135         .mod_clks = r9a07g044_mod_clks,
 136         .num_mod_clks = ARRAY_SIZE(r9a07g044_mod_clks),
 137         .num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,
 138
 139         /* Resets */
 140         .resets = r9a07g044_resets,
 141         .num_resets = ARRAY_SIZE(r9a07g044_resets),
 142 };