2 * r8a77970 Clock Pulse Generator / Module Standby and Software Reset
4 * Copyright (C) 2017-2018 Cogent Embedded Inc.
6 * Based on r8a7795-cpg-mssr.c
8 * Copyright (C) 2015 Glider bvba
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
15 #include <linux/clk-provider.h>
16 #include <linux/device.h>
17 #include <linux/init.h>
18 #include <linux/kernel.h>
19 #include <linux/soc/renesas/rcar-rst.h>
21 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
23 #include "renesas-cpg-mssr.h"
24 #include "rcar-gen3-cpg.h"
26 #define CPG_SD0CKCR 0x0074
28 enum r8a77970_clk_types {
29 CLK_TYPE_R8A77970_SD0H = CLK_TYPE_GEN3_SOC_BASE,
30 CLK_TYPE_R8A77970_SD0,
34 /* Core Clock Outputs exported to DT */
35 LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
37 /* External Input Clocks */
41 /* Internal Core Clocks */
53 static spinlock_t cpg_lock;
55 static const struct clk_div_table cpg_sd0h_div_table[] = {
56 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
57 { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
58 { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
61 static const struct clk_div_table cpg_sd0_div_table[] = {
62 { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
63 { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
67 static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
68 /* External Clock Inputs */
69 DEF_INPUT("extal", CLK_EXTAL),
70 DEF_INPUT("extalr", CLK_EXTALR),
72 /* Internal Core Clocks */
73 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
74 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
75 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
76 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
78 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
79 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
81 /* Core Clock Outputs */
82 DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
83 DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
84 DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
85 DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
86 DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_PLL1_DIV2, 4, 1),
87 DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_PLL1_DIV2, 8, 1),
88 DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_PLL1_DIV2, 16, 1),
89 DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_PLL1_DIV2, 6, 1),
90 DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_PLL1_DIV2, 12, 1),
91 DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_PLL1_DIV2, 24, 1),
93 DEF_BASE("sd0h", R8A77970_CLK_SD0H, CLK_TYPE_R8A77970_SD0H,
95 DEF_BASE("sd0", R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2),
97 DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
98 DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
100 DEF_DIV6P1("canfd", R8A77970_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
101 DEF_DIV6P1("mso", R8A77970_CLK_MSO, CLK_PLL1_DIV4, 0x014),
102 DEF_DIV6P1("csi0", R8A77970_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
104 DEF_FIXED("osc", R8A77970_CLK_OSC, CLK_PLL1_DIV2, 12*1024, 1),
105 DEF_FIXED("r", R8A77970_CLK_R, CLK_EXTALR, 1, 1),
108 static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
109 DEF_MOD("tmu4", 121, R8A77970_CLK_S2D2),
110 DEF_MOD("tmu3", 122, R8A77970_CLK_S2D2),
111 DEF_MOD("tmu2", 123, R8A77970_CLK_S2D2),
112 DEF_MOD("tmu1", 124, R8A77970_CLK_S2D2),
113 DEF_MOD("tmu0", 125, R8A77970_CLK_CP),
114 DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
115 DEF_MOD("scif4", 203, R8A77970_CLK_S2D4),
116 DEF_MOD("scif3", 204, R8A77970_CLK_S2D4),
117 DEF_MOD("scif1", 206, R8A77970_CLK_S2D4),
118 DEF_MOD("scif0", 207, R8A77970_CLK_S2D4),
119 DEF_MOD("msiof3", 208, R8A77970_CLK_MSO),
120 DEF_MOD("msiof2", 209, R8A77970_CLK_MSO),
121 DEF_MOD("msiof1", 210, R8A77970_CLK_MSO),
122 DEF_MOD("msiof0", 211, R8A77970_CLK_MSO),
123 DEF_MOD("mfis", 213, R8A77970_CLK_S2D2),
124 DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
125 DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),
126 DEF_MOD("cmt3", 300, R8A77970_CLK_R),
127 DEF_MOD("cmt2", 301, R8A77970_CLK_R),
128 DEF_MOD("cmt1", 302, R8A77970_CLK_R),
129 DEF_MOD("cmt0", 303, R8A77970_CLK_R),
130 DEF_MOD("tpu0", 304, R8A77970_CLK_S2D4),
131 DEF_MOD("sd-if", 314, R8A77970_CLK_SD0),
132 DEF_MOD("rwdt", 402, R8A77970_CLK_R),
133 DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
134 DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1),
135 DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1),
136 DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1),
137 DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1),
138 DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1),
139 DEF_MOD("thermal", 522, R8A77970_CLK_CP),
140 DEF_MOD("pwm", 523, R8A77970_CLK_S2D4),
141 DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1),
142 DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1),
143 DEF_MOD("csi40", 716, R8A77970_CLK_CSI0),
144 DEF_MOD("du0", 724, R8A77970_CLK_S2D1),
145 DEF_MOD("lvds", 727, R8A77970_CLK_S2D1),
146 DEF_MOD("vin3", 808, R8A77970_CLK_S2D1),
147 DEF_MOD("vin2", 809, R8A77970_CLK_S2D1),
148 DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
149 DEF_MOD("vin0", 811, R8A77970_CLK_S2D1),
150 DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2),
151 DEF_MOD("gpio5", 907, R8A77970_CLK_CP),
152 DEF_MOD("gpio4", 908, R8A77970_CLK_CP),
153 DEF_MOD("gpio3", 909, R8A77970_CLK_CP),
154 DEF_MOD("gpio2", 910, R8A77970_CLK_CP),
155 DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
156 DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
157 DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
158 DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
159 DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
160 DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
161 DEF_MOD("i2c1", 930, R8A77970_CLK_S2D2),
162 DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2),
165 static const unsigned int r8a77970_crit_mod_clks[] __initconst = {
166 MOD_CLK_ID(408), /* INTC-AP (GIC) */
175 * MD EXTAL PLL0 PLL1 PLL3
177 *-------------------------------------------------
178 * 0 0 0 16.66 x 1 x192 x192 x96
179 * 0 0 1 16.66 x 1 x192 x192 x80
180 * 0 1 0 20 x 1 x160 x160 x80
181 * 0 1 1 20 x 1 x160 x160 x66
182 * 1 0 0 27 / 2 x236 x236 x118
183 * 1 0 1 27 / 2 x236 x236 x98
184 * 1 1 0 33.33 / 2 x192 x192 x96
185 * 1 1 1 33.33 / 2 x192 x192 x80
187 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
188 (((md) & BIT(13)) >> 12) | \
189 (((md) & BIT(19)) >> 19))
191 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] __initconst = {
192 /* EXTAL div PLL1 mult/div PLL3 mult/div */
193 { 1, 192, 1, 96, 1, },
194 { 1, 192, 1, 80, 1, },
195 { 1, 160, 1, 80, 1, },
196 { 1, 160, 1, 66, 1, },
197 { 2, 236, 1, 118, 1, },
198 { 2, 236, 1, 98, 1, },
199 { 2, 192, 1, 96, 1, },
200 { 2, 192, 1, 80, 1, },
203 static int __init r8a77970_cpg_mssr_init(struct device *dev)
205 const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
209 error = rcar_rst_read_mode_pins(&cpg_mode);
213 spin_lock_init(&cpg_lock);
215 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
217 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
220 static struct clk * __init r8a77970_cpg_clk_register(struct device *dev,
221 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
222 struct clk **clks, void __iomem *base,
223 struct raw_notifier_head *notifiers)
225 const struct clk_div_table *table;
226 const struct clk *parent;
229 switch (core->type) {
230 case CLK_TYPE_R8A77970_SD0H:
231 table = cpg_sd0h_div_table;
234 case CLK_TYPE_R8A77970_SD0:
235 table = cpg_sd0_div_table;
239 return rcar_gen3_cpg_clk_register(dev, core, info, clks, base,
243 parent = clks[core->parent];
245 return ERR_CAST(parent);
247 return clk_register_divider_table(NULL, core->name,
248 __clk_get_name(parent), 0,
250 shift, 4, 0, table, &cpg_lock);
253 const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = {
255 .core_clks = r8a77970_core_clks,
256 .num_core_clks = ARRAY_SIZE(r8a77970_core_clks),
257 .last_dt_core_clk = LAST_DT_CORE_CLK,
258 .num_total_core_clks = MOD_CLK_BASE,
261 .mod_clks = r8a77970_mod_clks,
262 .num_mod_clks = ARRAY_SIZE(r8a77970_mod_clks),
263 .num_hw_mod_clks = 12 * 32,
265 /* Critical Module Clocks */
266 .crit_mod_clks = r8a77970_crit_mod_clks,
267 .num_crit_mod_clks = ARRAY_SIZE(r8a77970_crit_mod_clks),
270 .init = r8a77970_cpg_mssr_init,
271 .cpg_clk_register = r8a77970_cpg_clk_register,