1 // SPDX-License-Identifier: GPL-2.0
3 * sh73a0 Core CPG Clocks
5 * Copyright (C) 2014 Ulrich Hecht
8 #include <linux/clk-provider.h>
9 #include <linux/clk/renesas.h>
10 #include <linux/init.h>
11 #include <linux/kernel.h>
13 #include <linux/of_address.h>
14 #include <linux/slab.h>
15 #include <linux/spinlock.h>
18 struct clk_onecell_data data;
23 #define CPG_FRQCRA 0x00
24 #define CPG_FRQCRB 0x04
25 #define CPG_SD0CKCR 0x74
26 #define CPG_SD1CKCR 0x78
27 #define CPG_SD2CKCR 0x7c
28 #define CPG_PLLECR 0xd0
29 #define CPG_PLL0CR 0xd8
30 #define CPG_PLL1CR 0x28
31 #define CPG_PLL2CR 0x2c
32 #define CPG_PLL3CR 0xdc
33 #define CPG_CKSCR 0xc0
34 #define CPG_DSI0PHYCR 0x6c
35 #define CPG_DSI1PHYCR 0x70
37 #define CLK_ENABLE_ON_INIT BIT(0)
46 static const struct div4_clk div4_clks[] = {
47 { "zg", "pll0", CPG_FRQCRA, 16 },
48 { "m3", "pll1", CPG_FRQCRA, 12 },
49 { "b", "pll1", CPG_FRQCRA, 8 },
50 { "m1", "pll1", CPG_FRQCRA, 4 },
51 { "m2", "pll1", CPG_FRQCRA, 0 },
52 { "zx", "pll1", CPG_FRQCRB, 12 },
53 { "hp", "pll1", CPG_FRQCRB, 4 },
57 static const struct clk_div_table div4_div_table[] = {
58 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
59 { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 },
63 static const struct clk_div_table z_div_table[] = {
65 { 0, 1 }, { 1, 1 }, { 2, 1 }, { 3, 1 }, { 4, 1 }, { 5, 1 },
66 { 6, 1 }, { 7, 1 }, { 8, 1 }, { 9, 1 }, { 10, 1 }, { 11, 1 },
67 { 12, 1 }, { 13, 1 }, { 14, 1 }, { 15, 1 },
69 { 16, 2 }, { 17, 3 }, { 18, 4 }, { 19, 6 }, { 20, 8 }, { 21, 12 },
70 { 22, 16 }, { 24, 24 }, { 27, 48 }, { 0, 0 }
73 static struct clk * __init
74 sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
77 const struct clk_div_table *table = NULL;
78 unsigned int shift, reg, width;
79 const char *parent_name = NULL;
80 unsigned int mult = 1;
83 if (!strcmp(name, "main")) {
84 /* extal1, extal1_div2, extal2, extal2_div2 */
85 u32 parent_idx = (readl(cpg->reg + CPG_CKSCR) >> 28) & 3;
87 parent_name = of_clk_get_parent_name(np, parent_idx >> 1);
88 div = (parent_idx & 1) + 1;
89 } else if (!strncmp(name, "pll", 3)) {
90 void __iomem *enable_reg = cpg->reg;
91 u32 enable_bit = name[3] - '0';
96 enable_reg += CPG_PLL0CR;
99 enable_reg += CPG_PLL1CR;
102 enable_reg += CPG_PLL2CR;
105 enable_reg += CPG_PLL3CR;
108 return ERR_PTR(-EINVAL);
110 if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) {
111 mult = ((readl(enable_reg) >> 24) & 0x3f) + 1;
112 /* handle CFG bit for PLL1 and PLL2 */
113 if (enable_bit == 1 || enable_bit == 2)
114 if (readl(enable_reg) & BIT(20))
117 } else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) {
118 u32 phy_no = name[3] - '0';
119 void __iomem *dsi_reg = cpg->reg +
120 (phy_no ? CPG_DSI1PHYCR : CPG_DSI0PHYCR);
122 parent_name = phy_no ? "dsi1pck" : "dsi0pck";
123 mult = __raw_readl(dsi_reg);
124 if (!(mult & 0x8000))
127 mult = (mult & 0x3f) + 1;
128 } else if (!strcmp(name, "z")) {
129 parent_name = "pll0";
135 const struct div4_clk *c;
137 for (c = div4_clks; c->name; c++) {
138 if (!strcmp(name, c->name)) {
139 parent_name = c->parent;
140 table = div4_div_table;
148 return ERR_PTR(-EINVAL);
152 return clk_register_fixed_factor(NULL, name, parent_name, 0,
155 return clk_register_divider_table(NULL, name, parent_name, 0,
156 cpg->reg + reg, shift, width, 0,
161 static void __init sh73a0_cpg_clocks_init(struct device_node *np)
163 struct sh73a0_cpg *cpg;
168 num_clks = of_property_count_strings(np, "clock-output-names");
170 pr_err("%s: failed to count clocks\n", __func__);
174 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
175 clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
176 if (cpg == NULL || clks == NULL) {
177 /* We're leaking memory on purpose, there's no point in cleaning
178 * up as the system won't boot anyway.
183 spin_lock_init(&cpg->lock);
185 cpg->data.clks = clks;
186 cpg->data.clk_num = num_clks;
188 cpg->reg = of_iomap(np, 0);
189 if (WARN_ON(cpg->reg == NULL))
192 /* Set SDHI clocks to a known state */
193 writel(0x108, cpg->reg + CPG_SD0CKCR);
194 writel(0x108, cpg->reg + CPG_SD1CKCR);
195 writel(0x108, cpg->reg + CPG_SD2CKCR);
197 for (i = 0; i < num_clks; ++i) {
201 of_property_read_string_index(np, "clock-output-names", i,
204 clk = sh73a0_cpg_register_clock(np, cpg, name);
206 pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
207 __func__, np, name, PTR_ERR(clk));
209 cpg->data.clks[i] = clk;
212 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
214 CLK_OF_DECLARE(sh73a0_cpg_clks, "renesas,sh73a0-cpg-clocks",
215 sh73a0_cpg_clocks_init);