1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/regmap.h>
12 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
17 #include "clk-regmap.h"
18 #include "clk-regmap-divider.h"
25 P_VIDEO_PLL0_OUT_MAIN,
26 P_VIDEO_PLL1_OUT_MAIN,
29 static struct pll_vco lucid_vco[] = {
30 { 249600000, 2000000000, 0 },
33 static const struct alpha_pll_config video_pll0_config = {
36 .config_ctl_val = 0x20485699,
37 .config_ctl_hi_val = 0x00002261,
38 .config_ctl_hi1_val = 0x329A699C,
39 .user_ctl_val = 0x00000000,
40 .user_ctl_hi_val = 0x00000805,
41 .user_ctl_hi1_val = 0x00000000,
44 static struct clk_alpha_pll video_pll0 = {
46 .vco_table = lucid_vco,
47 .num_vco = ARRAY_SIZE(lucid_vco),
48 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
50 .hw.init = &(struct clk_init_data){
52 .parent_data = &(const struct clk_parent_data){
56 .ops = &clk_alpha_pll_lucid_ops,
61 static const struct alpha_pll_config video_pll1_config = {
64 .config_ctl_val = 0x20485699,
65 .config_ctl_hi_val = 0x00002261,
66 .config_ctl_hi1_val = 0x329A699C,
67 .user_ctl_val = 0x00000000,
68 .user_ctl_hi_val = 0x00000805,
69 .user_ctl_hi1_val = 0x00000000,
72 static struct clk_alpha_pll video_pll1 = {
74 .vco_table = lucid_vco,
75 .num_vco = ARRAY_SIZE(lucid_vco),
76 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
78 .hw.init = &(struct clk_init_data){
80 .parent_data = &(const struct clk_parent_data){
84 .ops = &clk_alpha_pll_lucid_ops,
89 static const struct parent_map video_cc_parent_map_1[] = {
91 { P_VIDEO_PLL0_OUT_MAIN, 1 },
94 static const struct clk_parent_data video_cc_parent_data_1[] = {
95 { .fw_name = "bi_tcxo" },
96 { .hw = &video_pll0.clkr.hw },
99 static const struct parent_map video_cc_parent_map_2[] = {
101 { P_VIDEO_PLL1_OUT_MAIN, 1 },
104 static const struct clk_parent_data video_cc_parent_data_2[] = {
105 { .fw_name = "bi_tcxo" },
106 { .hw = &video_pll1.clkr.hw },
109 static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
110 F(19200000, P_BI_TCXO, 1, 0, 0),
111 F(720000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
112 F(1014000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
113 F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
114 F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
118 static struct clk_rcg2 video_cc_mvs0_clk_src = {
122 .parent_map = video_cc_parent_map_1,
123 .freq_tbl = ftbl_video_cc_mvs0_clk_src,
124 .clkr.hw.init = &(struct clk_init_data){
125 .name = "video_cc_mvs0_clk_src",
126 .parent_data = video_cc_parent_data_1,
127 .num_parents = ARRAY_SIZE(video_cc_parent_data_1),
128 .flags = CLK_SET_RATE_PARENT,
129 .ops = &clk_rcg2_shared_ops,
133 static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
134 F(19200000, P_BI_TCXO, 1, 0, 0),
135 F(840000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
136 F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
137 F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
141 static struct clk_rcg2 video_cc_mvs1_clk_src = {
145 .parent_map = video_cc_parent_map_2,
146 .freq_tbl = ftbl_video_cc_mvs1_clk_src,
147 .clkr.hw.init = &(struct clk_init_data){
148 .name = "video_cc_mvs1_clk_src",
149 .parent_data = video_cc_parent_data_2,
150 .num_parents = ARRAY_SIZE(video_cc_parent_data_2),
151 .flags = CLK_SET_RATE_PARENT,
152 .ops = &clk_rcg2_shared_ops,
156 static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
160 .clkr.hw.init = &(struct clk_init_data) {
161 .name = "video_cc_mvs0c_div2_div_clk_src",
162 .parent_hws = (const struct clk_hw*[]){
163 &video_cc_mvs0_clk_src.clkr.hw,
166 .flags = CLK_SET_RATE_PARENT,
167 .ops = &clk_regmap_div_ro_ops,
171 static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
175 .clkr.hw.init = &(struct clk_init_data) {
176 .name = "video_cc_mvs0_div_clk_src",
177 .parent_hws = (const struct clk_hw*[]){
178 &video_cc_mvs0_clk_src.clkr.hw,
181 .flags = CLK_SET_RATE_PARENT,
182 .ops = &clk_regmap_div_ro_ops,
186 static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
190 .clkr.hw.init = &(struct clk_init_data) {
191 .name = "video_cc_mvs1c_div2_div_clk_src",
192 .parent_hws = (const struct clk_hw*[]){
193 &video_cc_mvs1_clk_src.clkr.hw,
196 .flags = CLK_SET_RATE_PARENT,
197 .ops = &clk_regmap_div_ro_ops,
201 static struct clk_branch video_cc_mvs0c_clk = {
203 .halt_check = BRANCH_HALT,
206 .enable_mask = BIT(0),
207 .hw.init = &(struct clk_init_data){
208 .name = "video_cc_mvs0c_clk",
209 .parent_hws = (const struct clk_hw*[]){
210 &video_cc_mvs0c_div2_div_clk_src.clkr.hw,
213 .flags = CLK_SET_RATE_PARENT,
214 .ops = &clk_branch2_ops,
219 static struct clk_branch video_cc_mvs0_clk = {
221 .halt_check = BRANCH_HALT_VOTED,
224 .enable_mask = BIT(0),
225 .hw.init = &(struct clk_init_data){
226 .name = "video_cc_mvs0_clk",
227 .parent_hws = (const struct clk_hw*[]){
228 &video_cc_mvs0_div_clk_src.clkr.hw,
231 .flags = CLK_SET_RATE_PARENT,
232 .ops = &clk_branch2_ops,
237 static struct clk_branch video_cc_mvs1_div2_clk = {
239 .halt_check = BRANCH_HALT_VOTED,
242 .enable_mask = BIT(0),
243 .hw.init = &(struct clk_init_data){
244 .name = "video_cc_mvs1_div2_clk",
245 .parent_hws = (const struct clk_hw*[]){
246 &video_cc_mvs1c_div2_div_clk_src.clkr.hw,
249 .flags = CLK_SET_RATE_PARENT,
250 .ops = &clk_branch2_ops,
255 static struct clk_branch video_cc_mvs1c_clk = {
257 .halt_check = BRANCH_HALT_VOTED,
260 .enable_mask = BIT(0),
261 .hw.init = &(struct clk_init_data){
262 .name = "video_cc_mvs1c_clk",
263 .parent_hws = (const struct clk_hw*[]){
264 &video_cc_mvs1c_div2_div_clk_src.clkr.hw,
267 .flags = CLK_SET_RATE_PARENT,
268 .ops = &clk_branch2_ops,
273 static struct gdsc mvs0c_gdsc = {
276 .name = "mvs0c_gdsc",
279 .pwrsts = PWRSTS_OFF_ON,
283 static struct gdsc mvs1c_gdsc = {
286 .name = "mvs1c_gdsc",
289 .pwrsts = PWRSTS_OFF_ON,
293 static struct gdsc mvs0_gdsc = {
299 .pwrsts = PWRSTS_OFF_ON,
303 static struct gdsc mvs1_gdsc = {
309 .pwrsts = PWRSTS_OFF_ON,
313 static struct clk_regmap *video_cc_sm8250_clocks[] = {
314 [VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
315 [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
316 [VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
317 [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
318 [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
319 [VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
320 [VIDEO_CC_MVS1_DIV2_CLK] = &video_cc_mvs1_div2_clk.clkr,
321 [VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
322 [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
323 [VIDEO_CC_PLL0] = &video_pll0.clkr,
324 [VIDEO_CC_PLL1] = &video_pll1.clkr,
327 static const struct qcom_reset_map video_cc_sm8250_resets[] = {
328 [VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 },
329 [VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 },
330 [VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 },
331 [VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 },
332 [VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 },
333 [VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 },
334 [VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 },
337 static struct gdsc *video_cc_sm8250_gdscs[] = {
338 [MVS0C_GDSC] = &mvs0c_gdsc,
339 [MVS1C_GDSC] = &mvs1c_gdsc,
340 [MVS0_GDSC] = &mvs0_gdsc,
341 [MVS1_GDSC] = &mvs1_gdsc,
344 static const struct regmap_config video_cc_sm8250_regmap_config = {
348 .max_register = 0xf4c,
352 static const struct qcom_cc_desc video_cc_sm8250_desc = {
353 .config = &video_cc_sm8250_regmap_config,
354 .clks = video_cc_sm8250_clocks,
355 .num_clks = ARRAY_SIZE(video_cc_sm8250_clocks),
356 .resets = video_cc_sm8250_resets,
357 .num_resets = ARRAY_SIZE(video_cc_sm8250_resets),
358 .gdscs = video_cc_sm8250_gdscs,
359 .num_gdscs = ARRAY_SIZE(video_cc_sm8250_gdscs),
362 static const struct of_device_id video_cc_sm8250_match_table[] = {
363 { .compatible = "qcom,sm8250-videocc" },
366 MODULE_DEVICE_TABLE(of, video_cc_sm8250_match_table);
368 static void video_cc_sm8250_pm_runtime_disable(void *data)
370 pm_runtime_disable(data);
373 static int video_cc_sm8250_probe(struct platform_device *pdev)
375 struct regmap *regmap;
378 pm_runtime_enable(&pdev->dev);
380 ret = devm_add_action_or_reset(&pdev->dev, video_cc_sm8250_pm_runtime_disable, &pdev->dev);
384 ret = pm_runtime_resume_and_get(&pdev->dev);
388 regmap = qcom_cc_map(pdev, &video_cc_sm8250_desc);
389 if (IS_ERR(regmap)) {
390 pm_runtime_put(&pdev->dev);
391 return PTR_ERR(regmap);
394 clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config);
395 clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config);
397 /* Keep VIDEO_CC_AHB_CLK and VIDEO_CC_XO_CLK ALWAYS-ON */
398 regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0));
399 regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0));
401 ret = qcom_cc_really_probe(pdev, &video_cc_sm8250_desc, regmap);
403 pm_runtime_put(&pdev->dev);
408 static struct platform_driver video_cc_sm8250_driver = {
409 .probe = video_cc_sm8250_probe,
411 .name = "sm8250-videocc",
412 .of_match_table = video_cc_sm8250_match_table,
416 static int __init video_cc_sm8250_init(void)
418 return platform_driver_register(&video_cc_sm8250_driver);
420 subsys_initcall(video_cc_sm8250_init);
422 static void __exit video_cc_sm8250_exit(void)
424 platform_driver_unregister(&video_cc_sm8250_driver);
426 module_exit(video_cc_sm8250_exit);
428 MODULE_LICENSE("GPL v2");
429 MODULE_DESCRIPTION("QTI VIDEOCC SM8250 Driver");