drivers/clk/qcom/videocc-sm8250.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk-provider.h>
   7 #include <linux/module.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/regmap.h>
  10
  11 #include <dt-bindings/clock/qcom,videocc-sm8250.h>
  12
  13 #include "clk-alpha-pll.h"
  14 #include "clk-branch.h"
  15 #include "clk-rcg.h"
  16 #include "clk-regmap.h"
  17 #include "clk-regmap-divider.h"
  18 #include "common.h"
  19 #include "reset.h"
  20 #include "gdsc.h"
  21
  22 enum {
  23         P_BI_TCXO,
  24         P_CHIP_SLEEP_CLK,
  25         P_CORE_BI_PLL_TEST_SE,
  26         P_VIDEO_PLL0_OUT_MAIN,
  27         P_VIDEO_PLL1_OUT_MAIN,
  28 };
  29
  30 static struct pll_vco lucid_vco[] = {
  31         { 249600000, 2000000000, 0 },
  32 };
  33
  34 static const struct alpha_pll_config video_pll0_config = {
  35         .l = 0x25,
  36         .alpha = 0x8000,
  37         .config_ctl_val = 0x20485699,
  38         .config_ctl_hi_val = 0x00002261,
  39         .config_ctl_hi1_val = 0x329A699C,
  40         .user_ctl_val = 0x00000000,
  41         .user_ctl_hi_val = 0x00000805,
  42         .user_ctl_hi1_val = 0x00000000,
  43 };
  44
  45 static struct clk_alpha_pll video_pll0 = {
  46         .offset = 0x42c,
  47         .vco_table = lucid_vco,
  48         .num_vco = ARRAY_SIZE(lucid_vco),
  49         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  50         .clkr = {
  51                 .hw.init = &(struct clk_init_data){
  52                         .name = "video_pll0",
  53                         .parent_data = &(const struct clk_parent_data){
  54                                 .fw_name = "bi_tcxo",
  55                         },
  56                         .num_parents = 1,
  57                         .ops = &clk_alpha_pll_lucid_ops,
  58                 },
  59         },
  60 };
  61
  62 static const struct alpha_pll_config video_pll1_config = {
  63         .l = 0x2B,
  64         .alpha = 0xC000,
  65         .config_ctl_val = 0x20485699,
  66         .config_ctl_hi_val = 0x00002261,
  67         .config_ctl_hi1_val = 0x329A699C,
  68         .user_ctl_val = 0x00000000,
  69         .user_ctl_hi_val = 0x00000805,
  70         .user_ctl_hi1_val = 0x00000000,
  71 };
  72
  73 static struct clk_alpha_pll video_pll1 = {
  74         .offset = 0x7d0,
  75         .vco_table = lucid_vco,
  76         .num_vco = ARRAY_SIZE(lucid_vco),
  77         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  78         .clkr = {
  79                 .hw.init = &(struct clk_init_data){
  80                         .name = "video_pll1",
  81                         .parent_data = &(const struct clk_parent_data){
  82                                 .fw_name = "bi_tcxo",
  83                         },
  84                         .num_parents = 1,
  85                         .ops = &clk_alpha_pll_lucid_ops,
  86                 },
  87         },
  88 };
  89
  90 static const struct parent_map video_cc_parent_map_1[] = {
  91         { P_BI_TCXO, 0 },
  92         { P_VIDEO_PLL0_OUT_MAIN, 1 },
  93 };
  94
  95 static const struct clk_parent_data video_cc_parent_data_1[] = {
  96         { .fw_name = "bi_tcxo" },
  97         { .hw = &video_pll0.clkr.hw },
  98 };
  99
 100 static const struct parent_map video_cc_parent_map_2[] = {
 101         { P_BI_TCXO, 0 },
 102         { P_VIDEO_PLL1_OUT_MAIN, 1 },
 103 };
 104
 105 static const struct clk_parent_data video_cc_parent_data_2[] = {
 106         { .fw_name = "bi_tcxo" },
 107         { .hw = &video_pll1.clkr.hw },
 108 };
 109
 110 static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
 111         F(19200000, P_BI_TCXO, 1, 0, 0),
 112         F(720000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
 113         F(1014000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
 114         F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
 115         F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
 116         { }
 117 };
 118
 119 static struct clk_rcg2 video_cc_mvs0_clk_src = {
 120         .cmd_rcgr = 0xb94,
 121         .mnd_width = 0,
 122         .hid_width = 5,
 123         .parent_map = video_cc_parent_map_1,
 124         .freq_tbl = ftbl_video_cc_mvs0_clk_src,
 125         .clkr.hw.init = &(struct clk_init_data){
 126                 .name = "video_cc_mvs0_clk_src",
 127                 .parent_data = video_cc_parent_data_1,
 128                 .num_parents = ARRAY_SIZE(video_cc_parent_data_1),
 129                 .flags = CLK_SET_RATE_PARENT,
 130                 .ops = &clk_rcg2_shared_ops,
 131         },
 132 };
 133
 134 static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
 135         F(19200000, P_BI_TCXO, 1, 0, 0),
 136         F(840000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
 137         F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
 138         F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
 139         { }
 140 };
 141
 142 static struct clk_rcg2 video_cc_mvs1_clk_src = {
 143         .cmd_rcgr = 0xbb4,
 144         .mnd_width = 0,
 145         .hid_width = 5,
 146         .parent_map = video_cc_parent_map_2,
 147         .freq_tbl = ftbl_video_cc_mvs1_clk_src,
 148         .clkr.hw.init = &(struct clk_init_data){
 149                 .name = "video_cc_mvs1_clk_src",
 150                 .parent_data = video_cc_parent_data_2,
 151                 .num_parents = ARRAY_SIZE(video_cc_parent_data_2),
 152                 .flags = CLK_SET_RATE_PARENT,
 153                 .ops = &clk_rcg2_shared_ops,
 154         },
 155 };
 156
 157 static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
 158         .reg = 0xc54,
 159         .shift = 0,
 160         .width = 2,
 161         .clkr.hw.init = &(struct clk_init_data) {
 162                 .name = "video_cc_mvs0c_div2_div_clk_src",
 163                 .parent_data = &(const struct clk_parent_data){
 164                         .hw = &video_cc_mvs0_clk_src.clkr.hw,
 165                 },
 166                 .num_parents = 1,
 167                 .flags = CLK_SET_RATE_PARENT,
 168                 .ops = &clk_regmap_div_ro_ops,
 169         },
 170 };
 171
 172 static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
 173         .reg = 0xd54,
 174         .shift = 0,
 175         .width = 2,
 176         .clkr.hw.init = &(struct clk_init_data) {
 177                 .name = "video_cc_mvs0_div_clk_src",
 178                 .parent_data = &(const struct clk_parent_data){
 179                         .hw = &video_cc_mvs0_clk_src.clkr.hw,
 180                 },
 181                 .num_parents = 1,
 182                 .flags = CLK_SET_RATE_PARENT,
 183                 .ops = &clk_regmap_div_ro_ops,
 184         },
 185 };
 186
 187 static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
 188         .reg = 0xcf4,
 189         .shift = 0,
 190         .width = 2,
 191         .clkr.hw.init = &(struct clk_init_data) {
 192                 .name = "video_cc_mvs1c_div2_div_clk_src",
 193                 .parent_data = &(const struct clk_parent_data){
 194                         .hw = &video_cc_mvs1_clk_src.clkr.hw,
 195                 },
 196                 .num_parents = 1,
 197                 .flags = CLK_SET_RATE_PARENT,
 198                 .ops = &clk_regmap_div_ro_ops,
 199         },
 200 };
 201
 202 static struct clk_branch video_cc_mvs0c_clk = {
 203         .halt_reg = 0xc34,
 204         .halt_check = BRANCH_HALT,
 205         .clkr = {
 206                 .enable_reg = 0xc34,
 207                 .enable_mask = BIT(0),
 208                 .hw.init = &(struct clk_init_data){
 209                         .name = "video_cc_mvs0c_clk",
 210                         .parent_data = &(const struct clk_parent_data){
 211                                 .hw = &video_cc_mvs0c_div2_div_clk_src.clkr.hw,
 212                         },
 213                         .num_parents = 1,
 214                         .flags = CLK_SET_RATE_PARENT,
 215                         .ops = &clk_branch2_ops,
 216                 },
 217         },
 218 };
 219
 220 static struct clk_branch video_cc_mvs0_clk = {
 221         .halt_reg = 0xd34,
 222         .halt_check = BRANCH_HALT_VOTED,
 223         .clkr = {
 224                 .enable_reg = 0xd34,
 225                 .enable_mask = BIT(0),
 226                 .hw.init = &(struct clk_init_data){
 227                         .name = "video_cc_mvs0_clk",
 228                         .parent_data = &(const struct clk_parent_data){
 229                                 .hw = &video_cc_mvs0_div_clk_src.clkr.hw,
 230                         },
 231                         .num_parents = 1,
 232                         .flags = CLK_SET_RATE_PARENT,
 233                         .ops = &clk_branch2_ops,
 234                 },
 235         },
 236 };
 237
 238 static struct clk_branch video_cc_mvs1_div2_clk = {
 239         .halt_reg = 0xdf4,
 240         .halt_check = BRANCH_HALT_VOTED,
 241         .clkr = {
 242                 .enable_reg = 0xdf4,
 243                 .enable_mask = BIT(0),
 244                 .hw.init = &(struct clk_init_data){
 245                         .name = "video_cc_mvs1_div2_clk",
 246                         .parent_data = &(const struct clk_parent_data){
 247                                 .hw = &video_cc_mvs1c_div2_div_clk_src.clkr.hw,
 248                         },
 249                         .num_parents = 1,
 250                         .flags = CLK_SET_RATE_PARENT,
 251                         .ops = &clk_branch2_ops,
 252                 },
 253         },
 254 };
 255
 256 static struct clk_branch video_cc_mvs1c_clk = {
 257         .halt_reg = 0xcd4,
 258         .halt_check = BRANCH_HALT_VOTED,
 259         .clkr = {
 260                 .enable_reg = 0xcd4,
 261                 .enable_mask = BIT(0),
 262                 .hw.init = &(struct clk_init_data){
 263                         .name = "video_cc_mvs1c_clk",
 264                         .parent_data = &(const struct clk_parent_data){
 265                                 .hw = &video_cc_mvs1c_div2_div_clk_src.clkr.hw,
 266                         },
 267                         .num_parents = 1,
 268                         .flags = CLK_SET_RATE_PARENT,
 269                         .ops = &clk_branch2_ops,
 270                 },
 271         },
 272 };
 273
 274 static struct gdsc mvs0c_gdsc = {
 275         .gdscr = 0xbf8,
 276         .pd = {
 277                 .name = "mvs0c_gdsc",
 278         },
 279         .flags = 0,
 280         .pwrsts = PWRSTS_OFF_ON,
 281         .supply = "mmcx",
 282 };
 283
 284 static struct gdsc mvs1c_gdsc = {
 285         .gdscr = 0xc98,
 286         .pd = {
 287                 .name = "mvs1c_gdsc",
 288         },
 289         .flags = 0,
 290         .pwrsts = PWRSTS_OFF_ON,
 291         .supply = "mmcx",
 292 };
 293
 294 static struct gdsc mvs0_gdsc = {
 295         .gdscr = 0xd18,
 296         .pd = {
 297                 .name = "mvs0_gdsc",
 298         },
 299         .flags = HW_CTRL,
 300         .pwrsts = PWRSTS_OFF_ON,
 301         .supply = "mmcx",
 302 };
 303
 304 static struct gdsc mvs1_gdsc = {
 305         .gdscr = 0xd98,
 306         .pd = {
 307                 .name = "mvs1_gdsc",
 308         },
 309         .flags = HW_CTRL,
 310         .pwrsts = PWRSTS_OFF_ON,
 311         .supply = "mmcx",
 312 };
 313
 314 static struct clk_regmap *video_cc_sm8250_clocks[] = {
 315         [VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
 316         [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
 317         [VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
 318         [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
 319         [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
 320         [VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
 321         [VIDEO_CC_MVS1_DIV2_CLK] = &video_cc_mvs1_div2_clk.clkr,
 322         [VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
 323         [VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
 324         [VIDEO_CC_PLL0] = &video_pll0.clkr,
 325         [VIDEO_CC_PLL1] = &video_pll1.clkr,
 326 };
 327
 328 static const struct qcom_reset_map video_cc_sm8250_resets[] = {
 329         [VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 },
 330         [VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 },
 331         [VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 },
 332         [VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 },
 333         [VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 },
 334         [VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 },
 335         [VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 },
 336 };
 337
 338 static struct gdsc *video_cc_sm8250_gdscs[] = {
 339         [MVS0C_GDSC] = &mvs0c_gdsc,
 340         [MVS1C_GDSC] = &mvs1c_gdsc,
 341         [MVS0_GDSC] = &mvs0_gdsc,
 342         [MVS1_GDSC] = &mvs1_gdsc,
 343 };
 344
 345 static const struct regmap_config video_cc_sm8250_regmap_config = {
 346         .reg_bits = 32,
 347         .reg_stride = 4,
 348         .val_bits = 32,
 349         .max_register = 0xf4c,
 350         .fast_io = true,
 351 };
 352
 353 static const struct qcom_cc_desc video_cc_sm8250_desc = {
 354         .config = &video_cc_sm8250_regmap_config,
 355         .clks = video_cc_sm8250_clocks,
 356         .num_clks = ARRAY_SIZE(video_cc_sm8250_clocks),
 357         .resets = video_cc_sm8250_resets,
 358         .num_resets = ARRAY_SIZE(video_cc_sm8250_resets),
 359         .gdscs = video_cc_sm8250_gdscs,
 360         .num_gdscs = ARRAY_SIZE(video_cc_sm8250_gdscs),
 361 };
 362
 363 static const struct of_device_id video_cc_sm8250_match_table[] = {
 364         { .compatible = "qcom,sm8250-videocc" },
 365         { }
 366 };
 367 MODULE_DEVICE_TABLE(of, video_cc_sm8250_match_table);
 368
 369 static int video_cc_sm8250_probe(struct platform_device *pdev)
 370 {
 371         struct regmap *regmap;
 372
 373         regmap = qcom_cc_map(pdev, &video_cc_sm8250_desc);
 374         if (IS_ERR(regmap))
 375                 return PTR_ERR(regmap);
 376
 377         clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config);
 378         clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config);
 379
 380         /* Keep VIDEO_CC_AHB_CLK and VIDEO_CC_XO_CLK ALWAYS-ON */
 381         regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0));
 382         regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0));
 383
 384         return qcom_cc_really_probe(pdev, &video_cc_sm8250_desc, regmap);
 385 }
 386
 387 static struct platform_driver video_cc_sm8250_driver = {
 388         .probe  = video_cc_sm8250_probe,
 389         .driver = {
 390                 .name = "sm8250-videocc",
 391                 .of_match_table = video_cc_sm8250_match_table,
 392         },
 393 };
 394
 395 static int __init video_cc_sm8250_init(void)
 396 {
 397         return platform_driver_register(&video_cc_sm8250_driver);
 398 }
 399 subsys_initcall(video_cc_sm8250_init);
 400
 401 static void __exit video_cc_sm8250_exit(void)
 402 {
 403         platform_driver_unregister(&video_cc_sm8250_driver);
 404 }
 405 module_exit(video_cc_sm8250_exit);
 406
 407 MODULE_LICENSE("GPL v2");
 408 MODULE_DESCRIPTION("QTI VIDEOCC SM8250 Driver");