1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020, Martin Botka <martin.botka@somainline.org>
5 * Copyright (c) 2020, Konrad Dybcio <konrad.dybcio@somainline.org>
8 #include <linux/kernel.h>
9 #include <linux/bitops.h>
10 #include <linux/err.h>
11 #include <linux/platform_device.h>
12 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/clk-provider.h>
16 #include <linux/regmap.h>
17 #include <linux/reset-controller.h>
18 #include <linux/clk.h>
21 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
24 #include "clk-regmap.h"
25 #include "clk-regmap-divider.h"
26 #include "clk-alpha-pll.h"
28 #include "clk-branch.h"
49 P_DP_PHY_PLL_LINK_CLK,
53 static const struct parent_map mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map[] = {
64 static struct clk_alpha_pll mmpll0 = {
66 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
69 .enable_mask = BIT(0),
70 .hw.init = &(struct clk_init_data){
72 .parent_data = &(const struct clk_parent_data){
76 .ops = &clk_alpha_pll_ops,
81 static struct clk_alpha_pll mmpll6 = {
83 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
86 .enable_mask = BIT(2),
87 .hw.init = &(struct clk_init_data){
89 .parent_data = &(const struct clk_parent_data){
93 .ops = &clk_alpha_pll_ops,
98 /* APSS controlled PLLs */
99 static struct pll_vco vco[] = {
100 { 1000000000, 2000000000, 0 },
101 { 750000000, 1500000000, 1 },
102 { 500000000, 1000000000, 2 },
103 { 250000000, 500000000, 3 },
106 static struct pll_vco mmpll3_vco[] = {
107 { 750000000, 1500000000, 1 },
110 static const struct alpha_pll_config mmpll10_config = {
112 .config_ctl_val = 0x00004289,
113 .main_output_mask = 0x1,
116 static struct clk_alpha_pll mmpll10 = {
118 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
120 .hw.init = &(struct clk_init_data){
122 .parent_data = &(const struct clk_parent_data){
126 .ops = &clk_alpha_pll_ops,
131 static const struct alpha_pll_config mmpll3_config = {
133 .config_ctl_val = 0x4001055b,
134 .vco_val = 0x1 << 20,
135 .vco_mask = 0x3 << 20,
136 .main_output_mask = 0x1,
139 static struct clk_alpha_pll mmpll3 = {
141 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
142 .vco_table = mmpll3_vco,
143 .num_vco = ARRAY_SIZE(mmpll3_vco),
145 .hw.init = &(struct clk_init_data){
147 .parent_data = &(const struct clk_parent_data){
151 .ops = &clk_alpha_pll_ops,
156 static const struct alpha_pll_config mmpll4_config = {
158 .config_ctl_val = 0x4001055b,
159 .vco_val = 0x2 << 20,
160 .vco_mask = 0x3 << 20,
161 .main_output_mask = 0x1,
164 static struct clk_alpha_pll mmpll4 = {
166 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
168 .num_vco = ARRAY_SIZE(vco),
170 .hw.init = &(struct clk_init_data){
172 .parent_data = &(const struct clk_parent_data){
176 .ops = &clk_alpha_pll_ops,
181 static const struct alpha_pll_config mmpll5_config = {
183 .config_ctl_val = 0x4001055b,
185 .alpha_en_mask = BIT(24),
186 .vco_val = 0x2 << 20,
187 .vco_mask = 0x3 << 20,
188 .main_output_mask = 0x1,
191 static struct clk_alpha_pll mmpll5 = {
193 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
195 .num_vco = ARRAY_SIZE(vco),
197 .hw.init = &(struct clk_init_data){
199 .parent_data = &(const struct clk_parent_data){
203 .ops = &clk_alpha_pll_ops,
208 static const struct alpha_pll_config mmpll7_config = {
210 .config_ctl_val = 0x4001055b,
211 .vco_val = 0x2 << 20,
212 .vco_mask = 0x3 << 20,
213 .main_output_mask = 0x1,
216 static struct clk_alpha_pll mmpll7 = {
218 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
220 .num_vco = ARRAY_SIZE(vco),
222 .hw.init = &(struct clk_init_data){
224 .parent_data = &(const struct clk_parent_data){
228 .ops = &clk_alpha_pll_ops,
233 static const struct alpha_pll_config mmpll8_config = {
236 .alpha_en_mask = BIT(24),
237 .config_ctl_val = 0x4001055b,
238 .vco_val = 0x2 << 20,
239 .vco_mask = 0x3 << 20,
240 .main_output_mask = 0x1,
243 static struct clk_alpha_pll mmpll8 = {
245 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
247 .num_vco = ARRAY_SIZE(vco),
249 .hw.init = &(struct clk_init_data){
251 .parent_data = &(const struct clk_parent_data){
255 .ops = &clk_alpha_pll_ops,
260 static const struct clk_parent_data mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div[] = {
262 { .hw = &mmpll0.clkr.hw },
263 { .hw = &mmpll4.clkr.hw },
264 { .hw = &mmpll7.clkr.hw },
265 { .hw = &mmpll8.clkr.hw },
266 { .fw_name = "gpll0" },
267 { .fw_name = "gpll0_div" },
270 static const struct parent_map mmcc_xo_dsibyte_map[] = {
272 { P_DSI0PLL_BYTE, 1 },
273 { P_DSI1PLL_BYTE, 2 },
276 static const struct clk_parent_data mmcc_xo_dsibyte[] = {
278 { .fw_name = "dsi0pllbyte" },
279 { .fw_name = "dsi1pllbyte" },
282 static const struct parent_map mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
292 static const struct clk_parent_data mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
294 { .hw = &mmpll0.clkr.hw },
295 { .hw = &mmpll4.clkr.hw },
296 { .hw = &mmpll7.clkr.hw },
297 { .hw = &mmpll10.clkr.hw },
298 { .fw_name = "gpll0" },
299 { .fw_name = "gpll0_div" },
302 static const struct parent_map mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map[] = {
312 static const struct clk_parent_data mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div[] = {
314 { .hw = &mmpll4.clkr.hw },
315 { .hw = &mmpll7.clkr.hw },
316 { .hw = &mmpll10.clkr.hw },
317 { .fw_name = "sleep_clk" },
318 { .fw_name = "gpll0" },
319 { .fw_name = "gpll0_div" },
322 static const struct parent_map mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map[] = {
332 static const struct clk_parent_data mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div[] = {
334 { .hw = &mmpll0.clkr.hw },
335 { .hw = &mmpll7.clkr.hw },
336 { .hw = &mmpll10.clkr.hw },
337 { .fw_name = "sleep_clk" },
338 { .fw_name = "gpll0" },
339 { .fw_name = "gpll0_div" },
342 static const struct parent_map mmcc_xo_gpll0_gpll0_div_map[] = {
348 static const struct clk_parent_data mmcc_xo_gpll0_gpll0_div[] = {
350 { .fw_name = "gpll0" },
351 { .fw_name = "gpll0_div" },
354 static const struct parent_map mmcc_xo_dplink_dpvco_map[] = {
356 { P_DP_PHY_PLL_LINK_CLK, 1 },
357 { P_DP_PHY_PLL_VCO_DIV, 2 },
360 static const struct clk_parent_data mmcc_xo_dplink_dpvco[] = {
362 { .fw_name = "dp_link_2x_clk_divsel_five" },
363 { .fw_name = "dp_vco_divided_clk_src_mux" },
366 static const struct parent_map mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div_map[] = {
375 static const struct clk_parent_data mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div[] = {
377 { .hw = &mmpll0.clkr.hw },
378 { .hw = &mmpll5.clkr.hw },
379 { .hw = &mmpll7.clkr.hw },
380 { .fw_name = "gpll0" },
381 { .fw_name = "gpll0_div" },
384 static const struct parent_map mmcc_xo_dsi0pll_dsi1pll_map[] = {
390 static const struct clk_parent_data mmcc_xo_dsi0pll_dsi1pll[] = {
392 { .fw_name = "dsi0pll" },
393 { .fw_name = "dsi1pll" },
396 static const struct parent_map mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0_map[] = {
406 static const struct clk_parent_data mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0[] = {
408 { .hw = &mmpll0.clkr.hw },
409 { .hw = &mmpll4.clkr.hw },
410 { .hw = &mmpll7.clkr.hw },
411 { .hw = &mmpll10.clkr.hw },
412 { .hw = &mmpll6.clkr.hw },
413 { .fw_name = "gpll0" },
416 static const struct parent_map mmcc_xo_mmpll0_gpll0_gpll0_div_map[] = {
423 static const struct clk_parent_data mmcc_xo_mmpll0_gpll0_gpll0_div[] = {
425 { .hw = &mmpll0.clkr.hw },
426 { .fw_name = "gpll0" },
427 { .fw_name = "gpll0_div" },
430 static const struct parent_map mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6_map[] = {
440 static const struct clk_parent_data mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6[] = {
442 { .hw = &mmpll0.clkr.hw },
443 { .hw = &mmpll4.clkr.hw },
444 { .hw = &mmpll7.clkr.hw },
445 { .hw = &mmpll10.clkr.hw },
446 { .fw_name = "gpll0" },
447 { .hw = &mmpll6.clkr.hw },
450 static const struct parent_map mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7_map[] = {
460 static const struct clk_parent_data mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7[] = {
462 { .hw = &mmpll0.clkr.hw },
463 { .hw = &mmpll8.clkr.hw },
464 { .hw = &mmpll3.clkr.hw },
465 { .hw = &mmpll6.clkr.hw },
466 { .fw_name = "gpll0" },
467 { .hw = &mmpll7.clkr.hw },
470 static const struct freq_tbl ftbl_ahb_clk_src[] = {
471 F(19200000, P_XO, 1, 0, 0),
472 F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
473 F(80800000, P_MMPLL0, 10, 0, 0),
477 static struct clk_rcg2 ahb_clk_src = {
481 .parent_map = mmcc_xo_mmpll0_gpll0_gpll0_div_map,
482 .freq_tbl = ftbl_ahb_clk_src,
483 .clkr.hw.init = &(struct clk_init_data){
484 .name = "ahb_clk_src",
485 .parent_data = mmcc_xo_mmpll0_gpll0_gpll0_div,
487 .ops = &clk_rcg2_ops,
491 static struct clk_rcg2 byte0_clk_src = {
495 .parent_map = mmcc_xo_dsibyte_map,
496 .clkr.hw.init = &(struct clk_init_data){
497 .name = "byte0_clk_src",
498 .parent_data = mmcc_xo_dsibyte,
500 .ops = &clk_byte2_ops,
501 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
505 static struct clk_rcg2 byte1_clk_src = {
509 .parent_map = mmcc_xo_dsibyte_map,
510 .clkr.hw.init = &(struct clk_init_data){
511 .name = "byte1_clk_src",
512 .parent_data = mmcc_xo_dsibyte,
514 .ops = &clk_byte2_ops,
515 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
519 static const struct freq_tbl ftbl_camss_gp0_clk_src[] = {
520 F(10000, P_XO, 16, 1, 120),
521 F(24000, P_XO, 16, 1, 50),
522 F(6000000, P_GPLL0_DIV, 10, 1, 5),
523 F(12000000, P_GPLL0_DIV, 10, 2, 5),
524 F(13043478, P_GPLL0_DIV, 1, 1, 23),
525 F(24000000, P_GPLL0_DIV, 1, 2, 25),
526 F(50000000, P_GPLL0_DIV, 6, 0, 0),
527 F(100000000, P_GPLL0_DIV, 3, 0, 0),
528 F(200000000, P_GPLL0, 3, 0, 0),
532 static struct clk_rcg2 camss_gp0_clk_src = {
536 .parent_map = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
537 .freq_tbl = ftbl_camss_gp0_clk_src,
538 .clkr.hw.init = &(struct clk_init_data){
539 .name = "camss_gp0_clk_src",
540 .parent_data = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
542 .ops = &clk_rcg2_ops,
546 static struct clk_rcg2 camss_gp1_clk_src = {
550 .parent_map = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
551 .freq_tbl = ftbl_camss_gp0_clk_src,
552 .clkr.hw.init = &(struct clk_init_data){
553 .name = "camss_gp1_clk_src",
554 .parent_data = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
556 .ops = &clk_rcg2_ops,
560 static const struct freq_tbl ftbl_cci_clk_src[] = {
561 F(37500000, P_GPLL0_DIV, 8, 0, 0),
562 F(50000000, P_GPLL0_DIV, 6, 0, 0),
563 F(100000000, P_GPLL0, 6, 0, 0),
567 static struct clk_rcg2 cci_clk_src = {
571 .parent_map = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
572 .freq_tbl = ftbl_cci_clk_src,
573 .clkr.hw.init = &(struct clk_init_data){
574 .name = "cci_clk_src",
575 .parent_data = mmcc_xo_mmpll0_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
577 .ops = &clk_rcg2_ops,
581 static const struct freq_tbl ftbl_cpp_clk_src[] = {
582 F(120000000, P_GPLL0, 5, 0, 0),
583 F(256000000, P_MMPLL4, 3, 0, 0),
584 F(384000000, P_MMPLL4, 2, 0, 0),
585 F(480000000, P_MMPLL7, 2, 0, 0),
586 F(540000000, P_MMPLL6, 2, 0, 0),
587 F(576000000, P_MMPLL10, 1, 0, 0),
591 static struct clk_rcg2 cpp_clk_src = {
595 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6_map,
596 .freq_tbl = ftbl_cpp_clk_src,
597 .clkr.hw.init = &(struct clk_init_data){
598 .name = "cpp_clk_src",
599 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_mmpll6,
601 .ops = &clk_rcg2_ops,
605 static const struct freq_tbl ftbl_csi0_clk_src[] = {
606 F(100000000, P_GPLL0_DIV, 3, 0, 0),
607 F(200000000, P_GPLL0, 3, 0, 0),
608 F(310000000, P_MMPLL8, 3, 0, 0),
609 F(404000000, P_MMPLL0, 2, 0, 0),
610 F(465000000, P_MMPLL8, 2, 0, 0),
614 static struct clk_rcg2 csi0_clk_src = {
618 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map,
619 .freq_tbl = ftbl_csi0_clk_src,
620 .clkr.hw.init = &(struct clk_init_data){
621 .name = "csi0_clk_src",
622 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div,
624 .ops = &clk_rcg2_ops,
628 static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = {
629 F(100000000, P_GPLL0_DIV, 3, 0, 0),
630 F(200000000, P_GPLL0, 3, 0, 0),
631 F(269333333, P_MMPLL0, 3, 0, 0),
635 static struct clk_rcg2 csi0phytimer_clk_src = {
639 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
640 .freq_tbl = ftbl_csi0phytimer_clk_src,
641 .clkr.hw.init = &(struct clk_init_data){
642 .name = "csi0phytimer_clk_src",
643 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
645 .ops = &clk_rcg2_ops,
649 static struct clk_rcg2 csi1_clk_src = {
653 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map,
654 .freq_tbl = ftbl_csi0_clk_src,
655 .clkr.hw.init = &(struct clk_init_data){
656 .name = "csi1_clk_src",
657 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div,
659 .ops = &clk_rcg2_ops,
663 static struct clk_rcg2 csi1phytimer_clk_src = {
667 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
668 .freq_tbl = ftbl_csi0phytimer_clk_src,
669 .clkr.hw.init = &(struct clk_init_data){
670 .name = "csi1phytimer_clk_src",
671 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
673 .ops = &clk_rcg2_ops,
677 static struct clk_rcg2 csi2_clk_src = {
681 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map,
682 .freq_tbl = ftbl_csi0_clk_src,
683 .clkr.hw.init = &(struct clk_init_data){
684 .name = "csi2_clk_src",
685 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div,
687 .ops = &clk_rcg2_ops,
691 static struct clk_rcg2 csi2phytimer_clk_src = {
695 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
696 .freq_tbl = ftbl_csi0phytimer_clk_src,
697 .clkr.hw.init = &(struct clk_init_data){
698 .name = "csi2phytimer_clk_src",
699 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
701 .ops = &clk_rcg2_ops,
705 static struct clk_rcg2 csi3_clk_src = {
709 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map,
710 .freq_tbl = ftbl_csi0_clk_src,
711 .clkr.hw.init = &(struct clk_init_data){
712 .name = "csi3_clk_src",
713 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div,
715 .ops = &clk_rcg2_ops,
719 static const struct freq_tbl ftbl_csiphy_clk_src[] = {
720 F(100000000, P_GPLL0_DIV, 3, 0, 0),
721 F(200000000, P_GPLL0, 3, 0, 0),
722 F(269333333, P_MMPLL0, 3, 0, 0),
723 F(320000000, P_MMPLL7, 3, 0, 0),
727 static struct clk_rcg2 csiphy_clk_src = {
731 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div_map,
732 .freq_tbl = ftbl_csiphy_clk_src,
733 .clkr.hw.init = &(struct clk_init_data){
734 .name = "csiphy_clk_src",
735 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll8_gpll0_gpll0_div,
737 .ops = &clk_rcg2_ops,
741 static const struct freq_tbl ftbl_dp_aux_clk_src[] = {
742 F(19200000, P_XO, 1, 0, 0),
746 static struct clk_rcg2 dp_aux_clk_src = {
750 .parent_map = mmcc_xo_gpll0_gpll0_div_map,
751 .freq_tbl = ftbl_dp_aux_clk_src,
752 .clkr.hw.init = &(struct clk_init_data){
753 .name = "dp_aux_clk_src",
754 .parent_data = mmcc_xo_gpll0_gpll0_div,
756 .ops = &clk_rcg2_ops,
760 static const struct freq_tbl ftbl_dp_crypto_clk_src[] = {
761 F(101250000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0),
762 F(168750000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0),
763 F(337500000, P_DP_PHY_PLL_VCO_DIV, 4, 0, 0),
767 static struct clk_rcg2 dp_crypto_clk_src = {
771 .parent_map = mmcc_xo_dplink_dpvco_map,
772 .freq_tbl = ftbl_dp_crypto_clk_src,
773 .clkr.hw.init = &(struct clk_init_data){
774 .name = "dp_crypto_clk_src",
775 .parent_data = mmcc_xo_dplink_dpvco,
777 .ops = &clk_rcg2_ops,
781 static const struct freq_tbl ftbl_dp_gtc_clk_src[] = {
782 F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
783 F(60000000, P_GPLL0, 10, 0, 0),
787 static struct clk_rcg2 dp_gtc_clk_src = {
791 .parent_map = mmcc_xo_gpll0_gpll0_div_map,
792 .freq_tbl = ftbl_dp_gtc_clk_src,
793 .clkr.hw.init = &(struct clk_init_data){
794 .name = "dp_gtc_clk_src",
795 .parent_data = mmcc_xo_gpll0_gpll0_div,
797 .ops = &clk_rcg2_ops,
801 static const struct freq_tbl ftbl_dp_link_clk_src[] = {
802 F(162000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0),
803 F(270000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0),
804 F(540000000, P_DP_PHY_PLL_LINK_CLK, 2, 0, 0),
808 static struct clk_rcg2 dp_link_clk_src = {
812 .parent_map = mmcc_xo_dplink_dpvco_map,
813 .freq_tbl = ftbl_dp_link_clk_src,
814 .clkr.hw.init = &(struct clk_init_data){
815 .name = "dp_link_clk_src",
816 .parent_data = mmcc_xo_dplink_dpvco,
818 .ops = &clk_rcg2_ops,
819 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
823 static struct clk_rcg2 dp_pixel_clk_src = {
827 .parent_map = mmcc_xo_dplink_dpvco_map,
828 .clkr.hw.init = &(struct clk_init_data){
829 .name = "dp_pixel_clk_src",
830 .parent_data = mmcc_xo_dplink_dpvco,
833 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
837 static struct clk_rcg2 esc0_clk_src = {
841 .parent_map = mmcc_xo_dsibyte_map,
842 .clkr.hw.init = &(struct clk_init_data){
843 .name = "esc0_clk_src",
844 .parent_data = mmcc_xo_dsibyte,
846 .ops = &clk_rcg2_ops,
850 static struct clk_rcg2 esc1_clk_src = {
854 .parent_map = mmcc_xo_dsibyte_map,
855 .clkr.hw.init = &(struct clk_init_data){
856 .name = "esc1_clk_src",
857 .parent_data = mmcc_xo_dsibyte,
859 .ops = &clk_rcg2_ops,
863 static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
864 F(66666667, P_GPLL0_DIV, 4.5, 0, 0),
865 F(133333333, P_GPLL0, 4.5, 0, 0),
866 F(219428571, P_MMPLL4, 3.5, 0, 0),
867 F(320000000, P_MMPLL7, 3, 0, 0),
868 F(480000000, P_MMPLL7, 2, 0, 0),
872 static struct clk_rcg2 jpeg0_clk_src = {
876 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
877 .freq_tbl = ftbl_jpeg0_clk_src,
878 .clkr.hw.init = &(struct clk_init_data){
879 .name = "jpeg0_clk_src",
880 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
882 .ops = &clk_rcg2_ops,
886 static const struct freq_tbl ftbl_mclk0_clk_src[] = {
887 F(4800000, P_XO, 4, 0, 0),
888 F(6000000, P_GPLL0_DIV, 10, 1, 5),
889 F(8000000, P_GPLL0_DIV, 1, 2, 75),
890 F(9600000, P_XO, 2, 0, 0),
891 F(16666667, P_GPLL0_DIV, 2, 1, 9),
892 F(19200000, P_XO, 1, 0, 0),
893 F(24000000, P_MMPLL10, 1, 1, 24),
894 F(33333333, P_GPLL0_DIV, 1, 1, 9),
895 F(48000000, P_GPLL0, 1, 2, 25),
896 F(66666667, P_GPLL0, 1, 1, 9),
900 static struct clk_rcg2 mclk0_clk_src = {
904 .parent_map = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
905 .freq_tbl = ftbl_mclk0_clk_src,
906 .clkr.hw.init = &(struct clk_init_data){
907 .name = "mclk0_clk_src",
908 .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
910 .ops = &clk_rcg2_ops,
914 static struct clk_rcg2 mclk1_clk_src = {
918 .parent_map = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
919 .freq_tbl = ftbl_mclk0_clk_src,
920 .clkr.hw.init = &(struct clk_init_data){
921 .name = "mclk1_clk_src",
922 .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
924 .ops = &clk_rcg2_ops,
928 static struct clk_rcg2 mclk2_clk_src = {
932 .parent_map = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
933 .freq_tbl = ftbl_mclk0_clk_src,
934 .clkr.hw.init = &(struct clk_init_data){
935 .name = "mclk2_clk_src",
936 .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
938 .ops = &clk_rcg2_ops,
942 static struct clk_rcg2 mclk3_clk_src = {
946 .parent_map = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div_map,
947 .freq_tbl = ftbl_mclk0_clk_src,
948 .clkr.hw.init = &(struct clk_init_data){
949 .name = "mclk3_clk_src",
950 .parent_data = mmcc_xo_mmpll4_mmpll7_mmpll10_sleep_gpll0_gpll0_div,
952 .ops = &clk_rcg2_ops,
956 static const struct freq_tbl ftbl_mdp_clk_src[] = {
957 F(100000000, P_GPLL0_DIV, 3, 0, 0),
958 F(150000000, P_GPLL0_DIV, 2, 0, 0),
959 F(171428571, P_GPLL0, 3.5, 0, 0),
960 F(200000000, P_GPLL0, 3, 0, 0),
961 F(275000000, P_MMPLL5, 3, 0, 0),
962 F(300000000, P_GPLL0, 2, 0, 0),
963 F(330000000, P_MMPLL5, 2.5, 0, 0),
964 F(412500000, P_MMPLL5, 2, 0, 0),
968 static struct clk_rcg2 mdp_clk_src = {
972 .parent_map = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div_map,
973 .freq_tbl = ftbl_mdp_clk_src,
974 .clkr.hw.init = &(struct clk_init_data){
975 .name = "mdp_clk_src",
976 .parent_data = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div,
978 .ops = &clk_rcg2_ops,
982 static struct clk_rcg2 pclk0_clk_src = {
986 .parent_map = mmcc_xo_dsi0pll_dsi1pll_map,
987 .clkr.hw.init = &(struct clk_init_data){
988 .name = "pclk0_clk_src",
989 .parent_data = mmcc_xo_dsi0pll_dsi1pll,
991 .ops = &clk_pixel_ops,
992 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
996 static struct clk_rcg2 pclk1_clk_src = {
1000 .parent_map = mmcc_xo_dsi0pll_dsi1pll_map,
1001 .clkr.hw.init = &(struct clk_init_data){
1002 .name = "pclk1_clk_src",
1003 .parent_data = mmcc_xo_dsi0pll_dsi1pll,
1005 .ops = &clk_pixel_ops,
1006 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
1010 static const struct freq_tbl ftbl_rot_clk_src[] = {
1011 F(171428571, P_GPLL0, 3.5, 0, 0),
1012 F(275000000, P_MMPLL5, 3, 0, 0),
1013 F(300000000, P_GPLL0, 2, 0, 0),
1014 F(330000000, P_MMPLL5, 2.5, 0, 0),
1015 F(412500000, P_MMPLL5, 2, 0, 0),
1019 static struct clk_rcg2 rot_clk_src = {
1023 .parent_map = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div_map,
1024 .freq_tbl = ftbl_rot_clk_src,
1025 .clkr.hw.init = &(struct clk_init_data){
1026 .name = "rot_clk_src",
1027 .parent_data = mmcc_xo_mmpll0_mmpll5_mmpll7_gpll0_gpll0_div,
1029 .ops = &clk_rcg2_ops,
1033 static const struct freq_tbl ftbl_vfe0_clk_src[] = {
1034 F(120000000, P_GPLL0, 5, 0, 0),
1035 F(200000000, P_GPLL0, 3, 0, 0),
1036 F(256000000, P_MMPLL4, 3, 0, 0),
1037 F(300000000, P_GPLL0, 2, 0, 0),
1038 F(404000000, P_MMPLL0, 2, 0, 0),
1039 F(480000000, P_MMPLL7, 2, 0, 0),
1040 F(540000000, P_MMPLL6, 2, 0, 0),
1041 F(576000000, P_MMPLL10, 1, 0, 0),
1045 static struct clk_rcg2 vfe0_clk_src = {
1049 .parent_map = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0_map,
1050 .freq_tbl = ftbl_vfe0_clk_src,
1051 .clkr.hw.init = &(struct clk_init_data){
1052 .name = "vfe0_clk_src",
1053 .parent_data = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0,
1055 .ops = &clk_rcg2_ops,
1059 static struct clk_rcg2 vfe1_clk_src = {
1063 .parent_map = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0_map,
1064 .freq_tbl = ftbl_vfe0_clk_src,
1065 .clkr.hw.init = &(struct clk_init_data){
1066 .name = "vfe1_clk_src",
1067 .parent_data = mmcc_mmpll0_mmpll4_mmpll7_mmpll10_mmpll6_gpll0,
1069 .ops = &clk_rcg2_ops,
1073 static const struct freq_tbl ftbl_video_core_clk_src[] = {
1074 F(133333333, P_GPLL0, 4.5, 0, 0),
1075 F(269333333, P_MMPLL0, 3, 0, 0),
1076 F(320000000, P_MMPLL7, 3, 0, 0),
1077 F(404000000, P_MMPLL0, 2, 0, 0),
1078 F(441600000, P_MMPLL3, 2, 0, 0),
1079 F(518400000, P_MMPLL3, 2, 0, 0),
1083 static struct clk_rcg2 video_core_clk_src = {
1087 .parent_map = mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7_map,
1088 .freq_tbl = ftbl_video_core_clk_src,
1089 .clkr.hw.init = &(struct clk_init_data){
1090 .name = "video_core_clk_src",
1091 .parent_data = mmcc_xo_mmpll0_mmpll8_mmpll3_mmpll6_gpll0_mmpll7,
1093 .ops = &clk_rcg2_ops,
1094 .flags = CLK_IS_CRITICAL,
1098 static struct clk_rcg2 vsync_clk_src = {
1102 .parent_map = mmcc_xo_gpll0_gpll0_div_map,
1103 .freq_tbl = ftbl_dp_aux_clk_src,
1104 .clkr.hw.init = &(struct clk_init_data){
1105 .name = "vsync_clk_src",
1106 .parent_data = mmcc_xo_gpll0_gpll0_div,
1108 .ops = &clk_rcg2_ops,
1112 static struct clk_branch bimc_smmu_ahb_clk = {
1114 .halt_check = BRANCH_VOTED,
1118 .enable_reg = 0xe004,
1119 .enable_mask = BIT(0),
1120 .hw.init = &(struct clk_init_data){
1121 .name = "bimc_smmu_ahb_clk",
1122 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1124 .ops = &clk_branch2_ops,
1129 static struct clk_branch bimc_smmu_axi_clk = {
1131 .halt_check = BRANCH_VOTED,
1135 .enable_reg = 0xe008,
1136 .enable_mask = BIT(0),
1137 .hw.init = &(struct clk_init_data){
1138 .name = "bimc_smmu_axi_clk",
1139 .ops = &clk_branch2_ops,
1144 static struct clk_branch camss_ahb_clk = {
1146 .halt_check = BRANCH_HALT,
1150 .enable_reg = 0x348c,
1151 .enable_mask = BIT(0),
1152 .hw.init = &(struct clk_init_data){
1153 .name = "camss_ahb_clk",
1154 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1156 .ops = &clk_branch2_ops,
1161 static struct clk_branch camss_cci_ahb_clk = {
1163 .halt_check = BRANCH_HALT,
1165 .enable_reg = 0x3348,
1166 .enable_mask = BIT(0),
1167 .hw.init = &(struct clk_init_data){
1168 .name = "camss_cci_ahb_clk",
1169 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1171 .flags = CLK_SET_RATE_PARENT,
1172 .ops = &clk_branch2_ops,
1177 static struct clk_branch camss_cci_clk = {
1179 .halt_check = BRANCH_HALT,
1181 .enable_reg = 0x3344,
1182 .enable_mask = BIT(0),
1183 .hw.init = &(struct clk_init_data){
1184 .name = "camss_cci_clk",
1185 .parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw },
1187 .flags = CLK_SET_RATE_PARENT,
1188 .ops = &clk_branch2_ops,
1193 static struct clk_branch camss_cpp_ahb_clk = {
1195 .halt_check = BRANCH_HALT,
1197 .enable_reg = 0x36b4,
1198 .enable_mask = BIT(0),
1199 .hw.init = &(struct clk_init_data){
1200 .name = "camss_cpp_ahb_clk",
1201 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1203 .ops = &clk_branch2_ops,
1208 static struct clk_branch camss_cpp_axi_clk = {
1210 .halt_check = BRANCH_HALT,
1212 .enable_reg = 0x36c4,
1213 .enable_mask = BIT(0),
1214 .hw.init = &(struct clk_init_data){
1215 .name = "camss_cpp_axi_clk",
1216 .ops = &clk_branch2_ops,
1221 static struct clk_branch camss_cpp_clk = {
1223 .halt_check = BRANCH_HALT,
1225 .enable_reg = 0x36b0,
1226 .enable_mask = BIT(0),
1227 .hw.init = &(struct clk_init_data){
1228 .name = "camss_cpp_clk",
1229 .parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw },
1231 .flags = CLK_SET_RATE_PARENT,
1232 .ops = &clk_branch2_ops,
1237 static struct clk_branch camss_cpp_vbif_ahb_clk = {
1239 .halt_check = BRANCH_HALT,
1241 .enable_reg = 0x36c8,
1242 .enable_mask = BIT(0),
1243 .hw.init = &(struct clk_init_data){
1244 .name = "camss_cpp_vbif_ahb_clk",
1245 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1247 .ops = &clk_branch2_ops,
1252 static struct clk_branch camss_csi0_ahb_clk = {
1254 .halt_check = BRANCH_HALT,
1256 .enable_reg = 0x30bc,
1257 .enable_mask = BIT(0),
1258 .hw.init = &(struct clk_init_data){
1259 .name = "camss_csi0_ahb_clk",
1260 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1262 .ops = &clk_branch2_ops,
1267 static struct clk_branch camss_csi0_clk = {
1269 .halt_check = BRANCH_HALT,
1271 .enable_reg = 0x30b4,
1272 .enable_mask = BIT(0),
1273 .hw.init = &(struct clk_init_data){
1274 .name = "camss_csi0_clk",
1275 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1277 .flags = CLK_SET_RATE_PARENT,
1278 .ops = &clk_branch2_ops,
1283 static struct clk_branch camss_csi0phytimer_clk = {
1285 .halt_check = BRANCH_HALT,
1287 .enable_reg = 0x3024,
1288 .enable_mask = BIT(0),
1289 .hw.init = &(struct clk_init_data){
1290 .name = "camss_csi0phytimer_clk",
1291 .parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw },
1293 .flags = CLK_SET_RATE_PARENT,
1294 .ops = &clk_branch2_ops,
1299 static struct clk_branch camss_csi0pix_clk = {
1301 .halt_check = BRANCH_HALT,
1303 .enable_reg = 0x30e4,
1304 .enable_mask = BIT(0),
1305 .hw.init = &(struct clk_init_data){
1306 .name = "camss_csi0pix_clk",
1307 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1309 .ops = &clk_branch2_ops,
1314 static struct clk_branch camss_csi0rdi_clk = {
1316 .halt_check = BRANCH_HALT,
1318 .enable_reg = 0x30d4,
1319 .enable_mask = BIT(0),
1320 .hw.init = &(struct clk_init_data){
1321 .name = "camss_csi0rdi_clk",
1322 .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1324 .ops = &clk_branch2_ops,
1329 static struct clk_branch camss_csi1_ahb_clk = {
1331 .halt_check = BRANCH_HALT,
1333 .enable_reg = 0x3128,
1334 .enable_mask = BIT(0),
1335 .hw.init = &(struct clk_init_data){
1336 .name = "camss_csi1_ahb_clk",
1337 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1339 .ops = &clk_branch2_ops,
1344 static struct clk_branch camss_csi1_clk = {
1346 .halt_check = BRANCH_HALT,
1348 .enable_reg = 0x3124,
1349 .enable_mask = BIT(0),
1350 .hw.init = &(struct clk_init_data){
1351 .name = "camss_csi1_clk",
1352 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1354 .flags = CLK_SET_RATE_PARENT,
1355 .ops = &clk_branch2_ops,
1360 static struct clk_branch camss_csi1phytimer_clk = {
1362 .halt_check = BRANCH_HALT,
1364 .enable_reg = 0x3054,
1365 .enable_mask = BIT(0),
1366 .hw.init = &(struct clk_init_data){
1367 .name = "camss_csi1phytimer_clk",
1368 .parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw },
1370 .flags = CLK_SET_RATE_PARENT,
1371 .ops = &clk_branch2_ops,
1376 static struct clk_branch camss_csi1pix_clk = {
1378 .halt_check = BRANCH_HALT,
1380 .enable_reg = 0x3154,
1381 .enable_mask = BIT(0),
1382 .hw.init = &(struct clk_init_data){
1383 .name = "camss_csi1pix_clk",
1384 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1386 .ops = &clk_branch2_ops,
1391 static struct clk_branch camss_csi1rdi_clk = {
1393 .halt_check = BRANCH_HALT,
1395 .enable_reg = 0x3144,
1396 .enable_mask = BIT(0),
1397 .hw.init = &(struct clk_init_data){
1398 .name = "camss_csi1rdi_clk",
1399 .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1401 .ops = &clk_branch2_ops,
1406 static struct clk_branch camss_csi2_ahb_clk = {
1408 .halt_check = BRANCH_HALT,
1410 .enable_reg = 0x3188,
1411 .enable_mask = BIT(0),
1412 .hw.init = &(struct clk_init_data){
1413 .name = "camss_csi2_ahb_clk",
1414 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1416 .ops = &clk_branch2_ops,
1421 static struct clk_branch camss_csi2_clk = {
1423 .halt_check = BRANCH_HALT,
1425 .enable_reg = 0x3184,
1426 .enable_mask = BIT(0),
1427 .hw.init = &(struct clk_init_data){
1428 .name = "camss_csi2_clk",
1429 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1431 .flags = CLK_SET_RATE_PARENT,
1432 .ops = &clk_branch2_ops,
1437 static struct clk_branch camss_csi2phytimer_clk = {
1439 .halt_check = BRANCH_HALT,
1441 .enable_reg = 0x3084,
1442 .enable_mask = BIT(0),
1443 .hw.init = &(struct clk_init_data){
1444 .name = "camss_csi2phytimer_clk",
1445 .parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw },
1447 .flags = CLK_SET_RATE_PARENT,
1448 .ops = &clk_branch2_ops,
1453 static struct clk_branch camss_csi2pix_clk = {
1455 .halt_check = BRANCH_HALT,
1457 .enable_reg = 0x31b4,
1458 .enable_mask = BIT(0),
1459 .hw.init = &(struct clk_init_data){
1460 .name = "camss_csi2pix_clk",
1461 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1463 .ops = &clk_branch2_ops,
1468 static struct clk_branch camss_csi2rdi_clk = {
1470 .halt_check = BRANCH_HALT,
1472 .enable_reg = 0x31a4,
1473 .enable_mask = BIT(0),
1474 .hw.init = &(struct clk_init_data){
1475 .name = "camss_csi2rdi_clk",
1476 .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1478 .ops = &clk_branch2_ops,
1483 static struct clk_branch camss_csi3_ahb_clk = {
1485 .halt_check = BRANCH_HALT,
1487 .enable_reg = 0x31e8,
1488 .enable_mask = BIT(0),
1489 .hw.init = &(struct clk_init_data){
1490 .name = "camss_csi3_ahb_clk",
1491 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1493 .ops = &clk_branch2_ops,
1498 static struct clk_branch camss_csi3_clk = {
1500 .halt_check = BRANCH_HALT,
1502 .enable_reg = 0x31e4,
1503 .enable_mask = BIT(0),
1504 .hw.init = &(struct clk_init_data){
1505 .name = "camss_csi3_clk",
1506 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1508 .flags = CLK_SET_RATE_PARENT,
1509 .ops = &clk_branch2_ops,
1514 static struct clk_branch camss_csi3pix_clk = {
1516 .halt_check = BRANCH_HALT,
1518 .enable_reg = 0x3214,
1519 .enable_mask = BIT(0),
1520 .hw.init = &(struct clk_init_data){
1521 .name = "camss_csi3pix_clk",
1522 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1524 .ops = &clk_branch2_ops,
1529 static struct clk_branch camss_csi3rdi_clk = {
1531 .halt_check = BRANCH_HALT,
1533 .enable_reg = 0x3204,
1534 .enable_mask = BIT(0),
1535 .hw.init = &(struct clk_init_data){
1536 .name = "camss_csi3rdi_clk",
1537 .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1539 .ops = &clk_branch2_ops,
1544 static struct clk_branch camss_csi_vfe0_clk = {
1546 .halt_check = BRANCH_HALT,
1548 .enable_reg = 0x3704,
1549 .enable_mask = BIT(0),
1550 .hw.init = &(struct clk_init_data){
1551 .name = "camss_csi_vfe0_clk",
1552 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
1554 .ops = &clk_branch2_ops,
1559 static struct clk_branch camss_csi_vfe1_clk = {
1561 .halt_check = BRANCH_HALT,
1563 .enable_reg = 0x3714,
1564 .enable_mask = BIT(0),
1565 .hw.init = &(struct clk_init_data){
1566 .name = "camss_csi_vfe1_clk",
1567 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
1569 .ops = &clk_branch2_ops,
1574 static struct clk_branch camss_csiphy0_clk = {
1576 .halt_check = BRANCH_HALT,
1578 .enable_reg = 0x3740,
1579 .enable_mask = BIT(0),
1580 .hw.init = &(struct clk_init_data){
1581 .name = "camss_csiphy0_clk",
1582 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
1584 .flags = CLK_SET_RATE_PARENT,
1585 .ops = &clk_branch2_ops,
1590 static struct clk_branch camss_csiphy1_clk = {
1592 .halt_check = BRANCH_HALT,
1594 .enable_reg = 0x3744,
1595 .enable_mask = BIT(0),
1596 .hw.init = &(struct clk_init_data){
1597 .name = "camss_csiphy1_clk",
1598 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
1600 .flags = CLK_SET_RATE_PARENT,
1601 .ops = &clk_branch2_ops,
1606 static struct clk_branch camss_csiphy2_clk = {
1608 .halt_check = BRANCH_HALT,
1610 .enable_reg = 0x3748,
1611 .enable_mask = BIT(0),
1612 .hw.init = &(struct clk_init_data){
1613 .name = "camss_csiphy2_clk",
1614 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
1616 .flags = CLK_SET_RATE_PARENT,
1617 .ops = &clk_branch2_ops,
1623 static struct clk_branch camss_cphy_csid0_clk = {
1625 .halt_check = BRANCH_HALT,
1627 .enable_reg = 0x3730,
1628 .enable_mask = BIT(0),
1629 .hw.init = &(struct clk_init_data){
1630 .name = "camss_cphy_csid0_clk",
1631 .parent_hws = (const struct clk_hw *[]){ &camss_csiphy0_clk.clkr.hw },
1633 .flags = CLK_SET_RATE_PARENT,
1634 .ops = &clk_branch2_ops,
1639 static struct clk_branch camss_cphy_csid1_clk = {
1641 .halt_check = BRANCH_HALT,
1643 .enable_reg = 0x3734,
1644 .enable_mask = BIT(0),
1645 .hw.init = &(struct clk_init_data){
1646 .name = "camss_cphy_csid1_clk",
1647 .parent_hws = (const struct clk_hw *[]){ &camss_csiphy1_clk.clkr.hw },
1649 .flags = CLK_SET_RATE_PARENT,
1650 .ops = &clk_branch2_ops,
1655 static struct clk_branch camss_cphy_csid2_clk = {
1657 .halt_check = BRANCH_HALT,
1659 .enable_reg = 0x3738,
1660 .enable_mask = BIT(0),
1661 .hw.init = &(struct clk_init_data){
1662 .name = "camss_cphy_csid2_clk",
1663 .parent_hws = (const struct clk_hw *[]){ &camss_csiphy2_clk.clkr.hw },
1665 .flags = CLK_SET_RATE_PARENT,
1666 .ops = &clk_branch2_ops,
1671 static struct clk_branch camss_cphy_csid3_clk = {
1673 .halt_check = BRANCH_HALT,
1675 .enable_reg = 0x373c,
1676 .enable_mask = BIT(0),
1677 .hw.init = &(struct clk_init_data){
1678 .name = "camss_cphy_csid3_clk",
1679 .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
1681 .flags = CLK_SET_RATE_PARENT,
1682 .ops = &clk_branch2_ops,
1687 static struct clk_branch camss_gp0_clk = {
1689 .halt_check = BRANCH_HALT,
1691 .enable_reg = 0x3444,
1692 .enable_mask = BIT(0),
1693 .hw.init = &(struct clk_init_data){
1694 .name = "camss_gp0_clk",
1695 .parent_hws = (const struct clk_hw *[]){ &camss_gp0_clk_src.clkr.hw },
1697 .flags = CLK_SET_RATE_PARENT,
1698 .ops = &clk_branch2_ops,
1703 static struct clk_branch camss_gp1_clk = {
1705 .halt_check = BRANCH_HALT,
1707 .enable_reg = 0x3474,
1708 .enable_mask = BIT(0),
1709 .hw.init = &(struct clk_init_data){
1710 .name = "camss_gp1_clk",
1711 .parent_hws = (const struct clk_hw *[]){ &camss_gp1_clk_src.clkr.hw },
1713 .flags = CLK_SET_RATE_PARENT,
1714 .ops = &clk_branch2_ops,
1719 static struct clk_branch camss_ispif_ahb_clk = {
1721 .halt_check = BRANCH_HALT,
1723 .enable_reg = 0x3224,
1724 .enable_mask = BIT(0),
1725 .hw.init = &(struct clk_init_data){
1726 .name = "camss_ispif_ahb_clk",
1727 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1729 .ops = &clk_branch2_ops,
1734 static struct clk_branch camss_jpeg0_clk = {
1736 .halt_check = BRANCH_HALT,
1738 .enable_reg = 0x35a8,
1739 .enable_mask = BIT(0),
1740 .hw.init = &(struct clk_init_data){
1741 .name = "camss_jpeg0_clk",
1742 .parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw },
1744 .flags = CLK_SET_RATE_PARENT,
1745 .ops = &clk_branch2_ops,
1750 static struct clk_branch camss_jpeg_ahb_clk = {
1752 .halt_check = BRANCH_HALT,
1754 .enable_reg = 0x35b4,
1755 .enable_mask = BIT(0),
1756 .hw.init = &(struct clk_init_data){
1757 .name = "camss_jpeg_ahb_clk",
1758 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1760 .ops = &clk_branch2_ops,
1765 static struct clk_branch camss_jpeg_axi_clk = {
1767 .halt_check = BRANCH_HALT,
1769 .enable_reg = 0x35b8,
1770 .enable_mask = BIT(0),
1771 .hw.init = &(struct clk_init_data){
1772 .name = "camss_jpeg_axi_clk",
1773 .ops = &clk_branch2_ops,
1778 static struct clk_branch throttle_camss_axi_clk = {
1780 .halt_check = BRANCH_HALT,
1782 .enable_reg = 0x3c3c,
1783 .enable_mask = BIT(0),
1784 .hw.init = &(struct clk_init_data){
1785 .name = "throttle_camss_axi_clk",
1786 .ops = &clk_branch2_ops,
1791 static struct clk_branch camss_mclk0_clk = {
1793 .halt_check = BRANCH_HALT,
1795 .enable_reg = 0x3384,
1796 .enable_mask = BIT(0),
1797 .hw.init = &(struct clk_init_data){
1798 .name = "camss_mclk0_clk",
1799 .parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw },
1801 .flags = CLK_SET_RATE_PARENT,
1802 .ops = &clk_branch2_ops,
1807 static struct clk_branch camss_mclk1_clk = {
1809 .halt_check = BRANCH_HALT,
1811 .enable_reg = 0x33b4,
1812 .enable_mask = BIT(0),
1813 .hw.init = &(struct clk_init_data){
1814 .name = "camss_mclk1_clk",
1815 .parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw },
1817 .flags = CLK_SET_RATE_PARENT,
1818 .ops = &clk_branch2_ops,
1823 static struct clk_branch camss_mclk2_clk = {
1825 .halt_check = BRANCH_HALT,
1827 .enable_reg = 0x33e4,
1828 .enable_mask = BIT(0),
1829 .hw.init = &(struct clk_init_data){
1830 .name = "camss_mclk2_clk",
1831 .parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw },
1833 .flags = CLK_SET_RATE_PARENT,
1834 .ops = &clk_branch2_ops,
1839 static struct clk_branch camss_mclk3_clk = {
1841 .halt_check = BRANCH_HALT,
1843 .enable_reg = 0x3414,
1844 .enable_mask = BIT(0),
1845 .hw.init = &(struct clk_init_data){
1846 .name = "camss_mclk3_clk",
1847 .parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw },
1849 .flags = CLK_SET_RATE_PARENT,
1850 .ops = &clk_branch2_ops,
1855 static struct clk_branch camss_micro_ahb_clk = {
1857 .halt_check = BRANCH_HALT,
1859 .enable_reg = 0x3494,
1860 .enable_mask = BIT(0),
1861 .hw.init = &(struct clk_init_data){
1862 .name = "camss_micro_ahb_clk",
1863 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1865 .ops = &clk_branch2_ops,
1870 static struct clk_branch camss_top_ahb_clk = {
1872 .halt_check = BRANCH_HALT,
1874 .enable_reg = 0x3484,
1875 .enable_mask = BIT(0),
1876 .hw.init = &(struct clk_init_data){
1877 .name = "camss_top_ahb_clk",
1878 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1880 .ops = &clk_branch2_ops,
1885 static struct clk_branch camss_vfe0_ahb_clk = {
1887 .halt_check = BRANCH_HALT,
1889 .enable_reg = 0x3668,
1890 .enable_mask = BIT(0),
1891 .hw.init = &(struct clk_init_data){
1892 .name = "camss_vfe0_ahb_clk",
1893 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1895 .ops = &clk_branch2_ops,
1900 static struct clk_branch camss_vfe0_clk = {
1902 .halt_check = BRANCH_HALT,
1904 .enable_reg = 0x36a8,
1905 .enable_mask = BIT(0),
1906 .hw.init = &(struct clk_init_data){
1907 .name = "camss_vfe0_clk",
1908 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
1910 .flags = CLK_SET_RATE_PARENT,
1911 .ops = &clk_branch2_ops,
1916 static struct clk_branch camss_vfe0_stream_clk = {
1918 .halt_check = BRANCH_HALT,
1920 .enable_reg = 0x3720,
1921 .enable_mask = BIT(0),
1922 .hw.init = &(struct clk_init_data){
1923 .name = "camss_vfe0_stream_clk",
1924 .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
1926 .ops = &clk_branch2_ops,
1931 static struct clk_branch camss_vfe1_ahb_clk = {
1933 .halt_check = BRANCH_HALT,
1935 .enable_reg = 0x3678,
1936 .enable_mask = BIT(0),
1937 .hw.init = &(struct clk_init_data){
1938 .name = "camss_vfe1_ahb_clk",
1939 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1941 .ops = &clk_branch2_ops,
1946 static struct clk_branch camss_vfe1_clk = {
1948 .halt_check = BRANCH_HALT,
1950 .enable_reg = 0x36ac,
1951 .enable_mask = BIT(0),
1952 .hw.init = &(struct clk_init_data){
1953 .name = "camss_vfe1_clk",
1954 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
1956 .flags = CLK_SET_RATE_PARENT,
1957 .ops = &clk_branch2_ops,
1962 static struct clk_branch camss_vfe1_stream_clk = {
1964 .halt_check = BRANCH_HALT,
1966 .enable_reg = 0x3724,
1967 .enable_mask = BIT(0),
1968 .hw.init = &(struct clk_init_data){
1969 .name = "camss_vfe1_stream_clk",
1970 .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
1972 .ops = &clk_branch2_ops,
1977 static struct clk_branch camss_vfe_vbif_ahb_clk = {
1979 .halt_check = BRANCH_HALT,
1981 .enable_reg = 0x36b8,
1982 .enable_mask = BIT(0),
1983 .hw.init = &(struct clk_init_data){
1984 .name = "camss_vfe_vbif_ahb_clk",
1985 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1987 .ops = &clk_branch2_ops,
1992 static struct clk_branch camss_vfe_vbif_axi_clk = {
1994 .halt_check = BRANCH_HALT,
1996 .enable_reg = 0x36bc,
1997 .enable_mask = BIT(0),
1998 .hw.init = &(struct clk_init_data){
1999 .name = "camss_vfe_vbif_axi_clk",
2000 .ops = &clk_branch2_ops,
2005 static struct clk_branch csiphy_ahb2crif_clk = {
2007 .halt_check = BRANCH_HALT,
2011 .enable_reg = 0x374c,
2012 .enable_mask = BIT(0),
2013 .hw.init = &(struct clk_init_data){
2014 .name = "csiphy_ahb2crif_clk",
2015 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2017 .ops = &clk_branch2_ops,
2022 static struct clk_branch mdss_ahb_clk = {
2024 .halt_check = BRANCH_HALT,
2025 .hwcg_reg = 0x8a004,
2028 .enable_reg = 0x2308,
2029 .enable_mask = BIT(0),
2030 .hw.init = &(struct clk_init_data){
2031 .name = "mdss_ahb_clk",
2032 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2033 .flags = CLK_SET_RATE_PARENT,
2035 .ops = &clk_branch2_ops,
2040 static const struct freq_tbl ftbl_axi_clk_src[] = {
2041 F(75000000, P_GPLL0, 8, 0, 0),
2042 F(171428571, P_GPLL0, 3.5, 0, 0),
2043 F(240000000, P_GPLL0, 2.5, 0, 0),
2044 F(323200000, P_MMPLL0, 2.5, 0, 0),
2045 F(406000000, P_MMPLL0, 2, 0, 0),
2050 static struct clk_rcg2 axi_clk_src = {
2053 .parent_map = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
2054 .freq_tbl = ftbl_axi_clk_src,
2055 .clkr.hw.init = &(struct clk_init_data){
2056 .name = "axi_clk_src",
2057 .parent_data = mmcc_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
2059 .ops = &clk_rcg2_ops,
2063 static struct clk_branch mdss_axi_clk = {
2065 .halt_check = BRANCH_HALT,
2067 .enable_reg = 0x2310,
2068 .enable_mask = BIT(0),
2069 .hw.init = &(struct clk_init_data){
2070 .name = "mdss_axi_clk",
2071 .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2072 .ops = &clk_branch2_ops,
2077 static struct clk_branch throttle_mdss_axi_clk = {
2079 .halt_check = BRANCH_HALT,
2083 .enable_reg = 0x246c,
2084 .enable_mask = BIT(0),
2085 .hw.init = &(struct clk_init_data){
2086 .name = "throttle_mdss_axi_clk",
2087 .ops = &clk_branch2_ops,
2092 static struct clk_branch mdss_byte0_clk = {
2094 .halt_check = BRANCH_HALT,
2096 .enable_reg = 0x233c,
2097 .enable_mask = BIT(0),
2098 .hw.init = &(struct clk_init_data){
2099 .name = "mdss_byte0_clk",
2100 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
2102 .flags = CLK_SET_RATE_PARENT,
2103 .ops = &clk_branch2_ops,
2108 static struct clk_regmap_div mdss_byte0_intf_div_clk = {
2113 * NOTE: Op does not work for div-3. Current assumption is that div-3
2114 * is not a recommended setting for this divider.
2117 .hw.init = &(struct clk_init_data){
2118 .name = "mdss_byte0_intf_div_clk",
2119 .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
2121 .ops = &clk_regmap_div_ops,
2122 .flags = CLK_GET_RATE_NOCACHE,
2127 static struct clk_branch mdss_byte0_intf_clk = {
2129 .halt_check = BRANCH_HALT,
2131 .enable_reg = 0x2374,
2132 .enable_mask = BIT(0),
2133 .hw.init = &(struct clk_init_data){
2134 .name = "mdss_byte0_intf_clk",
2135 .parent_hws = (const struct clk_hw *[]){ &mdss_byte0_intf_div_clk.clkr.hw },
2137 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2138 .ops = &clk_branch2_ops,
2143 static struct clk_branch mdss_byte1_clk = {
2145 .halt_check = BRANCH_HALT,
2147 .enable_reg = 0x2340,
2148 .enable_mask = BIT(0),
2149 .hw.init = &(struct clk_init_data){
2150 .name = "mdss_byte1_clk",
2151 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
2153 .flags = CLK_SET_RATE_PARENT,
2154 .ops = &clk_branch2_ops,
2159 static struct clk_regmap_div mdss_byte1_intf_div_clk = {
2164 * NOTE: Op does not work for div-3. Current assumption is that div-3
2165 * is not a recommended setting for this divider.
2168 .hw.init = &(struct clk_init_data){
2169 .name = "mdss_byte1_intf_div_clk",
2170 .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
2172 .ops = &clk_regmap_div_ops,
2173 .flags = CLK_GET_RATE_NOCACHE,
2178 static struct clk_branch mdss_byte1_intf_clk = {
2180 .halt_check = BRANCH_HALT,
2182 .enable_reg = 0x2378,
2183 .enable_mask = BIT(0),
2184 .hw.init = &(struct clk_init_data){
2185 .name = "mdss_byte1_intf_clk",
2186 .parent_hws = (const struct clk_hw *[]){ &mdss_byte1_intf_div_clk.clkr.hw },
2188 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2189 .ops = &clk_branch2_ops,
2194 static struct clk_branch mdss_dp_aux_clk = {
2196 .halt_check = BRANCH_HALT,
2198 .enable_reg = 0x2364,
2199 .enable_mask = BIT(0),
2200 .hw.init = &(struct clk_init_data){
2201 .name = "mdss_dp_aux_clk",
2202 .parent_hws = (const struct clk_hw *[]){ &dp_aux_clk_src.clkr.hw },
2204 .flags = CLK_SET_RATE_PARENT,
2205 .ops = &clk_branch2_ops,
2210 static struct clk_branch mdss_dp_crypto_clk = {
2212 .halt_check = BRANCH_HALT,
2214 .enable_reg = 0x235c,
2215 .enable_mask = BIT(0),
2216 .hw.init = &(struct clk_init_data){
2217 .name = "mdss_dp_crypto_clk",
2218 .parent_hws = (const struct clk_hw *[]){ &dp_crypto_clk_src.clkr.hw },
2220 .flags = CLK_SET_RATE_PARENT,
2221 .ops = &clk_branch2_ops,
2226 static struct clk_branch mdss_dp_gtc_clk = {
2228 .halt_check = BRANCH_HALT,
2230 .enable_reg = 0x2368,
2231 .enable_mask = BIT(0),
2232 .hw.init = &(struct clk_init_data){
2233 .name = "mdss_dp_gtc_clk",
2234 .parent_hws = (const struct clk_hw *[]){ &dp_gtc_clk_src.clkr.hw },
2236 .flags = CLK_SET_RATE_PARENT,
2237 .ops = &clk_branch2_ops,
2242 static struct clk_branch mdss_dp_link_clk = {
2244 .halt_check = BRANCH_HALT,
2246 .enable_reg = 0x2354,
2247 .enable_mask = BIT(0),
2248 .hw.init = &(struct clk_init_data){
2249 .name = "mdss_dp_link_clk",
2250 .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
2252 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2253 .ops = &clk_branch2_ops,
2258 /* Reset state of MDSS_DP_LINK_INTF_DIV is 0x3 (div-4) */
2259 static struct clk_branch mdss_dp_link_intf_clk = {
2261 .halt_check = BRANCH_HALT,
2263 .enable_reg = 0x2358,
2264 .enable_mask = BIT(0),
2265 .hw.init = &(struct clk_init_data){
2266 .name = "mdss_dp_link_intf_clk",
2267 .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
2269 .ops = &clk_branch2_ops,
2274 static struct clk_branch mdss_dp_pixel_clk = {
2276 .halt_check = BRANCH_HALT,
2278 .enable_reg = 0x2360,
2279 .enable_mask = BIT(0),
2280 .hw.init = &(struct clk_init_data){
2281 .name = "mdss_dp_pixel_clk",
2282 .parent_hws = (const struct clk_hw *[]){ &dp_pixel_clk_src.clkr.hw },
2284 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2285 .ops = &clk_branch2_ops,
2290 static struct clk_branch mdss_esc0_clk = {
2292 .halt_check = BRANCH_HALT,
2294 .enable_reg = 0x2344,
2295 .enable_mask = BIT(0),
2296 .hw.init = &(struct clk_init_data){
2297 .name = "mdss_esc0_clk",
2298 .parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw },
2300 .flags = CLK_SET_RATE_PARENT,
2301 .ops = &clk_branch2_ops,
2306 static struct clk_branch mdss_esc1_clk = {
2308 .halt_check = BRANCH_HALT,
2310 .enable_reg = 0x2348,
2311 .enable_mask = BIT(0),
2312 .hw.init = &(struct clk_init_data){
2313 .name = "mdss_esc1_clk",
2314 .parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw },
2316 .flags = CLK_SET_RATE_PARENT,
2317 .ops = &clk_branch2_ops,
2322 static struct clk_branch mdss_hdmi_dp_ahb_clk = {
2324 .halt_check = BRANCH_HALT,
2326 .enable_reg = 0x230c,
2327 .enable_mask = BIT(0),
2328 .hw.init = &(struct clk_init_data){
2329 .name = "mdss_hdmi_dp_ahb_clk",
2330 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2332 .ops = &clk_branch2_ops,
2337 static struct clk_branch mdss_mdp_clk = {
2339 .halt_check = BRANCH_HALT,
2341 .enable_reg = 0x231c,
2342 .enable_mask = BIT(0),
2343 .hw.init = &(struct clk_init_data){
2344 .name = "mdss_mdp_clk",
2345 .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
2347 .flags = CLK_SET_RATE_PARENT,
2348 .ops = &clk_branch2_ops,
2353 static struct clk_branch mdss_pclk0_clk = {
2355 .halt_check = BRANCH_HALT,
2357 .enable_reg = 0x2314,
2358 .enable_mask = BIT(0),
2359 .hw.init = &(struct clk_init_data){
2360 .name = "mdss_pclk0_clk",
2361 .parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw },
2363 .flags = CLK_SET_RATE_PARENT,
2364 .ops = &clk_branch2_ops,
2369 static struct clk_branch mdss_pclk1_clk = {
2371 .halt_check = BRANCH_HALT,
2373 .enable_reg = 0x2318,
2374 .enable_mask = BIT(0),
2375 .hw.init = &(struct clk_init_data){
2376 .name = "mdss_pclk1_clk",
2377 .parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw },
2379 .flags = CLK_SET_RATE_PARENT,
2380 .ops = &clk_branch2_ops,
2385 static struct clk_branch mdss_rot_clk = {
2387 .halt_check = BRANCH_HALT,
2389 .enable_reg = 0x2350,
2390 .enable_mask = BIT(0),
2391 .hw.init = &(struct clk_init_data){
2392 .name = "mdss_rot_clk",
2393 .parent_hws = (const struct clk_hw *[]){ &rot_clk_src.clkr.hw },
2395 .flags = CLK_SET_RATE_PARENT,
2396 .ops = &clk_branch2_ops,
2401 static struct clk_branch mdss_vsync_clk = {
2403 .halt_check = BRANCH_HALT,
2405 .enable_reg = 0x2328,
2406 .enable_mask = BIT(0),
2407 .hw.init = &(struct clk_init_data){
2408 .name = "mdss_vsync_clk",
2409 .parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw },
2411 .flags = CLK_SET_RATE_PARENT,
2412 .ops = &clk_branch2_ops,
2417 static struct clk_branch mnoc_ahb_clk = {
2419 .halt_check = BRANCH_VOTED,
2421 .enable_reg = 0x5024,
2422 .enable_mask = BIT(0),
2423 .hw.init = &(struct clk_init_data){
2424 .name = "mnoc_ahb_clk",
2425 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2427 .flags = CLK_SET_RATE_PARENT,
2428 .ops = &clk_branch2_ops,
2433 static struct clk_branch misc_ahb_clk = {
2435 .halt_check = BRANCH_HALT,
2439 .enable_reg = 0x328,
2440 .enable_mask = BIT(0),
2441 .hw.init = &(struct clk_init_data){
2442 .name = "misc_ahb_clk",
2444 * Dependency to be enabled before the branch is
2447 .parent_hws = (const struct clk_hw *[]){ &mnoc_ahb_clk.clkr.hw },
2449 .ops = &clk_branch2_ops,
2454 static struct clk_branch misc_cxo_clk = {
2456 .halt_check = BRANCH_HALT,
2458 .enable_reg = 0x324,
2459 .enable_mask = BIT(0),
2460 .hw.init = &(struct clk_init_data){
2461 .name = "misc_cxo_clk",
2462 .parent_data = &(const struct clk_parent_data){
2466 .ops = &clk_branch2_ops,
2471 static struct clk_branch snoc_dvm_axi_clk = {
2473 .halt_check = BRANCH_HALT,
2475 .enable_reg = 0xe040,
2476 .enable_mask = BIT(0),
2477 .hw.init = &(struct clk_init_data){
2478 .name = "snoc_dvm_axi_clk",
2479 .ops = &clk_branch2_ops,
2484 static struct clk_branch video_ahb_clk = {
2486 .halt_check = BRANCH_HALT,
2490 .enable_reg = 0x1030,
2491 .enable_mask = BIT(0),
2492 .hw.init = &(struct clk_init_data){
2493 .name = "video_ahb_clk",
2494 .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2496 .ops = &clk_branch2_ops,
2501 static struct clk_branch video_axi_clk = {
2503 .halt_check = BRANCH_HALT,
2505 .enable_reg = 0x1034,
2506 .enable_mask = BIT(0),
2507 .hw.init = &(struct clk_init_data){
2508 .name = "video_axi_clk",
2509 .ops = &clk_branch2_ops,
2514 static struct clk_branch throttle_video_axi_clk = {
2516 .halt_check = BRANCH_HALT,
2520 .enable_reg = 0x118c,
2521 .enable_mask = BIT(0),
2522 .hw.init = &(struct clk_init_data){
2523 .name = "throttle_video_axi_clk",
2524 .ops = &clk_branch2_ops,
2529 static struct clk_branch video_core_clk = {
2531 .halt_check = BRANCH_HALT,
2533 .enable_reg = 0x1028,
2534 .enable_mask = BIT(0),
2535 .hw.init = &(struct clk_init_data){
2536 .name = "video_core_clk",
2537 .parent_hws = (const struct clk_hw *[]){ &video_core_clk_src.clkr.hw },
2539 .flags = CLK_SET_RATE_PARENT,
2540 .ops = &clk_branch2_ops,
2545 static struct clk_branch video_subcore0_clk = {
2547 .halt_check = BRANCH_HALT,
2549 .enable_reg = 0x1048,
2550 .enable_mask = BIT(0),
2551 .hw.init = &(struct clk_init_data){
2552 .name = "video_subcore0_clk",
2553 .parent_hws = (const struct clk_hw *[]){ &video_core_clk_src.clkr.hw },
2555 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2556 .ops = &clk_branch2_ops,
2561 static struct gdsc venus_gdsc = {
2566 .pwrsts = PWRSTS_OFF_ON,
2569 static struct gdsc venus_core0_gdsc = {
2572 .name = "venus_core0",
2574 .parent = &venus_gdsc.pd,
2575 .pwrsts = PWRSTS_OFF_ON,
2578 static struct gdsc mdss_gdsc = {
2583 .cxcs = (unsigned int []){ 0x2040 },
2585 .pwrsts = PWRSTS_OFF_ON,
2588 static struct gdsc camss_top_gdsc = {
2591 .name = "camss_top",
2593 .pwrsts = PWRSTS_OFF_ON,
2596 static struct gdsc camss_vfe0_gdsc = {
2599 .name = "camss_vfe0",
2601 .parent = &camss_top_gdsc.pd,
2602 .pwrsts = PWRSTS_OFF_ON,
2605 static struct gdsc camss_vfe1_gdsc = {
2608 .name = "camss_vfe1_gdsc",
2610 .parent = &camss_top_gdsc.pd,
2611 .pwrsts = PWRSTS_OFF_ON,
2614 static struct gdsc camss_cpp_gdsc = {
2617 .name = "camss_cpp",
2619 .parent = &camss_top_gdsc.pd,
2620 .pwrsts = PWRSTS_OFF_ON,
2623 /* This GDSC seems to hang the whole multimedia subsystem.
2624 static struct gdsc bimc_smmu_gdsc = {
2626 .gds_hw_ctrl = 0xe024,
2628 .name = "bimc_smmu",
2630 .pwrsts = PWRSTS_OFF_ON,
2631 .parent = &bimc_smmu_gdsc.pd,
2636 static struct clk_regmap *mmcc_660_clocks[] = {
2637 [AHB_CLK_SRC] = &ahb_clk_src.clkr,
2638 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2639 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2640 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2641 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2642 [CCI_CLK_SRC] = &cci_clk_src.clkr,
2643 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2644 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2645 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2646 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2647 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2648 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2649 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2650 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2651 [CSIPHY_CLK_SRC] = &csiphy_clk_src.clkr,
2652 [DP_AUX_CLK_SRC] = &dp_aux_clk_src.clkr,
2653 [DP_CRYPTO_CLK_SRC] = &dp_crypto_clk_src.clkr,
2654 [DP_GTC_CLK_SRC] = &dp_gtc_clk_src.clkr,
2655 [DP_LINK_CLK_SRC] = &dp_link_clk_src.clkr,
2656 [DP_PIXEL_CLK_SRC] = &dp_pixel_clk_src.clkr,
2657 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2658 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2659 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2660 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2661 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2662 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2663 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2664 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2665 [MMPLL0_PLL] = &mmpll0.clkr,
2666 [MMPLL10_PLL] = &mmpll10.clkr,
2667 [MMPLL3_PLL] = &mmpll3.clkr,
2668 [MMPLL4_PLL] = &mmpll4.clkr,
2669 [MMPLL5_PLL] = &mmpll5.clkr,
2670 [MMPLL6_PLL] = &mmpll6.clkr,
2671 [MMPLL7_PLL] = &mmpll7.clkr,
2672 [MMPLL8_PLL] = &mmpll8.clkr,
2673 [BIMC_SMMU_AHB_CLK] = &bimc_smmu_ahb_clk.clkr,
2674 [BIMC_SMMU_AXI_CLK] = &bimc_smmu_axi_clk.clkr,
2675 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
2676 [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
2677 [CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
2678 [CAMSS_CPHY_CSID0_CLK] = &camss_cphy_csid0_clk.clkr,
2679 [CAMSS_CPHY_CSID1_CLK] = &camss_cphy_csid1_clk.clkr,
2680 [CAMSS_CPHY_CSID2_CLK] = &camss_cphy_csid2_clk.clkr,
2681 [CAMSS_CPHY_CSID3_CLK] = &camss_cphy_csid3_clk.clkr,
2682 [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
2683 [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
2684 [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
2685 [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
2686 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2687 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2688 [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
2689 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2690 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2691 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2692 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2693 [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
2694 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2695 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2696 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2697 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2698 [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
2699 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2700 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2701 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2702 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2703 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2704 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2705 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2706 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2707 [CAMSS_CSIPHY0_CLK] = &camss_csiphy0_clk.clkr,
2708 [CAMSS_CSIPHY1_CLK] = &camss_csiphy1_clk.clkr,
2709 [CAMSS_CSIPHY2_CLK] = &camss_csiphy2_clk.clkr,
2710 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2711 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2712 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2713 [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
2714 [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
2715 [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
2716 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2717 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2718 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2719 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2720 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2721 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2722 [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
2723 [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
2724 [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
2725 [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
2726 [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
2727 [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
2728 [CAMSS_VFE_VBIF_AHB_CLK] = &camss_vfe_vbif_ahb_clk.clkr,
2729 [CAMSS_VFE_VBIF_AXI_CLK] = &camss_vfe_vbif_axi_clk.clkr,
2730 [CSIPHY_AHB2CRIF_CLK] = &csiphy_ahb2crif_clk.clkr,
2731 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2732 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2733 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2734 [MDSS_BYTE0_INTF_CLK] = &mdss_byte0_intf_clk.clkr,
2735 [MDSS_BYTE0_INTF_DIV_CLK] = &mdss_byte0_intf_div_clk.clkr,
2736 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2737 [MDSS_BYTE1_INTF_CLK] = &mdss_byte1_intf_clk.clkr,
2738 [MDSS_DP_AUX_CLK] = &mdss_dp_aux_clk.clkr,
2739 [MDSS_DP_CRYPTO_CLK] = &mdss_dp_crypto_clk.clkr,
2740 [MDSS_DP_GTC_CLK] = &mdss_dp_gtc_clk.clkr,
2741 [MDSS_DP_LINK_CLK] = &mdss_dp_link_clk.clkr,
2742 [MDSS_DP_LINK_INTF_CLK] = &mdss_dp_link_intf_clk.clkr,
2743 [MDSS_DP_PIXEL_CLK] = &mdss_dp_pixel_clk.clkr,
2744 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2745 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2746 [MDSS_HDMI_DP_AHB_CLK] = &mdss_hdmi_dp_ahb_clk.clkr,
2747 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2748 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2749 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2750 [MDSS_ROT_CLK] = &mdss_rot_clk.clkr,
2751 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2752 [MISC_AHB_CLK] = &misc_ahb_clk.clkr,
2753 [MISC_CXO_CLK] = &misc_cxo_clk.clkr,
2754 [MNOC_AHB_CLK] = &mnoc_ahb_clk.clkr,
2755 [SNOC_DVM_AXI_CLK] = &snoc_dvm_axi_clk.clkr,
2756 [THROTTLE_CAMSS_AXI_CLK] = &throttle_camss_axi_clk.clkr,
2757 [THROTTLE_MDSS_AXI_CLK] = &throttle_mdss_axi_clk.clkr,
2758 [THROTTLE_VIDEO_AXI_CLK] = &throttle_video_axi_clk.clkr,
2759 [VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
2760 [VIDEO_AXI_CLK] = &video_axi_clk.clkr,
2761 [VIDEO_CORE_CLK] = &video_core_clk.clkr,
2762 [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
2763 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2764 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2765 [ROT_CLK_SRC] = &rot_clk_src.clkr,
2766 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2767 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2768 [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
2769 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2770 [MDSS_BYTE1_INTF_DIV_CLK] = &mdss_byte1_intf_div_clk.clkr,
2771 [AXI_CLK_SRC] = &axi_clk_src.clkr,
2774 static struct gdsc *mmcc_sdm660_gdscs[] = {
2775 [VENUS_GDSC] = &venus_gdsc,
2776 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
2777 [MDSS_GDSC] = &mdss_gdsc,
2778 [CAMSS_TOP_GDSC] = &camss_top_gdsc,
2779 [CAMSS_VFE0_GDSC] = &camss_vfe0_gdsc,
2780 [CAMSS_VFE1_GDSC] = &camss_vfe1_gdsc,
2781 [CAMSS_CPP_GDSC] = &camss_cpp_gdsc,
2784 static const struct qcom_reset_map mmcc_660_resets[] = {
2785 [CAMSS_MICRO_BCR] = { 0x3490 },
2788 static const struct regmap_config mmcc_660_regmap_config = {
2792 .max_register = 0x40000,
2796 static const struct qcom_cc_desc mmcc_660_desc = {
2797 .config = &mmcc_660_regmap_config,
2798 .clks = mmcc_660_clocks,
2799 .num_clks = ARRAY_SIZE(mmcc_660_clocks),
2800 .resets = mmcc_660_resets,
2801 .num_resets = ARRAY_SIZE(mmcc_660_resets),
2802 .gdscs = mmcc_sdm660_gdscs,
2803 .num_gdscs = ARRAY_SIZE(mmcc_sdm660_gdscs),
2806 static const struct of_device_id mmcc_660_match_table[] = {
2807 { .compatible = "qcom,mmcc-sdm660" },
2808 { .compatible = "qcom,mmcc-sdm630", .data = (void *)1UL },
2811 MODULE_DEVICE_TABLE(of, mmcc_660_match_table);
2813 static void sdm630_clock_override(void)
2815 /* SDM630 has only one DSI */
2816 mmcc_660_desc.clks[BYTE1_CLK_SRC] = NULL;
2817 mmcc_660_desc.clks[MDSS_BYTE1_CLK] = NULL;
2818 mmcc_660_desc.clks[MDSS_BYTE1_INTF_DIV_CLK] = NULL;
2819 mmcc_660_desc.clks[MDSS_BYTE1_INTF_CLK] = NULL;
2820 mmcc_660_desc.clks[ESC1_CLK_SRC] = NULL;
2821 mmcc_660_desc.clks[MDSS_ESC1_CLK] = NULL;
2822 mmcc_660_desc.clks[PCLK1_CLK_SRC] = NULL;
2823 mmcc_660_desc.clks[MDSS_PCLK1_CLK] = NULL;
2826 static int mmcc_660_probe(struct platform_device *pdev)
2828 const struct of_device_id *id;
2829 struct regmap *regmap;
2832 id = of_match_device(mmcc_660_match_table, &pdev->dev);
2835 is_sdm630 = !!(id->data);
2837 regmap = qcom_cc_map(pdev, &mmcc_660_desc);
2839 return PTR_ERR(regmap);
2842 sdm630_clock_override();
2844 clk_alpha_pll_configure(&mmpll3, regmap, &mmpll3_config);
2845 clk_alpha_pll_configure(&mmpll4, regmap, &mmpll4_config);
2846 clk_alpha_pll_configure(&mmpll5, regmap, &mmpll5_config);
2847 clk_alpha_pll_configure(&mmpll7, regmap, &mmpll7_config);
2848 clk_alpha_pll_configure(&mmpll8, regmap, &mmpll8_config);
2849 clk_alpha_pll_configure(&mmpll10, regmap, &mmpll10_config);
2851 return qcom_cc_really_probe(pdev, &mmcc_660_desc, regmap);
2854 static struct platform_driver mmcc_660_driver = {
2855 .probe = mmcc_660_probe,
2857 .name = "mmcc-sdm660",
2858 .of_match_table = mmcc_660_match_table,
2861 module_platform_driver(mmcc_660_driver);
2863 MODULE_DESCRIPTION("Qualcomm SDM630/SDM660 MMCC driver");
2864 MODULE_LICENSE("GPL v2");