drivers/clk/qcom/mmcc-msm8998.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset-controller.h>
  16
  17 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
  18
  19 #include "common.h"
  20 #include "clk-regmap.h"
  21 #include "clk-regmap-divider.h"
  22 #include "clk-alpha-pll.h"
  23 #include "clk-rcg.h"
  24 #include "clk-branch.h"
  25 #include "reset.h"
  26 #include "gdsc.h"
  27
  28 enum {
  29         P_XO,
  30         P_GPLL0,
  31         P_GPLL0_DIV,
  32         P_MMPLL0_OUT_EVEN,
  33         P_MMPLL1_OUT_EVEN,
  34         P_MMPLL3_OUT_EVEN,
  35         P_MMPLL4_OUT_EVEN,
  36         P_MMPLL5_OUT_EVEN,
  37         P_MMPLL6_OUT_EVEN,
  38         P_MMPLL7_OUT_EVEN,
  39         P_MMPLL10_OUT_EVEN,
  40         P_DSI0PLL,
  41         P_DSI1PLL,
  42         P_DSI0PLL_BYTE,
  43         P_DSI1PLL_BYTE,
  44         P_HDMIPLL,
  45         P_DPVCO,
  46         P_DPLINK,
  47         P_CORE_BI_PLL_TEST_SE,
  48 };
  49
  50 static struct clk_fixed_factor gpll0_div = {
  51         .mult = 1,
  52         .div = 2,
  53         .hw.init = &(struct clk_init_data){
  54                 .name = "mmss_gpll0_div",
  55                 .parent_data = &(const struct clk_parent_data){
  56                         .fw_name = "gpll0",
  57                         .name = "gpll0"
  58                 },
  59                 .num_parents = 1,
  60                 .ops = &clk_fixed_factor_ops,
  61         },
  62 };
  63
  64 static const struct clk_div_table post_div_table_fabia_even[] = {
  65         { 0x0, 1 },
  66         { 0x1, 2 },
  67         { 0x3, 4 },
  68         { 0x7, 8 },
  69         { }
  70 };
  71
  72 static struct clk_alpha_pll mmpll0 = {
  73         .offset = 0xc000,
  74         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  75         .clkr = {
  76                 .enable_reg = 0x1e0,
  77                 .enable_mask = BIT(0),
  78                 .hw.init = &(struct clk_init_data){
  79                         .name = "mmpll0",
  80                         .parent_data = &(const struct clk_parent_data){
  81                                 .fw_name = "xo",
  82                                 .name = "xo"
  83                         },
  84                         .num_parents = 1,
  85                         .ops = &clk_alpha_pll_fixed_fabia_ops,
  86                 },
  87         },
  88 };
  89
  90 static struct clk_alpha_pll_postdiv mmpll0_out_even = {
  91         .offset = 0xc000,
  92         .post_div_shift = 8,
  93         .post_div_table = post_div_table_fabia_even,
  94         .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
  95         .width = 4,
  96         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  97         .clkr.hw.init = &(struct clk_init_data){
  98                 .name = "mmpll0_out_even",
  99                 .parent_hws = (const struct clk_hw *[]){ &mmpll0.clkr.hw },
 100                 .num_parents = 1,
 101                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 102         },
 103 };
 104
 105 static struct clk_alpha_pll mmpll1 = {
 106         .offset = 0xc050,
 107         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 108         .clkr = {
 109                 .enable_reg = 0x1e0,
 110                 .enable_mask = BIT(1),
 111                 .hw.init = &(struct clk_init_data){
 112                         .name = "mmpll1",
 113                         .parent_data = &(const struct clk_parent_data){
 114                                 .fw_name = "xo",
 115                                 .name = "xo"
 116                         },
 117                         .num_parents = 1,
 118                         .ops = &clk_alpha_pll_fixed_fabia_ops,
 119                 },
 120         },
 121 };
 122
 123 static struct clk_alpha_pll_postdiv mmpll1_out_even = {
 124         .offset = 0xc050,
 125         .post_div_shift = 8,
 126         .post_div_table = post_div_table_fabia_even,
 127         .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
 128         .width = 4,
 129         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 130         .clkr.hw.init = &(struct clk_init_data){
 131                 .name = "mmpll1_out_even",
 132                 .parent_hws = (const struct clk_hw *[]){ &mmpll1.clkr.hw },
 133                 .num_parents = 1,
 134                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 135         },
 136 };
 137
 138 static struct clk_alpha_pll mmpll3 = {
 139         .offset = 0x0,
 140         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 141         .clkr.hw.init = &(struct clk_init_data){
 142                 .name = "mmpll3",
 143                 .parent_data = &(const struct clk_parent_data){
 144                         .fw_name = "xo",
 145                         .name = "xo"
 146                 },
 147                 .num_parents = 1,
 148                 .ops = &clk_alpha_pll_fixed_fabia_ops,
 149         },
 150 };
 151
 152 static struct clk_alpha_pll_postdiv mmpll3_out_even = {
 153         .offset = 0x0,
 154         .post_div_shift = 8,
 155         .post_div_table = post_div_table_fabia_even,
 156         .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
 157         .width = 4,
 158         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 159         .clkr.hw.init = &(struct clk_init_data){
 160                 .name = "mmpll3_out_even",
 161                 .parent_hws = (const struct clk_hw *[]){ &mmpll3.clkr.hw },
 162                 .num_parents = 1,
 163                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 164         },
 165 };
 166
 167 static struct clk_alpha_pll mmpll4 = {
 168         .offset = 0x50,
 169         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 170         .clkr.hw.init = &(struct clk_init_data){
 171                 .name = "mmpll4",
 172                 .parent_data = &(const struct clk_parent_data){
 173                         .fw_name = "xo",
 174                         .name = "xo"
 175                 },
 176                 .num_parents = 1,
 177                 .ops = &clk_alpha_pll_fixed_fabia_ops,
 178         },
 179 };
 180
 181 static struct clk_alpha_pll_postdiv mmpll4_out_even = {
 182         .offset = 0x50,
 183         .post_div_shift = 8,
 184         .post_div_table = post_div_table_fabia_even,
 185         .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
 186         .width = 4,
 187         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 188         .clkr.hw.init = &(struct clk_init_data){
 189                 .name = "mmpll4_out_even",
 190                 .parent_hws = (const struct clk_hw *[]){ &mmpll4.clkr.hw },
 191                 .num_parents = 1,
 192                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 193         },
 194 };
 195
 196 static struct clk_alpha_pll mmpll5 = {
 197         .offset = 0xa0,
 198         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 199         .clkr.hw.init = &(struct clk_init_data){
 200                 .name = "mmpll5",
 201                 .parent_data = &(const struct clk_parent_data){
 202                         .fw_name = "xo",
 203                         .name = "xo"
 204                 },
 205                 .num_parents = 1,
 206                 .ops = &clk_alpha_pll_fixed_fabia_ops,
 207         },
 208 };
 209
 210 static struct clk_alpha_pll_postdiv mmpll5_out_even = {
 211         .offset = 0xa0,
 212         .post_div_shift = 8,
 213         .post_div_table = post_div_table_fabia_even,
 214         .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
 215         .width = 4,
 216         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 217         .clkr.hw.init = &(struct clk_init_data){
 218                 .name = "mmpll5_out_even",
 219                 .parent_hws = (const struct clk_hw *[]){ &mmpll5.clkr.hw },
 220                 .num_parents = 1,
 221                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 222         },
 223 };
 224
 225 static struct clk_alpha_pll mmpll6 = {
 226         .offset = 0xf0,
 227         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 228         .clkr.hw.init = &(struct clk_init_data){
 229                 .name = "mmpll6",
 230                 .parent_data = &(const struct clk_parent_data){
 231                         .fw_name = "xo",
 232                         .name = "xo"
 233                 },
 234                 .num_parents = 1,
 235                 .ops = &clk_alpha_pll_fixed_fabia_ops,
 236         },
 237 };
 238
 239 static struct clk_alpha_pll_postdiv mmpll6_out_even = {
 240         .offset = 0xf0,
 241         .post_div_shift = 8,
 242         .post_div_table = post_div_table_fabia_even,
 243         .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
 244         .width = 4,
 245         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 246         .clkr.hw.init = &(struct clk_init_data){
 247                 .name = "mmpll6_out_even",
 248                 .parent_hws = (const struct clk_hw *[]){ &mmpll6.clkr.hw },
 249                 .num_parents = 1,
 250                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 251         },
 252 };
 253
 254 static struct clk_alpha_pll mmpll7 = {
 255         .offset = 0x140,
 256         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 257         .clkr.hw.init = &(struct clk_init_data){
 258                 .name = "mmpll7",
 259                 .parent_data = &(const struct clk_parent_data){
 260                         .fw_name = "xo",
 261                         .name = "xo"
 262                 },
 263                 .num_parents = 1,
 264                 .ops = &clk_alpha_pll_fixed_fabia_ops,
 265         },
 266 };
 267
 268 static struct clk_alpha_pll_postdiv mmpll7_out_even = {
 269         .offset = 0x140,
 270         .post_div_shift = 8,
 271         .post_div_table = post_div_table_fabia_even,
 272         .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
 273         .width = 4,
 274         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 275         .clkr.hw.init = &(struct clk_init_data){
 276                 .name = "mmpll7_out_even",
 277                 .parent_hws = (const struct clk_hw *[]){ &mmpll7.clkr.hw },
 278                 .num_parents = 1,
 279                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 280         },
 281 };
 282
 283 static struct clk_alpha_pll mmpll10 = {
 284         .offset = 0x190,
 285         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 286         .clkr.hw.init = &(struct clk_init_data){
 287                 .name = "mmpll10",
 288                 .parent_data = &(const struct clk_parent_data){
 289                         .fw_name = "xo",
 290                         .name = "xo"
 291                 },
 292                 .num_parents = 1,
 293                 .ops = &clk_alpha_pll_fixed_fabia_ops,
 294         },
 295 };
 296
 297 static struct clk_alpha_pll_postdiv mmpll10_out_even = {
 298         .offset = 0x190,
 299         .post_div_shift = 8,
 300         .post_div_table = post_div_table_fabia_even,
 301         .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
 302         .width = 4,
 303         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 304         .clkr.hw.init = &(struct clk_init_data){
 305                 .name = "mmpll10_out_even",
 306                 .parent_hws = (const struct clk_hw *[]){ &mmpll10.clkr.hw },
 307                 .num_parents = 1,
 308                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
 309         },
 310 };
 311
 312 static const struct parent_map mmss_xo_hdmi_map[] = {
 313         { P_XO, 0 },
 314         { P_HDMIPLL, 1 },
 315         { P_CORE_BI_PLL_TEST_SE, 7 }
 316 };
 317
 318 static const struct clk_parent_data mmss_xo_hdmi[] = {
 319         { .fw_name = "xo", .name = "xo" },
 320         { .fw_name = "hdmipll", .name = "hdmipll" },
 321         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 322 };
 323
 324 static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
 325         { P_XO, 0 },
 326         { P_DSI0PLL, 1 },
 327         { P_DSI1PLL, 2 },
 328         { P_CORE_BI_PLL_TEST_SE, 7 }
 329 };
 330
 331 static const struct clk_parent_data mmss_xo_dsi0pll_dsi1pll[] = {
 332         { .fw_name = "xo", .name = "xo" },
 333         { .fw_name = "dsi0dsi", .name = "dsi0dsi" },
 334         { .fw_name = "dsi1dsi", .name = "dsi1dsi" },
 335         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 336 };
 337
 338 static const struct parent_map mmss_xo_dsibyte_map[] = {
 339         { P_XO, 0 },
 340         { P_DSI0PLL_BYTE, 1 },
 341         { P_DSI1PLL_BYTE, 2 },
 342         { P_CORE_BI_PLL_TEST_SE, 7 }
 343 };
 344
 345 static const struct clk_parent_data mmss_xo_dsibyte[] = {
 346         { .fw_name = "xo", .name = "xo" },
 347         { .fw_name = "dsi0byte", .name = "dsi0byte" },
 348         { .fw_name = "dsi1byte", .name = "dsi1byte" },
 349         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 350 };
 351
 352 static const struct parent_map mmss_xo_dp_map[] = {
 353         { P_XO, 0 },
 354         { P_DPLINK, 1 },
 355         { P_DPVCO, 2 },
 356         { P_CORE_BI_PLL_TEST_SE, 7 }
 357 };
 358
 359 static const struct clk_parent_data mmss_xo_dp[] = {
 360         { .fw_name = "xo", .name = "xo" },
 361         { .fw_name = "dplink", .name = "dplink" },
 362         { .fw_name = "dpvco", .name = "dpvco" },
 363         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 364 };
 365
 366 static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
 367         { P_XO, 0 },
 368         { P_GPLL0, 5 },
 369         { P_GPLL0_DIV, 6 },
 370         { P_CORE_BI_PLL_TEST_SE, 7 }
 371 };
 372
 373 static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = {
 374         { .fw_name = "xo", .name = "xo" },
 375         { .fw_name = "gpll0", .name = "gpll0" },
 376         { .hw = &gpll0_div.hw },
 377         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 378 };
 379
 380 static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
 381         { P_XO, 0 },
 382         { P_MMPLL0_OUT_EVEN, 1 },
 383         { P_GPLL0, 5 },
 384         { P_GPLL0_DIV, 6 },
 385         { P_CORE_BI_PLL_TEST_SE, 7 }
 386 };
 387
 388 static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = {
 389         { .fw_name = "xo", .name = "xo" },
 390         { .hw = &mmpll0_out_even.clkr.hw },
 391         { .fw_name = "gpll0", .name = "gpll0" },
 392         { .hw = &gpll0_div.hw },
 393         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 394 };
 395
 396 static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
 397         { P_XO, 0 },
 398         { P_MMPLL0_OUT_EVEN, 1 },
 399         { P_MMPLL1_OUT_EVEN, 2 },
 400         { P_GPLL0, 5 },
 401         { P_GPLL0_DIV, 6 },
 402         { P_CORE_BI_PLL_TEST_SE, 7 }
 403 };
 404
 405 static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
 406         { .fw_name = "xo", .name = "xo" },
 407         { .hw = &mmpll0_out_even.clkr.hw },
 408         { .hw = &mmpll1_out_even.clkr.hw },
 409         { .fw_name = "gpll0", .name = "gpll0" },
 410         { .hw = &gpll0_div.hw },
 411         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 412 };
 413
 414 static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
 415         { P_XO, 0 },
 416         { P_MMPLL0_OUT_EVEN, 1 },
 417         { P_MMPLL5_OUT_EVEN, 2 },
 418         { P_GPLL0, 5 },
 419         { P_GPLL0_DIV, 6 },
 420         { P_CORE_BI_PLL_TEST_SE, 7 }
 421 };
 422
 423 static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
 424         { .fw_name = "xo", .name = "xo" },
 425         { .hw = &mmpll0_out_even.clkr.hw },
 426         { .hw = &mmpll5_out_even.clkr.hw },
 427         { .fw_name = "gpll0", .name = "gpll0" },
 428         { .hw = &gpll0_div.hw },
 429         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 430 };
 431
 432 static const struct parent_map mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map[] = {
 433         { P_XO, 0 },
 434         { P_MMPLL0_OUT_EVEN, 1 },
 435         { P_MMPLL3_OUT_EVEN, 3 },
 436         { P_MMPLL6_OUT_EVEN, 4 },
 437         { P_GPLL0, 5 },
 438         { P_GPLL0_DIV, 6 },
 439         { P_CORE_BI_PLL_TEST_SE, 7 }
 440 };
 441
 442 static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div[] = {
 443         { .fw_name = "xo", .name = "xo" },
 444         { .hw = &mmpll0_out_even.clkr.hw },
 445         { .hw = &mmpll3_out_even.clkr.hw },
 446         { .hw = &mmpll6_out_even.clkr.hw },
 447         { .fw_name = "gpll0", .name = "gpll0" },
 448         { .hw = &gpll0_div.hw },
 449         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 450 };
 451
 452 static const struct parent_map mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
 453         { P_XO, 0 },
 454         { P_MMPLL4_OUT_EVEN, 1 },
 455         { P_MMPLL7_OUT_EVEN, 2 },
 456         { P_MMPLL10_OUT_EVEN, 3 },
 457         { P_GPLL0, 5 },
 458         { P_GPLL0_DIV, 6 },
 459         { P_CORE_BI_PLL_TEST_SE, 7 }
 460 };
 461
 462 static const struct clk_parent_data mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
 463         { .fw_name = "xo", .name = "xo" },
 464         { .hw = &mmpll4_out_even.clkr.hw },
 465         { .hw = &mmpll7_out_even.clkr.hw },
 466         { .hw = &mmpll10_out_even.clkr.hw },
 467         { .fw_name = "gpll0", .name = "gpll0" },
 468         { .hw = &gpll0_div.hw },
 469         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 470 };
 471
 472 static const struct parent_map mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
 473         { P_XO, 0 },
 474         { P_MMPLL0_OUT_EVEN, 1 },
 475         { P_MMPLL7_OUT_EVEN, 2 },
 476         { P_MMPLL10_OUT_EVEN, 3 },
 477         { P_GPLL0, 5 },
 478         { P_GPLL0_DIV, 6 },
 479         { P_CORE_BI_PLL_TEST_SE, 7 }
 480 };
 481
 482 static const struct clk_parent_data mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div[] = {
 483         { .fw_name = "xo", .name = "xo" },
 484         { .hw = &mmpll0_out_even.clkr.hw },
 485         { .hw = &mmpll7_out_even.clkr.hw },
 486         { .hw = &mmpll10_out_even.clkr.hw },
 487         { .fw_name = "gpll0", .name = "gpll0" },
 488         { .hw = &gpll0_div.hw },
 489         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 490 };
 491
 492 static const struct parent_map mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
 493         { P_XO, 0 },
 494         { P_MMPLL0_OUT_EVEN, 1 },
 495         { P_MMPLL4_OUT_EVEN, 2 },
 496         { P_MMPLL7_OUT_EVEN, 3 },
 497         { P_MMPLL10_OUT_EVEN, 4 },
 498         { P_GPLL0, 5 },
 499         { P_GPLL0_DIV, 6 },
 500         { P_CORE_BI_PLL_TEST_SE, 7 }
 501 };
 502
 503 static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
 504         { .fw_name = "xo", .name = "xo" },
 505         { .hw = &mmpll0_out_even.clkr.hw },
 506         { .hw = &mmpll4_out_even.clkr.hw },
 507         { .hw = &mmpll7_out_even.clkr.hw },
 508         { .hw = &mmpll10_out_even.clkr.hw },
 509         { .fw_name = "gpll0", .name = "gpll0" },
 510         { .hw = &gpll0_div.hw },
 511         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 512 };
 513
 514 static struct clk_rcg2 byte0_clk_src = {
 515         .cmd_rcgr = 0x2120,
 516         .hid_width = 5,
 517         .parent_map = mmss_xo_dsibyte_map,
 518         .clkr.hw.init = &(struct clk_init_data){
 519                 .name = "byte0_clk_src",
 520                 .parent_data = mmss_xo_dsibyte,
 521                 .num_parents = 4,
 522                 .ops = &clk_byte2_ops,
 523                 .flags = CLK_SET_RATE_PARENT,
 524         },
 525 };
 526
 527 static struct clk_rcg2 byte1_clk_src = {
 528         .cmd_rcgr = 0x2140,
 529         .hid_width = 5,
 530         .parent_map = mmss_xo_dsibyte_map,
 531         .clkr.hw.init = &(struct clk_init_data){
 532                 .name = "byte1_clk_src",
 533                 .parent_data = mmss_xo_dsibyte,
 534                 .num_parents = 4,
 535                 .ops = &clk_byte2_ops,
 536                 .flags = CLK_SET_RATE_PARENT,
 537         },
 538 };
 539
 540 static const struct freq_tbl ftbl_cci_clk_src[] = {
 541         F(37500000, P_GPLL0, 16, 0, 0),
 542         F(50000000, P_GPLL0, 12, 0, 0),
 543         F(100000000, P_GPLL0, 6, 0, 0),
 544         { }
 545 };
 546
 547 static struct clk_rcg2 cci_clk_src = {
 548         .cmd_rcgr = 0x3300,
 549         .hid_width = 5,
 550         .parent_map = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map,
 551         .freq_tbl = ftbl_cci_clk_src,
 552         .clkr.hw.init = &(struct clk_init_data){
 553                 .name = "cci_clk_src",
 554                 .parent_data = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div,
 555                 .num_parents = 7,
 556                 .ops = &clk_rcg2_ops,
 557         },
 558 };
 559
 560 static const struct freq_tbl ftbl_cpp_clk_src[] = {
 561         F(100000000, P_GPLL0, 6, 0, 0),
 562         F(200000000, P_GPLL0, 3, 0, 0),
 563         F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
 564         F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
 565         F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
 566         F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
 567         F(600000000, P_GPLL0, 1, 0, 0),
 568         { }
 569 };
 570
 571 static struct clk_rcg2 cpp_clk_src = {
 572         .cmd_rcgr = 0x3640,
 573         .hid_width = 5,
 574         .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
 575         .freq_tbl = ftbl_cpp_clk_src,
 576         .clkr.hw.init = &(struct clk_init_data){
 577                 .name = "cpp_clk_src",
 578                 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
 579                 .num_parents = 8,
 580                 .ops = &clk_rcg2_ops,
 581         },
 582 };
 583
 584 static const struct freq_tbl ftbl_csi_clk_src[] = {
 585         F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
 586         F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
 587         F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
 588         F(300000000, P_GPLL0, 2, 0, 0),
 589         F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
 590         F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
 591         { }
 592 };
 593
 594 static struct clk_rcg2 csi0_clk_src = {
 595         .cmd_rcgr = 0x3090,
 596         .hid_width = 5,
 597         .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
 598         .freq_tbl = ftbl_csi_clk_src,
 599         .clkr.hw.init = &(struct clk_init_data){
 600                 .name = "csi0_clk_src",
 601                 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
 602                 .num_parents = 8,
 603                 .ops = &clk_rcg2_ops,
 604         },
 605 };
 606
 607 static struct clk_rcg2 csi1_clk_src = {
 608         .cmd_rcgr = 0x3100,
 609         .hid_width = 5,
 610         .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
 611         .freq_tbl = ftbl_csi_clk_src,
 612         .clkr.hw.init = &(struct clk_init_data){
 613                 .name = "csi1_clk_src",
 614                 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
 615                 .num_parents = 8,
 616                 .ops = &clk_rcg2_ops,
 617         },
 618 };
 619
 620 static struct clk_rcg2 csi2_clk_src = {
 621         .cmd_rcgr = 0x3160,
 622         .hid_width = 5,
 623         .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
 624         .freq_tbl = ftbl_csi_clk_src,
 625         .clkr.hw.init = &(struct clk_init_data){
 626                 .name = "csi2_clk_src",
 627                 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
 628                 .num_parents = 8,
 629                 .ops = &clk_rcg2_ops,
 630         },
 631 };
 632
 633 static struct clk_rcg2 csi3_clk_src = {
 634         .cmd_rcgr = 0x31c0,
 635         .hid_width = 5,
 636         .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
 637         .freq_tbl = ftbl_csi_clk_src,
 638         .clkr.hw.init = &(struct clk_init_data){
 639                 .name = "csi3_clk_src",
 640                 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
 641                 .num_parents = 8,
 642                 .ops = &clk_rcg2_ops,
 643         },
 644 };
 645
 646 static const struct freq_tbl ftbl_csiphy_clk_src[] = {
 647         F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
 648         F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
 649         F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
 650         F(300000000, P_GPLL0, 2, 0, 0),
 651         F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
 652         { }
 653 };
 654
 655 static struct clk_rcg2 csiphy_clk_src = {
 656         .cmd_rcgr = 0x3800,
 657         .hid_width = 5,
 658         .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
 659         .freq_tbl = ftbl_csiphy_clk_src,
 660         .clkr.hw.init = &(struct clk_init_data){
 661                 .name = "csiphy_clk_src",
 662                 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
 663                 .num_parents = 8,
 664                 .ops = &clk_rcg2_ops,
 665         },
 666 };
 667
 668 static const struct freq_tbl ftbl_csiphytimer_clk_src[] = {
 669         F(200000000, P_GPLL0, 3, 0, 0),
 670         F(269333333, P_MMPLL0_OUT_EVEN, 3, 0, 0),
 671         { }
 672 };
 673
 674 static struct clk_rcg2 csi0phytimer_clk_src = {
 675         .cmd_rcgr = 0x3000,
 676         .hid_width = 5,
 677         .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
 678         .freq_tbl = ftbl_csiphytimer_clk_src,
 679         .clkr.hw.init = &(struct clk_init_data){
 680                 .name = "csi0phytimer_clk_src",
 681                 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
 682                 .num_parents = 8,
 683                 .ops = &clk_rcg2_ops,
 684         },
 685 };
 686
 687 static struct clk_rcg2 csi1phytimer_clk_src = {
 688         .cmd_rcgr = 0x3030,
 689         .hid_width = 5,
 690         .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
 691         .freq_tbl = ftbl_csiphytimer_clk_src,
 692         .clkr.hw.init = &(struct clk_init_data){
 693                 .name = "csi1phytimer_clk_src",
 694                 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
 695                 .num_parents = 8,
 696                 .ops = &clk_rcg2_ops,
 697         },
 698 };
 699
 700 static struct clk_rcg2 csi2phytimer_clk_src = {
 701         .cmd_rcgr = 0x3060,
 702         .hid_width = 5,
 703         .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
 704         .freq_tbl = ftbl_csiphytimer_clk_src,
 705         .clkr.hw.init = &(struct clk_init_data){
 706                 .name = "csi2phytimer_clk_src",
 707                 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
 708                 .num_parents = 8,
 709                 .ops = &clk_rcg2_ops,
 710         },
 711 };
 712
 713 static const struct freq_tbl ftbl_dp_aux_clk_src[] = {
 714         F(19200000, P_XO, 1, 0, 0),
 715         { }
 716 };
 717
 718 static struct clk_rcg2 dp_aux_clk_src = {
 719         .cmd_rcgr = 0x2260,
 720         .hid_width = 5,
 721         .parent_map = mmss_xo_gpll0_gpll0_div_map,
 722         .freq_tbl = ftbl_dp_aux_clk_src,
 723         .clkr.hw.init = &(struct clk_init_data){
 724                 .name = "dp_aux_clk_src",
 725                 .parent_data = mmss_xo_gpll0_gpll0_div,
 726                 .num_parents = 4,
 727                 .ops = &clk_rcg2_ops,
 728         },
 729 };
 730
 731 static const struct freq_tbl ftbl_dp_crypto_clk_src[] = {
 732         F(101250, P_DPLINK, 1, 5, 16),
 733         F(168750, P_DPLINK, 1, 5, 16),
 734         F(337500, P_DPLINK, 1, 5, 16),
 735         { }
 736 };
 737
 738 static struct clk_rcg2 dp_crypto_clk_src = {
 739         .cmd_rcgr = 0x2220,
 740         .hid_width = 5,
 741         .parent_map = mmss_xo_dp_map,
 742         .freq_tbl = ftbl_dp_crypto_clk_src,
 743         .clkr.hw.init = &(struct clk_init_data){
 744                 .name = "dp_crypto_clk_src",
 745                 .parent_data = mmss_xo_dp,
 746                 .num_parents = 4,
 747                 .ops = &clk_rcg2_ops,
 748         },
 749 };
 750
 751 static const struct freq_tbl ftbl_dp_link_clk_src[] = {
 752         F(162000, P_DPLINK, 2, 0, 0),
 753         F(270000, P_DPLINK, 2, 0, 0),
 754         F(540000, P_DPLINK, 2, 0, 0),
 755         { }
 756 };
 757
 758 static struct clk_rcg2 dp_link_clk_src = {
 759         .cmd_rcgr = 0x2200,
 760         .hid_width = 5,
 761         .parent_map = mmss_xo_dp_map,
 762         .freq_tbl = ftbl_dp_link_clk_src,
 763         .clkr.hw.init = &(struct clk_init_data){
 764                 .name = "dp_link_clk_src",
 765                 .parent_data = mmss_xo_dp,
 766                 .num_parents = 4,
 767                 .ops = &clk_rcg2_ops,
 768         },
 769 };
 770
 771 static const struct freq_tbl ftbl_dp_pixel_clk_src[] = {
 772         F(154000000, P_DPVCO, 1, 0, 0),
 773         F(337500000, P_DPVCO, 2, 0, 0),
 774         F(675000000, P_DPVCO, 2, 0, 0),
 775         { }
 776 };
 777
 778 static struct clk_rcg2 dp_pixel_clk_src = {
 779         .cmd_rcgr = 0x2240,
 780         .hid_width = 5,
 781         .parent_map = mmss_xo_dp_map,
 782         .freq_tbl = ftbl_dp_pixel_clk_src,
 783         .clkr.hw.init = &(struct clk_init_data){
 784                 .name = "dp_pixel_clk_src",
 785                 .parent_data = mmss_xo_dp,
 786                 .num_parents = 4,
 787                 .ops = &clk_rcg2_ops,
 788         },
 789 };
 790
 791 static const struct freq_tbl ftbl_esc_clk_src[] = {
 792         F(19200000, P_XO, 1, 0, 0),
 793         { }
 794 };
 795
 796 static struct clk_rcg2 esc0_clk_src = {
 797         .cmd_rcgr = 0x2160,
 798         .hid_width = 5,
 799         .parent_map = mmss_xo_dsibyte_map,
 800         .freq_tbl = ftbl_esc_clk_src,
 801         .clkr.hw.init = &(struct clk_init_data){
 802                 .name = "esc0_clk_src",
 803                 .parent_data = mmss_xo_dsibyte,
 804                 .num_parents = 4,
 805                 .ops = &clk_rcg2_ops,
 806         },
 807 };
 808
 809 static struct clk_rcg2 esc1_clk_src = {
 810         .cmd_rcgr = 0x2180,
 811         .hid_width = 5,
 812         .parent_map = mmss_xo_dsibyte_map,
 813         .freq_tbl = ftbl_esc_clk_src,
 814         .clkr.hw.init = &(struct clk_init_data){
 815                 .name = "esc1_clk_src",
 816                 .parent_data = mmss_xo_dsibyte,
 817                 .num_parents = 4,
 818                 .ops = &clk_rcg2_ops,
 819         },
 820 };
 821
 822 static const struct freq_tbl ftbl_extpclk_clk_src[] = {
 823         { .src = P_HDMIPLL },
 824         { }
 825 };
 826
 827 static struct clk_rcg2 extpclk_clk_src = {
 828         .cmd_rcgr = 0x2060,
 829         .hid_width = 5,
 830         .parent_map = mmss_xo_hdmi_map,
 831         .freq_tbl = ftbl_extpclk_clk_src,
 832         .clkr.hw.init = &(struct clk_init_data){
 833                 .name = "extpclk_clk_src",
 834                 .parent_data = mmss_xo_hdmi,
 835                 .num_parents = 3,
 836                 .ops = &clk_byte_ops,
 837                 .flags = CLK_SET_RATE_PARENT,
 838         },
 839 };
 840
 841 static const struct freq_tbl ftbl_fd_core_clk_src[] = {
 842         F(100000000, P_GPLL0, 6, 0, 0),
 843         F(200000000, P_GPLL0, 3, 0, 0),
 844         F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
 845         F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
 846         F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
 847         { }
 848 };
 849
 850 static struct clk_rcg2 fd_core_clk_src = {
 851         .cmd_rcgr = 0x3b00,
 852         .hid_width = 5,
 853         .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
 854         .freq_tbl = ftbl_fd_core_clk_src,
 855         .clkr.hw.init = &(struct clk_init_data){
 856                 .name = "fd_core_clk_src",
 857                 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
 858                 .num_parents = 8,
 859                 .ops = &clk_rcg2_ops,
 860         },
 861 };
 862
 863 static const struct freq_tbl ftbl_hdmi_clk_src[] = {
 864         F(19200000, P_XO, 1, 0, 0),
 865         { }
 866 };
 867
 868 static struct clk_rcg2 hdmi_clk_src = {
 869         .cmd_rcgr = 0x2100,
 870         .hid_width = 5,
 871         .parent_map = mmss_xo_gpll0_gpll0_div_map,
 872         .freq_tbl = ftbl_hdmi_clk_src,
 873         .clkr.hw.init = &(struct clk_init_data){
 874                 .name = "hdmi_clk_src",
 875                 .parent_data = mmss_xo_gpll0_gpll0_div,
 876                 .num_parents = 4,
 877                 .ops = &clk_rcg2_ops,
 878         },
 879 };
 880
 881 static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
 882         F(75000000, P_GPLL0, 8, 0, 0),
 883         F(150000000, P_GPLL0, 4, 0, 0),
 884         F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
 885         F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
 886         { }
 887 };
 888
 889 static struct clk_rcg2 jpeg0_clk_src = {
 890         .cmd_rcgr = 0x3500,
 891         .hid_width = 5,
 892         .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
 893         .freq_tbl = ftbl_jpeg0_clk_src,
 894         .clkr.hw.init = &(struct clk_init_data){
 895                 .name = "jpeg0_clk_src",
 896                 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
 897                 .num_parents = 8,
 898                 .ops = &clk_rcg2_ops,
 899         },
 900 };
 901
 902 static const struct freq_tbl ftbl_maxi_clk_src[] = {
 903         F(19200000, P_XO, 1, 0, 0),
 904         F(75000000, P_GPLL0_DIV, 4, 0, 0),
 905         F(171428571, P_GPLL0, 3.5, 0, 0),
 906         F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
 907         F(406000000, P_MMPLL1_OUT_EVEN, 2, 0, 0),
 908         { }
 909 };
 910
 911 static struct clk_rcg2 maxi_clk_src = {
 912         .cmd_rcgr = 0xf020,
 913         .hid_width = 5,
 914         .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
 915         .freq_tbl = ftbl_maxi_clk_src,
 916         .clkr.hw.init = &(struct clk_init_data){
 917                 .name = "maxi_clk_src",
 918                 .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
 919                 .num_parents = 6,
 920                 .ops = &clk_rcg2_ops,
 921         },
 922 };
 923
 924 static const struct freq_tbl ftbl_mclk_clk_src[] = {
 925         F(4800000, P_XO, 4, 0, 0),
 926         F(6000000, P_GPLL0_DIV, 10, 1, 5),
 927         F(8000000, P_GPLL0_DIV, 1, 2, 75),
 928         F(9600000, P_XO, 2, 0, 0),
 929         F(16666667, P_GPLL0_DIV, 2, 1, 9),
 930         F(19200000, P_XO, 1, 0, 0),
 931         F(24000000, P_GPLL0_DIV, 1, 2, 25),
 932         F(33333333, P_GPLL0_DIV, 1, 2, 9),
 933         F(48000000, P_GPLL0, 1, 2, 25),
 934         F(66666667, P_GPLL0, 1, 2, 9),
 935         { }
 936 };
 937
 938 static struct clk_rcg2 mclk0_clk_src = {
 939         .cmd_rcgr = 0x3360,
 940         .hid_width = 5,
 941         .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
 942         .freq_tbl = ftbl_mclk_clk_src,
 943         .clkr.hw.init = &(struct clk_init_data){
 944                 .name = "mclk0_clk_src",
 945                 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
 946                 .num_parents = 7,
 947                 .ops = &clk_rcg2_ops,
 948         },
 949 };
 950
 951 static struct clk_rcg2 mclk1_clk_src = {
 952         .cmd_rcgr = 0x3390,
 953         .hid_width = 5,
 954         .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
 955         .freq_tbl = ftbl_mclk_clk_src,
 956         .clkr.hw.init = &(struct clk_init_data){
 957                 .name = "mclk1_clk_src",
 958                 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
 959                 .num_parents = 7,
 960                 .ops = &clk_rcg2_ops,
 961         },
 962 };
 963
 964 static struct clk_rcg2 mclk2_clk_src = {
 965         .cmd_rcgr = 0x33c0,
 966         .hid_width = 5,
 967         .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
 968         .freq_tbl = ftbl_mclk_clk_src,
 969         .clkr.hw.init = &(struct clk_init_data){
 970                 .name = "mclk2_clk_src",
 971                 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
 972                 .num_parents = 7,
 973                 .ops = &clk_rcg2_ops,
 974         },
 975 };
 976
 977 static struct clk_rcg2 mclk3_clk_src = {
 978         .cmd_rcgr = 0x33f0,
 979         .hid_width = 5,
 980         .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
 981         .freq_tbl = ftbl_mclk_clk_src,
 982         .clkr.hw.init = &(struct clk_init_data){
 983                 .name = "mclk3_clk_src",
 984                 .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
 985                 .num_parents = 7,
 986                 .ops = &clk_rcg2_ops,
 987         },
 988 };
 989
 990 static const struct freq_tbl ftbl_mdp_clk_src[] = {
 991         F(85714286, P_GPLL0, 7, 0, 0),
 992         F(100000000, P_GPLL0, 6, 0, 0),
 993         F(150000000, P_GPLL0, 4, 0, 0),
 994         F(171428571, P_GPLL0, 3.5, 0, 0),
 995         F(200000000, P_GPLL0, 3, 0, 0),
 996         F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
 997         F(300000000, P_GPLL0, 2, 0, 0),
 998         F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
 999         F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
1000         { }
1001 };
1002
1003 static struct clk_rcg2 mdp_clk_src = {
1004         .cmd_rcgr = 0x2040,
1005         .hid_width = 5,
1006         .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
1007         .freq_tbl = ftbl_mdp_clk_src,
1008         .clkr.hw.init = &(struct clk_init_data){
1009                 .name = "mdp_clk_src",
1010                 .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
1011                 .num_parents = 6,
1012                 .ops = &clk_rcg2_ops,
1013         },
1014 };
1015
1016 static const struct freq_tbl ftbl_vsync_clk_src[] = {
1017         F(19200000, P_XO, 1, 0, 0),
1018         { }
1019 };
1020
1021 static struct clk_rcg2 vsync_clk_src = {
1022         .cmd_rcgr = 0x2080,
1023         .hid_width = 5,
1024         .parent_map = mmss_xo_gpll0_gpll0_div_map,
1025         .freq_tbl = ftbl_vsync_clk_src,
1026         .clkr.hw.init = &(struct clk_init_data){
1027                 .name = "vsync_clk_src",
1028                 .parent_data = mmss_xo_gpll0_gpll0_div,
1029                 .num_parents = 4,
1030                 .ops = &clk_rcg2_ops,
1031         },
1032 };
1033
1034 static const struct freq_tbl ftbl_ahb_clk_src[] = {
1035         F(19200000, P_XO, 1, 0, 0),
1036         F(40000000, P_GPLL0, 15, 0, 0),
1037         F(80800000, P_MMPLL0_OUT_EVEN, 10, 0, 0),
1038         { }
1039 };
1040
1041 static struct clk_rcg2 ahb_clk_src = {
1042         .cmd_rcgr = 0x5000,
1043         .hid_width = 5,
1044         .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
1045         .freq_tbl = ftbl_ahb_clk_src,
1046         .clkr.hw.init = &(struct clk_init_data){
1047                 .name = "ahb_clk_src",
1048                 .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
1049                 .num_parents = 5,
1050                 .ops = &clk_rcg2_ops,
1051         },
1052 };
1053
1054 static const struct freq_tbl ftbl_axi_clk_src[] = {
1055         F(75000000, P_GPLL0, 8, 0, 0),
1056         F(171428571, P_GPLL0, 3.5, 0, 0),
1057         F(240000000, P_GPLL0, 2.5, 0, 0),
1058         F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
1059         F(406000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1060         { }
1061 };
1062
1063 /* RO to linux */
1064 static struct clk_rcg2 axi_clk_src = {
1065         .cmd_rcgr = 0xd000,
1066         .hid_width = 5,
1067         .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
1068         .freq_tbl = ftbl_axi_clk_src,
1069         .clkr.hw.init = &(struct clk_init_data){
1070                 .name = "axi_clk_src",
1071                 .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
1072                 .num_parents = 6,
1073                 .ops = &clk_rcg2_ops,
1074         },
1075 };
1076
1077 static struct clk_rcg2 pclk0_clk_src = {
1078         .cmd_rcgr = 0x2000,
1079         .mnd_width = 8,
1080         .hid_width = 5,
1081         .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
1082         .clkr.hw.init = &(struct clk_init_data){
1083                 .name = "pclk0_clk_src",
1084                 .parent_data = mmss_xo_dsi0pll_dsi1pll,
1085                 .num_parents = 4,
1086                 .ops = &clk_pixel_ops,
1087                 .flags = CLK_SET_RATE_PARENT,
1088         },
1089 };
1090
1091 static struct clk_rcg2 pclk1_clk_src = {
1092         .cmd_rcgr = 0x2020,
1093         .mnd_width = 8,
1094         .hid_width = 5,
1095         .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
1096         .clkr.hw.init = &(struct clk_init_data){
1097                 .name = "pclk1_clk_src",
1098                 .parent_data = mmss_xo_dsi0pll_dsi1pll,
1099                 .num_parents = 4,
1100                 .ops = &clk_pixel_ops,
1101                 .flags = CLK_SET_RATE_PARENT,
1102         },
1103 };
1104
1105 static const struct freq_tbl ftbl_rot_clk_src[] = {
1106         F(171428571, P_GPLL0, 3.5, 0, 0),
1107         F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
1108         F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
1109         F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
1110         { }
1111 };
1112
1113 static struct clk_rcg2 rot_clk_src = {
1114         .cmd_rcgr = 0x21a0,
1115         .hid_width = 5,
1116         .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
1117         .freq_tbl = ftbl_rot_clk_src,
1118         .clkr.hw.init = &(struct clk_init_data){
1119                 .name = "rot_clk_src",
1120                 .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
1121                 .num_parents = 6,
1122                 .ops = &clk_rcg2_ops,
1123         },
1124 };
1125
1126 static const struct freq_tbl ftbl_video_core_clk_src[] = {
1127         F(200000000, P_GPLL0, 3, 0, 0),
1128         F(269330000, P_MMPLL0_OUT_EVEN, 3, 0, 0),
1129         F(355200000, P_MMPLL6_OUT_EVEN, 2.5, 0, 0),
1130         F(444000000, P_MMPLL6_OUT_EVEN, 2, 0, 0),
1131         F(533000000, P_MMPLL3_OUT_EVEN, 2, 0, 0),
1132         { }
1133 };
1134
1135 static struct clk_rcg2 video_core_clk_src = {
1136         .cmd_rcgr = 0x1000,
1137         .hid_width = 5,
1138         .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1139         .freq_tbl = ftbl_video_core_clk_src,
1140         .clkr.hw.init = &(struct clk_init_data){
1141                 .name = "video_core_clk_src",
1142                 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1143                 .num_parents = 7,
1144                 .ops = &clk_rcg2_ops,
1145         },
1146 };
1147
1148 static struct clk_rcg2 video_subcore0_clk_src = {
1149         .cmd_rcgr = 0x1060,
1150         .hid_width = 5,
1151         .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1152         .freq_tbl = ftbl_video_core_clk_src,
1153         .clkr.hw.init = &(struct clk_init_data){
1154                 .name = "video_subcore0_clk_src",
1155                 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1156                 .num_parents = 7,
1157                 .ops = &clk_rcg2_ops,
1158         },
1159 };
1160
1161 static struct clk_rcg2 video_subcore1_clk_src = {
1162         .cmd_rcgr = 0x1080,
1163         .hid_width = 5,
1164         .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1165         .freq_tbl = ftbl_video_core_clk_src,
1166         .clkr.hw.init = &(struct clk_init_data){
1167                 .name = "video_subcore1_clk_src",
1168                 .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1169                 .num_parents = 7,
1170                 .ops = &clk_rcg2_ops,
1171         },
1172 };
1173
1174 static const struct freq_tbl ftbl_vfe_clk_src[] = {
1175         F(200000000, P_GPLL0, 3, 0, 0),
1176         F(300000000, P_GPLL0, 2, 0, 0),
1177         F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
1178         F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
1179         F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1180         F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
1181         F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
1182         F(600000000, P_GPLL0, 1, 0, 0),
1183         { }
1184 };
1185
1186 static struct clk_rcg2 vfe0_clk_src = {
1187         .cmd_rcgr = 0x3600,
1188         .hid_width = 5,
1189         .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
1190         .freq_tbl = ftbl_vfe_clk_src,
1191         .clkr.hw.init = &(struct clk_init_data){
1192                 .name = "vfe0_clk_src",
1193                 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
1194                 .num_parents = 8,
1195                 .ops = &clk_rcg2_ops,
1196         },
1197 };
1198
1199 static struct clk_rcg2 vfe1_clk_src = {
1200         .cmd_rcgr = 0x3620,
1201         .hid_width = 5,
1202         .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
1203         .freq_tbl = ftbl_vfe_clk_src,
1204         .clkr.hw.init = &(struct clk_init_data){
1205                 .name = "vfe1_clk_src",
1206                 .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
1207                 .num_parents = 8,
1208                 .ops = &clk_rcg2_ops,
1209         },
1210 };
1211
1212 static struct clk_branch misc_ahb_clk = {
1213         .halt_reg = 0x328,
1214         .hwcg_reg = 0x328,
1215         .hwcg_bit = 1,
1216         .clkr = {
1217                 .enable_reg = 0x328,
1218                 .enable_mask = BIT(0),
1219                 .hw.init = &(struct clk_init_data){
1220                         .name = "misc_ahb_clk",
1221                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1222                         .num_parents = 1,
1223                         .ops = &clk_branch2_ops,
1224                         .flags = CLK_SET_RATE_PARENT,
1225                 },
1226         },
1227 };
1228
1229 static struct clk_branch video_core_clk = {
1230         .halt_reg = 0x1028,
1231         .clkr = {
1232                 .enable_reg = 0x1028,
1233                 .enable_mask = BIT(0),
1234                 .hw.init = &(struct clk_init_data){
1235                         .name = "video_core_clk",
1236                         .parent_hws = (const struct clk_hw *[]){ &video_core_clk_src.clkr.hw },
1237                         .num_parents = 1,
1238                         .ops = &clk_branch2_ops,
1239                         .flags = CLK_SET_RATE_PARENT,
1240                 },
1241         },
1242 };
1243
1244 static struct clk_branch video_ahb_clk = {
1245         .halt_reg = 0x1030,
1246         .hwcg_reg = 0x1030,
1247         .hwcg_bit = 1,
1248         .clkr = {
1249                 .enable_reg = 0x1030,
1250                 .enable_mask = BIT(0),
1251                 .hw.init = &(struct clk_init_data){
1252                         .name = "video_ahb_clk",
1253                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1254                         .num_parents = 1,
1255                         .ops = &clk_branch2_ops,
1256                         .flags = CLK_SET_RATE_PARENT,
1257                 },
1258         },
1259 };
1260
1261 static struct clk_branch video_axi_clk = {
1262         .halt_reg = 0x1034,
1263         .clkr = {
1264                 .enable_reg = 0x1034,
1265                 .enable_mask = BIT(0),
1266                 .hw.init = &(struct clk_init_data){
1267                         .name = "video_axi_clk",
1268                         .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1269                         .num_parents = 1,
1270                         .ops = &clk_branch2_ops,
1271                 },
1272         },
1273 };
1274
1275 static struct clk_branch video_maxi_clk = {
1276         .halt_reg = 0x1038,
1277         .clkr = {
1278                 .enable_reg = 0x1038,
1279                 .enable_mask = BIT(0),
1280                 .hw.init = &(struct clk_init_data){
1281                         .name = "video_maxi_clk",
1282                         .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
1283                         .num_parents = 1,
1284                         .ops = &clk_branch2_ops,
1285                         .flags = CLK_SET_RATE_PARENT,
1286                 },
1287         },
1288 };
1289
1290 static struct clk_branch video_subcore0_clk = {
1291         .halt_reg = 0x1048,
1292         .clkr = {
1293                 .enable_reg = 0x1048,
1294                 .enable_mask = BIT(0),
1295                 .hw.init = &(struct clk_init_data){
1296                         .name = "video_subcore0_clk",
1297                         .parent_hws = (const struct clk_hw *[]){ &video_subcore0_clk_src.clkr.hw },
1298                         .num_parents = 1,
1299                         .ops = &clk_branch2_ops,
1300                         .flags = CLK_SET_RATE_PARENT,
1301                 },
1302         },
1303 };
1304
1305 static struct clk_branch video_subcore1_clk = {
1306         .halt_reg = 0x104c,
1307         .clkr = {
1308                 .enable_reg = 0x104c,
1309                 .enable_mask = BIT(0),
1310                 .hw.init = &(struct clk_init_data){
1311                         .name = "video_subcore1_clk",
1312                         .parent_hws = (const struct clk_hw *[]){ &video_subcore1_clk_src.clkr.hw },
1313                         .num_parents = 1,
1314                         .ops = &clk_branch2_ops,
1315                         .flags = CLK_SET_RATE_PARENT,
1316                 },
1317         },
1318 };
1319
1320 static struct clk_branch mdss_ahb_clk = {
1321         .halt_reg = 0x2308,
1322         .hwcg_reg = 0x2308,
1323         .hwcg_bit = 1,
1324         .clkr = {
1325                 .enable_reg = 0x2308,
1326                 .enable_mask = BIT(0),
1327                 .hw.init = &(struct clk_init_data){
1328                         .name = "mdss_ahb_clk",
1329                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1330                         .num_parents = 1,
1331                         .ops = &clk_branch2_ops,
1332                         .flags = CLK_SET_RATE_PARENT,
1333                 },
1334         },
1335 };
1336
1337 static struct clk_branch mdss_hdmi_dp_ahb_clk = {
1338         .halt_reg = 0x230c,
1339         .clkr = {
1340                 .enable_reg = 0x230c,
1341                 .enable_mask = BIT(0),
1342                 .hw.init = &(struct clk_init_data){
1343                         .name = "mdss_hdmi_dp_ahb_clk",
1344                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1345                         .num_parents = 1,
1346                         .ops = &clk_branch2_ops,
1347                         .flags = CLK_SET_RATE_PARENT,
1348                 },
1349         },
1350 };
1351
1352 static struct clk_branch mdss_axi_clk = {
1353         .halt_reg = 0x2310,
1354         .clkr = {
1355                 .enable_reg = 0x2310,
1356                 .enable_mask = BIT(0),
1357                 .hw.init = &(struct clk_init_data){
1358                         .name = "mdss_axi_clk",
1359                         .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1360                         .num_parents = 1,
1361                         .ops = &clk_branch2_ops,
1362                 },
1363         },
1364 };
1365
1366 static struct clk_branch mdss_pclk0_clk = {
1367         .halt_reg = 0x2314,
1368         .clkr = {
1369                 .enable_reg = 0x2314,
1370                 .enable_mask = BIT(0),
1371                 .hw.init = &(struct clk_init_data){
1372                         .name = "mdss_pclk0_clk",
1373                         .parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw },
1374                         .num_parents = 1,
1375                         .ops = &clk_branch2_ops,
1376                         .flags = CLK_SET_RATE_PARENT,
1377                 },
1378         },
1379 };
1380
1381 static struct clk_branch mdss_pclk1_clk = {
1382         .halt_reg = 0x2318,
1383         .clkr = {
1384                 .enable_reg = 0x2318,
1385                 .enable_mask = BIT(0),
1386                 .hw.init = &(struct clk_init_data){
1387                         .name = "mdss_pclk1_clk",
1388                         .parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw },
1389                         .num_parents = 1,
1390                         .ops = &clk_branch2_ops,
1391                         .flags = CLK_SET_RATE_PARENT,
1392                 },
1393         },
1394 };
1395
1396 static struct clk_branch mdss_mdp_clk = {
1397         .halt_reg = 0x231c,
1398         .clkr = {
1399                 .enable_reg = 0x231c,
1400                 .enable_mask = BIT(0),
1401                 .hw.init = &(struct clk_init_data){
1402                         .name = "mdss_mdp_clk",
1403                         .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
1404                         .num_parents = 1,
1405                         .ops = &clk_branch2_ops,
1406                         .flags = CLK_SET_RATE_PARENT,
1407                 },
1408         },
1409 };
1410
1411 static struct clk_branch mdss_mdp_lut_clk = {
1412         .halt_reg = 0x2320,
1413         .clkr = {
1414                 .enable_reg = 0x2320,
1415                 .enable_mask = BIT(0),
1416                 .hw.init = &(struct clk_init_data){
1417                         .name = "mdss_mdp_lut_clk",
1418                         .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
1419                         .num_parents = 1,
1420                         .ops = &clk_branch2_ops,
1421                         .flags = CLK_SET_RATE_PARENT,
1422                 },
1423         },
1424 };
1425
1426 static struct clk_branch mdss_extpclk_clk = {
1427         .halt_reg = 0x2324,
1428         .clkr = {
1429                 .enable_reg = 0x2324,
1430                 .enable_mask = BIT(0),
1431                 .hw.init = &(struct clk_init_data){
1432                         .name = "mdss_extpclk_clk",
1433                         .parent_hws = (const struct clk_hw *[]){ &extpclk_clk_src.clkr.hw },
1434                         .num_parents = 1,
1435                         .ops = &clk_branch2_ops,
1436                         .flags = CLK_SET_RATE_PARENT,
1437                 },
1438         },
1439 };
1440
1441 static struct clk_branch mdss_vsync_clk = {
1442         .halt_reg = 0x2328,
1443         .clkr = {
1444                 .enable_reg = 0x2328,
1445                 .enable_mask = BIT(0),
1446                 .hw.init = &(struct clk_init_data){
1447                         .name = "mdss_vsync_clk",
1448                         .parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw },
1449                         .num_parents = 1,
1450                         .ops = &clk_branch2_ops,
1451                         .flags = CLK_SET_RATE_PARENT,
1452                 },
1453         },
1454 };
1455
1456 static struct clk_branch mdss_hdmi_clk = {
1457         .halt_reg = 0x2338,
1458         .clkr = {
1459                 .enable_reg = 0x2338,
1460                 .enable_mask = BIT(0),
1461                 .hw.init = &(struct clk_init_data){
1462                         .name = "mdss_hdmi_clk",
1463                         .parent_hws = (const struct clk_hw *[]){ &hdmi_clk_src.clkr.hw },
1464                         .num_parents = 1,
1465                         .ops = &clk_branch2_ops,
1466                         .flags = CLK_SET_RATE_PARENT,
1467                 },
1468         },
1469 };
1470
1471 static struct clk_branch mdss_byte0_clk = {
1472         .halt_reg = 0x233c,
1473         .clkr = {
1474                 .enable_reg = 0x233c,
1475                 .enable_mask = BIT(0),
1476                 .hw.init = &(struct clk_init_data){
1477                         .name = "mdss_byte0_clk",
1478                         .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
1479                         .num_parents = 1,
1480                         .ops = &clk_branch2_ops,
1481                         .flags = CLK_SET_RATE_PARENT,
1482                 },
1483         },
1484 };
1485
1486 static struct clk_branch mdss_byte1_clk = {
1487         .halt_reg = 0x2340,
1488         .clkr = {
1489                 .enable_reg = 0x2340,
1490                 .enable_mask = BIT(0),
1491                 .hw.init = &(struct clk_init_data){
1492                         .name = "mdss_byte1_clk",
1493                         .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
1494                         .num_parents = 1,
1495                         .ops = &clk_branch2_ops,
1496                         .flags = CLK_SET_RATE_PARENT,
1497                 },
1498         },
1499 };
1500
1501 static struct clk_branch mdss_esc0_clk = {
1502         .halt_reg = 0x2344,
1503         .clkr = {
1504                 .enable_reg = 0x2344,
1505                 .enable_mask = BIT(0),
1506                 .hw.init = &(struct clk_init_data){
1507                         .name = "mdss_esc0_clk",
1508                         .parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw },
1509                         .num_parents = 1,
1510                         .ops = &clk_branch2_ops,
1511                         .flags = CLK_SET_RATE_PARENT,
1512                 },
1513         },
1514 };
1515
1516 static struct clk_branch mdss_esc1_clk = {
1517         .halt_reg = 0x2348,
1518         .clkr = {
1519                 .enable_reg = 0x2348,
1520                 .enable_mask = BIT(0),
1521                 .hw.init = &(struct clk_init_data){
1522                         .name = "mdss_esc1_clk",
1523                         .parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw },
1524                         .num_parents = 1,
1525                         .ops = &clk_branch2_ops,
1526                         .flags = CLK_SET_RATE_PARENT,
1527                 },
1528         },
1529 };
1530
1531 static struct clk_branch mdss_rot_clk = {
1532         .halt_reg = 0x2350,
1533         .clkr = {
1534                 .enable_reg = 0x2350,
1535                 .enable_mask = BIT(0),
1536                 .hw.init = &(struct clk_init_data){
1537                         .name = "mdss_rot_clk",
1538                         .parent_hws = (const struct clk_hw *[]){ &rot_clk_src.clkr.hw },
1539                         .num_parents = 1,
1540                         .ops = &clk_branch2_ops,
1541                         .flags = CLK_SET_RATE_PARENT,
1542                 },
1543         },
1544 };
1545
1546 static struct clk_branch mdss_dp_link_clk = {
1547         .halt_reg = 0x2354,
1548         .clkr = {
1549                 .enable_reg = 0x2354,
1550                 .enable_mask = BIT(0),
1551                 .hw.init = &(struct clk_init_data){
1552                         .name = "mdss_dp_link_clk",
1553                         .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
1554                         .num_parents = 1,
1555                         .ops = &clk_branch2_ops,
1556                         .flags = CLK_SET_RATE_PARENT,
1557                 },
1558         },
1559 };
1560
1561 static struct clk_branch mdss_dp_link_intf_clk = {
1562         .halt_reg = 0x2358,
1563         .clkr = {
1564                 .enable_reg = 0x2358,
1565                 .enable_mask = BIT(0),
1566                 .hw.init = &(struct clk_init_data){
1567                         .name = "mdss_dp_link_intf_clk",
1568                         .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
1569                         .num_parents = 1,
1570                         .ops = &clk_branch2_ops,
1571                         .flags = CLK_SET_RATE_PARENT,
1572                 },
1573         },
1574 };
1575
1576 static struct clk_branch mdss_dp_crypto_clk = {
1577         .halt_reg = 0x235c,
1578         .clkr = {
1579                 .enable_reg = 0x235c,
1580                 .enable_mask = BIT(0),
1581                 .hw.init = &(struct clk_init_data){
1582                         .name = "mdss_dp_crypto_clk",
1583                         .parent_hws = (const struct clk_hw *[]){ &dp_crypto_clk_src.clkr.hw },
1584                         .num_parents = 1,
1585                         .ops = &clk_branch2_ops,
1586                         .flags = CLK_SET_RATE_PARENT,
1587                 },
1588         },
1589 };
1590
1591 static struct clk_branch mdss_dp_pixel_clk = {
1592         .halt_reg = 0x2360,
1593         .clkr = {
1594                 .enable_reg = 0x2360,
1595                 .enable_mask = BIT(0),
1596                 .hw.init = &(struct clk_init_data){
1597                         .name = "mdss_dp_pixel_clk",
1598                         .parent_hws = (const struct clk_hw *[]){ &dp_pixel_clk_src.clkr.hw },
1599                         .num_parents = 1,
1600                         .ops = &clk_branch2_ops,
1601                         .flags = CLK_SET_RATE_PARENT,
1602                 },
1603         },
1604 };
1605
1606 static struct clk_branch mdss_dp_aux_clk = {
1607         .halt_reg = 0x2364,
1608         .clkr = {
1609                 .enable_reg = 0x2364,
1610                 .enable_mask = BIT(0),
1611                 .hw.init = &(struct clk_init_data){
1612                         .name = "mdss_dp_aux_clk",
1613                         .parent_hws = (const struct clk_hw *[]){ &dp_aux_clk_src.clkr.hw },
1614                         .num_parents = 1,
1615                         .ops = &clk_branch2_ops,
1616                         .flags = CLK_SET_RATE_PARENT,
1617                 },
1618         },
1619 };
1620
1621 static struct clk_branch mdss_byte0_intf_clk = {
1622         .halt_reg = 0x2374,
1623         .clkr = {
1624                 .enable_reg = 0x2374,
1625                 .enable_mask = BIT(0),
1626                 .hw.init = &(struct clk_init_data){
1627                         .name = "mdss_byte0_intf_clk",
1628                         .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
1629                         .num_parents = 1,
1630                         .ops = &clk_branch2_ops,
1631                         .flags = CLK_SET_RATE_PARENT,
1632                 },
1633         },
1634 };
1635
1636 static struct clk_branch mdss_byte1_intf_clk = {
1637         .halt_reg = 0x2378,
1638         .clkr = {
1639                 .enable_reg = 0x2378,
1640                 .enable_mask = BIT(0),
1641                 .hw.init = &(struct clk_init_data){
1642                         .name = "mdss_byte1_intf_clk",
1643                         .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
1644                         .num_parents = 1,
1645                         .ops = &clk_branch2_ops,
1646                         .flags = CLK_SET_RATE_PARENT,
1647                 },
1648         },
1649 };
1650
1651 static struct clk_branch camss_csi0phytimer_clk = {
1652         .halt_reg = 0x3024,
1653         .clkr = {
1654                 .enable_reg = 0x3024,
1655                 .enable_mask = BIT(0),
1656                 .hw.init = &(struct clk_init_data){
1657                         .name = "camss_csi0phytimer_clk",
1658                         .parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw },
1659                         .num_parents = 1,
1660                         .ops = &clk_branch2_ops,
1661                         .flags = CLK_SET_RATE_PARENT,
1662                 },
1663         },
1664 };
1665
1666 static struct clk_branch camss_csi1phytimer_clk = {
1667         .halt_reg = 0x3054,
1668         .clkr = {
1669                 .enable_reg = 0x3054,
1670                 .enable_mask = BIT(0),
1671                 .hw.init = &(struct clk_init_data){
1672                         .name = "camss_csi1phytimer_clk",
1673                         .parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw },
1674                         .num_parents = 1,
1675                         .ops = &clk_branch2_ops,
1676                         .flags = CLK_SET_RATE_PARENT,
1677                 },
1678         },
1679 };
1680
1681 static struct clk_branch camss_csi2phytimer_clk = {
1682         .halt_reg = 0x3084,
1683         .clkr = {
1684                 .enable_reg = 0x3084,
1685                 .enable_mask = BIT(0),
1686                 .hw.init = &(struct clk_init_data){
1687                         .name = "camss_csi2phytimer_clk",
1688                         .parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw },
1689                         .num_parents = 1,
1690                         .ops = &clk_branch2_ops,
1691                         .flags = CLK_SET_RATE_PARENT,
1692                 },
1693         },
1694 };
1695
1696 static struct clk_branch camss_csi0_clk = {
1697         .halt_reg = 0x30b4,
1698         .clkr = {
1699                 .enable_reg = 0x30b4,
1700                 .enable_mask = BIT(0),
1701                 .hw.init = &(struct clk_init_data){
1702                         .name = "camss_csi0_clk",
1703                         .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1704                         .num_parents = 1,
1705                         .ops = &clk_branch2_ops,
1706                         .flags = CLK_SET_RATE_PARENT,
1707                 },
1708         },
1709 };
1710
1711 static struct clk_branch camss_csi0_ahb_clk = {
1712         .halt_reg = 0x30bc,
1713         .clkr = {
1714                 .enable_reg = 0x30bc,
1715                 .enable_mask = BIT(0),
1716                 .hw.init = &(struct clk_init_data){
1717                         .name = "camss_csi0_ahb_clk",
1718                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1719                         .num_parents = 1,
1720                         .ops = &clk_branch2_ops,
1721                         .flags = CLK_SET_RATE_PARENT,
1722                 },
1723         },
1724 };
1725
1726 static struct clk_branch camss_csi0rdi_clk = {
1727         .halt_reg = 0x30d4,
1728         .clkr = {
1729                 .enable_reg = 0x30d4,
1730                 .enable_mask = BIT(0),
1731                 .hw.init = &(struct clk_init_data){
1732                         .name = "camss_csi0rdi_clk",
1733                         .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1734                         .num_parents = 1,
1735                         .ops = &clk_branch2_ops,
1736                         .flags = CLK_SET_RATE_PARENT,
1737                 },
1738         },
1739 };
1740
1741 static struct clk_branch camss_csi0pix_clk = {
1742         .halt_reg = 0x30e4,
1743         .clkr = {
1744                 .enable_reg = 0x30e4,
1745                 .enable_mask = BIT(0),
1746                 .hw.init = &(struct clk_init_data){
1747                         .name = "camss_csi0pix_clk",
1748                         .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1749                         .num_parents = 1,
1750                         .ops = &clk_branch2_ops,
1751                         .flags = CLK_SET_RATE_PARENT,
1752                 },
1753         },
1754 };
1755
1756 static struct clk_branch camss_csi1_clk = {
1757         .halt_reg = 0x3124,
1758         .clkr = {
1759                 .enable_reg = 0x3124,
1760                 .enable_mask = BIT(0),
1761                 .hw.init = &(struct clk_init_data){
1762                         .name = "camss_csi1_clk",
1763                         .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1764                         .num_parents = 1,
1765                         .ops = &clk_branch2_ops,
1766                         .flags = CLK_SET_RATE_PARENT,
1767                 },
1768         },
1769 };
1770
1771 static struct clk_branch camss_csi1_ahb_clk = {
1772         .halt_reg = 0x3128,
1773         .clkr = {
1774                 .enable_reg = 0x3128,
1775                 .enable_mask = BIT(0),
1776                 .hw.init = &(struct clk_init_data){
1777                         .name = "camss_csi1_ahb_clk",
1778                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1779                         .num_parents = 1,
1780                         .ops = &clk_branch2_ops,
1781                         .flags = CLK_SET_RATE_PARENT,
1782                 },
1783         },
1784 };
1785
1786 static struct clk_branch camss_csi1rdi_clk = {
1787         .halt_reg = 0x3144,
1788         .clkr = {
1789                 .enable_reg = 0x3144,
1790                 .enable_mask = BIT(0),
1791                 .hw.init = &(struct clk_init_data){
1792                         .name = "camss_csi1rdi_clk",
1793                         .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1794                         .num_parents = 1,
1795                         .ops = &clk_branch2_ops,
1796                         .flags = CLK_SET_RATE_PARENT,
1797                 },
1798         },
1799 };
1800
1801 static struct clk_branch camss_csi1pix_clk = {
1802         .halt_reg = 0x3154,
1803         .clkr = {
1804                 .enable_reg = 0x3154,
1805                 .enable_mask = BIT(0),
1806                 .hw.init = &(struct clk_init_data){
1807                         .name = "camss_csi1pix_clk",
1808                         .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1809                         .num_parents = 1,
1810                         .ops = &clk_branch2_ops,
1811                         .flags = CLK_SET_RATE_PARENT,
1812                 },
1813         },
1814 };
1815
1816 static struct clk_branch camss_csi2_clk = {
1817         .halt_reg = 0x3184,
1818         .clkr = {
1819                 .enable_reg = 0x3184,
1820                 .enable_mask = BIT(0),
1821                 .hw.init = &(struct clk_init_data){
1822                         .name = "camss_csi2_clk",
1823                         .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1824                         .num_parents = 1,
1825                         .ops = &clk_branch2_ops,
1826                         .flags = CLK_SET_RATE_PARENT,
1827                 },
1828         },
1829 };
1830
1831 static struct clk_branch camss_csi2_ahb_clk = {
1832         .halt_reg = 0x3188,
1833         .clkr = {
1834                 .enable_reg = 0x3188,
1835                 .enable_mask = BIT(0),
1836                 .hw.init = &(struct clk_init_data){
1837                         .name = "camss_csi2_ahb_clk",
1838                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1839                         .num_parents = 1,
1840                         .ops = &clk_branch2_ops,
1841                         .flags = CLK_SET_RATE_PARENT,
1842                 },
1843         },
1844 };
1845
1846 static struct clk_branch camss_csi2rdi_clk = {
1847         .halt_reg = 0x31a4,
1848         .clkr = {
1849                 .enable_reg = 0x31a4,
1850                 .enable_mask = BIT(0),
1851                 .hw.init = &(struct clk_init_data){
1852                         .name = "camss_csi2rdi_clk",
1853                         .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1854                         .num_parents = 1,
1855                         .ops = &clk_branch2_ops,
1856                         .flags = CLK_SET_RATE_PARENT,
1857                 },
1858         },
1859 };
1860
1861 static struct clk_branch camss_csi2pix_clk = {
1862         .halt_reg = 0x31b4,
1863         .clkr = {
1864                 .enable_reg = 0x31b4,
1865                 .enable_mask = BIT(0),
1866                 .hw.init = &(struct clk_init_data){
1867                         .name = "camss_csi2pix_clk",
1868                         .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1869                         .num_parents = 1,
1870                         .ops = &clk_branch2_ops,
1871                         .flags = CLK_SET_RATE_PARENT,
1872                 },
1873         },
1874 };
1875
1876 static struct clk_branch camss_csi3_clk = {
1877         .halt_reg = 0x31e4,
1878         .clkr = {
1879                 .enable_reg = 0x31e4,
1880                 .enable_mask = BIT(0),
1881                 .hw.init = &(struct clk_init_data){
1882                         .name = "camss_csi3_clk",
1883                         .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1884                         .num_parents = 1,
1885                         .ops = &clk_branch2_ops,
1886                         .flags = CLK_SET_RATE_PARENT,
1887                 },
1888         },
1889 };
1890
1891 static struct clk_branch camss_csi3_ahb_clk = {
1892         .halt_reg = 0x31e8,
1893         .clkr = {
1894                 .enable_reg = 0x31e8,
1895                 .enable_mask = BIT(0),
1896                 .hw.init = &(struct clk_init_data){
1897                         .name = "camss_csi3_ahb_clk",
1898                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1899                         .num_parents = 1,
1900                         .ops = &clk_branch2_ops,
1901                         .flags = CLK_SET_RATE_PARENT,
1902                 },
1903         },
1904 };
1905
1906 static struct clk_branch camss_csi3rdi_clk = {
1907         .halt_reg = 0x3204,
1908         .clkr = {
1909                 .enable_reg = 0x3204,
1910                 .enable_mask = BIT(0),
1911                 .hw.init = &(struct clk_init_data){
1912                         .name = "camss_csi3rdi_clk",
1913                         .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1914                         .num_parents = 1,
1915                         .ops = &clk_branch2_ops,
1916                         .flags = CLK_SET_RATE_PARENT,
1917                 },
1918         },
1919 };
1920
1921 static struct clk_branch camss_csi3pix_clk = {
1922         .halt_reg = 0x3214,
1923         .clkr = {
1924                 .enable_reg = 0x3214,
1925                 .enable_mask = BIT(0),
1926                 .hw.init = &(struct clk_init_data){
1927                         .name = "camss_csi3pix_clk",
1928                         .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1929                         .num_parents = 1,
1930                         .ops = &clk_branch2_ops,
1931                         .flags = CLK_SET_RATE_PARENT,
1932                 },
1933         },
1934 };
1935
1936 static struct clk_branch camss_ispif_ahb_clk = {
1937         .halt_reg = 0x3224,
1938         .clkr = {
1939                 .enable_reg = 0x3224,
1940                 .enable_mask = BIT(0),
1941                 .hw.init = &(struct clk_init_data){
1942                         .name = "camss_ispif_ahb_clk",
1943                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1944                         .num_parents = 1,
1945                         .ops = &clk_branch2_ops,
1946                         .flags = CLK_SET_RATE_PARENT,
1947                 },
1948         },
1949 };
1950
1951 static struct clk_branch camss_cci_clk = {
1952         .halt_reg = 0x3344,
1953         .clkr = {
1954                 .enable_reg = 0x3344,
1955                 .enable_mask = BIT(0),
1956                 .hw.init = &(struct clk_init_data){
1957                         .name = "camss_cci_clk",
1958                         .parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw },
1959                         .num_parents = 1,
1960                         .ops = &clk_branch2_ops,
1961                         .flags = CLK_SET_RATE_PARENT,
1962                 },
1963         },
1964 };
1965
1966 static struct clk_branch camss_cci_ahb_clk = {
1967         .halt_reg = 0x3348,
1968         .clkr = {
1969                 .enable_reg = 0x3348,
1970                 .enable_mask = BIT(0),
1971                 .hw.init = &(struct clk_init_data){
1972                         .name = "camss_cci_ahb_clk",
1973                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1974                         .num_parents = 1,
1975                         .ops = &clk_branch2_ops,
1976                         .flags = CLK_SET_RATE_PARENT,
1977                 },
1978         },
1979 };
1980
1981 static struct clk_branch camss_mclk0_clk = {
1982         .halt_reg = 0x3384,
1983         .clkr = {
1984                 .enable_reg = 0x3384,
1985                 .enable_mask = BIT(0),
1986                 .hw.init = &(struct clk_init_data){
1987                         .name = "camss_mclk0_clk",
1988                         .parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw },
1989                         .num_parents = 1,
1990                         .ops = &clk_branch2_ops,
1991                         .flags = CLK_SET_RATE_PARENT,
1992                 },
1993         },
1994 };
1995
1996 static struct clk_branch camss_mclk1_clk = {
1997         .halt_reg = 0x33b4,
1998         .clkr = {
1999                 .enable_reg = 0x33b4,
2000                 .enable_mask = BIT(0),
2001                 .hw.init = &(struct clk_init_data){
2002                         .name = "camss_mclk1_clk",
2003                         .parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw },
2004                         .num_parents = 1,
2005                         .ops = &clk_branch2_ops,
2006                         .flags = CLK_SET_RATE_PARENT,
2007                 },
2008         },
2009 };
2010
2011 static struct clk_branch camss_mclk2_clk = {
2012         .halt_reg = 0x33e4,
2013         .clkr = {
2014                 .enable_reg = 0x33e4,
2015                 .enable_mask = BIT(0),
2016                 .hw.init = &(struct clk_init_data){
2017                         .name = "camss_mclk2_clk",
2018                         .parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw },
2019                         .num_parents = 1,
2020                         .ops = &clk_branch2_ops,
2021                         .flags = CLK_SET_RATE_PARENT,
2022                 },
2023         },
2024 };
2025
2026 static struct clk_branch camss_mclk3_clk = {
2027         .halt_reg = 0x3414,
2028         .clkr = {
2029                 .enable_reg = 0x3414,
2030                 .enable_mask = BIT(0),
2031                 .hw.init = &(struct clk_init_data){
2032                         .name = "camss_mclk3_clk",
2033                         .parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw },
2034                         .num_parents = 1,
2035                         .ops = &clk_branch2_ops,
2036                         .flags = CLK_SET_RATE_PARENT,
2037                 },
2038         },
2039 };
2040
2041 static struct clk_branch camss_top_ahb_clk = {
2042         .halt_reg = 0x3484,
2043         .clkr = {
2044                 .enable_reg = 0x3484,
2045                 .enable_mask = BIT(0),
2046                 .hw.init = &(struct clk_init_data){
2047                         .name = "camss_top_ahb_clk",
2048                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2049                         .num_parents = 1,
2050                         .ops = &clk_branch2_ops,
2051                         .flags = CLK_SET_RATE_PARENT,
2052                 },
2053         },
2054 };
2055
2056 static struct clk_branch camss_ahb_clk = {
2057         .halt_reg = 0x348c,
2058         .clkr = {
2059                 .enable_reg = 0x348c,
2060                 .enable_mask = BIT(0),
2061                 .hw.init = &(struct clk_init_data){
2062                         .name = "camss_ahb_clk",
2063                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2064                         .num_parents = 1,
2065                         .ops = &clk_branch2_ops,
2066                         .flags = CLK_SET_RATE_PARENT,
2067                 },
2068         },
2069 };
2070
2071 static struct clk_branch camss_micro_ahb_clk = {
2072         .halt_reg = 0x3494,
2073         .clkr = {
2074                 .enable_reg = 0x3494,
2075                 .enable_mask = BIT(0),
2076                 .hw.init = &(struct clk_init_data){
2077                         .name = "camss_micro_ahb_clk",
2078                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2079                         .num_parents = 1,
2080                         .ops = &clk_branch2_ops,
2081                         .flags = CLK_SET_RATE_PARENT,
2082                 },
2083         },
2084 };
2085
2086 static struct clk_branch camss_jpeg0_clk = {
2087         .halt_reg = 0x35a8,
2088         .clkr = {
2089                 .enable_reg = 0x35a8,
2090                 .enable_mask = BIT(0),
2091                 .hw.init = &(struct clk_init_data){
2092                         .name = "camss_jpeg0_clk",
2093                         .parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw },
2094                         .num_parents = 1,
2095                         .ops = &clk_branch2_ops,
2096                         .flags = CLK_SET_RATE_PARENT,
2097                 },
2098         },
2099 };
2100
2101 static struct clk_branch camss_jpeg_ahb_clk = {
2102         .halt_reg = 0x35b4,
2103         .clkr = {
2104                 .enable_reg = 0x35b4,
2105                 .enable_mask = BIT(0),
2106                 .hw.init = &(struct clk_init_data){
2107                         .name = "camss_jpeg_ahb_clk",
2108                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2109                         .num_parents = 1,
2110                         .ops = &clk_branch2_ops,
2111                         .flags = CLK_SET_RATE_PARENT,
2112                 },
2113         },
2114 };
2115
2116 static struct clk_branch camss_jpeg_axi_clk = {
2117         .halt_reg = 0x35b8,
2118         .clkr = {
2119                 .enable_reg = 0x35b8,
2120                 .enable_mask = BIT(0),
2121                 .hw.init = &(struct clk_init_data){
2122                         .name = "camss_jpeg_axi_clk",
2123                         .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2124                         .num_parents = 1,
2125                         .ops = &clk_branch2_ops,
2126                 },
2127         },
2128 };
2129
2130 static struct clk_branch camss_vfe0_ahb_clk = {
2131         .halt_reg = 0x3668,
2132         .clkr = {
2133                 .enable_reg = 0x3668,
2134                 .enable_mask = BIT(0),
2135                 .hw.init = &(struct clk_init_data){
2136                         .name = "camss_vfe0_ahb_clk",
2137                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2138                         .num_parents = 1,
2139                         .ops = &clk_branch2_ops,
2140                         .flags = CLK_SET_RATE_PARENT,
2141                 },
2142         },
2143 };
2144
2145 static struct clk_branch camss_vfe1_ahb_clk = {
2146         .halt_reg = 0x3678,
2147         .clkr = {
2148                 .enable_reg = 0x3678,
2149                 .enable_mask = BIT(0),
2150                 .hw.init = &(struct clk_init_data){
2151                         .name = "camss_vfe1_ahb_clk",
2152                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2153                         .num_parents = 1,
2154                         .ops = &clk_branch2_ops,
2155                         .flags = CLK_SET_RATE_PARENT,
2156                 },
2157         },
2158 };
2159
2160 static struct clk_branch camss_vfe0_clk = {
2161         .halt_reg = 0x36a8,
2162         .clkr = {
2163                 .enable_reg = 0x36a8,
2164                 .enable_mask = BIT(0),
2165                 .hw.init = &(struct clk_init_data){
2166                         .name = "camss_vfe0_clk",
2167                         .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2168                         .num_parents = 1,
2169                         .ops = &clk_branch2_ops,
2170                         .flags = CLK_SET_RATE_PARENT,
2171                 },
2172         },
2173 };
2174
2175 static struct clk_branch camss_vfe1_clk = {
2176         .halt_reg = 0x36ac,
2177         .clkr = {
2178                 .enable_reg = 0x36ac,
2179                 .enable_mask = BIT(0),
2180                 .hw.init = &(struct clk_init_data){
2181                         .name = "camss_vfe1_clk",
2182                         .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2183                         .num_parents = 1,
2184                         .ops = &clk_branch2_ops,
2185                         .flags = CLK_SET_RATE_PARENT,
2186                 },
2187         },
2188 };
2189
2190 static struct clk_branch camss_cpp_clk = {
2191         .halt_reg = 0x36b0,
2192         .clkr = {
2193                 .enable_reg = 0x36b0,
2194                 .enable_mask = BIT(0),
2195                 .hw.init = &(struct clk_init_data){
2196                         .name = "camss_cpp_clk",
2197                         .parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw },
2198                         .num_parents = 1,
2199                         .ops = &clk_branch2_ops,
2200                         .flags = CLK_SET_RATE_PARENT,
2201                 },
2202         },
2203 };
2204
2205 static struct clk_branch camss_cpp_ahb_clk = {
2206         .halt_reg = 0x36b4,
2207         .clkr = {
2208                 .enable_reg = 0x36b4,
2209                 .enable_mask = BIT(0),
2210                 .hw.init = &(struct clk_init_data){
2211                         .name = "camss_cpp_ahb_clk",
2212                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2213                         .num_parents = 1,
2214                         .ops = &clk_branch2_ops,
2215                         .flags = CLK_SET_RATE_PARENT,
2216                 },
2217         },
2218 };
2219
2220 static struct clk_branch camss_vfe_vbif_ahb_clk = {
2221         .halt_reg = 0x36b8,
2222         .clkr = {
2223                 .enable_reg = 0x36b8,
2224                 .enable_mask = BIT(0),
2225                 .hw.init = &(struct clk_init_data){
2226                         .name = "camss_vfe_vbif_ahb_clk",
2227                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2228                         .num_parents = 1,
2229                         .ops = &clk_branch2_ops,
2230                         .flags = CLK_SET_RATE_PARENT,
2231                 },
2232         },
2233 };
2234
2235 static struct clk_branch camss_vfe_vbif_axi_clk = {
2236         .halt_reg = 0x36bc,
2237         .clkr = {
2238                 .enable_reg = 0x36bc,
2239                 .enable_mask = BIT(0),
2240                 .hw.init = &(struct clk_init_data){
2241                         .name = "camss_vfe_vbif_axi_clk",
2242                         .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2243                         .num_parents = 1,
2244                         .ops = &clk_branch2_ops,
2245                 },
2246         },
2247 };
2248
2249 static struct clk_branch camss_cpp_axi_clk = {
2250         .halt_reg = 0x36c4,
2251         .clkr = {
2252                 .enable_reg = 0x36c4,
2253                 .enable_mask = BIT(0),
2254                 .hw.init = &(struct clk_init_data){
2255                         .name = "camss_cpp_axi_clk",
2256                         .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2257                         .num_parents = 1,
2258                         .ops = &clk_branch2_ops,
2259                 },
2260         },
2261 };
2262
2263 static struct clk_branch camss_cpp_vbif_ahb_clk = {
2264         .halt_reg = 0x36c8,
2265         .clkr = {
2266                 .enable_reg = 0x36c8,
2267                 .enable_mask = BIT(0),
2268                 .hw.init = &(struct clk_init_data){
2269                         .name = "camss_cpp_vbif_ahb_clk",
2270                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2271                         .num_parents = 1,
2272                         .ops = &clk_branch2_ops,
2273                         .flags = CLK_SET_RATE_PARENT,
2274                 },
2275         },
2276 };
2277
2278 static struct clk_branch camss_csi_vfe0_clk = {
2279         .halt_reg = 0x3704,
2280         .clkr = {
2281                 .enable_reg = 0x3704,
2282                 .enable_mask = BIT(0),
2283                 .hw.init = &(struct clk_init_data){
2284                         .name = "camss_csi_vfe0_clk",
2285                         .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2286                         .num_parents = 1,
2287                         .ops = &clk_branch2_ops,
2288                         .flags = CLK_SET_RATE_PARENT,
2289                 },
2290         },
2291 };
2292
2293 static struct clk_branch camss_csi_vfe1_clk = {
2294         .halt_reg = 0x3714,
2295         .clkr = {
2296                 .enable_reg = 0x3714,
2297                 .enable_mask = BIT(0),
2298                 .hw.init = &(struct clk_init_data){
2299                         .name = "camss_csi_vfe1_clk",
2300                         .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2301                         .num_parents = 1,
2302                         .ops = &clk_branch2_ops,
2303                         .flags = CLK_SET_RATE_PARENT,
2304                 },
2305         },
2306 };
2307
2308 static struct clk_branch camss_vfe0_stream_clk = {
2309         .halt_reg = 0x3720,
2310         .clkr = {
2311                 .enable_reg = 0x3720,
2312                 .enable_mask = BIT(0),
2313                 .hw.init = &(struct clk_init_data){
2314                         .name = "camss_vfe0_stream_clk",
2315                         .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2316                         .num_parents = 1,
2317                         .ops = &clk_branch2_ops,
2318                         .flags = CLK_SET_RATE_PARENT,
2319                 },
2320         },
2321 };
2322
2323 static struct clk_branch camss_vfe1_stream_clk = {
2324         .halt_reg = 0x3724,
2325         .clkr = {
2326                 .enable_reg = 0x3724,
2327                 .enable_mask = BIT(0),
2328                 .hw.init = &(struct clk_init_data){
2329                         .name = "camss_vfe1_stream_clk",
2330                         .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2331                         .num_parents = 1,
2332                         .ops = &clk_branch2_ops,
2333                         .flags = CLK_SET_RATE_PARENT,
2334                 },
2335         },
2336 };
2337
2338 static struct clk_branch camss_cphy_csid0_clk = {
2339         .halt_reg = 0x3730,
2340         .clkr = {
2341                 .enable_reg = 0x3730,
2342                 .enable_mask = BIT(0),
2343                 .hw.init = &(struct clk_init_data){
2344                         .name = "camss_cphy_csid0_clk",
2345                         .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2346                         .num_parents = 1,
2347                         .ops = &clk_branch2_ops,
2348                         .flags = CLK_SET_RATE_PARENT,
2349                 },
2350         },
2351 };
2352
2353 static struct clk_branch camss_cphy_csid1_clk = {
2354         .halt_reg = 0x3734,
2355         .clkr = {
2356                 .enable_reg = 0x3734,
2357                 .enable_mask = BIT(0),
2358                 .hw.init = &(struct clk_init_data){
2359                         .name = "camss_cphy_csid1_clk",
2360                         .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2361                         .num_parents = 1,
2362                         .ops = &clk_branch2_ops,
2363                         .flags = CLK_SET_RATE_PARENT,
2364                 },
2365         },
2366 };
2367
2368 static struct clk_branch camss_cphy_csid2_clk = {
2369         .halt_reg = 0x3738,
2370         .clkr = {
2371                 .enable_reg = 0x3738,
2372                 .enable_mask = BIT(0),
2373                 .hw.init = &(struct clk_init_data){
2374                         .name = "camss_cphy_csid2_clk",
2375                         .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2376                         .num_parents = 1,
2377                         .ops = &clk_branch2_ops,
2378                         .flags = CLK_SET_RATE_PARENT,
2379                 },
2380         },
2381 };
2382
2383 static struct clk_branch camss_cphy_csid3_clk = {
2384         .halt_reg = 0x373c,
2385         .clkr = {
2386                 .enable_reg = 0x373c,
2387                 .enable_mask = BIT(0),
2388                 .hw.init = &(struct clk_init_data){
2389                         .name = "camss_cphy_csid3_clk",
2390                         .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2391                         .num_parents = 1,
2392                         .ops = &clk_branch2_ops,
2393                         .flags = CLK_SET_RATE_PARENT,
2394                 },
2395         },
2396 };
2397
2398 static struct clk_branch camss_csiphy0_clk = {
2399         .halt_reg = 0x3740,
2400         .clkr = {
2401                 .enable_reg = 0x3740,
2402                 .enable_mask = BIT(0),
2403                 .hw.init = &(struct clk_init_data){
2404                         .name = "camss_csiphy0_clk",
2405                         .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2406                         .num_parents = 1,
2407                         .ops = &clk_branch2_ops,
2408                         .flags = CLK_SET_RATE_PARENT,
2409                 },
2410         },
2411 };
2412
2413 static struct clk_branch camss_csiphy1_clk = {
2414         .halt_reg = 0x3744,
2415         .clkr = {
2416                 .enable_reg = 0x3744,
2417                 .enable_mask = BIT(0),
2418                 .hw.init = &(struct clk_init_data){
2419                         .name = "camss_csiphy1_clk",
2420                         .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2421                         .num_parents = 1,
2422                         .ops = &clk_branch2_ops,
2423                         .flags = CLK_SET_RATE_PARENT,
2424                 },
2425         },
2426 };
2427
2428 static struct clk_branch camss_csiphy2_clk = {
2429         .halt_reg = 0x3748,
2430         .clkr = {
2431                 .enable_reg = 0x3748,
2432                 .enable_mask = BIT(0),
2433                 .hw.init = &(struct clk_init_data){
2434                         .name = "camss_csiphy2_clk",
2435                         .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2436                         .num_parents = 1,
2437                         .ops = &clk_branch2_ops,
2438                         .flags = CLK_SET_RATE_PARENT,
2439                 },
2440         },
2441 };
2442
2443 static struct clk_branch fd_core_clk = {
2444         .halt_reg = 0x3b68,
2445         .clkr = {
2446                 .enable_reg = 0x3b68,
2447                 .enable_mask = BIT(0),
2448                 .hw.init = &(struct clk_init_data){
2449                         .name = "fd_core_clk",
2450                         .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
2451                         .num_parents = 1,
2452                         .ops = &clk_branch2_ops,
2453                         .flags = CLK_SET_RATE_PARENT,
2454                 },
2455         },
2456 };
2457
2458 static struct clk_branch fd_core_uar_clk = {
2459         .halt_reg = 0x3b6c,
2460         .clkr = {
2461                 .enable_reg = 0x3b6c,
2462                 .enable_mask = BIT(0),
2463                 .hw.init = &(struct clk_init_data){
2464                         .name = "fd_core_uar_clk",
2465                         .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
2466                         .num_parents = 1,
2467                         .ops = &clk_branch2_ops,
2468                         .flags = CLK_SET_RATE_PARENT,
2469                 },
2470         },
2471 };
2472
2473 static struct clk_branch fd_ahb_clk = {
2474         .halt_reg = 0x3b74,
2475         .clkr = {
2476                 .enable_reg = 0x3b74,
2477                 .enable_mask = BIT(0),
2478                 .hw.init = &(struct clk_init_data){
2479                         .name = "fd_ahb_clk",
2480                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2481                         .num_parents = 1,
2482                         .ops = &clk_branch2_ops,
2483                         .flags = CLK_SET_RATE_PARENT,
2484                 },
2485         },
2486 };
2487
2488 static struct clk_branch mnoc_ahb_clk = {
2489         .halt_reg = 0x5024,
2490         .clkr = {
2491                 .enable_reg = 0x5024,
2492                 .enable_mask = BIT(0),
2493                 .hw.init = &(struct clk_init_data){
2494                         .name = "mnoc_ahb_clk",
2495                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2496                         .num_parents = 1,
2497                         .ops = &clk_branch2_ops,
2498                         .flags = CLK_SET_RATE_PARENT,
2499                 },
2500         },
2501 };
2502
2503 static struct clk_branch bimc_smmu_ahb_clk = {
2504         .halt_reg = 0xe004,
2505         .hwcg_reg = 0xe004,
2506         .hwcg_bit = 1,
2507         .clkr = {
2508                 .enable_reg = 0xe004,
2509                 .enable_mask = BIT(0),
2510                 .hw.init = &(struct clk_init_data){
2511                         .name = "bimc_smmu_ahb_clk",
2512                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2513                         .num_parents = 1,
2514                         .ops = &clk_branch2_ops,
2515                         .flags = CLK_SET_RATE_PARENT,
2516                 },
2517         },
2518 };
2519
2520 static struct clk_branch bimc_smmu_axi_clk = {
2521         .halt_reg = 0xe008,
2522         .hwcg_reg = 0xe008,
2523         .hwcg_bit = 1,
2524         .clkr = {
2525                 .enable_reg = 0xe008,
2526                 .enable_mask = BIT(0),
2527                 .hw.init = &(struct clk_init_data){
2528                         .name = "bimc_smmu_axi_clk",
2529                         .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2530                         .num_parents = 1,
2531                         .ops = &clk_branch2_ops,
2532                 },
2533         },
2534 };
2535
2536 static struct clk_branch mnoc_maxi_clk = {
2537         .halt_reg = 0xf004,
2538         .clkr = {
2539                 .enable_reg = 0xf004,
2540                 .enable_mask = BIT(0),
2541                 .hw.init = &(struct clk_init_data){
2542                         .name = "mnoc_maxi_clk",
2543                         .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
2544                         .num_parents = 1,
2545                         .ops = &clk_branch2_ops,
2546                         .flags = CLK_SET_RATE_PARENT,
2547                 },
2548         },
2549 };
2550
2551 static struct clk_branch vmem_maxi_clk = {
2552         .halt_reg = 0xf064,
2553         .clkr = {
2554                 .enable_reg = 0xf064,
2555                 .enable_mask = BIT(0),
2556                 .hw.init = &(struct clk_init_data){
2557                         .name = "vmem_maxi_clk",
2558                         .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
2559                         .num_parents = 1,
2560                         .ops = &clk_branch2_ops,
2561                         .flags = CLK_SET_RATE_PARENT,
2562                 },
2563         },
2564 };
2565
2566 static struct clk_branch vmem_ahb_clk = {
2567         .halt_reg = 0xf068,
2568         .clkr = {
2569                 .enable_reg = 0xf068,
2570                 .enable_mask = BIT(0),
2571                 .hw.init = &(struct clk_init_data){
2572                         .name = "vmem_ahb_clk",
2573                         .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2574                         .num_parents = 1,
2575                         .ops = &clk_branch2_ops,
2576                         .flags = CLK_SET_RATE_PARENT,
2577                 },
2578         },
2579 };
2580
2581 static struct clk_hw *mmcc_msm8998_hws[] = {
2582         &gpll0_div.hw,
2583 };
2584
2585 static struct gdsc video_top_gdsc = {
2586         .gdscr = 0x1024,
2587         .pd = {
2588                 .name = "video_top",
2589         },
2590         .pwrsts = PWRSTS_OFF_ON,
2591 };
2592
2593 static struct gdsc video_subcore0_gdsc = {
2594         .gdscr = 0x1040,
2595         .pd = {
2596                 .name = "video_subcore0",
2597         },
2598         .parent = &video_top_gdsc.pd,
2599         .pwrsts = PWRSTS_OFF_ON,
2600 };
2601
2602 static struct gdsc video_subcore1_gdsc = {
2603         .gdscr = 0x1044,
2604         .pd = {
2605                 .name = "video_subcore1",
2606         },
2607         .parent = &video_top_gdsc.pd,
2608         .pwrsts = PWRSTS_OFF_ON,
2609 };
2610
2611 static struct gdsc mdss_gdsc = {
2612         .gdscr = 0x2304,
2613         .cxcs = (unsigned int []){ 0x2310, 0x2350, 0x231c, 0x2320 },
2614         .cxc_count = 4,
2615         .pd = {
2616                 .name = "mdss",
2617         },
2618         .pwrsts = PWRSTS_OFF_ON,
2619 };
2620
2621 static struct gdsc camss_top_gdsc = {
2622         .gdscr = 0x34a0,
2623         .cxcs = (unsigned int []){ 0x35b8, 0x36c4, 0x3704, 0x3714, 0x3494,
2624                                    0x35a8, 0x3868 },
2625         .cxc_count = 7,
2626         .pd = {
2627                 .name = "camss_top",
2628         },
2629         .pwrsts = PWRSTS_OFF_ON,
2630 };
2631
2632 static struct gdsc camss_vfe0_gdsc = {
2633         .gdscr = 0x3664,
2634         .pd = {
2635                 .name = "camss_vfe0",
2636         },
2637         .parent = &camss_top_gdsc.pd,
2638         .pwrsts = PWRSTS_OFF_ON,
2639 };
2640
2641 static struct gdsc camss_vfe1_gdsc = {
2642         .gdscr = 0x3674,
2643         .pd = {
2644                 .name = "camss_vfe1_gdsc",
2645         },
2646         .parent = &camss_top_gdsc.pd,
2647         .pwrsts = PWRSTS_OFF_ON,
2648 };
2649
2650 static struct gdsc camss_cpp_gdsc = {
2651         .gdscr = 0x36d4,
2652         .pd = {
2653                 .name = "camss_cpp",
2654         },
2655         .parent = &camss_top_gdsc.pd,
2656         .pwrsts = PWRSTS_OFF_ON,
2657 };
2658
2659 static struct gdsc bimc_smmu_gdsc = {
2660         .gdscr = 0xe020,
2661         .gds_hw_ctrl = 0xe024,
2662         .pd = {
2663                 .name = "bimc_smmu",
2664         },
2665         .pwrsts = PWRSTS_OFF_ON,
2666         .flags = HW_CTRL | ALWAYS_ON,
2667 };
2668
2669 static struct clk_regmap *mmcc_msm8998_clocks[] = {
2670         [MMPLL0] = &mmpll0.clkr,
2671         [MMPLL0_OUT_EVEN] = &mmpll0_out_even.clkr,
2672         [MMPLL1] = &mmpll1.clkr,
2673         [MMPLL1_OUT_EVEN] = &mmpll1_out_even.clkr,
2674         [MMPLL3] = &mmpll3.clkr,
2675         [MMPLL3_OUT_EVEN] = &mmpll3_out_even.clkr,
2676         [MMPLL4] = &mmpll4.clkr,
2677         [MMPLL4_OUT_EVEN] = &mmpll4_out_even.clkr,
2678         [MMPLL5] = &mmpll5.clkr,
2679         [MMPLL5_OUT_EVEN] = &mmpll5_out_even.clkr,
2680         [MMPLL6] = &mmpll6.clkr,
2681         [MMPLL6_OUT_EVEN] = &mmpll6_out_even.clkr,
2682         [MMPLL7] = &mmpll7.clkr,
2683         [MMPLL7_OUT_EVEN] = &mmpll7_out_even.clkr,
2684         [MMPLL10] = &mmpll10.clkr,
2685         [MMPLL10_OUT_EVEN] = &mmpll10_out_even.clkr,
2686         [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2687         [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2688         [CCI_CLK_SRC] = &cci_clk_src.clkr,
2689         [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2690         [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2691         [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2692         [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2693         [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2694         [CSIPHY_CLK_SRC] = &csiphy_clk_src.clkr,
2695         [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2696         [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2697         [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2698         [DP_AUX_CLK_SRC] = &dp_aux_clk_src.clkr,
2699         [DP_CRYPTO_CLK_SRC] = &dp_crypto_clk_src.clkr,
2700         [DP_LINK_CLK_SRC] = &dp_link_clk_src.clkr,
2701         [DP_PIXEL_CLK_SRC] = &dp_pixel_clk_src.clkr,
2702         [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2703         [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2704         [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2705         [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
2706         [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2707         [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2708         [MAXI_CLK_SRC] = &maxi_clk_src.clkr,
2709         [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2710         [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2711         [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2712         [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2713         [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2714         [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2715         [AHB_CLK_SRC] = &ahb_clk_src.clkr,
2716         [AXI_CLK_SRC] = &axi_clk_src.clkr,
2717         [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2718         [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2719         [ROT_CLK_SRC] = &rot_clk_src.clkr,
2720         [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
2721         [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr,
2722         [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr,
2723         [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2724         [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2725         [MISC_AHB_CLK] = &misc_ahb_clk.clkr,
2726         [VIDEO_CORE_CLK] = &video_core_clk.clkr,
2727         [VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
2728         [VIDEO_AXI_CLK] = &video_axi_clk.clkr,
2729         [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr,
2730         [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
2731         [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr,
2732         [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2733         [MDSS_HDMI_DP_AHB_CLK] = &mdss_hdmi_dp_ahb_clk.clkr,
2734         [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2735         [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2736         [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2737         [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2738         [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2739         [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2740         [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2741         [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2742         [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2743         [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2744         [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2745         [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2746         [MDSS_ROT_CLK] = &mdss_rot_clk.clkr,
2747         [MDSS_DP_LINK_CLK] = &mdss_dp_link_clk.clkr,
2748         [MDSS_DP_LINK_INTF_CLK] = &mdss_dp_link_intf_clk.clkr,
2749         [MDSS_DP_CRYPTO_CLK] = &mdss_dp_crypto_clk.clkr,
2750         [MDSS_DP_PIXEL_CLK] = &mdss_dp_pixel_clk.clkr,
2751         [MDSS_DP_AUX_CLK] = &mdss_dp_aux_clk.clkr,
2752         [MDSS_BYTE0_INTF_CLK] = &mdss_byte0_intf_clk.clkr,
2753         [MDSS_BYTE1_INTF_CLK] = &mdss_byte1_intf_clk.clkr,
2754         [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
2755         [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
2756         [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
2757         [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2758         [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2759         [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2760         [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2761         [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2762         [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2763         [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2764         [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2765         [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2766         [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2767         [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2768         [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2769         [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2770         [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2771         [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2772         [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2773         [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2774         [CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
2775         [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
2776         [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2777         [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2778         [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2779         [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2780         [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2781         [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
2782         [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2783         [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
2784         [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
2785         [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
2786         [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
2787         [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
2788         [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
2789         [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
2790         [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
2791         [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
2792         [CAMSS_VFE_VBIF_AHB_CLK] = &camss_vfe_vbif_ahb_clk.clkr,
2793         [CAMSS_VFE_VBIF_AXI_CLK] = &camss_vfe_vbif_axi_clk.clkr,
2794         [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
2795         [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
2796         [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2797         [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2798         [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
2799         [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
2800         [CAMSS_CPHY_CSID0_CLK] = &camss_cphy_csid0_clk.clkr,
2801         [CAMSS_CPHY_CSID1_CLK] = &camss_cphy_csid1_clk.clkr,
2802         [CAMSS_CPHY_CSID2_CLK] = &camss_cphy_csid2_clk.clkr,
2803         [CAMSS_CPHY_CSID3_CLK] = &camss_cphy_csid3_clk.clkr,
2804         [CAMSS_CSIPHY0_CLK] = &camss_csiphy0_clk.clkr,
2805         [CAMSS_CSIPHY1_CLK] = &camss_csiphy1_clk.clkr,
2806         [CAMSS_CSIPHY2_CLK] = &camss_csiphy2_clk.clkr,
2807         [FD_CORE_CLK] = &fd_core_clk.clkr,
2808         [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
2809         [FD_AHB_CLK] = &fd_ahb_clk.clkr,
2810         [MNOC_AHB_CLK] = &mnoc_ahb_clk.clkr,
2811         [BIMC_SMMU_AHB_CLK] = &bimc_smmu_ahb_clk.clkr,
2812         [BIMC_SMMU_AXI_CLK] = &bimc_smmu_axi_clk.clkr,
2813         [MNOC_MAXI_CLK] = &mnoc_maxi_clk.clkr,
2814         [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr,
2815         [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr,
2816 };
2817
2818 static struct gdsc *mmcc_msm8998_gdscs[] = {
2819         [VIDEO_TOP_GDSC] = &video_top_gdsc,
2820         [VIDEO_SUBCORE0_GDSC] = &video_subcore0_gdsc,
2821         [VIDEO_SUBCORE1_GDSC] = &video_subcore1_gdsc,
2822         [MDSS_GDSC] = &mdss_gdsc,
2823         [CAMSS_TOP_GDSC] = &camss_top_gdsc,
2824         [CAMSS_VFE0_GDSC] = &camss_vfe0_gdsc,
2825         [CAMSS_VFE1_GDSC] = &camss_vfe1_gdsc,
2826         [CAMSS_CPP_GDSC] = &camss_cpp_gdsc,
2827         [BIMC_SMMU_GDSC] = &bimc_smmu_gdsc,
2828 };
2829
2830 static const struct qcom_reset_map mmcc_msm8998_resets[] = {
2831         [SPDM_BCR] = { 0x200 },
2832         [SPDM_RM_BCR] = { 0x300 },
2833         [MISC_BCR] = { 0x320 },
2834         [VIDEO_TOP_BCR] = { 0x1020 },
2835         [THROTTLE_VIDEO_BCR] = { 0x1180 },
2836         [MDSS_BCR] = { 0x2300 },
2837         [THROTTLE_MDSS_BCR] = { 0x2460 },
2838         [CAMSS_PHY0_BCR] = { 0x3020 },
2839         [CAMSS_PHY1_BCR] = { 0x3050 },
2840         [CAMSS_PHY2_BCR] = { 0x3080 },
2841         [CAMSS_CSI0_BCR] = { 0x30b0 },
2842         [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
2843         [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
2844         [CAMSS_CSI1_BCR] = { 0x3120 },
2845         [CAMSS_CSI1RDI_BCR] = { 0x3140 },
2846         [CAMSS_CSI1PIX_BCR] = { 0x3150 },
2847         [CAMSS_CSI2_BCR] = { 0x3180 },
2848         [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
2849         [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
2850         [CAMSS_CSI3_BCR] = { 0x31e0 },
2851         [CAMSS_CSI3RDI_BCR] = { 0x3200 },
2852         [CAMSS_CSI3PIX_BCR] = { 0x3210 },
2853         [CAMSS_ISPIF_BCR] = { 0x3220 },
2854         [CAMSS_CCI_BCR] = { 0x3340 },
2855         [CAMSS_TOP_BCR] = { 0x3480 },
2856         [CAMSS_AHB_BCR] = { 0x3488 },
2857         [CAMSS_MICRO_BCR] = { 0x3490 },
2858         [CAMSS_JPEG_BCR] = { 0x35a0 },
2859         [CAMSS_VFE0_BCR] = { 0x3660 },
2860         [CAMSS_VFE1_BCR] = { 0x3670 },
2861         [CAMSS_VFE_VBIF_BCR] = { 0x36a0 },
2862         [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
2863         [CAMSS_CPP_BCR] = { 0x36d0 },
2864         [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
2865         [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
2866         [CAMSS_FD_BCR] = { 0x3b60 },
2867         [THROTTLE_CAMSS_BCR] = { 0x3c30 },
2868         [MNOCAHB_BCR] = { 0x5020 },
2869         [MNOCAXI_BCR] = { 0xd020 },
2870         [BMIC_SMMU_BCR] = { 0xe000 },
2871         [MNOC_MAXI_BCR] = { 0xf000 },
2872         [VMEM_BCR] = { 0xf060 },
2873         [BTO_BCR] = { 0x10004 },
2874 };
2875
2876 static const struct regmap_config mmcc_msm8998_regmap_config = {
2877         .reg_bits       = 32,
2878         .reg_stride     = 4,
2879         .val_bits       = 32,
2880         .max_register   = 0x10004,
2881         .fast_io        = true,
2882 };
2883
2884 static const struct qcom_cc_desc mmcc_msm8998_desc = {
2885         .config = &mmcc_msm8998_regmap_config,
2886         .clks = mmcc_msm8998_clocks,
2887         .num_clks = ARRAY_SIZE(mmcc_msm8998_clocks),
2888         .resets = mmcc_msm8998_resets,
2889         .num_resets = ARRAY_SIZE(mmcc_msm8998_resets),
2890         .gdscs = mmcc_msm8998_gdscs,
2891         .num_gdscs = ARRAY_SIZE(mmcc_msm8998_gdscs),
2892         .clk_hws = mmcc_msm8998_hws,
2893         .num_clk_hws = ARRAY_SIZE(mmcc_msm8998_hws),
2894 };
2895
2896 static const struct of_device_id mmcc_msm8998_match_table[] = {
2897         { .compatible = "qcom,mmcc-msm8998" },
2898         { }
2899 };
2900 MODULE_DEVICE_TABLE(of, mmcc_msm8998_match_table);
2901
2902 static int mmcc_msm8998_probe(struct platform_device *pdev)
2903 {
2904         struct regmap *regmap;
2905
2906         regmap = qcom_cc_map(pdev, &mmcc_msm8998_desc);
2907         if (IS_ERR(regmap))
2908                 return PTR_ERR(regmap);
2909
2910         return qcom_cc_really_probe(pdev, &mmcc_msm8998_desc, regmap);
2911 }
2912
2913 static struct platform_driver mmcc_msm8998_driver = {
2914         .probe          = mmcc_msm8998_probe,
2915         .driver         = {
2916                 .name   = "mmcc-msm8998",
2917                 .of_match_table = mmcc_msm8998_match_table,
2918         },
2919 };
2920 module_platform_driver(mmcc_msm8998_driver);
2921
2922 MODULE_DESCRIPTION("QCOM MMCC MSM8998 Driver");
2923 MODULE_LICENSE("GPL v2");