1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
12 #include <linux/clk-provider.h>
13 #include <linux/regmap.h>
14 #include <linux/reset-controller.h>
15 #include <linux/clk.h>
17 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
20 #include "clk-regmap.h"
21 #include "clk-regmap-divider.h"
22 #include "clk-alpha-pll.h"
24 #include "clk-branch.h"
47 static struct clk_fixed_factor gpll0_div = {
50 .hw.init = &(struct clk_init_data){
52 .parent_data = (const struct clk_parent_data[]){
53 { .fw_name = "gpll0", .name = "gpll0" },
56 .ops = &clk_fixed_factor_ops,
60 static const struct pll_vco mmpll_p_vco[] = {
61 { 250000000, 500000000, 3 },
62 { 500000000, 1000000000, 2 },
63 { 1000000000, 1500000000, 1 },
64 { 1500000000, 2000000000, 0 },
67 static const struct pll_vco mmpll_gfx_vco[] = {
68 { 400000000, 1000000000, 2 },
69 { 1000000000, 1500000000, 1 },
70 { 1500000000, 2000000000, 0 },
73 static const struct pll_vco mmpll_t_vco[] = {
74 { 500000000, 1500000000, 0 },
77 static struct clk_alpha_pll mmpll0_early = {
79 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
80 .vco_table = mmpll_p_vco,
81 .num_vco = ARRAY_SIZE(mmpll_p_vco),
84 .enable_mask = BIT(0),
85 .hw.init = &(struct clk_init_data){
86 .name = "mmpll0_early",
87 .parent_data = (const struct clk_parent_data[]){
88 { .fw_name = "xo", .name = "xo_board" },
91 .ops = &clk_alpha_pll_ops,
96 static struct clk_alpha_pll_postdiv mmpll0 = {
98 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
100 .clkr.hw.init = &(struct clk_init_data){
102 .parent_hws = (const struct clk_hw*[]){
103 &mmpll0_early.clkr.hw
106 .ops = &clk_alpha_pll_postdiv_ops,
107 .flags = CLK_SET_RATE_PARENT,
111 static struct clk_alpha_pll mmpll1_early = {
113 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
114 .vco_table = mmpll_p_vco,
115 .num_vco = ARRAY_SIZE(mmpll_p_vco),
118 .enable_mask = BIT(1),
119 .hw.init = &(struct clk_init_data){
120 .name = "mmpll1_early",
121 .parent_data = (const struct clk_parent_data[]){
122 { .fw_name = "xo", .name = "xo_board" },
125 .ops = &clk_alpha_pll_ops,
130 static struct clk_alpha_pll_postdiv mmpll1 = {
132 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
134 .clkr.hw.init = &(struct clk_init_data){
136 .parent_hws = (const struct clk_hw*[]){
137 &mmpll1_early.clkr.hw
140 .ops = &clk_alpha_pll_postdiv_ops,
141 .flags = CLK_SET_RATE_PARENT,
145 static struct clk_alpha_pll mmpll2_early = {
147 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
148 .vco_table = mmpll_gfx_vco,
149 .num_vco = ARRAY_SIZE(mmpll_gfx_vco),
150 .clkr.hw.init = &(struct clk_init_data){
151 .name = "mmpll2_early",
152 .parent_data = (const struct clk_parent_data[]){
153 { .fw_name = "xo", .name = "xo_board" },
156 .ops = &clk_alpha_pll_ops,
160 static struct clk_alpha_pll_postdiv mmpll2 = {
162 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
164 .clkr.hw.init = &(struct clk_init_data){
166 .parent_hws = (const struct clk_hw*[]){
167 &mmpll2_early.clkr.hw
170 .ops = &clk_alpha_pll_postdiv_ops,
171 .flags = CLK_SET_RATE_PARENT,
175 static struct clk_alpha_pll mmpll3_early = {
177 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
178 .vco_table = mmpll_p_vco,
179 .num_vco = ARRAY_SIZE(mmpll_p_vco),
180 .clkr.hw.init = &(struct clk_init_data){
181 .name = "mmpll3_early",
182 .parent_data = (const struct clk_parent_data[]){
183 { .fw_name = "xo", .name = "xo_board" },
186 .ops = &clk_alpha_pll_ops,
190 static struct clk_alpha_pll_postdiv mmpll3 = {
192 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
194 .clkr.hw.init = &(struct clk_init_data){
196 .parent_hws = (const struct clk_hw*[]){
197 &mmpll3_early.clkr.hw
200 .ops = &clk_alpha_pll_postdiv_ops,
201 .flags = CLK_SET_RATE_PARENT,
205 static struct clk_alpha_pll mmpll4_early = {
207 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
208 .vco_table = mmpll_t_vco,
209 .num_vco = ARRAY_SIZE(mmpll_t_vco),
210 .clkr.hw.init = &(struct clk_init_data){
211 .name = "mmpll4_early",
212 .parent_data = (const struct clk_parent_data[]){
213 { .fw_name = "xo", .name = "xo_board" },
216 .ops = &clk_alpha_pll_ops,
220 static struct clk_alpha_pll_postdiv mmpll4 = {
222 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
224 .clkr.hw.init = &(struct clk_init_data){
226 .parent_hws = (const struct clk_hw*[]){
227 &mmpll4_early.clkr.hw
230 .ops = &clk_alpha_pll_postdiv_ops,
231 .flags = CLK_SET_RATE_PARENT,
235 static struct clk_alpha_pll mmpll5_early = {
237 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
238 .vco_table = mmpll_p_vco,
239 .num_vco = ARRAY_SIZE(mmpll_p_vco),
240 .clkr.hw.init = &(struct clk_init_data){
241 .name = "mmpll5_early",
242 .parent_data = (const struct clk_parent_data[]){
243 { .fw_name = "xo", .name = "xo_board" },
246 .ops = &clk_alpha_pll_ops,
250 static struct clk_alpha_pll_postdiv mmpll5 = {
252 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
254 .clkr.hw.init = &(struct clk_init_data){
256 .parent_hws = (const struct clk_hw*[]){
257 &mmpll5_early.clkr.hw
260 .ops = &clk_alpha_pll_postdiv_ops,
261 .flags = CLK_SET_RATE_PARENT,
265 static struct clk_alpha_pll mmpll8_early = {
267 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
268 .vco_table = mmpll_gfx_vco,
269 .num_vco = ARRAY_SIZE(mmpll_gfx_vco),
270 .clkr.hw.init = &(struct clk_init_data){
271 .name = "mmpll8_early",
272 .parent_data = (const struct clk_parent_data[]){
273 { .fw_name = "xo", .name = "xo_board" },
276 .ops = &clk_alpha_pll_ops,
280 static struct clk_alpha_pll_postdiv mmpll8 = {
282 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
284 .clkr.hw.init = &(struct clk_init_data){
286 .parent_hws = (const struct clk_hw*[]){
287 &mmpll8_early.clkr.hw
290 .ops = &clk_alpha_pll_postdiv_ops,
291 .flags = CLK_SET_RATE_PARENT,
295 static struct clk_alpha_pll mmpll9_early = {
297 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
298 .vco_table = mmpll_t_vco,
299 .num_vco = ARRAY_SIZE(mmpll_t_vco),
300 .clkr.hw.init = &(struct clk_init_data){
301 .name = "mmpll9_early",
302 .parent_data = (const struct clk_parent_data[]){
303 { .fw_name = "xo", .name = "xo_board" },
306 .ops = &clk_alpha_pll_ops,
310 static struct clk_alpha_pll_postdiv mmpll9 = {
312 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
314 .clkr.hw.init = &(struct clk_init_data){
316 .parent_hws = (const struct clk_hw*[]){
317 &mmpll9_early.clkr.hw
320 .ops = &clk_alpha_pll_postdiv_ops,
321 .flags = CLK_SET_RATE_PARENT,
325 static const struct parent_map mmss_xo_hdmi_map[] = {
330 static const struct clk_parent_data mmss_xo_hdmi[] = {
331 { .fw_name = "xo", .name = "xo_board" },
332 { .fw_name = "hdmipll", .name = "hdmipll" }
335 static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
341 static const struct clk_parent_data mmss_xo_dsi0pll_dsi1pll[] = {
342 { .fw_name = "xo", .name = "xo_board" },
343 { .fw_name = "dsi0pll", .name = "dsi0pll" },
344 { .fw_name = "dsi1pll", .name = "dsi1pll" }
347 static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
353 static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = {
354 { .fw_name = "xo", .name = "xo_board" },
355 { .fw_name = "gpll0", .name = "gpll0" },
356 { .hw = &gpll0_div.hw }
359 static const struct parent_map mmss_xo_dsibyte_map[] = {
361 { P_DSI0PLL_BYTE, 1 },
362 { P_DSI1PLL_BYTE, 2 }
365 static const struct clk_parent_data mmss_xo_dsibyte[] = {
366 { .fw_name = "xo", .name = "xo_board" },
367 { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
368 { .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" }
371 static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
378 static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = {
379 { .fw_name = "xo", .name = "xo_board" },
380 { .hw = &mmpll0.clkr.hw },
381 { .fw_name = "gpll0", .name = "gpll0" },
382 { .hw = &gpll0_div.hw }
385 static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
393 static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
394 { .fw_name = "xo", .name = "xo_board" },
395 { .hw = &mmpll0.clkr.hw },
396 { .hw = &mmpll1.clkr.hw },
397 { .fw_name = "gpll0", .name = "gpll0" },
398 { .hw = &gpll0_div.hw }
401 static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = {
409 static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = {
410 { .fw_name = "xo", .name = "xo_board" },
411 { .hw = &mmpll0.clkr.hw },
412 { .hw = &mmpll3.clkr.hw },
413 { .fw_name = "gpll0", .name = "gpll0" },
414 { .hw = &gpll0_div.hw }
417 static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
425 static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
426 { .fw_name = "xo", .name = "xo_board" },
427 { .hw = &mmpll0.clkr.hw },
428 { .hw = &mmpll5.clkr.hw },
429 { .fw_name = "gpll0", .name = "gpll0" },
430 { .hw = &gpll0_div.hw }
433 static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = {
441 static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = {
442 { .fw_name = "xo", .name = "xo_board" },
443 { .hw = &mmpll0.clkr.hw },
444 { .hw = &mmpll4.clkr.hw },
445 { .fw_name = "gpll0", .name = "gpll0" },
446 { .hw = &gpll0_div.hw }
449 static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = {
458 static const struct clk_parent_data mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = {
459 { .fw_name = "xo", .name = "xo_board" },
460 { .hw = &mmpll0.clkr.hw },
461 { .hw = &mmpll9.clkr.hw },
462 { .hw = &mmpll2.clkr.hw },
463 { .hw = &mmpll8.clkr.hw },
464 { .fw_name = "gpll0", .name = "gpll0" },
467 static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = {
477 static const struct clk_parent_data mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = {
478 { .fw_name = "xo", .name = "xo_board" },
479 { .hw = &mmpll0.clkr.hw },
480 { .hw = &mmpll9.clkr.hw },
481 { .hw = &mmpll2.clkr.hw },
482 { .hw = &mmpll8.clkr.hw },
483 { .fw_name = "gpll0", .name = "gpll0" },
484 { .hw = &gpll0_div.hw }
487 static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = {
497 static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = {
498 { .fw_name = "xo", .name = "xo_board" },
499 { .hw = &mmpll0.clkr.hw },
500 { .hw = &mmpll1.clkr.hw },
501 { .hw = &mmpll4.clkr.hw },
502 { .hw = &mmpll3.clkr.hw },
503 { .fw_name = "gpll0", .name = "gpll0" },
504 { .hw = &gpll0_div.hw }
507 static const struct freq_tbl ftbl_ahb_clk_src[] = {
508 F(19200000, P_XO, 1, 0, 0),
509 F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
510 F(80000000, P_MMPLL0, 10, 0, 0),
514 static struct clk_rcg2 ahb_clk_src = {
517 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
518 .freq_tbl = ftbl_ahb_clk_src,
519 .clkr.hw.init = &(struct clk_init_data){
520 .name = "ahb_clk_src",
521 .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
522 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div),
523 .ops = &clk_rcg2_ops,
527 static const struct freq_tbl ftbl_axi_clk_src[] = {
528 F(19200000, P_XO, 1, 0, 0),
529 F(75000000, P_GPLL0_DIV, 4, 0, 0),
530 F(100000000, P_GPLL0, 6, 0, 0),
531 F(171430000, P_GPLL0, 3.5, 0, 0),
532 F(200000000, P_GPLL0, 3, 0, 0),
533 F(320000000, P_MMPLL0, 2.5, 0, 0),
534 F(400000000, P_MMPLL0, 2, 0, 0),
538 static struct clk_rcg2 axi_clk_src = {
541 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
542 .freq_tbl = ftbl_axi_clk_src,
543 .clkr.hw.init = &(struct clk_init_data){
544 .name = "axi_clk_src",
545 .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
546 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div),
547 .ops = &clk_rcg2_ops,
551 static struct clk_rcg2 maxi_clk_src = {
554 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
555 .freq_tbl = ftbl_axi_clk_src,
556 .clkr.hw.init = &(struct clk_init_data){
557 .name = "maxi_clk_src",
558 .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
559 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div),
560 .ops = &clk_rcg2_ops,
564 static struct clk_rcg2_gfx3d gfx3d_clk_src = {
568 .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map,
569 .clkr.hw.init = &(struct clk_init_data){
570 .name = "gfx3d_clk_src",
571 .parent_data = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0,
572 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0),
573 .ops = &clk_gfx3d_ops,
574 .flags = CLK_SET_RATE_PARENT,
577 .hws = (struct clk_hw*[]) {
584 static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
585 F(19200000, P_XO, 1, 0, 0),
589 static struct clk_rcg2 rbbmtimer_clk_src = {
592 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
593 .freq_tbl = ftbl_rbbmtimer_clk_src,
594 .clkr.hw.init = &(struct clk_init_data){
595 .name = "rbbmtimer_clk_src",
596 .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
597 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div),
598 .ops = &clk_rcg2_ops,
602 static struct clk_rcg2 isense_clk_src = {
605 .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map,
606 .clkr.hw.init = &(struct clk_init_data){
607 .name = "isense_clk_src",
608 .parent_data = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div,
609 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div),
610 .ops = &clk_rcg2_ops,
614 static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
615 F(19200000, P_XO, 1, 0, 0),
616 F(50000000, P_GPLL0, 12, 0, 0),
620 static struct clk_rcg2 rbcpr_clk_src = {
623 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
624 .freq_tbl = ftbl_rbcpr_clk_src,
625 .clkr.hw.init = &(struct clk_init_data){
626 .name = "rbcpr_clk_src",
627 .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
628 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div),
629 .ops = &clk_rcg2_ops,
633 static const struct freq_tbl ftbl_video_core_clk_src[] = {
634 F(75000000, P_GPLL0_DIV, 4, 0, 0),
635 F(150000000, P_GPLL0, 4, 0, 0),
636 F(346666667, P_MMPLL3, 3, 0, 0),
637 F(520000000, P_MMPLL3, 2, 0, 0),
641 static struct clk_rcg2 video_core_clk_src = {
645 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
646 .freq_tbl = ftbl_video_core_clk_src,
647 .clkr.hw.init = &(struct clk_init_data){
648 .name = "video_core_clk_src",
649 .parent_data = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
650 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div),
651 .ops = &clk_rcg2_ops,
655 static struct clk_rcg2 video_subcore0_clk_src = {
659 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
660 .freq_tbl = ftbl_video_core_clk_src,
661 .clkr.hw.init = &(struct clk_init_data){
662 .name = "video_subcore0_clk_src",
663 .parent_data = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
664 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div),
665 .ops = &clk_rcg2_ops,
669 static struct clk_rcg2 video_subcore1_clk_src = {
673 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
674 .freq_tbl = ftbl_video_core_clk_src,
675 .clkr.hw.init = &(struct clk_init_data){
676 .name = "video_subcore1_clk_src",
677 .parent_data = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
678 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div),
679 .ops = &clk_rcg2_ops,
683 static struct clk_rcg2 pclk0_clk_src = {
687 .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
688 .clkr.hw.init = &(struct clk_init_data){
689 .name = "pclk0_clk_src",
690 .parent_data = mmss_xo_dsi0pll_dsi1pll,
691 .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll),
692 .ops = &clk_pixel_ops,
693 .flags = CLK_SET_RATE_PARENT,
697 static struct clk_rcg2 pclk1_clk_src = {
701 .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
702 .clkr.hw.init = &(struct clk_init_data){
703 .name = "pclk1_clk_src",
704 .parent_data = mmss_xo_dsi0pll_dsi1pll,
705 .num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll),
706 .ops = &clk_pixel_ops,
707 .flags = CLK_SET_RATE_PARENT,
711 static const struct freq_tbl ftbl_mdp_clk_src[] = {
712 F(85714286, P_GPLL0, 7, 0, 0),
713 F(100000000, P_GPLL0, 6, 0, 0),
714 F(150000000, P_GPLL0, 4, 0, 0),
715 F(171428571, P_GPLL0, 3.5, 0, 0),
716 F(200000000, P_GPLL0, 3, 0, 0),
717 F(275000000, P_MMPLL5, 3, 0, 0),
718 F(300000000, P_GPLL0, 2, 0, 0),
719 F(330000000, P_MMPLL5, 2.5, 0, 0),
720 F(412500000, P_MMPLL5, 2, 0, 0),
724 static struct clk_rcg2 mdp_clk_src = {
727 .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
728 .freq_tbl = ftbl_mdp_clk_src,
729 .clkr.hw.init = &(struct clk_init_data){
730 .name = "mdp_clk_src",
731 .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
732 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div),
733 .ops = &clk_rcg2_ops,
737 static struct freq_tbl extpclk_freq_tbl[] = {
738 { .src = P_HDMIPLL },
742 static struct clk_rcg2 extpclk_clk_src = {
745 .parent_map = mmss_xo_hdmi_map,
746 .freq_tbl = extpclk_freq_tbl,
747 .clkr.hw.init = &(struct clk_init_data){
748 .name = "extpclk_clk_src",
749 .parent_data = mmss_xo_hdmi,
750 .num_parents = ARRAY_SIZE(mmss_xo_hdmi),
751 .ops = &clk_byte_ops,
752 .flags = CLK_SET_RATE_PARENT,
756 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
757 F(19200000, P_XO, 1, 0, 0),
761 static struct clk_rcg2 vsync_clk_src = {
764 .parent_map = mmss_xo_gpll0_gpll0_div_map,
765 .freq_tbl = ftbl_mdss_vsync_clk,
766 .clkr.hw.init = &(struct clk_init_data){
767 .name = "vsync_clk_src",
768 .parent_data = mmss_xo_gpll0_gpll0_div,
769 .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
770 .ops = &clk_rcg2_ops,
774 static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
775 F(19200000, P_XO, 1, 0, 0),
779 static struct clk_rcg2 hdmi_clk_src = {
782 .parent_map = mmss_xo_gpll0_gpll0_div_map,
783 .freq_tbl = ftbl_mdss_hdmi_clk,
784 .clkr.hw.init = &(struct clk_init_data){
785 .name = "hdmi_clk_src",
786 .parent_data = mmss_xo_gpll0_gpll0_div,
787 .num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
788 .ops = &clk_rcg2_ops,
792 static struct clk_rcg2 byte0_clk_src = {
795 .parent_map = mmss_xo_dsibyte_map,
796 .clkr.hw.init = &(struct clk_init_data){
797 .name = "byte0_clk_src",
798 .parent_data = mmss_xo_dsibyte,
799 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
800 .ops = &clk_byte2_ops,
801 .flags = CLK_SET_RATE_PARENT,
805 static struct clk_rcg2 byte1_clk_src = {
808 .parent_map = mmss_xo_dsibyte_map,
809 .clkr.hw.init = &(struct clk_init_data){
810 .name = "byte1_clk_src",
811 .parent_data = mmss_xo_dsibyte,
812 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
813 .ops = &clk_byte2_ops,
814 .flags = CLK_SET_RATE_PARENT,
818 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
819 F(19200000, P_XO, 1, 0, 0),
823 static struct clk_rcg2 esc0_clk_src = {
826 .parent_map = mmss_xo_dsibyte_map,
827 .freq_tbl = ftbl_mdss_esc0_1_clk,
828 .clkr.hw.init = &(struct clk_init_data){
829 .name = "esc0_clk_src",
830 .parent_data = mmss_xo_dsibyte,
831 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
832 .ops = &clk_rcg2_ops,
836 static struct clk_rcg2 esc1_clk_src = {
839 .parent_map = mmss_xo_dsibyte_map,
840 .freq_tbl = ftbl_mdss_esc0_1_clk,
841 .clkr.hw.init = &(struct clk_init_data){
842 .name = "esc1_clk_src",
843 .parent_data = mmss_xo_dsibyte,
844 .num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
845 .ops = &clk_rcg2_ops,
849 static const struct freq_tbl ftbl_camss_gp0_clk_src[] = {
850 F(10000, P_XO, 16, 1, 120),
851 F(24000, P_XO, 16, 1, 50),
852 F(6000000, P_GPLL0_DIV, 10, 1, 5),
853 F(12000000, P_GPLL0_DIV, 1, 1, 25),
854 F(13000000, P_GPLL0_DIV, 2, 13, 150),
855 F(24000000, P_GPLL0_DIV, 1, 2, 25),
859 static struct clk_rcg2 camss_gp0_clk_src = {
863 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
864 .freq_tbl = ftbl_camss_gp0_clk_src,
865 .clkr.hw.init = &(struct clk_init_data){
866 .name = "camss_gp0_clk_src",
867 .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
868 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
869 .ops = &clk_rcg2_ops,
873 static struct clk_rcg2 camss_gp1_clk_src = {
877 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
878 .freq_tbl = ftbl_camss_gp0_clk_src,
879 .clkr.hw.init = &(struct clk_init_data){
880 .name = "camss_gp1_clk_src",
881 .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
882 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
883 .ops = &clk_rcg2_ops,
887 static const struct freq_tbl ftbl_mclk0_clk_src[] = {
888 F(4800000, P_XO, 4, 0, 0),
889 F(6000000, P_GPLL0_DIV, 10, 1, 5),
890 F(8000000, P_GPLL0_DIV, 1, 2, 75),
891 F(9600000, P_XO, 2, 0, 0),
892 F(16666667, P_GPLL0_DIV, 2, 1, 9),
893 F(19200000, P_XO, 1, 0, 0),
894 F(24000000, P_GPLL0_DIV, 1, 2, 25),
895 F(33333333, P_GPLL0_DIV, 1, 1, 9),
896 F(48000000, P_GPLL0, 1, 2, 25),
897 F(66666667, P_GPLL0, 1, 1, 9),
901 static struct clk_rcg2 mclk0_clk_src = {
905 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
906 .freq_tbl = ftbl_mclk0_clk_src,
907 .clkr.hw.init = &(struct clk_init_data){
908 .name = "mclk0_clk_src",
909 .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
910 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
911 .ops = &clk_rcg2_ops,
915 static struct clk_rcg2 mclk1_clk_src = {
919 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
920 .freq_tbl = ftbl_mclk0_clk_src,
921 .clkr.hw.init = &(struct clk_init_data){
922 .name = "mclk1_clk_src",
923 .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
924 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
925 .ops = &clk_rcg2_ops,
929 static struct clk_rcg2 mclk2_clk_src = {
933 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
934 .freq_tbl = ftbl_mclk0_clk_src,
935 .clkr.hw.init = &(struct clk_init_data){
936 .name = "mclk2_clk_src",
937 .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
938 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
939 .ops = &clk_rcg2_ops,
943 static struct clk_rcg2 mclk3_clk_src = {
947 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
948 .freq_tbl = ftbl_mclk0_clk_src,
949 .clkr.hw.init = &(struct clk_init_data){
950 .name = "mclk3_clk_src",
951 .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
952 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
953 .ops = &clk_rcg2_ops,
957 static const struct freq_tbl ftbl_cci_clk_src[] = {
958 F(19200000, P_XO, 1, 0, 0),
959 F(37500000, P_GPLL0, 16, 0, 0),
960 F(50000000, P_GPLL0, 12, 0, 0),
961 F(100000000, P_GPLL0, 6, 0, 0),
965 static struct clk_rcg2 cci_clk_src = {
969 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
970 .freq_tbl = ftbl_cci_clk_src,
971 .clkr.hw.init = &(struct clk_init_data){
972 .name = "cci_clk_src",
973 .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
974 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
975 .ops = &clk_rcg2_ops,
979 static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = {
980 F(100000000, P_GPLL0_DIV, 3, 0, 0),
981 F(200000000, P_GPLL0, 3, 0, 0),
982 F(266666667, P_MMPLL0, 3, 0, 0),
986 static struct clk_rcg2 csi0phytimer_clk_src = {
989 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
990 .freq_tbl = ftbl_csi0phytimer_clk_src,
991 .clkr.hw.init = &(struct clk_init_data){
992 .name = "csi0phytimer_clk_src",
993 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
994 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
995 .ops = &clk_rcg2_ops,
999 static struct clk_rcg2 csi1phytimer_clk_src = {
1002 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1003 .freq_tbl = ftbl_csi0phytimer_clk_src,
1004 .clkr.hw.init = &(struct clk_init_data){
1005 .name = "csi1phytimer_clk_src",
1006 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1007 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1008 .ops = &clk_rcg2_ops,
1012 static struct clk_rcg2 csi2phytimer_clk_src = {
1015 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1016 .freq_tbl = ftbl_csi0phytimer_clk_src,
1017 .clkr.hw.init = &(struct clk_init_data){
1018 .name = "csi2phytimer_clk_src",
1019 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1020 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1021 .ops = &clk_rcg2_ops,
1025 static const struct freq_tbl ftbl_csiphy0_3p_clk_src[] = {
1026 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1027 F(200000000, P_GPLL0, 3, 0, 0),
1028 F(320000000, P_MMPLL4, 3, 0, 0),
1029 F(384000000, P_MMPLL4, 2.5, 0, 0),
1033 static struct clk_rcg2 csiphy0_3p_clk_src = {
1036 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1037 .freq_tbl = ftbl_csiphy0_3p_clk_src,
1038 .clkr.hw.init = &(struct clk_init_data){
1039 .name = "csiphy0_3p_clk_src",
1040 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1041 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1042 .ops = &clk_rcg2_ops,
1046 static struct clk_rcg2 csiphy1_3p_clk_src = {
1049 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1050 .freq_tbl = ftbl_csiphy0_3p_clk_src,
1051 .clkr.hw.init = &(struct clk_init_data){
1052 .name = "csiphy1_3p_clk_src",
1053 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1054 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1055 .ops = &clk_rcg2_ops,
1059 static struct clk_rcg2 csiphy2_3p_clk_src = {
1062 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1063 .freq_tbl = ftbl_csiphy0_3p_clk_src,
1064 .clkr.hw.init = &(struct clk_init_data){
1065 .name = "csiphy2_3p_clk_src",
1066 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1067 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1068 .ops = &clk_rcg2_ops,
1072 static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
1073 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1074 F(150000000, P_GPLL0, 4, 0, 0),
1075 F(228571429, P_MMPLL0, 3.5, 0, 0),
1076 F(266666667, P_MMPLL0, 3, 0, 0),
1077 F(320000000, P_MMPLL0, 2.5, 0, 0),
1078 F(480000000, P_MMPLL4, 2, 0, 0),
1082 static struct clk_rcg2 jpeg0_clk_src = {
1085 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1086 .freq_tbl = ftbl_jpeg0_clk_src,
1087 .clkr.hw.init = &(struct clk_init_data){
1088 .name = "jpeg0_clk_src",
1089 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1090 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1091 .ops = &clk_rcg2_ops,
1095 static const struct freq_tbl ftbl_jpeg2_clk_src[] = {
1096 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1097 F(150000000, P_GPLL0, 4, 0, 0),
1098 F(228571429, P_MMPLL0, 3.5, 0, 0),
1099 F(266666667, P_MMPLL0, 3, 0, 0),
1100 F(320000000, P_MMPLL0, 2.5, 0, 0),
1104 static struct clk_rcg2 jpeg2_clk_src = {
1107 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1108 .freq_tbl = ftbl_jpeg2_clk_src,
1109 .clkr.hw.init = &(struct clk_init_data){
1110 .name = "jpeg2_clk_src",
1111 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1112 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1113 .ops = &clk_rcg2_ops,
1117 static struct clk_rcg2 jpeg_dma_clk_src = {
1120 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1121 .freq_tbl = ftbl_jpeg0_clk_src,
1122 .clkr.hw.init = &(struct clk_init_data){
1123 .name = "jpeg_dma_clk_src",
1124 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1125 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1126 .ops = &clk_rcg2_ops,
1130 static const struct freq_tbl ftbl_vfe0_clk_src[] = {
1131 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1132 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1133 F(300000000, P_GPLL0, 2, 0, 0),
1134 F(320000000, P_MMPLL0, 2.5, 0, 0),
1135 F(480000000, P_MMPLL4, 2, 0, 0),
1136 F(600000000, P_GPLL0, 1, 0, 0),
1140 static struct clk_rcg2 vfe0_clk_src = {
1143 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1144 .freq_tbl = ftbl_vfe0_clk_src,
1145 .clkr.hw.init = &(struct clk_init_data){
1146 .name = "vfe0_clk_src",
1147 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1148 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1149 .ops = &clk_rcg2_ops,
1153 static struct clk_rcg2 vfe1_clk_src = {
1156 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1157 .freq_tbl = ftbl_vfe0_clk_src,
1158 .clkr.hw.init = &(struct clk_init_data){
1159 .name = "vfe1_clk_src",
1160 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1161 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1162 .ops = &clk_rcg2_ops,
1166 static const struct freq_tbl ftbl_cpp_clk_src[] = {
1167 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1168 F(200000000, P_GPLL0, 3, 0, 0),
1169 F(320000000, P_MMPLL0, 2.5, 0, 0),
1170 F(480000000, P_MMPLL4, 2, 0, 0),
1171 F(640000000, P_MMPLL4, 1.5, 0, 0),
1175 static struct clk_rcg2 cpp_clk_src = {
1178 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1179 .freq_tbl = ftbl_cpp_clk_src,
1180 .clkr.hw.init = &(struct clk_init_data){
1181 .name = "cpp_clk_src",
1182 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1183 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1184 .ops = &clk_rcg2_ops,
1188 static const struct freq_tbl ftbl_csi0_clk_src[] = {
1189 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1190 F(200000000, P_GPLL0, 3, 0, 0),
1191 F(266666667, P_MMPLL0, 3, 0, 0),
1192 F(480000000, P_MMPLL4, 2, 0, 0),
1193 F(600000000, P_GPLL0, 1, 0, 0),
1197 static struct clk_rcg2 csi0_clk_src = {
1200 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1201 .freq_tbl = ftbl_csi0_clk_src,
1202 .clkr.hw.init = &(struct clk_init_data){
1203 .name = "csi0_clk_src",
1204 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1205 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1206 .ops = &clk_rcg2_ops,
1210 static struct clk_rcg2 csi1_clk_src = {
1213 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1214 .freq_tbl = ftbl_csi0_clk_src,
1215 .clkr.hw.init = &(struct clk_init_data){
1216 .name = "csi1_clk_src",
1217 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1218 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1219 .ops = &clk_rcg2_ops,
1223 static struct clk_rcg2 csi2_clk_src = {
1226 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1227 .freq_tbl = ftbl_csi0_clk_src,
1228 .clkr.hw.init = &(struct clk_init_data){
1229 .name = "csi2_clk_src",
1230 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1231 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1232 .ops = &clk_rcg2_ops,
1236 static struct clk_rcg2 csi3_clk_src = {
1239 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1240 .freq_tbl = ftbl_csi0_clk_src,
1241 .clkr.hw.init = &(struct clk_init_data){
1242 .name = "csi3_clk_src",
1243 .parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1244 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1245 .ops = &clk_rcg2_ops,
1249 static const struct freq_tbl ftbl_fd_core_clk_src[] = {
1250 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1251 F(200000000, P_GPLL0, 3, 0, 0),
1252 F(400000000, P_MMPLL0, 2, 0, 0),
1256 static struct clk_rcg2 fd_core_clk_src = {
1259 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
1260 .freq_tbl = ftbl_fd_core_clk_src,
1261 .clkr.hw.init = &(struct clk_init_data){
1262 .name = "fd_core_clk_src",
1263 .parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
1264 .num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
1265 .ops = &clk_rcg2_ops,
1269 static struct clk_branch mmss_mmagic_ahb_clk = {
1272 .enable_reg = 0x5024,
1273 .enable_mask = BIT(0),
1274 .hw.init = &(struct clk_init_data){
1275 .name = "mmss_mmagic_ahb_clk",
1276 .parent_hws = (const struct clk_hw*[]){
1277 &ahb_clk_src.clkr.hw
1280 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1281 .ops = &clk_branch2_ops,
1286 static struct clk_branch mmss_mmagic_cfg_ahb_clk = {
1289 .enable_reg = 0x5054,
1290 .enable_mask = BIT(0),
1291 .hw.init = &(struct clk_init_data){
1292 .name = "mmss_mmagic_cfg_ahb_clk",
1293 .parent_hws = (const struct clk_hw*[]){
1294 &ahb_clk_src.clkr.hw
1297 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1298 .ops = &clk_branch2_ops,
1303 static struct clk_branch mmss_misc_ahb_clk = {
1306 .enable_reg = 0x5018,
1307 .enable_mask = BIT(0),
1308 .hw.init = &(struct clk_init_data){
1309 .name = "mmss_misc_ahb_clk",
1310 .parent_hws = (const struct clk_hw*[]){
1311 &ahb_clk_src.clkr.hw
1314 .flags = CLK_SET_RATE_PARENT,
1315 .ops = &clk_branch2_ops,
1320 static struct clk_branch mmss_misc_cxo_clk = {
1323 .enable_reg = 0x5014,
1324 .enable_mask = BIT(0),
1325 .hw.init = &(struct clk_init_data){
1326 .name = "mmss_misc_cxo_clk",
1327 .parent_data = (const struct clk_parent_data[]){
1328 { .fw_name = "xo", .name = "xo_board" },
1331 .ops = &clk_branch2_ops,
1336 static struct clk_branch mmss_mmagic_maxi_clk = {
1339 .enable_reg = 0x5074,
1340 .enable_mask = BIT(0),
1341 .hw.init = &(struct clk_init_data){
1342 .name = "mmss_mmagic_maxi_clk",
1343 .parent_hws = (const struct clk_hw*[]){
1344 &maxi_clk_src.clkr.hw
1347 .flags = CLK_SET_RATE_PARENT,
1348 .ops = &clk_branch2_ops,
1353 static struct clk_branch mmagic_camss_axi_clk = {
1356 .enable_reg = 0x3c44,
1357 .enable_mask = BIT(0),
1358 .hw.init = &(struct clk_init_data){
1359 .name = "mmagic_camss_axi_clk",
1360 .parent_hws = (const struct clk_hw*[]){
1361 &axi_clk_src.clkr.hw
1364 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1365 .ops = &clk_branch2_ops,
1370 static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = {
1373 .enable_reg = 0x3c48,
1374 .enable_mask = BIT(0),
1375 .hw.init = &(struct clk_init_data){
1376 .name = "mmagic_camss_noc_cfg_ahb_clk",
1377 .parent_data = (const struct clk_parent_data[]){
1378 { .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" },
1381 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1382 .ops = &clk_branch2_ops,
1387 static struct clk_branch smmu_vfe_ahb_clk = {
1390 .enable_reg = 0x3c04,
1391 .enable_mask = BIT(0),
1392 .hw.init = &(struct clk_init_data){
1393 .name = "smmu_vfe_ahb_clk",
1394 .parent_hws = (const struct clk_hw*[]){
1395 &ahb_clk_src.clkr.hw
1398 .flags = CLK_SET_RATE_PARENT,
1399 .ops = &clk_branch2_ops,
1404 static struct clk_branch smmu_vfe_axi_clk = {
1407 .enable_reg = 0x3c08,
1408 .enable_mask = BIT(0),
1409 .hw.init = &(struct clk_init_data){
1410 .name = "smmu_vfe_axi_clk",
1411 .parent_hws = (const struct clk_hw*[]){
1412 &axi_clk_src.clkr.hw
1415 .flags = CLK_SET_RATE_PARENT,
1416 .ops = &clk_branch2_ops,
1421 static struct clk_branch smmu_cpp_ahb_clk = {
1424 .enable_reg = 0x3c14,
1425 .enable_mask = BIT(0),
1426 .hw.init = &(struct clk_init_data){
1427 .name = "smmu_cpp_ahb_clk",
1428 .parent_hws = (const struct clk_hw*[]){
1429 &ahb_clk_src.clkr.hw
1432 .flags = CLK_SET_RATE_PARENT,
1433 .ops = &clk_branch2_ops,
1438 static struct clk_branch smmu_cpp_axi_clk = {
1441 .enable_reg = 0x3c18,
1442 .enable_mask = BIT(0),
1443 .hw.init = &(struct clk_init_data){
1444 .name = "smmu_cpp_axi_clk",
1445 .parent_hws = (const struct clk_hw*[]){
1446 &axi_clk_src.clkr.hw
1449 .flags = CLK_SET_RATE_PARENT,
1450 .ops = &clk_branch2_ops,
1455 static struct clk_branch smmu_jpeg_ahb_clk = {
1458 .enable_reg = 0x3c24,
1459 .enable_mask = BIT(0),
1460 .hw.init = &(struct clk_init_data){
1461 .name = "smmu_jpeg_ahb_clk",
1462 .parent_hws = (const struct clk_hw*[]){
1463 &ahb_clk_src.clkr.hw
1466 .flags = CLK_SET_RATE_PARENT,
1467 .ops = &clk_branch2_ops,
1472 static struct clk_branch smmu_jpeg_axi_clk = {
1475 .enable_reg = 0x3c28,
1476 .enable_mask = BIT(0),
1477 .hw.init = &(struct clk_init_data){
1478 .name = "smmu_jpeg_axi_clk",
1479 .parent_hws = (const struct clk_hw*[]){
1480 &axi_clk_src.clkr.hw
1483 .flags = CLK_SET_RATE_PARENT,
1484 .ops = &clk_branch2_ops,
1489 static struct clk_branch mmagic_mdss_axi_clk = {
1492 .enable_reg = 0x2474,
1493 .enable_mask = BIT(0),
1494 .hw.init = &(struct clk_init_data){
1495 .name = "mmagic_mdss_axi_clk",
1496 .parent_hws = (const struct clk_hw*[]){
1497 &axi_clk_src.clkr.hw
1500 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1501 .ops = &clk_branch2_ops,
1506 static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = {
1509 .enable_reg = 0x2478,
1510 .enable_mask = BIT(0),
1511 .hw.init = &(struct clk_init_data){
1512 .name = "mmagic_mdss_noc_cfg_ahb_clk",
1513 .parent_data = (const struct clk_parent_data[]){
1514 { .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" },
1517 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1518 .ops = &clk_branch2_ops,
1523 static struct clk_branch smmu_rot_ahb_clk = {
1526 .enable_reg = 0x2444,
1527 .enable_mask = BIT(0),
1528 .hw.init = &(struct clk_init_data){
1529 .name = "smmu_rot_ahb_clk",
1530 .parent_hws = (const struct clk_hw*[]){
1531 &ahb_clk_src.clkr.hw
1534 .flags = CLK_SET_RATE_PARENT,
1535 .ops = &clk_branch2_ops,
1540 static struct clk_branch smmu_rot_axi_clk = {
1543 .enable_reg = 0x2448,
1544 .enable_mask = BIT(0),
1545 .hw.init = &(struct clk_init_data){
1546 .name = "smmu_rot_axi_clk",
1547 .parent_hws = (const struct clk_hw*[]){
1548 &axi_clk_src.clkr.hw
1551 .flags = CLK_SET_RATE_PARENT,
1552 .ops = &clk_branch2_ops,
1557 static struct clk_branch smmu_mdp_ahb_clk = {
1560 .enable_reg = 0x2454,
1561 .enable_mask = BIT(0),
1562 .hw.init = &(struct clk_init_data){
1563 .name = "smmu_mdp_ahb_clk",
1564 .parent_hws = (const struct clk_hw*[]){
1565 &ahb_clk_src.clkr.hw
1568 .flags = CLK_SET_RATE_PARENT,
1569 .ops = &clk_branch2_ops,
1574 static struct clk_branch smmu_mdp_axi_clk = {
1577 .enable_reg = 0x2458,
1578 .enable_mask = BIT(0),
1579 .hw.init = &(struct clk_init_data){
1580 .name = "smmu_mdp_axi_clk",
1581 .parent_hws = (const struct clk_hw*[]){
1582 &axi_clk_src.clkr.hw
1585 .flags = CLK_SET_RATE_PARENT,
1586 .ops = &clk_branch2_ops,
1591 static struct clk_branch mmagic_video_axi_clk = {
1594 .enable_reg = 0x1194,
1595 .enable_mask = BIT(0),
1596 .hw.init = &(struct clk_init_data){
1597 .name = "mmagic_video_axi_clk",
1598 .parent_hws = (const struct clk_hw*[]){
1599 &axi_clk_src.clkr.hw
1602 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1603 .ops = &clk_branch2_ops,
1608 static struct clk_branch mmagic_video_noc_cfg_ahb_clk = {
1611 .enable_reg = 0x1198,
1612 .enable_mask = BIT(0),
1613 .hw.init = &(struct clk_init_data){
1614 .name = "mmagic_video_noc_cfg_ahb_clk",
1615 .parent_data = (const struct clk_parent_data[]){
1616 { .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" },
1619 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1620 .ops = &clk_branch2_ops,
1625 static struct clk_branch smmu_video_ahb_clk = {
1628 .enable_reg = 0x1174,
1629 .enable_mask = BIT(0),
1630 .hw.init = &(struct clk_init_data){
1631 .name = "smmu_video_ahb_clk",
1632 .parent_hws = (const struct clk_hw*[]){
1633 &ahb_clk_src.clkr.hw
1636 .flags = CLK_SET_RATE_PARENT,
1637 .ops = &clk_branch2_ops,
1642 static struct clk_branch smmu_video_axi_clk = {
1645 .enable_reg = 0x1178,
1646 .enable_mask = BIT(0),
1647 .hw.init = &(struct clk_init_data){
1648 .name = "smmu_video_axi_clk",
1649 .parent_hws = (const struct clk_hw*[]){
1650 &axi_clk_src.clkr.hw
1653 .flags = CLK_SET_RATE_PARENT,
1654 .ops = &clk_branch2_ops,
1659 static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = {
1662 .enable_reg = 0x5298,
1663 .enable_mask = BIT(0),
1664 .hw.init = &(struct clk_init_data){
1665 .name = "mmagic_bimc_noc_cfg_ahb_clk",
1666 .parent_data = (const struct clk_parent_data[]){
1667 { .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" },
1670 .flags = CLK_SET_RATE_PARENT,
1671 .ops = &clk_branch2_ops,
1676 static struct clk_branch gpu_gx_gfx3d_clk = {
1679 .enable_reg = 0x4028,
1680 .enable_mask = BIT(0),
1681 .hw.init = &(struct clk_init_data){
1682 .name = "gpu_gx_gfx3d_clk",
1683 .parent_hws = (const struct clk_hw*[]){
1684 &gfx3d_clk_src.rcg.clkr.hw
1687 .flags = CLK_SET_RATE_PARENT,
1688 .ops = &clk_branch2_ops,
1693 static struct clk_branch gpu_gx_rbbmtimer_clk = {
1696 .enable_reg = 0x40b0,
1697 .enable_mask = BIT(0),
1698 .hw.init = &(struct clk_init_data){
1699 .name = "gpu_gx_rbbmtimer_clk",
1700 .parent_hws = (const struct clk_hw*[]){
1701 &rbbmtimer_clk_src.clkr.hw
1704 .flags = CLK_SET_RATE_PARENT,
1705 .ops = &clk_branch2_ops,
1710 static struct clk_branch gpu_ahb_clk = {
1713 .enable_reg = 0x403c,
1714 .enable_mask = BIT(0),
1715 .hw.init = &(struct clk_init_data){
1716 .name = "gpu_ahb_clk",
1717 .parent_hws = (const struct clk_hw*[]){
1718 &ahb_clk_src.clkr.hw
1721 .flags = CLK_SET_RATE_PARENT,
1722 .ops = &clk_branch2_ops,
1727 static struct clk_branch gpu_aon_isense_clk = {
1730 .enable_reg = 0x4044,
1731 .enable_mask = BIT(0),
1732 .hw.init = &(struct clk_init_data){
1733 .name = "gpu_aon_isense_clk",
1734 .parent_hws = (const struct clk_hw*[]){
1735 &isense_clk_src.clkr.hw
1738 .flags = CLK_SET_RATE_PARENT,
1739 .ops = &clk_branch2_ops,
1744 static struct clk_branch vmem_maxi_clk = {
1747 .enable_reg = 0x1204,
1748 .enable_mask = BIT(0),
1749 .hw.init = &(struct clk_init_data){
1750 .name = "vmem_maxi_clk",
1751 .parent_hws = (const struct clk_hw*[]){
1752 &maxi_clk_src.clkr.hw
1755 .flags = CLK_SET_RATE_PARENT,
1756 .ops = &clk_branch2_ops,
1761 static struct clk_branch vmem_ahb_clk = {
1764 .enable_reg = 0x1208,
1765 .enable_mask = BIT(0),
1766 .hw.init = &(struct clk_init_data){
1767 .name = "vmem_ahb_clk",
1768 .parent_hws = (const struct clk_hw*[]){
1769 &ahb_clk_src.clkr.hw
1772 .flags = CLK_SET_RATE_PARENT,
1773 .ops = &clk_branch2_ops,
1778 static struct clk_branch mmss_rbcpr_clk = {
1781 .enable_reg = 0x4084,
1782 .enable_mask = BIT(0),
1783 .hw.init = &(struct clk_init_data){
1784 .name = "mmss_rbcpr_clk",
1785 .parent_hws = (const struct clk_hw*[]){
1786 &rbcpr_clk_src.clkr.hw
1789 .flags = CLK_SET_RATE_PARENT,
1790 .ops = &clk_branch2_ops,
1795 static struct clk_branch mmss_rbcpr_ahb_clk = {
1798 .enable_reg = 0x4088,
1799 .enable_mask = BIT(0),
1800 .hw.init = &(struct clk_init_data){
1801 .name = "mmss_rbcpr_ahb_clk",
1802 .parent_hws = (const struct clk_hw*[]){
1803 &ahb_clk_src.clkr.hw
1806 .flags = CLK_SET_RATE_PARENT,
1807 .ops = &clk_branch2_ops,
1812 static struct clk_branch video_core_clk = {
1815 .enable_reg = 0x1028,
1816 .enable_mask = BIT(0),
1817 .hw.init = &(struct clk_init_data){
1818 .name = "video_core_clk",
1819 .parent_hws = (const struct clk_hw*[]){
1820 &video_core_clk_src.clkr.hw
1823 .flags = CLK_SET_RATE_PARENT,
1824 .ops = &clk_branch2_ops,
1829 static struct clk_branch video_axi_clk = {
1832 .enable_reg = 0x1034,
1833 .enable_mask = BIT(0),
1834 .hw.init = &(struct clk_init_data){
1835 .name = "video_axi_clk",
1836 .parent_hws = (const struct clk_hw*[]){
1837 &axi_clk_src.clkr.hw
1840 .flags = CLK_SET_RATE_PARENT,
1841 .ops = &clk_branch2_ops,
1846 static struct clk_branch video_maxi_clk = {
1849 .enable_reg = 0x1038,
1850 .enable_mask = BIT(0),
1851 .hw.init = &(struct clk_init_data){
1852 .name = "video_maxi_clk",
1853 .parent_hws = (const struct clk_hw*[]){
1854 &maxi_clk_src.clkr.hw
1857 .flags = CLK_SET_RATE_PARENT,
1858 .ops = &clk_branch2_ops,
1863 static struct clk_branch video_ahb_clk = {
1866 .enable_reg = 0x1030,
1867 .enable_mask = BIT(0),
1868 .hw.init = &(struct clk_init_data){
1869 .name = "video_ahb_clk",
1870 .parent_hws = (const struct clk_hw*[]){
1871 &ahb_clk_src.clkr.hw
1874 .flags = CLK_SET_RATE_PARENT,
1875 .ops = &clk_branch2_ops,
1880 static struct clk_branch video_subcore0_clk = {
1883 .enable_reg = 0x1048,
1884 .enable_mask = BIT(0),
1885 .hw.init = &(struct clk_init_data){
1886 .name = "video_subcore0_clk",
1887 .parent_hws = (const struct clk_hw*[]){
1888 &video_subcore0_clk_src.clkr.hw
1891 .flags = CLK_SET_RATE_PARENT,
1892 .ops = &clk_branch2_ops,
1897 static struct clk_branch video_subcore1_clk = {
1900 .enable_reg = 0x104c,
1901 .enable_mask = BIT(0),
1902 .hw.init = &(struct clk_init_data){
1903 .name = "video_subcore1_clk",
1904 .parent_hws = (const struct clk_hw*[]){
1905 &video_subcore1_clk_src.clkr.hw
1908 .flags = CLK_SET_RATE_PARENT,
1909 .ops = &clk_branch2_ops,
1914 static struct clk_branch mdss_ahb_clk = {
1917 .enable_reg = 0x2308,
1918 .enable_mask = BIT(0),
1919 .hw.init = &(struct clk_init_data){
1920 .name = "mdss_ahb_clk",
1921 .parent_hws = (const struct clk_hw*[]){
1922 &ahb_clk_src.clkr.hw
1925 .flags = CLK_SET_RATE_PARENT,
1926 .ops = &clk_branch2_ops,
1931 static struct clk_branch mdss_hdmi_ahb_clk = {
1934 .enable_reg = 0x230c,
1935 .enable_mask = BIT(0),
1936 .hw.init = &(struct clk_init_data){
1937 .name = "mdss_hdmi_ahb_clk",
1938 .parent_hws = (const struct clk_hw*[]){
1939 &ahb_clk_src.clkr.hw
1942 .flags = CLK_SET_RATE_PARENT,
1943 .ops = &clk_branch2_ops,
1948 static struct clk_branch mdss_axi_clk = {
1951 .enable_reg = 0x2310,
1952 .enable_mask = BIT(0),
1953 .hw.init = &(struct clk_init_data){
1954 .name = "mdss_axi_clk",
1955 .parent_hws = (const struct clk_hw*[]){
1956 &axi_clk_src.clkr.hw
1959 .flags = CLK_SET_RATE_PARENT,
1960 .ops = &clk_branch2_ops,
1965 static struct clk_branch mdss_pclk0_clk = {
1968 .enable_reg = 0x2314,
1969 .enable_mask = BIT(0),
1970 .hw.init = &(struct clk_init_data){
1971 .name = "mdss_pclk0_clk",
1972 .parent_hws = (const struct clk_hw*[]){
1973 &pclk0_clk_src.clkr.hw
1976 .flags = CLK_SET_RATE_PARENT,
1977 .ops = &clk_branch2_ops,
1982 static struct clk_branch mdss_pclk1_clk = {
1985 .enable_reg = 0x2318,
1986 .enable_mask = BIT(0),
1987 .hw.init = &(struct clk_init_data){
1988 .name = "mdss_pclk1_clk",
1989 .parent_hws = (const struct clk_hw*[]){
1990 &pclk1_clk_src.clkr.hw
1993 .flags = CLK_SET_RATE_PARENT,
1994 .ops = &clk_branch2_ops,
1999 static struct clk_branch mdss_mdp_clk = {
2002 .enable_reg = 0x231c,
2003 .enable_mask = BIT(0),
2004 .hw.init = &(struct clk_init_data){
2005 .name = "mdss_mdp_clk",
2006 .parent_hws = (const struct clk_hw*[]){
2007 &mdp_clk_src.clkr.hw
2010 .flags = CLK_SET_RATE_PARENT,
2011 .ops = &clk_branch2_ops,
2016 static struct clk_branch mdss_extpclk_clk = {
2019 .enable_reg = 0x2324,
2020 .enable_mask = BIT(0),
2021 .hw.init = &(struct clk_init_data){
2022 .name = "mdss_extpclk_clk",
2023 .parent_hws = (const struct clk_hw*[]){
2024 &extpclk_clk_src.clkr.hw
2027 .flags = CLK_SET_RATE_PARENT,
2028 .ops = &clk_branch2_ops,
2033 static struct clk_branch mdss_vsync_clk = {
2036 .enable_reg = 0x2328,
2037 .enable_mask = BIT(0),
2038 .hw.init = &(struct clk_init_data){
2039 .name = "mdss_vsync_clk",
2040 .parent_hws = (const struct clk_hw*[]){
2041 &vsync_clk_src.clkr.hw
2044 .flags = CLK_SET_RATE_PARENT,
2045 .ops = &clk_branch2_ops,
2050 static struct clk_branch mdss_hdmi_clk = {
2053 .enable_reg = 0x2338,
2054 .enable_mask = BIT(0),
2055 .hw.init = &(struct clk_init_data){
2056 .name = "mdss_hdmi_clk",
2057 .parent_hws = (const struct clk_hw*[]){
2058 &hdmi_clk_src.clkr.hw
2061 .flags = CLK_SET_RATE_PARENT,
2062 .ops = &clk_branch2_ops,
2067 static struct clk_branch mdss_byte0_clk = {
2070 .enable_reg = 0x233c,
2071 .enable_mask = BIT(0),
2072 .hw.init = &(struct clk_init_data){
2073 .name = "mdss_byte0_clk",
2074 .parent_hws = (const struct clk_hw*[]){
2075 &byte0_clk_src.clkr.hw
2078 .flags = CLK_SET_RATE_PARENT,
2079 .ops = &clk_branch2_ops,
2084 static struct clk_branch mdss_byte1_clk = {
2087 .enable_reg = 0x2340,
2088 .enable_mask = BIT(0),
2089 .hw.init = &(struct clk_init_data){
2090 .name = "mdss_byte1_clk",
2091 .parent_hws = (const struct clk_hw*[]){
2092 &byte1_clk_src.clkr.hw
2095 .flags = CLK_SET_RATE_PARENT,
2096 .ops = &clk_branch2_ops,
2101 static struct clk_branch mdss_esc0_clk = {
2104 .enable_reg = 0x2344,
2105 .enable_mask = BIT(0),
2106 .hw.init = &(struct clk_init_data){
2107 .name = "mdss_esc0_clk",
2108 .parent_hws = (const struct clk_hw*[]){
2109 &esc0_clk_src.clkr.hw
2112 .flags = CLK_SET_RATE_PARENT,
2113 .ops = &clk_branch2_ops,
2118 static struct clk_branch mdss_esc1_clk = {
2121 .enable_reg = 0x2348,
2122 .enable_mask = BIT(0),
2123 .hw.init = &(struct clk_init_data){
2124 .name = "mdss_esc1_clk",
2125 .parent_hws = (const struct clk_hw*[]){
2126 &esc1_clk_src.clkr.hw
2129 .flags = CLK_SET_RATE_PARENT,
2130 .ops = &clk_branch2_ops,
2135 static struct clk_branch camss_top_ahb_clk = {
2138 .enable_reg = 0x3484,
2139 .enable_mask = BIT(0),
2140 .hw.init = &(struct clk_init_data){
2141 .name = "camss_top_ahb_clk",
2142 .parent_hws = (const struct clk_hw*[]){
2143 &ahb_clk_src.clkr.hw
2146 .flags = CLK_SET_RATE_PARENT,
2147 .ops = &clk_branch2_ops,
2152 static struct clk_branch camss_ahb_clk = {
2155 .enable_reg = 0x348c,
2156 .enable_mask = BIT(0),
2157 .hw.init = &(struct clk_init_data){
2158 .name = "camss_ahb_clk",
2159 .parent_hws = (const struct clk_hw*[]){
2160 &ahb_clk_src.clkr.hw
2163 .flags = CLK_SET_RATE_PARENT,
2164 .ops = &clk_branch2_ops,
2169 static struct clk_branch camss_micro_ahb_clk = {
2172 .enable_reg = 0x3494,
2173 .enable_mask = BIT(0),
2174 .hw.init = &(struct clk_init_data){
2175 .name = "camss_micro_ahb_clk",
2176 .parent_hws = (const struct clk_hw*[]){
2177 &ahb_clk_src.clkr.hw
2180 .flags = CLK_SET_RATE_PARENT,
2181 .ops = &clk_branch2_ops,
2186 static struct clk_branch camss_gp0_clk = {
2189 .enable_reg = 0x3444,
2190 .enable_mask = BIT(0),
2191 .hw.init = &(struct clk_init_data){
2192 .name = "camss_gp0_clk",
2193 .parent_hws = (const struct clk_hw*[]){
2194 &camss_gp0_clk_src.clkr.hw
2197 .flags = CLK_SET_RATE_PARENT,
2198 .ops = &clk_branch2_ops,
2203 static struct clk_branch camss_gp1_clk = {
2206 .enable_reg = 0x3474,
2207 .enable_mask = BIT(0),
2208 .hw.init = &(struct clk_init_data){
2209 .name = "camss_gp1_clk",
2210 .parent_hws = (const struct clk_hw*[]){
2211 &camss_gp1_clk_src.clkr.hw
2214 .flags = CLK_SET_RATE_PARENT,
2215 .ops = &clk_branch2_ops,
2220 static struct clk_branch camss_mclk0_clk = {
2223 .enable_reg = 0x3384,
2224 .enable_mask = BIT(0),
2225 .hw.init = &(struct clk_init_data){
2226 .name = "camss_mclk0_clk",
2227 .parent_hws = (const struct clk_hw*[]){
2228 &mclk0_clk_src.clkr.hw
2231 .flags = CLK_SET_RATE_PARENT,
2232 .ops = &clk_branch2_ops,
2237 static struct clk_branch camss_mclk1_clk = {
2240 .enable_reg = 0x33b4,
2241 .enable_mask = BIT(0),
2242 .hw.init = &(struct clk_init_data){
2243 .name = "camss_mclk1_clk",
2244 .parent_hws = (const struct clk_hw*[]){
2245 &mclk1_clk_src.clkr.hw
2248 .flags = CLK_SET_RATE_PARENT,
2249 .ops = &clk_branch2_ops,
2254 static struct clk_branch camss_mclk2_clk = {
2257 .enable_reg = 0x33e4,
2258 .enable_mask = BIT(0),
2259 .hw.init = &(struct clk_init_data){
2260 .name = "camss_mclk2_clk",
2261 .parent_hws = (const struct clk_hw*[]){
2262 &mclk2_clk_src.clkr.hw
2265 .flags = CLK_SET_RATE_PARENT,
2266 .ops = &clk_branch2_ops,
2271 static struct clk_branch camss_mclk3_clk = {
2274 .enable_reg = 0x3414,
2275 .enable_mask = BIT(0),
2276 .hw.init = &(struct clk_init_data){
2277 .name = "camss_mclk3_clk",
2278 .parent_hws = (const struct clk_hw*[]){
2279 &mclk3_clk_src.clkr.hw
2282 .flags = CLK_SET_RATE_PARENT,
2283 .ops = &clk_branch2_ops,
2288 static struct clk_branch camss_cci_clk = {
2291 .enable_reg = 0x3344,
2292 .enable_mask = BIT(0),
2293 .hw.init = &(struct clk_init_data){
2294 .name = "camss_cci_clk",
2295 .parent_hws = (const struct clk_hw*[]){
2296 &cci_clk_src.clkr.hw
2299 .flags = CLK_SET_RATE_PARENT,
2300 .ops = &clk_branch2_ops,
2305 static struct clk_branch camss_cci_ahb_clk = {
2308 .enable_reg = 0x3348,
2309 .enable_mask = BIT(0),
2310 .hw.init = &(struct clk_init_data){
2311 .name = "camss_cci_ahb_clk",
2312 .parent_hws = (const struct clk_hw*[]){
2313 &ahb_clk_src.clkr.hw
2316 .flags = CLK_SET_RATE_PARENT,
2317 .ops = &clk_branch2_ops,
2322 static struct clk_branch camss_csi0phytimer_clk = {
2325 .enable_reg = 0x3024,
2326 .enable_mask = BIT(0),
2327 .hw.init = &(struct clk_init_data){
2328 .name = "camss_csi0phytimer_clk",
2329 .parent_hws = (const struct clk_hw*[]){
2330 &csi0phytimer_clk_src.clkr.hw
2333 .flags = CLK_SET_RATE_PARENT,
2334 .ops = &clk_branch2_ops,
2339 static struct clk_branch camss_csi1phytimer_clk = {
2342 .enable_reg = 0x3054,
2343 .enable_mask = BIT(0),
2344 .hw.init = &(struct clk_init_data){
2345 .name = "camss_csi1phytimer_clk",
2346 .parent_hws = (const struct clk_hw*[]){
2347 &csi1phytimer_clk_src.clkr.hw
2350 .flags = CLK_SET_RATE_PARENT,
2351 .ops = &clk_branch2_ops,
2356 static struct clk_branch camss_csi2phytimer_clk = {
2359 .enable_reg = 0x3084,
2360 .enable_mask = BIT(0),
2361 .hw.init = &(struct clk_init_data){
2362 .name = "camss_csi2phytimer_clk",
2363 .parent_hws = (const struct clk_hw*[]){
2364 &csi2phytimer_clk_src.clkr.hw
2367 .flags = CLK_SET_RATE_PARENT,
2368 .ops = &clk_branch2_ops,
2373 static struct clk_branch camss_csiphy0_3p_clk = {
2376 .enable_reg = 0x3234,
2377 .enable_mask = BIT(0),
2378 .hw.init = &(struct clk_init_data){
2379 .name = "camss_csiphy0_3p_clk",
2380 .parent_hws = (const struct clk_hw*[]){
2381 &csiphy0_3p_clk_src.clkr.hw
2384 .flags = CLK_SET_RATE_PARENT,
2385 .ops = &clk_branch2_ops,
2390 static struct clk_branch camss_csiphy1_3p_clk = {
2393 .enable_reg = 0x3254,
2394 .enable_mask = BIT(0),
2395 .hw.init = &(struct clk_init_data){
2396 .name = "camss_csiphy1_3p_clk",
2397 .parent_hws = (const struct clk_hw*[]){
2398 &csiphy1_3p_clk_src.clkr.hw
2401 .flags = CLK_SET_RATE_PARENT,
2402 .ops = &clk_branch2_ops,
2407 static struct clk_branch camss_csiphy2_3p_clk = {
2410 .enable_reg = 0x3274,
2411 .enable_mask = BIT(0),
2412 .hw.init = &(struct clk_init_data){
2413 .name = "camss_csiphy2_3p_clk",
2414 .parent_hws = (const struct clk_hw*[]){
2415 &csiphy2_3p_clk_src.clkr.hw
2418 .flags = CLK_SET_RATE_PARENT,
2419 .ops = &clk_branch2_ops,
2424 static struct clk_branch camss_jpeg0_clk = {
2427 .enable_reg = 0x35a8,
2428 .enable_mask = BIT(0),
2429 .hw.init = &(struct clk_init_data){
2430 .name = "camss_jpeg0_clk",
2431 .parent_hws = (const struct clk_hw*[]){
2432 &jpeg0_clk_src.clkr.hw
2435 .flags = CLK_SET_RATE_PARENT,
2436 .ops = &clk_branch2_ops,
2441 static struct clk_branch camss_jpeg2_clk = {
2444 .enable_reg = 0x35b0,
2445 .enable_mask = BIT(0),
2446 .hw.init = &(struct clk_init_data){
2447 .name = "camss_jpeg2_clk",
2448 .parent_hws = (const struct clk_hw*[]){
2449 &jpeg2_clk_src.clkr.hw
2452 .flags = CLK_SET_RATE_PARENT,
2453 .ops = &clk_branch2_ops,
2458 static struct clk_branch camss_jpeg_dma_clk = {
2461 .enable_reg = 0x35c0,
2462 .enable_mask = BIT(0),
2463 .hw.init = &(struct clk_init_data){
2464 .name = "camss_jpeg_dma_clk",
2465 .parent_hws = (const struct clk_hw*[]){
2466 &jpeg_dma_clk_src.clkr.hw
2469 .flags = CLK_SET_RATE_PARENT,
2470 .ops = &clk_branch2_ops,
2475 static struct clk_branch camss_jpeg_ahb_clk = {
2478 .enable_reg = 0x35b4,
2479 .enable_mask = BIT(0),
2480 .hw.init = &(struct clk_init_data){
2481 .name = "camss_jpeg_ahb_clk",
2482 .parent_hws = (const struct clk_hw*[]){
2483 &ahb_clk_src.clkr.hw
2486 .flags = CLK_SET_RATE_PARENT,
2487 .ops = &clk_branch2_ops,
2492 static struct clk_branch camss_jpeg_axi_clk = {
2495 .enable_reg = 0x35b8,
2496 .enable_mask = BIT(0),
2497 .hw.init = &(struct clk_init_data){
2498 .name = "camss_jpeg_axi_clk",
2499 .parent_hws = (const struct clk_hw*[]){
2500 &axi_clk_src.clkr.hw
2503 .flags = CLK_SET_RATE_PARENT,
2504 .ops = &clk_branch2_ops,
2509 static struct clk_branch camss_vfe_ahb_clk = {
2512 .enable_reg = 0x36b8,
2513 .enable_mask = BIT(0),
2514 .hw.init = &(struct clk_init_data){
2515 .name = "camss_vfe_ahb_clk",
2516 .parent_hws = (const struct clk_hw*[]){
2517 &ahb_clk_src.clkr.hw
2520 .flags = CLK_SET_RATE_PARENT,
2521 .ops = &clk_branch2_ops,
2526 static struct clk_branch camss_vfe_axi_clk = {
2529 .enable_reg = 0x36bc,
2530 .enable_mask = BIT(0),
2531 .hw.init = &(struct clk_init_data){
2532 .name = "camss_vfe_axi_clk",
2533 .parent_hws = (const struct clk_hw*[]){
2534 &axi_clk_src.clkr.hw
2537 .flags = CLK_SET_RATE_PARENT,
2538 .ops = &clk_branch2_ops,
2543 static struct clk_branch camss_vfe0_clk = {
2546 .enable_reg = 0x36a8,
2547 .enable_mask = BIT(0),
2548 .hw.init = &(struct clk_init_data){
2549 .name = "camss_vfe0_clk",
2550 .parent_hws = (const struct clk_hw*[]){
2551 &vfe0_clk_src.clkr.hw
2554 .flags = CLK_SET_RATE_PARENT,
2555 .ops = &clk_branch2_ops,
2560 static struct clk_branch camss_vfe0_stream_clk = {
2563 .enable_reg = 0x3720,
2564 .enable_mask = BIT(0),
2565 .hw.init = &(struct clk_init_data){
2566 .name = "camss_vfe0_stream_clk",
2567 .parent_hws = (const struct clk_hw*[]){
2568 &vfe0_clk_src.clkr.hw
2571 .flags = CLK_SET_RATE_PARENT,
2572 .ops = &clk_branch2_ops,
2577 static struct clk_branch camss_vfe0_ahb_clk = {
2580 .enable_reg = 0x3668,
2581 .enable_mask = BIT(0),
2582 .hw.init = &(struct clk_init_data){
2583 .name = "camss_vfe0_ahb_clk",
2584 .parent_hws = (const struct clk_hw*[]){
2585 &ahb_clk_src.clkr.hw
2588 .flags = CLK_SET_RATE_PARENT,
2589 .ops = &clk_branch2_ops,
2594 static struct clk_branch camss_vfe1_clk = {
2597 .enable_reg = 0x36ac,
2598 .enable_mask = BIT(0),
2599 .hw.init = &(struct clk_init_data){
2600 .name = "camss_vfe1_clk",
2601 .parent_hws = (const struct clk_hw*[]){
2602 &vfe1_clk_src.clkr.hw
2605 .flags = CLK_SET_RATE_PARENT,
2606 .ops = &clk_branch2_ops,
2611 static struct clk_branch camss_vfe1_stream_clk = {
2614 .enable_reg = 0x3724,
2615 .enable_mask = BIT(0),
2616 .hw.init = &(struct clk_init_data){
2617 .name = "camss_vfe1_stream_clk",
2618 .parent_hws = (const struct clk_hw*[]){
2619 &vfe1_clk_src.clkr.hw
2622 .flags = CLK_SET_RATE_PARENT,
2623 .ops = &clk_branch2_ops,
2628 static struct clk_branch camss_vfe1_ahb_clk = {
2631 .enable_reg = 0x3678,
2632 .enable_mask = BIT(0),
2633 .hw.init = &(struct clk_init_data){
2634 .name = "camss_vfe1_ahb_clk",
2635 .parent_hws = (const struct clk_hw*[]){
2636 &ahb_clk_src.clkr.hw
2639 .flags = CLK_SET_RATE_PARENT,
2640 .ops = &clk_branch2_ops,
2645 static struct clk_branch camss_csi_vfe0_clk = {
2648 .enable_reg = 0x3704,
2649 .enable_mask = BIT(0),
2650 .hw.init = &(struct clk_init_data){
2651 .name = "camss_csi_vfe0_clk",
2652 .parent_hws = (const struct clk_hw*[]){
2653 &vfe0_clk_src.clkr.hw
2656 .flags = CLK_SET_RATE_PARENT,
2657 .ops = &clk_branch2_ops,
2662 static struct clk_branch camss_csi_vfe1_clk = {
2665 .enable_reg = 0x3714,
2666 .enable_mask = BIT(0),
2667 .hw.init = &(struct clk_init_data){
2668 .name = "camss_csi_vfe1_clk",
2669 .parent_hws = (const struct clk_hw*[]){
2670 &vfe1_clk_src.clkr.hw
2673 .flags = CLK_SET_RATE_PARENT,
2674 .ops = &clk_branch2_ops,
2679 static struct clk_branch camss_cpp_vbif_ahb_clk = {
2682 .enable_reg = 0x36c8,
2683 .enable_mask = BIT(0),
2684 .hw.init = &(struct clk_init_data){
2685 .name = "camss_cpp_vbif_ahb_clk",
2686 .parent_hws = (const struct clk_hw*[]){
2687 &ahb_clk_src.clkr.hw
2690 .flags = CLK_SET_RATE_PARENT,
2691 .ops = &clk_branch2_ops,
2696 static struct clk_branch camss_cpp_axi_clk = {
2699 .enable_reg = 0x36c4,
2700 .enable_mask = BIT(0),
2701 .hw.init = &(struct clk_init_data){
2702 .name = "camss_cpp_axi_clk",
2703 .parent_hws = (const struct clk_hw*[]){
2704 &axi_clk_src.clkr.hw
2707 .flags = CLK_SET_RATE_PARENT,
2708 .ops = &clk_branch2_ops,
2713 static struct clk_branch camss_cpp_clk = {
2716 .enable_reg = 0x36b0,
2717 .enable_mask = BIT(0),
2718 .hw.init = &(struct clk_init_data){
2719 .name = "camss_cpp_clk",
2720 .parent_hws = (const struct clk_hw*[]){
2721 &cpp_clk_src.clkr.hw
2724 .flags = CLK_SET_RATE_PARENT,
2725 .ops = &clk_branch2_ops,
2730 static struct clk_branch camss_cpp_ahb_clk = {
2733 .enable_reg = 0x36b4,
2734 .enable_mask = BIT(0),
2735 .hw.init = &(struct clk_init_data){
2736 .name = "camss_cpp_ahb_clk",
2737 .parent_hws = (const struct clk_hw*[]){
2738 &ahb_clk_src.clkr.hw
2741 .flags = CLK_SET_RATE_PARENT,
2742 .ops = &clk_branch2_ops,
2747 static struct clk_branch camss_csi0_clk = {
2750 .enable_reg = 0x30b4,
2751 .enable_mask = BIT(0),
2752 .hw.init = &(struct clk_init_data){
2753 .name = "camss_csi0_clk",
2754 .parent_hws = (const struct clk_hw*[]){
2755 &csi0_clk_src.clkr.hw
2758 .flags = CLK_SET_RATE_PARENT,
2759 .ops = &clk_branch2_ops,
2764 static struct clk_branch camss_csi0_ahb_clk = {
2767 .enable_reg = 0x30bc,
2768 .enable_mask = BIT(0),
2769 .hw.init = &(struct clk_init_data){
2770 .name = "camss_csi0_ahb_clk",
2771 .parent_hws = (const struct clk_hw*[]){
2772 &ahb_clk_src.clkr.hw
2775 .flags = CLK_SET_RATE_PARENT,
2776 .ops = &clk_branch2_ops,
2781 static struct clk_branch camss_csi0phy_clk = {
2784 .enable_reg = 0x30c4,
2785 .enable_mask = BIT(0),
2786 .hw.init = &(struct clk_init_data){
2787 .name = "camss_csi0phy_clk",
2788 .parent_hws = (const struct clk_hw*[]){
2789 &csi0_clk_src.clkr.hw
2792 .flags = CLK_SET_RATE_PARENT,
2793 .ops = &clk_branch2_ops,
2798 static struct clk_branch camss_csi0rdi_clk = {
2801 .enable_reg = 0x30d4,
2802 .enable_mask = BIT(0),
2803 .hw.init = &(struct clk_init_data){
2804 .name = "camss_csi0rdi_clk",
2805 .parent_hws = (const struct clk_hw*[]){
2806 &csi0_clk_src.clkr.hw
2809 .flags = CLK_SET_RATE_PARENT,
2810 .ops = &clk_branch2_ops,
2815 static struct clk_branch camss_csi0pix_clk = {
2818 .enable_reg = 0x30e4,
2819 .enable_mask = BIT(0),
2820 .hw.init = &(struct clk_init_data){
2821 .name = "camss_csi0pix_clk",
2822 .parent_hws = (const struct clk_hw*[]){
2823 &csi0_clk_src.clkr.hw
2826 .flags = CLK_SET_RATE_PARENT,
2827 .ops = &clk_branch2_ops,
2832 static struct clk_branch camss_csi1_clk = {
2835 .enable_reg = 0x3124,
2836 .enable_mask = BIT(0),
2837 .hw.init = &(struct clk_init_data){
2838 .name = "camss_csi1_clk",
2839 .parent_hws = (const struct clk_hw*[]){
2840 &csi1_clk_src.clkr.hw
2843 .flags = CLK_SET_RATE_PARENT,
2844 .ops = &clk_branch2_ops,
2849 static struct clk_branch camss_csi1_ahb_clk = {
2852 .enable_reg = 0x3128,
2853 .enable_mask = BIT(0),
2854 .hw.init = &(struct clk_init_data){
2855 .name = "camss_csi1_ahb_clk",
2856 .parent_hws = (const struct clk_hw*[]){
2857 &ahb_clk_src.clkr.hw
2860 .flags = CLK_SET_RATE_PARENT,
2861 .ops = &clk_branch2_ops,
2866 static struct clk_branch camss_csi1phy_clk = {
2869 .enable_reg = 0x3134,
2870 .enable_mask = BIT(0),
2871 .hw.init = &(struct clk_init_data){
2872 .name = "camss_csi1phy_clk",
2873 .parent_hws = (const struct clk_hw*[]){
2874 &csi1_clk_src.clkr.hw
2877 .flags = CLK_SET_RATE_PARENT,
2878 .ops = &clk_branch2_ops,
2883 static struct clk_branch camss_csi1rdi_clk = {
2886 .enable_reg = 0x3144,
2887 .enable_mask = BIT(0),
2888 .hw.init = &(struct clk_init_data){
2889 .name = "camss_csi1rdi_clk",
2890 .parent_hws = (const struct clk_hw*[]){
2891 &csi1_clk_src.clkr.hw
2894 .flags = CLK_SET_RATE_PARENT,
2895 .ops = &clk_branch2_ops,
2900 static struct clk_branch camss_csi1pix_clk = {
2903 .enable_reg = 0x3154,
2904 .enable_mask = BIT(0),
2905 .hw.init = &(struct clk_init_data){
2906 .name = "camss_csi1pix_clk",
2907 .parent_hws = (const struct clk_hw*[]){
2908 &csi1_clk_src.clkr.hw
2911 .flags = CLK_SET_RATE_PARENT,
2912 .ops = &clk_branch2_ops,
2917 static struct clk_branch camss_csi2_clk = {
2920 .enable_reg = 0x3184,
2921 .enable_mask = BIT(0),
2922 .hw.init = &(struct clk_init_data){
2923 .name = "camss_csi2_clk",
2924 .parent_hws = (const struct clk_hw*[]){
2925 &csi2_clk_src.clkr.hw
2928 .flags = CLK_SET_RATE_PARENT,
2929 .ops = &clk_branch2_ops,
2934 static struct clk_branch camss_csi2_ahb_clk = {
2937 .enable_reg = 0x3188,
2938 .enable_mask = BIT(0),
2939 .hw.init = &(struct clk_init_data){
2940 .name = "camss_csi2_ahb_clk",
2941 .parent_hws = (const struct clk_hw*[]){
2942 &ahb_clk_src.clkr.hw
2945 .flags = CLK_SET_RATE_PARENT,
2946 .ops = &clk_branch2_ops,
2951 static struct clk_branch camss_csi2phy_clk = {
2954 .enable_reg = 0x3194,
2955 .enable_mask = BIT(0),
2956 .hw.init = &(struct clk_init_data){
2957 .name = "camss_csi2phy_clk",
2958 .parent_hws = (const struct clk_hw*[]){
2959 &csi2_clk_src.clkr.hw
2962 .flags = CLK_SET_RATE_PARENT,
2963 .ops = &clk_branch2_ops,
2968 static struct clk_branch camss_csi2rdi_clk = {
2971 .enable_reg = 0x31a4,
2972 .enable_mask = BIT(0),
2973 .hw.init = &(struct clk_init_data){
2974 .name = "camss_csi2rdi_clk",
2975 .parent_hws = (const struct clk_hw*[]){
2976 &csi2_clk_src.clkr.hw
2979 .flags = CLK_SET_RATE_PARENT,
2980 .ops = &clk_branch2_ops,
2985 static struct clk_branch camss_csi2pix_clk = {
2988 .enable_reg = 0x31b4,
2989 .enable_mask = BIT(0),
2990 .hw.init = &(struct clk_init_data){
2991 .name = "camss_csi2pix_clk",
2992 .parent_hws = (const struct clk_hw*[]){
2993 &csi2_clk_src.clkr.hw
2996 .flags = CLK_SET_RATE_PARENT,
2997 .ops = &clk_branch2_ops,
3002 static struct clk_branch camss_csi3_clk = {
3005 .enable_reg = 0x31e4,
3006 .enable_mask = BIT(0),
3007 .hw.init = &(struct clk_init_data){
3008 .name = "camss_csi3_clk",
3009 .parent_hws = (const struct clk_hw*[]){
3010 &csi3_clk_src.clkr.hw
3013 .flags = CLK_SET_RATE_PARENT,
3014 .ops = &clk_branch2_ops,
3019 static struct clk_branch camss_csi3_ahb_clk = {
3022 .enable_reg = 0x31e8,
3023 .enable_mask = BIT(0),
3024 .hw.init = &(struct clk_init_data){
3025 .name = "camss_csi3_ahb_clk",
3026 .parent_hws = (const struct clk_hw*[]){
3027 &ahb_clk_src.clkr.hw
3030 .flags = CLK_SET_RATE_PARENT,
3031 .ops = &clk_branch2_ops,
3036 static struct clk_branch camss_csi3phy_clk = {
3039 .enable_reg = 0x31f4,
3040 .enable_mask = BIT(0),
3041 .hw.init = &(struct clk_init_data){
3042 .name = "camss_csi3phy_clk",
3043 .parent_hws = (const struct clk_hw*[]){
3044 &csi3_clk_src.clkr.hw
3047 .flags = CLK_SET_RATE_PARENT,
3048 .ops = &clk_branch2_ops,
3053 static struct clk_branch camss_csi3rdi_clk = {
3056 .enable_reg = 0x3204,
3057 .enable_mask = BIT(0),
3058 .hw.init = &(struct clk_init_data){
3059 .name = "camss_csi3rdi_clk",
3060 .parent_hws = (const struct clk_hw*[]){
3061 &csi3_clk_src.clkr.hw
3064 .flags = CLK_SET_RATE_PARENT,
3065 .ops = &clk_branch2_ops,
3070 static struct clk_branch camss_csi3pix_clk = {
3073 .enable_reg = 0x3214,
3074 .enable_mask = BIT(0),
3075 .hw.init = &(struct clk_init_data){
3076 .name = "camss_csi3pix_clk",
3077 .parent_hws = (const struct clk_hw*[]){
3078 &csi3_clk_src.clkr.hw
3081 .flags = CLK_SET_RATE_PARENT,
3082 .ops = &clk_branch2_ops,
3087 static struct clk_branch camss_ispif_ahb_clk = {
3090 .enable_reg = 0x3224,
3091 .enable_mask = BIT(0),
3092 .hw.init = &(struct clk_init_data){
3093 .name = "camss_ispif_ahb_clk",
3094 .parent_hws = (const struct clk_hw*[]){
3095 &ahb_clk_src.clkr.hw
3098 .flags = CLK_SET_RATE_PARENT,
3099 .ops = &clk_branch2_ops,
3104 static struct clk_branch fd_core_clk = {
3107 .enable_reg = 0x3b68,
3108 .enable_mask = BIT(0),
3109 .hw.init = &(struct clk_init_data){
3110 .name = "fd_core_clk",
3111 .parent_hws = (const struct clk_hw*[]){
3112 &fd_core_clk_src.clkr.hw
3115 .flags = CLK_SET_RATE_PARENT,
3116 .ops = &clk_branch2_ops,
3121 static struct clk_branch fd_core_uar_clk = {
3124 .enable_reg = 0x3b6c,
3125 .enable_mask = BIT(0),
3126 .hw.init = &(struct clk_init_data){
3127 .name = "fd_core_uar_clk",
3128 .parent_hws = (const struct clk_hw*[]){
3129 &fd_core_clk_src.clkr.hw
3132 .flags = CLK_SET_RATE_PARENT,
3133 .ops = &clk_branch2_ops,
3138 static struct clk_branch fd_ahb_clk = {
3139 .halt_reg = 0x3ba74,
3141 .enable_reg = 0x3ba74,
3142 .enable_mask = BIT(0),
3143 .hw.init = &(struct clk_init_data){
3144 .name = "fd_ahb_clk",
3145 .parent_hws = (const struct clk_hw*[]){
3146 &ahb_clk_src.clkr.hw
3149 .flags = CLK_SET_RATE_PARENT,
3150 .ops = &clk_branch2_ops,
3155 static struct clk_hw *mmcc_msm8996_hws[] = {
3159 static struct gdsc mmagic_bimc_gdsc = {
3162 .name = "mmagic_bimc",
3164 .pwrsts = PWRSTS_OFF_ON,
3168 static struct gdsc mmagic_video_gdsc = {
3170 .gds_hw_ctrl = 0x120c,
3172 .name = "mmagic_video",
3174 .pwrsts = PWRSTS_OFF_ON,
3175 .flags = VOTABLE | ALWAYS_ON,
3178 static struct gdsc mmagic_mdss_gdsc = {
3180 .gds_hw_ctrl = 0x2480,
3182 .name = "mmagic_mdss",
3184 .pwrsts = PWRSTS_OFF_ON,
3185 .flags = VOTABLE | ALWAYS_ON,
3188 static struct gdsc mmagic_camss_gdsc = {
3190 .gds_hw_ctrl = 0x3c50,
3192 .name = "mmagic_camss",
3194 .pwrsts = PWRSTS_OFF_ON,
3195 .flags = VOTABLE | ALWAYS_ON,
3198 static struct gdsc venus_gdsc = {
3200 .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
3205 .parent = &mmagic_video_gdsc.pd,
3206 .pwrsts = PWRSTS_OFF_ON,
3209 static struct gdsc venus_core0_gdsc = {
3211 .cxcs = (unsigned int []){ 0x1048 },
3214 .name = "venus_core0",
3216 .parent = &venus_gdsc.pd,
3217 .pwrsts = PWRSTS_OFF_ON,
3221 static struct gdsc venus_core1_gdsc = {
3223 .cxcs = (unsigned int []){ 0x104c },
3226 .name = "venus_core1",
3228 .parent = &venus_gdsc.pd,
3229 .pwrsts = PWRSTS_OFF_ON,
3233 static struct gdsc camss_gdsc = {
3235 .cxcs = (unsigned int []){ 0x36bc, 0x36c4 },
3240 .parent = &mmagic_camss_gdsc.pd,
3241 .pwrsts = PWRSTS_OFF_ON,
3244 static struct gdsc vfe0_gdsc = {
3246 .cxcs = (unsigned int []){ 0x36a8 },
3251 .parent = &camss_gdsc.pd,
3252 .pwrsts = PWRSTS_OFF_ON,
3255 static struct gdsc vfe1_gdsc = {
3257 .cxcs = (unsigned int []){ 0x36ac },
3262 .parent = &camss_gdsc.pd,
3263 .pwrsts = PWRSTS_OFF_ON,
3266 static struct gdsc jpeg_gdsc = {
3268 .cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 },
3273 .parent = &camss_gdsc.pd,
3274 .pwrsts = PWRSTS_OFF_ON,
3277 static struct gdsc cpp_gdsc = {
3279 .cxcs = (unsigned int []){ 0x36b0 },
3284 .parent = &camss_gdsc.pd,
3285 .pwrsts = PWRSTS_OFF_ON,
3288 static struct gdsc fd_gdsc = {
3290 .cxcs = (unsigned int []){ 0x3b68, 0x3b6c },
3295 .parent = &camss_gdsc.pd,
3296 .pwrsts = PWRSTS_OFF_ON,
3299 static struct gdsc mdss_gdsc = {
3301 .cxcs = (unsigned int []){ 0x2310, 0x231c },
3306 .parent = &mmagic_mdss_gdsc.pd,
3307 .pwrsts = PWRSTS_OFF_ON,
3310 static struct gdsc gpu_gdsc = {
3312 .gds_hw_ctrl = 0x4038,
3316 .pwrsts = PWRSTS_OFF_ON,
3320 static struct gdsc gpu_gx_gdsc = {
3322 .clamp_io_ctrl = 0x4300,
3323 .cxcs = (unsigned int []){ 0x4028 },
3328 .pwrsts = PWRSTS_OFF_ON,
3329 .parent = &gpu_gdsc.pd,
3331 .supply = "vdd-gfx",
3334 static struct clk_regmap *mmcc_msm8996_clocks[] = {
3335 [MMPLL0_EARLY] = &mmpll0_early.clkr,
3336 [MMPLL0_PLL] = &mmpll0.clkr,
3337 [MMPLL1_EARLY] = &mmpll1_early.clkr,
3338 [MMPLL1_PLL] = &mmpll1.clkr,
3339 [MMPLL2_EARLY] = &mmpll2_early.clkr,
3340 [MMPLL2_PLL] = &mmpll2.clkr,
3341 [MMPLL3_EARLY] = &mmpll3_early.clkr,
3342 [MMPLL3_PLL] = &mmpll3.clkr,
3343 [MMPLL4_EARLY] = &mmpll4_early.clkr,
3344 [MMPLL4_PLL] = &mmpll4.clkr,
3345 [MMPLL5_EARLY] = &mmpll5_early.clkr,
3346 [MMPLL5_PLL] = &mmpll5.clkr,
3347 [MMPLL8_EARLY] = &mmpll8_early.clkr,
3348 [MMPLL8_PLL] = &mmpll8.clkr,
3349 [MMPLL9_EARLY] = &mmpll9_early.clkr,
3350 [MMPLL9_PLL] = &mmpll9.clkr,
3351 [AHB_CLK_SRC] = &ahb_clk_src.clkr,
3352 [AXI_CLK_SRC] = &axi_clk_src.clkr,
3353 [MAXI_CLK_SRC] = &maxi_clk_src.clkr,
3354 [GFX3D_CLK_SRC] = &gfx3d_clk_src.rcg.clkr,
3355 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
3356 [ISENSE_CLK_SRC] = &isense_clk_src.clkr,
3357 [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
3358 [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
3359 [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr,
3360 [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr,
3361 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3362 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3363 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3364 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
3365 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3366 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
3367 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3368 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3369 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3370 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3371 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3372 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3373 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3374 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3375 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
3376 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
3377 [CCI_CLK_SRC] = &cci_clk_src.clkr,
3378 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3379 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3380 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
3381 [CSIPHY0_3P_CLK_SRC] = &csiphy0_3p_clk_src.clkr,
3382 [CSIPHY1_3P_CLK_SRC] = &csiphy1_3p_clk_src.clkr,
3383 [CSIPHY2_3P_CLK_SRC] = &csiphy2_3p_clk_src.clkr,
3384 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3385 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
3386 [JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr,
3387 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3388 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3389 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3390 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3391 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3392 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3393 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
3394 [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
3395 [MMSS_MMAGIC_AHB_CLK] = &mmss_mmagic_ahb_clk.clkr,
3396 [MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr,
3397 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
3398 [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr,
3399 [MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr,
3400 [MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr,
3401 [MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr,
3402 [SMMU_VFE_AHB_CLK] = &smmu_vfe_ahb_clk.clkr,
3403 [SMMU_VFE_AXI_CLK] = &smmu_vfe_axi_clk.clkr,
3404 [SMMU_CPP_AHB_CLK] = &smmu_cpp_ahb_clk.clkr,
3405 [SMMU_CPP_AXI_CLK] = &smmu_cpp_axi_clk.clkr,
3406 [SMMU_JPEG_AHB_CLK] = &smmu_jpeg_ahb_clk.clkr,
3407 [SMMU_JPEG_AXI_CLK] = &smmu_jpeg_axi_clk.clkr,
3408 [MMAGIC_MDSS_AXI_CLK] = &mmagic_mdss_axi_clk.clkr,
3409 [MMAGIC_MDSS_NOC_CFG_AHB_CLK] = &mmagic_mdss_noc_cfg_ahb_clk.clkr,
3410 [SMMU_ROT_AHB_CLK] = &smmu_rot_ahb_clk.clkr,
3411 [SMMU_ROT_AXI_CLK] = &smmu_rot_axi_clk.clkr,
3412 [SMMU_MDP_AHB_CLK] = &smmu_mdp_ahb_clk.clkr,
3413 [SMMU_MDP_AXI_CLK] = &smmu_mdp_axi_clk.clkr,
3414 [MMAGIC_VIDEO_AXI_CLK] = &mmagic_video_axi_clk.clkr,
3415 [MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr,
3416 [SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr,
3417 [SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr,
3418 [MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr,
3419 [GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr,
3420 [GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr,
3421 [GPU_AHB_CLK] = &gpu_ahb_clk.clkr,
3422 [GPU_AON_ISENSE_CLK] = &gpu_aon_isense_clk.clkr,
3423 [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr,
3424 [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr,
3425 [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
3426 [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
3427 [VIDEO_CORE_CLK] = &video_core_clk.clkr,
3428 [VIDEO_AXI_CLK] = &video_axi_clk.clkr,
3429 [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr,
3430 [VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
3431 [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
3432 [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr,
3433 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
3434 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
3435 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
3436 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
3437 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
3438 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
3439 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
3440 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
3441 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
3442 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
3443 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
3444 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
3445 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
3446 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
3447 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
3448 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
3449 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
3450 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
3451 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
3452 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
3453 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
3454 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
3455 [CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
3456 [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
3457 [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
3458 [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
3459 [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
3460 [CAMSS_CSIPHY0_3P_CLK] = &camss_csiphy0_3p_clk.clkr,
3461 [CAMSS_CSIPHY1_3P_CLK] = &camss_csiphy1_3p_clk.clkr,
3462 [CAMSS_CSIPHY2_3P_CLK] = &camss_csiphy2_3p_clk.clkr,
3463 [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
3464 [CAMSS_JPEG2_CLK] = &camss_jpeg2_clk.clkr,
3465 [CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr,
3466 [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
3467 [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
3468 [CAMSS_VFE_AHB_CLK] = &camss_vfe_ahb_clk.clkr,
3469 [CAMSS_VFE_AXI_CLK] = &camss_vfe_axi_clk.clkr,
3470 [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
3471 [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
3472 [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
3473 [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
3474 [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
3475 [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
3476 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
3477 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
3478 [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
3479 [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
3480 [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
3481 [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
3482 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
3483 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
3484 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
3485 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
3486 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
3487 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
3488 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
3489 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
3490 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
3491 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
3492 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
3493 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
3494 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
3495 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
3496 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
3497 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
3498 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
3499 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
3500 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
3501 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
3502 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
3503 [FD_CORE_CLK] = &fd_core_clk.clkr,
3504 [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
3505 [FD_AHB_CLK] = &fd_ahb_clk.clkr,
3508 static struct gdsc *mmcc_msm8996_gdscs[] = {
3509 [MMAGIC_BIMC_GDSC] = &mmagic_bimc_gdsc,
3510 [MMAGIC_VIDEO_GDSC] = &mmagic_video_gdsc,
3511 [MMAGIC_MDSS_GDSC] = &mmagic_mdss_gdsc,
3512 [MMAGIC_CAMSS_GDSC] = &mmagic_camss_gdsc,
3513 [VENUS_GDSC] = &venus_gdsc,
3514 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
3515 [VENUS_CORE1_GDSC] = &venus_core1_gdsc,
3516 [CAMSS_GDSC] = &camss_gdsc,
3517 [VFE0_GDSC] = &vfe0_gdsc,
3518 [VFE1_GDSC] = &vfe1_gdsc,
3519 [JPEG_GDSC] = &jpeg_gdsc,
3520 [CPP_GDSC] = &cpp_gdsc,
3521 [FD_GDSC] = &fd_gdsc,
3522 [MDSS_GDSC] = &mdss_gdsc,
3523 [GPU_GDSC] = &gpu_gdsc,
3524 [GPU_GX_GDSC] = &gpu_gx_gdsc,
3527 static const struct qcom_reset_map mmcc_msm8996_resets[] = {
3528 [MMAGICAHB_BCR] = { 0x5020 },
3529 [MMAGIC_CFG_BCR] = { 0x5050 },
3530 [MISC_BCR] = { 0x5010 },
3531 [BTO_BCR] = { 0x5030 },
3532 [MMAGICAXI_BCR] = { 0x5060 },
3533 [MMAGICMAXI_BCR] = { 0x5070 },
3534 [DSA_BCR] = { 0x50a0 },
3535 [MMAGIC_CAMSS_BCR] = { 0x3c40 },
3536 [THROTTLE_CAMSS_BCR] = { 0x3c30 },
3537 [SMMU_VFE_BCR] = { 0x3c00 },
3538 [SMMU_CPP_BCR] = { 0x3c10 },
3539 [SMMU_JPEG_BCR] = { 0x3c20 },
3540 [MMAGIC_MDSS_BCR] = { 0x2470 },
3541 [THROTTLE_MDSS_BCR] = { 0x2460 },
3542 [SMMU_ROT_BCR] = { 0x2440 },
3543 [SMMU_MDP_BCR] = { 0x2450 },
3544 [MMAGIC_VIDEO_BCR] = { 0x1190 },
3545 [THROTTLE_VIDEO_BCR] = { 0x1180 },
3546 [SMMU_VIDEO_BCR] = { 0x1170 },
3547 [MMAGIC_BIMC_BCR] = { 0x5290 },
3548 [GPU_GX_BCR] = { 0x4020 },
3549 [GPU_BCR] = { 0x4030 },
3550 [GPU_AON_BCR] = { 0x4040 },
3551 [VMEM_BCR] = { 0x1200 },
3552 [MMSS_RBCPR_BCR] = { 0x4080 },
3553 [VIDEO_BCR] = { 0x1020 },
3554 [MDSS_BCR] = { 0x2300 },
3555 [CAMSS_TOP_BCR] = { 0x3480 },
3556 [CAMSS_AHB_BCR] = { 0x3488 },
3557 [CAMSS_MICRO_BCR] = { 0x3490 },
3558 [CAMSS_CCI_BCR] = { 0x3340 },
3559 [CAMSS_PHY0_BCR] = { 0x3020 },
3560 [CAMSS_PHY1_BCR] = { 0x3050 },
3561 [CAMSS_PHY2_BCR] = { 0x3080 },
3562 [CAMSS_CSIPHY0_3P_BCR] = { 0x3230 },
3563 [CAMSS_CSIPHY1_3P_BCR] = { 0x3250 },
3564 [CAMSS_CSIPHY2_3P_BCR] = { 0x3270 },
3565 [CAMSS_JPEG_BCR] = { 0x35a0 },
3566 [CAMSS_VFE_BCR] = { 0x36a0 },
3567 [CAMSS_VFE0_BCR] = { 0x3660 },
3568 [CAMSS_VFE1_BCR] = { 0x3670 },
3569 [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
3570 [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
3571 [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
3572 [CAMSS_CPP_BCR] = { 0x36d0 },
3573 [CAMSS_CSI0_BCR] = { 0x30b0 },
3574 [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
3575 [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
3576 [CAMSS_CSI1_BCR] = { 0x3120 },
3577 [CAMSS_CSI1RDI_BCR] = { 0x3140 },
3578 [CAMSS_CSI1PIX_BCR] = { 0x3150 },
3579 [CAMSS_CSI2_BCR] = { 0x3180 },
3580 [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
3581 [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
3582 [CAMSS_CSI3_BCR] = { 0x31e0 },
3583 [CAMSS_CSI3RDI_BCR] = { 0x3200 },
3584 [CAMSS_CSI3PIX_BCR] = { 0x3210 },
3585 [CAMSS_ISPIF_BCR] = { 0x3220 },
3586 [FD_BCR] = { 0x3b60 },
3587 [MMSS_SPDM_RM_BCR] = { 0x300 },
3590 static const struct regmap_config mmcc_msm8996_regmap_config = {
3594 .max_register = 0xb008,
3598 static const struct qcom_cc_desc mmcc_msm8996_desc = {
3599 .config = &mmcc_msm8996_regmap_config,
3600 .clks = mmcc_msm8996_clocks,
3601 .num_clks = ARRAY_SIZE(mmcc_msm8996_clocks),
3602 .resets = mmcc_msm8996_resets,
3603 .num_resets = ARRAY_SIZE(mmcc_msm8996_resets),
3604 .gdscs = mmcc_msm8996_gdscs,
3605 .num_gdscs = ARRAY_SIZE(mmcc_msm8996_gdscs),
3606 .clk_hws = mmcc_msm8996_hws,
3607 .num_clk_hws = ARRAY_SIZE(mmcc_msm8996_hws),
3610 static const struct of_device_id mmcc_msm8996_match_table[] = {
3611 { .compatible = "qcom,mmcc-msm8996" },
3614 MODULE_DEVICE_TABLE(of, mmcc_msm8996_match_table);
3616 static int mmcc_msm8996_probe(struct platform_device *pdev)
3618 struct regmap *regmap;
3620 regmap = qcom_cc_map(pdev, &mmcc_msm8996_desc);
3622 return PTR_ERR(regmap);
3624 /* Disable the AHB DCD */
3625 regmap_update_bits(regmap, 0x50d8, BIT(31), 0);
3626 /* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */
3627 regmap_update_bits(regmap, 0x5054, BIT(15), 0);
3629 return qcom_cc_really_probe(&pdev->dev, &mmcc_msm8996_desc, regmap);
3632 static struct platform_driver mmcc_msm8996_driver = {
3633 .probe = mmcc_msm8996_probe,
3635 .name = "mmcc-msm8996",
3636 .of_match_table = mmcc_msm8996_match_table,
3639 module_platform_driver(mmcc_msm8996_driver);
3641 MODULE_DESCRIPTION("QCOM MMCC MSM8996 Driver");
3642 MODULE_LICENSE("GPL v2");
3643 MODULE_ALIAS("platform:mmcc-msm8996");