1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
16 #include <linux/clk.h>
18 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
21 #include "clk-regmap.h"
22 #include "clk-regmap-divider.h"
23 #include "clk-alpha-pll.h"
25 #include "clk-branch.h"
48 static const struct parent_map mmss_xo_hdmi_map[] = {
53 static const char * const mmss_xo_hdmi[] = {
58 static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
64 static const char * const mmss_xo_dsi0pll_dsi1pll[] = {
70 static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
76 static const char * const mmss_xo_gpll0_gpll0_div[] = {
82 static const struct parent_map mmss_xo_dsibyte_map[] = {
84 { P_DSI0PLL_BYTE, 1 },
88 static const char * const mmss_xo_dsibyte[] = {
94 static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
101 static const char * const mmss_xo_mmpll0_gpll0_gpll0_div[] = {
108 static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
116 static const char * const mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
124 static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = {
132 static const char * const mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = {
140 static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
148 static const char * const mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
156 static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = {
164 static const char * const mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = {
172 static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = {
181 static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = {
190 static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = {
200 static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = {
210 static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = {
220 static const char * const mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = {
230 static struct clk_fixed_factor gpll0_div = {
233 .hw.init = &(struct clk_init_data){
235 .parent_names = (const char *[]){ "gpll0" },
237 .ops = &clk_fixed_factor_ops,
241 static struct pll_vco mmpll_p_vco[] = {
242 { 250000000, 500000000, 3 },
243 { 500000000, 1000000000, 2 },
244 { 1000000000, 1500000000, 1 },
245 { 1500000000, 2000000000, 0 },
248 static struct pll_vco mmpll_gfx_vco[] = {
249 { 400000000, 1000000000, 2 },
250 { 1000000000, 1500000000, 1 },
251 { 1500000000, 2000000000, 0 },
254 static struct pll_vco mmpll_t_vco[] = {
255 { 500000000, 1500000000, 0 },
258 static struct clk_alpha_pll mmpll0_early = {
260 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
261 .vco_table = mmpll_p_vco,
262 .num_vco = ARRAY_SIZE(mmpll_p_vco),
265 .enable_mask = BIT(0),
266 .hw.init = &(struct clk_init_data){
267 .name = "mmpll0_early",
268 .parent_names = (const char *[]){ "xo" },
270 .ops = &clk_alpha_pll_ops,
275 static struct clk_alpha_pll_postdiv mmpll0 = {
277 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
279 .clkr.hw.init = &(struct clk_init_data){
281 .parent_names = (const char *[]){ "mmpll0_early" },
283 .ops = &clk_alpha_pll_postdiv_ops,
284 .flags = CLK_SET_RATE_PARENT,
288 static struct clk_alpha_pll mmpll1_early = {
290 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
291 .vco_table = mmpll_p_vco,
292 .num_vco = ARRAY_SIZE(mmpll_p_vco),
295 .enable_mask = BIT(1),
296 .hw.init = &(struct clk_init_data){
297 .name = "mmpll1_early",
298 .parent_names = (const char *[]){ "xo" },
300 .ops = &clk_alpha_pll_ops,
305 static struct clk_alpha_pll_postdiv mmpll1 = {
307 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
309 .clkr.hw.init = &(struct clk_init_data){
311 .parent_names = (const char *[]){ "mmpll1_early" },
313 .ops = &clk_alpha_pll_postdiv_ops,
314 .flags = CLK_SET_RATE_PARENT,
318 static struct clk_alpha_pll mmpll2_early = {
320 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
321 .vco_table = mmpll_gfx_vco,
322 .num_vco = ARRAY_SIZE(mmpll_gfx_vco),
323 .clkr.hw.init = &(struct clk_init_data){
324 .name = "mmpll2_early",
325 .parent_names = (const char *[]){ "xo" },
327 .ops = &clk_alpha_pll_ops,
331 static struct clk_alpha_pll_postdiv mmpll2 = {
333 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
335 .clkr.hw.init = &(struct clk_init_data){
337 .parent_names = (const char *[]){ "mmpll2_early" },
339 .ops = &clk_alpha_pll_postdiv_ops,
340 .flags = CLK_SET_RATE_PARENT,
344 static struct clk_alpha_pll mmpll3_early = {
346 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
347 .vco_table = mmpll_p_vco,
348 .num_vco = ARRAY_SIZE(mmpll_p_vco),
349 .clkr.hw.init = &(struct clk_init_data){
350 .name = "mmpll3_early",
351 .parent_names = (const char *[]){ "xo" },
353 .ops = &clk_alpha_pll_ops,
357 static struct clk_alpha_pll_postdiv mmpll3 = {
359 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
361 .clkr.hw.init = &(struct clk_init_data){
363 .parent_names = (const char *[]){ "mmpll3_early" },
365 .ops = &clk_alpha_pll_postdiv_ops,
366 .flags = CLK_SET_RATE_PARENT,
370 static struct clk_alpha_pll mmpll4_early = {
372 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
373 .vco_table = mmpll_t_vco,
374 .num_vco = ARRAY_SIZE(mmpll_t_vco),
375 .clkr.hw.init = &(struct clk_init_data){
376 .name = "mmpll4_early",
377 .parent_names = (const char *[]){ "xo" },
379 .ops = &clk_alpha_pll_ops,
383 static struct clk_alpha_pll_postdiv mmpll4 = {
385 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
387 .clkr.hw.init = &(struct clk_init_data){
389 .parent_names = (const char *[]){ "mmpll4_early" },
391 .ops = &clk_alpha_pll_postdiv_ops,
392 .flags = CLK_SET_RATE_PARENT,
396 static struct clk_alpha_pll mmpll5_early = {
398 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
399 .vco_table = mmpll_p_vco,
400 .num_vco = ARRAY_SIZE(mmpll_p_vco),
401 .clkr.hw.init = &(struct clk_init_data){
402 .name = "mmpll5_early",
403 .parent_names = (const char *[]){ "xo" },
405 .ops = &clk_alpha_pll_ops,
409 static struct clk_alpha_pll_postdiv mmpll5 = {
411 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
413 .clkr.hw.init = &(struct clk_init_data){
415 .parent_names = (const char *[]){ "mmpll5_early" },
417 .ops = &clk_alpha_pll_postdiv_ops,
418 .flags = CLK_SET_RATE_PARENT,
422 static struct clk_alpha_pll mmpll8_early = {
424 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
425 .vco_table = mmpll_gfx_vco,
426 .num_vco = ARRAY_SIZE(mmpll_gfx_vco),
427 .clkr.hw.init = &(struct clk_init_data){
428 .name = "mmpll8_early",
429 .parent_names = (const char *[]){ "xo" },
431 .ops = &clk_alpha_pll_ops,
435 static struct clk_alpha_pll_postdiv mmpll8 = {
437 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
439 .clkr.hw.init = &(struct clk_init_data){
441 .parent_names = (const char *[]){ "mmpll8_early" },
443 .ops = &clk_alpha_pll_postdiv_ops,
444 .flags = CLK_SET_RATE_PARENT,
448 static struct clk_alpha_pll mmpll9_early = {
450 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
451 .vco_table = mmpll_t_vco,
452 .num_vco = ARRAY_SIZE(mmpll_t_vco),
453 .clkr.hw.init = &(struct clk_init_data){
454 .name = "mmpll9_early",
455 .parent_names = (const char *[]){ "xo" },
457 .ops = &clk_alpha_pll_ops,
461 static struct clk_alpha_pll_postdiv mmpll9 = {
463 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
465 .clkr.hw.init = &(struct clk_init_data){
467 .parent_names = (const char *[]){ "mmpll9_early" },
469 .ops = &clk_alpha_pll_postdiv_ops,
470 .flags = CLK_SET_RATE_PARENT,
474 static const struct freq_tbl ftbl_ahb_clk_src[] = {
475 F(19200000, P_XO, 1, 0, 0),
476 F(40000000, P_GPLL0_DIV, 7.5, 0, 0),
477 F(80000000, P_MMPLL0, 10, 0, 0),
481 static struct clk_rcg2 ahb_clk_src = {
484 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
485 .freq_tbl = ftbl_ahb_clk_src,
486 .clkr.hw.init = &(struct clk_init_data){
487 .name = "ahb_clk_src",
488 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
490 .ops = &clk_rcg2_ops,
494 static const struct freq_tbl ftbl_axi_clk_src[] = {
495 F(19200000, P_XO, 1, 0, 0),
496 F(75000000, P_GPLL0_DIV, 4, 0, 0),
497 F(100000000, P_GPLL0, 6, 0, 0),
498 F(171430000, P_GPLL0, 3.5, 0, 0),
499 F(200000000, P_GPLL0, 3, 0, 0),
500 F(320000000, P_MMPLL0, 2.5, 0, 0),
501 F(400000000, P_MMPLL0, 2, 0, 0),
505 static struct clk_rcg2 axi_clk_src = {
508 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
509 .freq_tbl = ftbl_axi_clk_src,
510 .clkr.hw.init = &(struct clk_init_data){
511 .name = "axi_clk_src",
512 .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
514 .ops = &clk_rcg2_ops,
518 static struct clk_rcg2 maxi_clk_src = {
521 .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
522 .freq_tbl = ftbl_axi_clk_src,
523 .clkr.hw.init = &(struct clk_init_data){
524 .name = "maxi_clk_src",
525 .parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
527 .ops = &clk_rcg2_ops,
531 static struct clk_rcg2_gfx3d gfx3d_clk_src = {
535 .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map,
536 .clkr.hw.init = &(struct clk_init_data){
537 .name = "gfx3d_clk_src",
538 .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0,
540 .ops = &clk_gfx3d_ops,
541 .flags = CLK_SET_RATE_PARENT,
544 .hws = (struct clk_hw*[]) {
551 static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
552 F(19200000, P_XO, 1, 0, 0),
556 static struct clk_rcg2 rbbmtimer_clk_src = {
559 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
560 .freq_tbl = ftbl_rbbmtimer_clk_src,
561 .clkr.hw.init = &(struct clk_init_data){
562 .name = "rbbmtimer_clk_src",
563 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
565 .ops = &clk_rcg2_ops,
569 static struct clk_rcg2 isense_clk_src = {
572 .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map,
573 .clkr.hw.init = &(struct clk_init_data){
574 .name = "isense_clk_src",
575 .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div,
577 .ops = &clk_rcg2_ops,
581 static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
582 F(19200000, P_XO, 1, 0, 0),
583 F(50000000, P_GPLL0, 12, 0, 0),
587 static struct clk_rcg2 rbcpr_clk_src = {
590 .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
591 .freq_tbl = ftbl_rbcpr_clk_src,
592 .clkr.hw.init = &(struct clk_init_data){
593 .name = "rbcpr_clk_src",
594 .parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
596 .ops = &clk_rcg2_ops,
600 static const struct freq_tbl ftbl_video_core_clk_src[] = {
601 F(75000000, P_GPLL0_DIV, 4, 0, 0),
602 F(150000000, P_GPLL0, 4, 0, 0),
603 F(346666667, P_MMPLL3, 3, 0, 0),
604 F(520000000, P_MMPLL3, 2, 0, 0),
608 static struct clk_rcg2 video_core_clk_src = {
612 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
613 .freq_tbl = ftbl_video_core_clk_src,
614 .clkr.hw.init = &(struct clk_init_data){
615 .name = "video_core_clk_src",
616 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
618 .ops = &clk_rcg2_ops,
622 static struct clk_rcg2 video_subcore0_clk_src = {
626 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
627 .freq_tbl = ftbl_video_core_clk_src,
628 .clkr.hw.init = &(struct clk_init_data){
629 .name = "video_subcore0_clk_src",
630 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
632 .ops = &clk_rcg2_ops,
636 static struct clk_rcg2 video_subcore1_clk_src = {
640 .parent_map = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map,
641 .freq_tbl = ftbl_video_core_clk_src,
642 .clkr.hw.init = &(struct clk_init_data){
643 .name = "video_subcore1_clk_src",
644 .parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
646 .ops = &clk_rcg2_ops,
650 static struct clk_rcg2 pclk0_clk_src = {
654 .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
655 .clkr.hw.init = &(struct clk_init_data){
656 .name = "pclk0_clk_src",
657 .parent_names = mmss_xo_dsi0pll_dsi1pll,
659 .ops = &clk_pixel_ops,
660 .flags = CLK_SET_RATE_PARENT,
664 static struct clk_rcg2 pclk1_clk_src = {
668 .parent_map = mmss_xo_dsi0pll_dsi1pll_map,
669 .clkr.hw.init = &(struct clk_init_data){
670 .name = "pclk1_clk_src",
671 .parent_names = mmss_xo_dsi0pll_dsi1pll,
673 .ops = &clk_pixel_ops,
674 .flags = CLK_SET_RATE_PARENT,
678 static const struct freq_tbl ftbl_mdp_clk_src[] = {
679 F(85714286, P_GPLL0, 7, 0, 0),
680 F(100000000, P_GPLL0, 6, 0, 0),
681 F(150000000, P_GPLL0, 4, 0, 0),
682 F(171428571, P_GPLL0, 3.5, 0, 0),
683 F(200000000, P_GPLL0, 3, 0, 0),
684 F(275000000, P_MMPLL5, 3, 0, 0),
685 F(300000000, P_GPLL0, 2, 0, 0),
686 F(330000000, P_MMPLL5, 2.5, 0, 0),
687 F(412500000, P_MMPLL5, 2, 0, 0),
691 static struct clk_rcg2 mdp_clk_src = {
694 .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
695 .freq_tbl = ftbl_mdp_clk_src,
696 .clkr.hw.init = &(struct clk_init_data){
697 .name = "mdp_clk_src",
698 .parent_names = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
700 .ops = &clk_rcg2_ops,
704 static struct freq_tbl extpclk_freq_tbl[] = {
705 { .src = P_HDMIPLL },
709 static struct clk_rcg2 extpclk_clk_src = {
712 .parent_map = mmss_xo_hdmi_map,
713 .freq_tbl = extpclk_freq_tbl,
714 .clkr.hw.init = &(struct clk_init_data){
715 .name = "extpclk_clk_src",
716 .parent_names = mmss_xo_hdmi,
718 .ops = &clk_byte_ops,
719 .flags = CLK_SET_RATE_PARENT,
723 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
724 F(19200000, P_XO, 1, 0, 0),
728 static struct clk_rcg2 vsync_clk_src = {
731 .parent_map = mmss_xo_gpll0_gpll0_div_map,
732 .freq_tbl = ftbl_mdss_vsync_clk,
733 .clkr.hw.init = &(struct clk_init_data){
734 .name = "vsync_clk_src",
735 .parent_names = mmss_xo_gpll0_gpll0_div,
737 .ops = &clk_rcg2_ops,
741 static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
742 F(19200000, P_XO, 1, 0, 0),
746 static struct clk_rcg2 hdmi_clk_src = {
749 .parent_map = mmss_xo_gpll0_gpll0_div_map,
750 .freq_tbl = ftbl_mdss_hdmi_clk,
751 .clkr.hw.init = &(struct clk_init_data){
752 .name = "hdmi_clk_src",
753 .parent_names = mmss_xo_gpll0_gpll0_div,
755 .ops = &clk_rcg2_ops,
759 static struct clk_rcg2 byte0_clk_src = {
762 .parent_map = mmss_xo_dsibyte_map,
763 .clkr.hw.init = &(struct clk_init_data){
764 .name = "byte0_clk_src",
765 .parent_names = mmss_xo_dsibyte,
767 .ops = &clk_byte2_ops,
768 .flags = CLK_SET_RATE_PARENT,
772 static struct clk_rcg2 byte1_clk_src = {
775 .parent_map = mmss_xo_dsibyte_map,
776 .clkr.hw.init = &(struct clk_init_data){
777 .name = "byte1_clk_src",
778 .parent_names = mmss_xo_dsibyte,
780 .ops = &clk_byte2_ops,
781 .flags = CLK_SET_RATE_PARENT,
785 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
786 F(19200000, P_XO, 1, 0, 0),
790 static struct clk_rcg2 esc0_clk_src = {
793 .parent_map = mmss_xo_dsibyte_map,
794 .freq_tbl = ftbl_mdss_esc0_1_clk,
795 .clkr.hw.init = &(struct clk_init_data){
796 .name = "esc0_clk_src",
797 .parent_names = mmss_xo_dsibyte,
799 .ops = &clk_rcg2_ops,
803 static struct clk_rcg2 esc1_clk_src = {
806 .parent_map = mmss_xo_dsibyte_map,
807 .freq_tbl = ftbl_mdss_esc0_1_clk,
808 .clkr.hw.init = &(struct clk_init_data){
809 .name = "esc1_clk_src",
810 .parent_names = mmss_xo_dsibyte,
812 .ops = &clk_rcg2_ops,
816 static const struct freq_tbl ftbl_camss_gp0_clk_src[] = {
817 F(10000, P_XO, 16, 1, 120),
818 F(24000, P_XO, 16, 1, 50),
819 F(6000000, P_GPLL0_DIV, 10, 1, 5),
820 F(12000000, P_GPLL0_DIV, 1, 1, 25),
821 F(13000000, P_GPLL0_DIV, 2, 13, 150),
822 F(24000000, P_GPLL0_DIV, 1, 2, 25),
826 static struct clk_rcg2 camss_gp0_clk_src = {
830 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
831 .freq_tbl = ftbl_camss_gp0_clk_src,
832 .clkr.hw.init = &(struct clk_init_data){
833 .name = "camss_gp0_clk_src",
834 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
836 .ops = &clk_rcg2_ops,
840 static struct clk_rcg2 camss_gp1_clk_src = {
844 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
845 .freq_tbl = ftbl_camss_gp0_clk_src,
846 .clkr.hw.init = &(struct clk_init_data){
847 .name = "camss_gp1_clk_src",
848 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
850 .ops = &clk_rcg2_ops,
854 static const struct freq_tbl ftbl_mclk0_clk_src[] = {
855 F(4800000, P_XO, 4, 0, 0),
856 F(6000000, P_GPLL0_DIV, 10, 1, 5),
857 F(8000000, P_GPLL0_DIV, 1, 2, 75),
858 F(9600000, P_XO, 2, 0, 0),
859 F(16666667, P_GPLL0_DIV, 2, 1, 9),
860 F(19200000, P_XO, 1, 0, 0),
861 F(24000000, P_GPLL0_DIV, 1, 2, 25),
862 F(33333333, P_GPLL0_DIV, 1, 1, 9),
863 F(48000000, P_GPLL0, 1, 2, 25),
864 F(66666667, P_GPLL0, 1, 1, 9),
868 static struct clk_rcg2 mclk0_clk_src = {
872 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
873 .freq_tbl = ftbl_mclk0_clk_src,
874 .clkr.hw.init = &(struct clk_init_data){
875 .name = "mclk0_clk_src",
876 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
878 .ops = &clk_rcg2_ops,
882 static struct clk_rcg2 mclk1_clk_src = {
886 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
887 .freq_tbl = ftbl_mclk0_clk_src,
888 .clkr.hw.init = &(struct clk_init_data){
889 .name = "mclk1_clk_src",
890 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
892 .ops = &clk_rcg2_ops,
896 static struct clk_rcg2 mclk2_clk_src = {
900 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
901 .freq_tbl = ftbl_mclk0_clk_src,
902 .clkr.hw.init = &(struct clk_init_data){
903 .name = "mclk2_clk_src",
904 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
906 .ops = &clk_rcg2_ops,
910 static struct clk_rcg2 mclk3_clk_src = {
914 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
915 .freq_tbl = ftbl_mclk0_clk_src,
916 .clkr.hw.init = &(struct clk_init_data){
917 .name = "mclk3_clk_src",
918 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
920 .ops = &clk_rcg2_ops,
924 static const struct freq_tbl ftbl_cci_clk_src[] = {
925 F(19200000, P_XO, 1, 0, 0),
926 F(37500000, P_GPLL0, 16, 0, 0),
927 F(50000000, P_GPLL0, 12, 0, 0),
928 F(100000000, P_GPLL0, 6, 0, 0),
932 static struct clk_rcg2 cci_clk_src = {
936 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
937 .freq_tbl = ftbl_cci_clk_src,
938 .clkr.hw.init = &(struct clk_init_data){
939 .name = "cci_clk_src",
940 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
942 .ops = &clk_rcg2_ops,
946 static const struct freq_tbl ftbl_csi0phytimer_clk_src[] = {
947 F(100000000, P_GPLL0_DIV, 3, 0, 0),
948 F(200000000, P_GPLL0, 3, 0, 0),
949 F(266666667, P_MMPLL0, 3, 0, 0),
953 static struct clk_rcg2 csi0phytimer_clk_src = {
956 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
957 .freq_tbl = ftbl_csi0phytimer_clk_src,
958 .clkr.hw.init = &(struct clk_init_data){
959 .name = "csi0phytimer_clk_src",
960 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
962 .ops = &clk_rcg2_ops,
966 static struct clk_rcg2 csi1phytimer_clk_src = {
969 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
970 .freq_tbl = ftbl_csi0phytimer_clk_src,
971 .clkr.hw.init = &(struct clk_init_data){
972 .name = "csi1phytimer_clk_src",
973 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
975 .ops = &clk_rcg2_ops,
979 static struct clk_rcg2 csi2phytimer_clk_src = {
982 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
983 .freq_tbl = ftbl_csi0phytimer_clk_src,
984 .clkr.hw.init = &(struct clk_init_data){
985 .name = "csi2phytimer_clk_src",
986 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
988 .ops = &clk_rcg2_ops,
992 static const struct freq_tbl ftbl_csiphy0_3p_clk_src[] = {
993 F(100000000, P_GPLL0_DIV, 3, 0, 0),
994 F(200000000, P_GPLL0, 3, 0, 0),
995 F(320000000, P_MMPLL4, 3, 0, 0),
996 F(384000000, P_MMPLL4, 2.5, 0, 0),
1000 static struct clk_rcg2 csiphy0_3p_clk_src = {
1003 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1004 .freq_tbl = ftbl_csiphy0_3p_clk_src,
1005 .clkr.hw.init = &(struct clk_init_data){
1006 .name = "csiphy0_3p_clk_src",
1007 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1009 .ops = &clk_rcg2_ops,
1013 static struct clk_rcg2 csiphy1_3p_clk_src = {
1016 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1017 .freq_tbl = ftbl_csiphy0_3p_clk_src,
1018 .clkr.hw.init = &(struct clk_init_data){
1019 .name = "csiphy1_3p_clk_src",
1020 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1022 .ops = &clk_rcg2_ops,
1026 static struct clk_rcg2 csiphy2_3p_clk_src = {
1029 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1030 .freq_tbl = ftbl_csiphy0_3p_clk_src,
1031 .clkr.hw.init = &(struct clk_init_data){
1032 .name = "csiphy2_3p_clk_src",
1033 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1035 .ops = &clk_rcg2_ops,
1039 static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
1040 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1041 F(150000000, P_GPLL0, 4, 0, 0),
1042 F(228571429, P_MMPLL0, 3.5, 0, 0),
1043 F(266666667, P_MMPLL0, 3, 0, 0),
1044 F(320000000, P_MMPLL0, 2.5, 0, 0),
1045 F(480000000, P_MMPLL4, 2, 0, 0),
1049 static struct clk_rcg2 jpeg0_clk_src = {
1052 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1053 .freq_tbl = ftbl_jpeg0_clk_src,
1054 .clkr.hw.init = &(struct clk_init_data){
1055 .name = "jpeg0_clk_src",
1056 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1058 .ops = &clk_rcg2_ops,
1062 static const struct freq_tbl ftbl_jpeg2_clk_src[] = {
1063 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1064 F(150000000, P_GPLL0, 4, 0, 0),
1065 F(228571429, P_MMPLL0, 3.5, 0, 0),
1066 F(266666667, P_MMPLL0, 3, 0, 0),
1067 F(320000000, P_MMPLL0, 2.5, 0, 0),
1071 static struct clk_rcg2 jpeg2_clk_src = {
1074 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1075 .freq_tbl = ftbl_jpeg2_clk_src,
1076 .clkr.hw.init = &(struct clk_init_data){
1077 .name = "jpeg2_clk_src",
1078 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1080 .ops = &clk_rcg2_ops,
1084 static struct clk_rcg2 jpeg_dma_clk_src = {
1087 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1088 .freq_tbl = ftbl_jpeg0_clk_src,
1089 .clkr.hw.init = &(struct clk_init_data){
1090 .name = "jpeg_dma_clk_src",
1091 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1093 .ops = &clk_rcg2_ops,
1097 static const struct freq_tbl ftbl_vfe0_clk_src[] = {
1098 F(75000000, P_GPLL0_DIV, 4, 0, 0),
1099 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1100 F(300000000, P_GPLL0, 2, 0, 0),
1101 F(320000000, P_MMPLL0, 2.5, 0, 0),
1102 F(480000000, P_MMPLL4, 2, 0, 0),
1103 F(600000000, P_GPLL0, 1, 0, 0),
1107 static struct clk_rcg2 vfe0_clk_src = {
1110 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1111 .freq_tbl = ftbl_vfe0_clk_src,
1112 .clkr.hw.init = &(struct clk_init_data){
1113 .name = "vfe0_clk_src",
1114 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1116 .ops = &clk_rcg2_ops,
1120 static struct clk_rcg2 vfe1_clk_src = {
1123 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1124 .freq_tbl = ftbl_vfe0_clk_src,
1125 .clkr.hw.init = &(struct clk_init_data){
1126 .name = "vfe1_clk_src",
1127 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1129 .ops = &clk_rcg2_ops,
1133 static const struct freq_tbl ftbl_cpp_clk_src[] = {
1134 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1135 F(200000000, P_GPLL0, 3, 0, 0),
1136 F(320000000, P_MMPLL0, 2.5, 0, 0),
1137 F(480000000, P_MMPLL4, 2, 0, 0),
1138 F(640000000, P_MMPLL4, 1.5, 0, 0),
1142 static struct clk_rcg2 cpp_clk_src = {
1145 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1146 .freq_tbl = ftbl_cpp_clk_src,
1147 .clkr.hw.init = &(struct clk_init_data){
1148 .name = "cpp_clk_src",
1149 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1151 .ops = &clk_rcg2_ops,
1155 static const struct freq_tbl ftbl_csi0_clk_src[] = {
1156 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1157 F(200000000, P_GPLL0, 3, 0, 0),
1158 F(266666667, P_MMPLL0, 3, 0, 0),
1159 F(480000000, P_MMPLL4, 2, 0, 0),
1160 F(600000000, P_GPLL0, 1, 0, 0),
1164 static struct clk_rcg2 csi0_clk_src = {
1167 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1168 .freq_tbl = ftbl_csi0_clk_src,
1169 .clkr.hw.init = &(struct clk_init_data){
1170 .name = "csi0_clk_src",
1171 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1173 .ops = &clk_rcg2_ops,
1177 static struct clk_rcg2 csi1_clk_src = {
1180 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1181 .freq_tbl = ftbl_csi0_clk_src,
1182 .clkr.hw.init = &(struct clk_init_data){
1183 .name = "csi1_clk_src",
1184 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1186 .ops = &clk_rcg2_ops,
1190 static struct clk_rcg2 csi2_clk_src = {
1193 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1194 .freq_tbl = ftbl_csi0_clk_src,
1195 .clkr.hw.init = &(struct clk_init_data){
1196 .name = "csi2_clk_src",
1197 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1199 .ops = &clk_rcg2_ops,
1203 static struct clk_rcg2 csi3_clk_src = {
1206 .parent_map = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map,
1207 .freq_tbl = ftbl_csi0_clk_src,
1208 .clkr.hw.init = &(struct clk_init_data){
1209 .name = "csi3_clk_src",
1210 .parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1212 .ops = &clk_rcg2_ops,
1216 static const struct freq_tbl ftbl_fd_core_clk_src[] = {
1217 F(100000000, P_GPLL0_DIV, 3, 0, 0),
1218 F(200000000, P_GPLL0, 3, 0, 0),
1219 F(400000000, P_MMPLL0, 2, 0, 0),
1223 static struct clk_rcg2 fd_core_clk_src = {
1226 .parent_map = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map,
1227 .freq_tbl = ftbl_fd_core_clk_src,
1228 .clkr.hw.init = &(struct clk_init_data){
1229 .name = "fd_core_clk_src",
1230 .parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
1232 .ops = &clk_rcg2_ops,
1236 static struct clk_branch mmss_mmagic_ahb_clk = {
1239 .enable_reg = 0x5024,
1240 .enable_mask = BIT(0),
1241 .hw.init = &(struct clk_init_data){
1242 .name = "mmss_mmagic_ahb_clk",
1243 .parent_names = (const char *[]){ "ahb_clk_src" },
1245 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1246 .ops = &clk_branch2_ops,
1251 static struct clk_branch mmss_mmagic_cfg_ahb_clk = {
1254 .enable_reg = 0x5054,
1255 .enable_mask = BIT(0),
1256 .hw.init = &(struct clk_init_data){
1257 .name = "mmss_mmagic_cfg_ahb_clk",
1258 .parent_names = (const char *[]){ "ahb_clk_src" },
1260 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1261 .ops = &clk_branch2_ops,
1266 static struct clk_branch mmss_misc_ahb_clk = {
1269 .enable_reg = 0x5018,
1270 .enable_mask = BIT(0),
1271 .hw.init = &(struct clk_init_data){
1272 .name = "mmss_misc_ahb_clk",
1273 .parent_names = (const char *[]){ "ahb_clk_src" },
1275 .flags = CLK_SET_RATE_PARENT,
1276 .ops = &clk_branch2_ops,
1281 static struct clk_branch mmss_misc_cxo_clk = {
1284 .enable_reg = 0x5014,
1285 .enable_mask = BIT(0),
1286 .hw.init = &(struct clk_init_data){
1287 .name = "mmss_misc_cxo_clk",
1288 .parent_names = (const char *[]){ "xo" },
1290 .ops = &clk_branch2_ops,
1295 static struct clk_branch mmss_mmagic_maxi_clk = {
1298 .enable_reg = 0x5074,
1299 .enable_mask = BIT(0),
1300 .hw.init = &(struct clk_init_data){
1301 .name = "mmss_mmagic_maxi_clk",
1302 .parent_names = (const char *[]){ "maxi_clk_src" },
1304 .flags = CLK_SET_RATE_PARENT,
1305 .ops = &clk_branch2_ops,
1310 static struct clk_branch mmagic_camss_axi_clk = {
1313 .enable_reg = 0x3c44,
1314 .enable_mask = BIT(0),
1315 .hw.init = &(struct clk_init_data){
1316 .name = "mmagic_camss_axi_clk",
1317 .parent_names = (const char *[]){ "axi_clk_src" },
1319 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1320 .ops = &clk_branch2_ops,
1325 static struct clk_branch mmagic_camss_noc_cfg_ahb_clk = {
1328 .enable_reg = 0x3c48,
1329 .enable_mask = BIT(0),
1330 .hw.init = &(struct clk_init_data){
1331 .name = "mmagic_camss_noc_cfg_ahb_clk",
1332 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1334 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1335 .ops = &clk_branch2_ops,
1340 static struct clk_branch smmu_vfe_ahb_clk = {
1343 .enable_reg = 0x3c04,
1344 .enable_mask = BIT(0),
1345 .hw.init = &(struct clk_init_data){
1346 .name = "smmu_vfe_ahb_clk",
1347 .parent_names = (const char *[]){ "ahb_clk_src" },
1349 .flags = CLK_SET_RATE_PARENT,
1350 .ops = &clk_branch2_ops,
1355 static struct clk_branch smmu_vfe_axi_clk = {
1358 .enable_reg = 0x3c08,
1359 .enable_mask = BIT(0),
1360 .hw.init = &(struct clk_init_data){
1361 .name = "smmu_vfe_axi_clk",
1362 .parent_names = (const char *[]){ "axi_clk_src" },
1364 .flags = CLK_SET_RATE_PARENT,
1365 .ops = &clk_branch2_ops,
1370 static struct clk_branch smmu_cpp_ahb_clk = {
1373 .enable_reg = 0x3c14,
1374 .enable_mask = BIT(0),
1375 .hw.init = &(struct clk_init_data){
1376 .name = "smmu_cpp_ahb_clk",
1377 .parent_names = (const char *[]){ "ahb_clk_src" },
1379 .flags = CLK_SET_RATE_PARENT,
1380 .ops = &clk_branch2_ops,
1385 static struct clk_branch smmu_cpp_axi_clk = {
1388 .enable_reg = 0x3c18,
1389 .enable_mask = BIT(0),
1390 .hw.init = &(struct clk_init_data){
1391 .name = "smmu_cpp_axi_clk",
1392 .parent_names = (const char *[]){ "axi_clk_src" },
1394 .flags = CLK_SET_RATE_PARENT,
1395 .ops = &clk_branch2_ops,
1400 static struct clk_branch smmu_jpeg_ahb_clk = {
1403 .enable_reg = 0x3c24,
1404 .enable_mask = BIT(0),
1405 .hw.init = &(struct clk_init_data){
1406 .name = "smmu_jpeg_ahb_clk",
1407 .parent_names = (const char *[]){ "ahb_clk_src" },
1409 .flags = CLK_SET_RATE_PARENT,
1410 .ops = &clk_branch2_ops,
1415 static struct clk_branch smmu_jpeg_axi_clk = {
1418 .enable_reg = 0x3c28,
1419 .enable_mask = BIT(0),
1420 .hw.init = &(struct clk_init_data){
1421 .name = "smmu_jpeg_axi_clk",
1422 .parent_names = (const char *[]){ "axi_clk_src" },
1424 .flags = CLK_SET_RATE_PARENT,
1425 .ops = &clk_branch2_ops,
1430 static struct clk_branch mmagic_mdss_axi_clk = {
1433 .enable_reg = 0x2474,
1434 .enable_mask = BIT(0),
1435 .hw.init = &(struct clk_init_data){
1436 .name = "mmagic_mdss_axi_clk",
1437 .parent_names = (const char *[]){ "axi_clk_src" },
1439 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1440 .ops = &clk_branch2_ops,
1445 static struct clk_branch mmagic_mdss_noc_cfg_ahb_clk = {
1448 .enable_reg = 0x2478,
1449 .enable_mask = BIT(0),
1450 .hw.init = &(struct clk_init_data){
1451 .name = "mmagic_mdss_noc_cfg_ahb_clk",
1452 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1454 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1455 .ops = &clk_branch2_ops,
1460 static struct clk_branch smmu_rot_ahb_clk = {
1463 .enable_reg = 0x2444,
1464 .enable_mask = BIT(0),
1465 .hw.init = &(struct clk_init_data){
1466 .name = "smmu_rot_ahb_clk",
1467 .parent_names = (const char *[]){ "ahb_clk_src" },
1469 .flags = CLK_SET_RATE_PARENT,
1470 .ops = &clk_branch2_ops,
1475 static struct clk_branch smmu_rot_axi_clk = {
1478 .enable_reg = 0x2448,
1479 .enable_mask = BIT(0),
1480 .hw.init = &(struct clk_init_data){
1481 .name = "smmu_rot_axi_clk",
1482 .parent_names = (const char *[]){ "axi_clk_src" },
1484 .flags = CLK_SET_RATE_PARENT,
1485 .ops = &clk_branch2_ops,
1490 static struct clk_branch smmu_mdp_ahb_clk = {
1493 .enable_reg = 0x2454,
1494 .enable_mask = BIT(0),
1495 .hw.init = &(struct clk_init_data){
1496 .name = "smmu_mdp_ahb_clk",
1497 .parent_names = (const char *[]){ "ahb_clk_src" },
1499 .flags = CLK_SET_RATE_PARENT,
1500 .ops = &clk_branch2_ops,
1505 static struct clk_branch smmu_mdp_axi_clk = {
1508 .enable_reg = 0x2458,
1509 .enable_mask = BIT(0),
1510 .hw.init = &(struct clk_init_data){
1511 .name = "smmu_mdp_axi_clk",
1512 .parent_names = (const char *[]){ "axi_clk_src" },
1514 .flags = CLK_SET_RATE_PARENT,
1515 .ops = &clk_branch2_ops,
1520 static struct clk_branch mmagic_video_axi_clk = {
1523 .enable_reg = 0x1194,
1524 .enable_mask = BIT(0),
1525 .hw.init = &(struct clk_init_data){
1526 .name = "mmagic_video_axi_clk",
1527 .parent_names = (const char *[]){ "axi_clk_src" },
1529 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1530 .ops = &clk_branch2_ops,
1535 static struct clk_branch mmagic_video_noc_cfg_ahb_clk = {
1538 .enable_reg = 0x1198,
1539 .enable_mask = BIT(0),
1540 .hw.init = &(struct clk_init_data){
1541 .name = "mmagic_video_noc_cfg_ahb_clk",
1542 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1544 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1545 .ops = &clk_branch2_ops,
1550 static struct clk_branch smmu_video_ahb_clk = {
1553 .enable_reg = 0x1174,
1554 .enable_mask = BIT(0),
1555 .hw.init = &(struct clk_init_data){
1556 .name = "smmu_video_ahb_clk",
1557 .parent_names = (const char *[]){ "ahb_clk_src" },
1559 .flags = CLK_SET_RATE_PARENT,
1560 .ops = &clk_branch2_ops,
1565 static struct clk_branch smmu_video_axi_clk = {
1568 .enable_reg = 0x1178,
1569 .enable_mask = BIT(0),
1570 .hw.init = &(struct clk_init_data){
1571 .name = "smmu_video_axi_clk",
1572 .parent_names = (const char *[]){ "axi_clk_src" },
1574 .flags = CLK_SET_RATE_PARENT,
1575 .ops = &clk_branch2_ops,
1580 static struct clk_branch mmagic_bimc_noc_cfg_ahb_clk = {
1583 .enable_reg = 0x5298,
1584 .enable_mask = BIT(0),
1585 .hw.init = &(struct clk_init_data){
1586 .name = "mmagic_bimc_noc_cfg_ahb_clk",
1587 .parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1589 .flags = CLK_SET_RATE_PARENT,
1590 .ops = &clk_branch2_ops,
1595 static struct clk_branch gpu_gx_gfx3d_clk = {
1598 .enable_reg = 0x4028,
1599 .enable_mask = BIT(0),
1600 .hw.init = &(struct clk_init_data){
1601 .name = "gpu_gx_gfx3d_clk",
1602 .parent_names = (const char *[]){ "gfx3d_clk_src" },
1604 .flags = CLK_SET_RATE_PARENT,
1605 .ops = &clk_branch2_ops,
1610 static struct clk_branch gpu_gx_rbbmtimer_clk = {
1613 .enable_reg = 0x40b0,
1614 .enable_mask = BIT(0),
1615 .hw.init = &(struct clk_init_data){
1616 .name = "gpu_gx_rbbmtimer_clk",
1617 .parent_names = (const char *[]){ "rbbmtimer_clk_src" },
1619 .flags = CLK_SET_RATE_PARENT,
1620 .ops = &clk_branch2_ops,
1625 static struct clk_branch gpu_ahb_clk = {
1628 .enable_reg = 0x403c,
1629 .enable_mask = BIT(0),
1630 .hw.init = &(struct clk_init_data){
1631 .name = "gpu_ahb_clk",
1632 .parent_names = (const char *[]){ "ahb_clk_src" },
1634 .flags = CLK_SET_RATE_PARENT,
1635 .ops = &clk_branch2_ops,
1640 static struct clk_branch gpu_aon_isense_clk = {
1643 .enable_reg = 0x4044,
1644 .enable_mask = BIT(0),
1645 .hw.init = &(struct clk_init_data){
1646 .name = "gpu_aon_isense_clk",
1647 .parent_names = (const char *[]){ "isense_clk_src" },
1649 .flags = CLK_SET_RATE_PARENT,
1650 .ops = &clk_branch2_ops,
1655 static struct clk_branch vmem_maxi_clk = {
1658 .enable_reg = 0x1204,
1659 .enable_mask = BIT(0),
1660 .hw.init = &(struct clk_init_data){
1661 .name = "vmem_maxi_clk",
1662 .parent_names = (const char *[]){ "maxi_clk_src" },
1664 .flags = CLK_SET_RATE_PARENT,
1665 .ops = &clk_branch2_ops,
1670 static struct clk_branch vmem_ahb_clk = {
1673 .enable_reg = 0x1208,
1674 .enable_mask = BIT(0),
1675 .hw.init = &(struct clk_init_data){
1676 .name = "vmem_ahb_clk",
1677 .parent_names = (const char *[]){ "ahb_clk_src" },
1679 .flags = CLK_SET_RATE_PARENT,
1680 .ops = &clk_branch2_ops,
1685 static struct clk_branch mmss_rbcpr_clk = {
1688 .enable_reg = 0x4084,
1689 .enable_mask = BIT(0),
1690 .hw.init = &(struct clk_init_data){
1691 .name = "mmss_rbcpr_clk",
1692 .parent_names = (const char *[]){ "rbcpr_clk_src" },
1694 .flags = CLK_SET_RATE_PARENT,
1695 .ops = &clk_branch2_ops,
1700 static struct clk_branch mmss_rbcpr_ahb_clk = {
1703 .enable_reg = 0x4088,
1704 .enable_mask = BIT(0),
1705 .hw.init = &(struct clk_init_data){
1706 .name = "mmss_rbcpr_ahb_clk",
1707 .parent_names = (const char *[]){ "ahb_clk_src" },
1709 .flags = CLK_SET_RATE_PARENT,
1710 .ops = &clk_branch2_ops,
1715 static struct clk_branch video_core_clk = {
1718 .enable_reg = 0x1028,
1719 .enable_mask = BIT(0),
1720 .hw.init = &(struct clk_init_data){
1721 .name = "video_core_clk",
1722 .parent_names = (const char *[]){ "video_core_clk_src" },
1724 .flags = CLK_SET_RATE_PARENT,
1725 .ops = &clk_branch2_ops,
1730 static struct clk_branch video_axi_clk = {
1733 .enable_reg = 0x1034,
1734 .enable_mask = BIT(0),
1735 .hw.init = &(struct clk_init_data){
1736 .name = "video_axi_clk",
1737 .parent_names = (const char *[]){ "axi_clk_src" },
1739 .flags = CLK_SET_RATE_PARENT,
1740 .ops = &clk_branch2_ops,
1745 static struct clk_branch video_maxi_clk = {
1748 .enable_reg = 0x1038,
1749 .enable_mask = BIT(0),
1750 .hw.init = &(struct clk_init_data){
1751 .name = "video_maxi_clk",
1752 .parent_names = (const char *[]){ "maxi_clk_src" },
1754 .flags = CLK_SET_RATE_PARENT,
1755 .ops = &clk_branch2_ops,
1760 static struct clk_branch video_ahb_clk = {
1763 .enable_reg = 0x1030,
1764 .enable_mask = BIT(0),
1765 .hw.init = &(struct clk_init_data){
1766 .name = "video_ahb_clk",
1767 .parent_names = (const char *[]){ "ahb_clk_src" },
1769 .flags = CLK_SET_RATE_PARENT,
1770 .ops = &clk_branch2_ops,
1775 static struct clk_branch video_subcore0_clk = {
1778 .enable_reg = 0x1048,
1779 .enable_mask = BIT(0),
1780 .hw.init = &(struct clk_init_data){
1781 .name = "video_subcore0_clk",
1782 .parent_names = (const char *[]){ "video_subcore0_clk_src" },
1784 .flags = CLK_SET_RATE_PARENT,
1785 .ops = &clk_branch2_ops,
1790 static struct clk_branch video_subcore1_clk = {
1793 .enable_reg = 0x104c,
1794 .enable_mask = BIT(0),
1795 .hw.init = &(struct clk_init_data){
1796 .name = "video_subcore1_clk",
1797 .parent_names = (const char *[]){ "video_subcore1_clk_src" },
1799 .flags = CLK_SET_RATE_PARENT,
1800 .ops = &clk_branch2_ops,
1805 static struct clk_branch mdss_ahb_clk = {
1808 .enable_reg = 0x2308,
1809 .enable_mask = BIT(0),
1810 .hw.init = &(struct clk_init_data){
1811 .name = "mdss_ahb_clk",
1812 .parent_names = (const char *[]){ "ahb_clk_src" },
1814 .flags = CLK_SET_RATE_PARENT,
1815 .ops = &clk_branch2_ops,
1820 static struct clk_branch mdss_hdmi_ahb_clk = {
1823 .enable_reg = 0x230c,
1824 .enable_mask = BIT(0),
1825 .hw.init = &(struct clk_init_data){
1826 .name = "mdss_hdmi_ahb_clk",
1827 .parent_names = (const char *[]){ "ahb_clk_src" },
1829 .flags = CLK_SET_RATE_PARENT,
1830 .ops = &clk_branch2_ops,
1835 static struct clk_branch mdss_axi_clk = {
1838 .enable_reg = 0x2310,
1839 .enable_mask = BIT(0),
1840 .hw.init = &(struct clk_init_data){
1841 .name = "mdss_axi_clk",
1842 .parent_names = (const char *[]){ "axi_clk_src" },
1844 .flags = CLK_SET_RATE_PARENT,
1845 .ops = &clk_branch2_ops,
1850 static struct clk_branch mdss_pclk0_clk = {
1853 .enable_reg = 0x2314,
1854 .enable_mask = BIT(0),
1855 .hw.init = &(struct clk_init_data){
1856 .name = "mdss_pclk0_clk",
1857 .parent_names = (const char *[]){ "pclk0_clk_src" },
1859 .flags = CLK_SET_RATE_PARENT,
1860 .ops = &clk_branch2_ops,
1865 static struct clk_branch mdss_pclk1_clk = {
1868 .enable_reg = 0x2318,
1869 .enable_mask = BIT(0),
1870 .hw.init = &(struct clk_init_data){
1871 .name = "mdss_pclk1_clk",
1872 .parent_names = (const char *[]){ "pclk1_clk_src" },
1874 .flags = CLK_SET_RATE_PARENT,
1875 .ops = &clk_branch2_ops,
1880 static struct clk_branch mdss_mdp_clk = {
1883 .enable_reg = 0x231c,
1884 .enable_mask = BIT(0),
1885 .hw.init = &(struct clk_init_data){
1886 .name = "mdss_mdp_clk",
1887 .parent_names = (const char *[]){ "mdp_clk_src" },
1889 .flags = CLK_SET_RATE_PARENT,
1890 .ops = &clk_branch2_ops,
1895 static struct clk_branch mdss_extpclk_clk = {
1898 .enable_reg = 0x2324,
1899 .enable_mask = BIT(0),
1900 .hw.init = &(struct clk_init_data){
1901 .name = "mdss_extpclk_clk",
1902 .parent_names = (const char *[]){ "extpclk_clk_src" },
1904 .flags = CLK_SET_RATE_PARENT,
1905 .ops = &clk_branch2_ops,
1910 static struct clk_branch mdss_vsync_clk = {
1913 .enable_reg = 0x2328,
1914 .enable_mask = BIT(0),
1915 .hw.init = &(struct clk_init_data){
1916 .name = "mdss_vsync_clk",
1917 .parent_names = (const char *[]){ "vsync_clk_src" },
1919 .flags = CLK_SET_RATE_PARENT,
1920 .ops = &clk_branch2_ops,
1925 static struct clk_branch mdss_hdmi_clk = {
1928 .enable_reg = 0x2338,
1929 .enable_mask = BIT(0),
1930 .hw.init = &(struct clk_init_data){
1931 .name = "mdss_hdmi_clk",
1932 .parent_names = (const char *[]){ "hdmi_clk_src" },
1934 .flags = CLK_SET_RATE_PARENT,
1935 .ops = &clk_branch2_ops,
1940 static struct clk_branch mdss_byte0_clk = {
1943 .enable_reg = 0x233c,
1944 .enable_mask = BIT(0),
1945 .hw.init = &(struct clk_init_data){
1946 .name = "mdss_byte0_clk",
1947 .parent_names = (const char *[]){ "byte0_clk_src" },
1949 .flags = CLK_SET_RATE_PARENT,
1950 .ops = &clk_branch2_ops,
1955 static struct clk_branch mdss_byte1_clk = {
1958 .enable_reg = 0x2340,
1959 .enable_mask = BIT(0),
1960 .hw.init = &(struct clk_init_data){
1961 .name = "mdss_byte1_clk",
1962 .parent_names = (const char *[]){ "byte1_clk_src" },
1964 .flags = CLK_SET_RATE_PARENT,
1965 .ops = &clk_branch2_ops,
1970 static struct clk_branch mdss_esc0_clk = {
1973 .enable_reg = 0x2344,
1974 .enable_mask = BIT(0),
1975 .hw.init = &(struct clk_init_data){
1976 .name = "mdss_esc0_clk",
1977 .parent_names = (const char *[]){ "esc0_clk_src" },
1979 .flags = CLK_SET_RATE_PARENT,
1980 .ops = &clk_branch2_ops,
1985 static struct clk_branch mdss_esc1_clk = {
1988 .enable_reg = 0x2348,
1989 .enable_mask = BIT(0),
1990 .hw.init = &(struct clk_init_data){
1991 .name = "mdss_esc1_clk",
1992 .parent_names = (const char *[]){ "esc1_clk_src" },
1994 .flags = CLK_SET_RATE_PARENT,
1995 .ops = &clk_branch2_ops,
2000 static struct clk_branch camss_top_ahb_clk = {
2003 .enable_reg = 0x3484,
2004 .enable_mask = BIT(0),
2005 .hw.init = &(struct clk_init_data){
2006 .name = "camss_top_ahb_clk",
2007 .parent_names = (const char *[]){ "ahb_clk_src" },
2009 .flags = CLK_SET_RATE_PARENT,
2010 .ops = &clk_branch2_ops,
2015 static struct clk_branch camss_ahb_clk = {
2018 .enable_reg = 0x348c,
2019 .enable_mask = BIT(0),
2020 .hw.init = &(struct clk_init_data){
2021 .name = "camss_ahb_clk",
2022 .parent_names = (const char *[]){ "ahb_clk_src" },
2024 .flags = CLK_SET_RATE_PARENT,
2025 .ops = &clk_branch2_ops,
2030 static struct clk_branch camss_micro_ahb_clk = {
2033 .enable_reg = 0x3494,
2034 .enable_mask = BIT(0),
2035 .hw.init = &(struct clk_init_data){
2036 .name = "camss_micro_ahb_clk",
2037 .parent_names = (const char *[]){ "ahb_clk_src" },
2039 .flags = CLK_SET_RATE_PARENT,
2040 .ops = &clk_branch2_ops,
2045 static struct clk_branch camss_gp0_clk = {
2048 .enable_reg = 0x3444,
2049 .enable_mask = BIT(0),
2050 .hw.init = &(struct clk_init_data){
2051 .name = "camss_gp0_clk",
2052 .parent_names = (const char *[]){ "camss_gp0_clk_src" },
2054 .flags = CLK_SET_RATE_PARENT,
2055 .ops = &clk_branch2_ops,
2060 static struct clk_branch camss_gp1_clk = {
2063 .enable_reg = 0x3474,
2064 .enable_mask = BIT(0),
2065 .hw.init = &(struct clk_init_data){
2066 .name = "camss_gp1_clk",
2067 .parent_names = (const char *[]){ "camss_gp1_clk_src" },
2069 .flags = CLK_SET_RATE_PARENT,
2070 .ops = &clk_branch2_ops,
2075 static struct clk_branch camss_mclk0_clk = {
2078 .enable_reg = 0x3384,
2079 .enable_mask = BIT(0),
2080 .hw.init = &(struct clk_init_data){
2081 .name = "camss_mclk0_clk",
2082 .parent_names = (const char *[]){ "mclk0_clk_src" },
2084 .flags = CLK_SET_RATE_PARENT,
2085 .ops = &clk_branch2_ops,
2090 static struct clk_branch camss_mclk1_clk = {
2093 .enable_reg = 0x33b4,
2094 .enable_mask = BIT(0),
2095 .hw.init = &(struct clk_init_data){
2096 .name = "camss_mclk1_clk",
2097 .parent_names = (const char *[]){ "mclk1_clk_src" },
2099 .flags = CLK_SET_RATE_PARENT,
2100 .ops = &clk_branch2_ops,
2105 static struct clk_branch camss_mclk2_clk = {
2108 .enable_reg = 0x33e4,
2109 .enable_mask = BIT(0),
2110 .hw.init = &(struct clk_init_data){
2111 .name = "camss_mclk2_clk",
2112 .parent_names = (const char *[]){ "mclk2_clk_src" },
2114 .flags = CLK_SET_RATE_PARENT,
2115 .ops = &clk_branch2_ops,
2120 static struct clk_branch camss_mclk3_clk = {
2123 .enable_reg = 0x3414,
2124 .enable_mask = BIT(0),
2125 .hw.init = &(struct clk_init_data){
2126 .name = "camss_mclk3_clk",
2127 .parent_names = (const char *[]){ "mclk3_clk_src" },
2129 .flags = CLK_SET_RATE_PARENT,
2130 .ops = &clk_branch2_ops,
2135 static struct clk_branch camss_cci_clk = {
2138 .enable_reg = 0x3344,
2139 .enable_mask = BIT(0),
2140 .hw.init = &(struct clk_init_data){
2141 .name = "camss_cci_clk",
2142 .parent_names = (const char *[]){ "cci_clk_src" },
2144 .flags = CLK_SET_RATE_PARENT,
2145 .ops = &clk_branch2_ops,
2150 static struct clk_branch camss_cci_ahb_clk = {
2153 .enable_reg = 0x3348,
2154 .enable_mask = BIT(0),
2155 .hw.init = &(struct clk_init_data){
2156 .name = "camss_cci_ahb_clk",
2157 .parent_names = (const char *[]){ "ahb_clk_src" },
2159 .flags = CLK_SET_RATE_PARENT,
2160 .ops = &clk_branch2_ops,
2165 static struct clk_branch camss_csi0phytimer_clk = {
2168 .enable_reg = 0x3024,
2169 .enable_mask = BIT(0),
2170 .hw.init = &(struct clk_init_data){
2171 .name = "camss_csi0phytimer_clk",
2172 .parent_names = (const char *[]){ "csi0phytimer_clk_src" },
2174 .flags = CLK_SET_RATE_PARENT,
2175 .ops = &clk_branch2_ops,
2180 static struct clk_branch camss_csi1phytimer_clk = {
2183 .enable_reg = 0x3054,
2184 .enable_mask = BIT(0),
2185 .hw.init = &(struct clk_init_data){
2186 .name = "camss_csi1phytimer_clk",
2187 .parent_names = (const char *[]){ "csi1phytimer_clk_src" },
2189 .flags = CLK_SET_RATE_PARENT,
2190 .ops = &clk_branch2_ops,
2195 static struct clk_branch camss_csi2phytimer_clk = {
2198 .enable_reg = 0x3084,
2199 .enable_mask = BIT(0),
2200 .hw.init = &(struct clk_init_data){
2201 .name = "camss_csi2phytimer_clk",
2202 .parent_names = (const char *[]){ "csi2phytimer_clk_src" },
2204 .flags = CLK_SET_RATE_PARENT,
2205 .ops = &clk_branch2_ops,
2210 static struct clk_branch camss_csiphy0_3p_clk = {
2213 .enable_reg = 0x3234,
2214 .enable_mask = BIT(0),
2215 .hw.init = &(struct clk_init_data){
2216 .name = "camss_csiphy0_3p_clk",
2217 .parent_names = (const char *[]){ "csiphy0_3p_clk_src" },
2219 .flags = CLK_SET_RATE_PARENT,
2220 .ops = &clk_branch2_ops,
2225 static struct clk_branch camss_csiphy1_3p_clk = {
2228 .enable_reg = 0x3254,
2229 .enable_mask = BIT(0),
2230 .hw.init = &(struct clk_init_data){
2231 .name = "camss_csiphy1_3p_clk",
2232 .parent_names = (const char *[]){ "csiphy1_3p_clk_src" },
2234 .flags = CLK_SET_RATE_PARENT,
2235 .ops = &clk_branch2_ops,
2240 static struct clk_branch camss_csiphy2_3p_clk = {
2243 .enable_reg = 0x3274,
2244 .enable_mask = BIT(0),
2245 .hw.init = &(struct clk_init_data){
2246 .name = "camss_csiphy2_3p_clk",
2247 .parent_names = (const char *[]){ "csiphy2_3p_clk_src" },
2249 .flags = CLK_SET_RATE_PARENT,
2250 .ops = &clk_branch2_ops,
2255 static struct clk_branch camss_jpeg0_clk = {
2258 .enable_reg = 0x35a8,
2259 .enable_mask = BIT(0),
2260 .hw.init = &(struct clk_init_data){
2261 .name = "camss_jpeg0_clk",
2262 .parent_names = (const char *[]){ "jpeg0_clk_src" },
2264 .flags = CLK_SET_RATE_PARENT,
2265 .ops = &clk_branch2_ops,
2270 static struct clk_branch camss_jpeg2_clk = {
2273 .enable_reg = 0x35b0,
2274 .enable_mask = BIT(0),
2275 .hw.init = &(struct clk_init_data){
2276 .name = "camss_jpeg2_clk",
2277 .parent_names = (const char *[]){ "jpeg2_clk_src" },
2279 .flags = CLK_SET_RATE_PARENT,
2280 .ops = &clk_branch2_ops,
2285 static struct clk_branch camss_jpeg_dma_clk = {
2288 .enable_reg = 0x35c0,
2289 .enable_mask = BIT(0),
2290 .hw.init = &(struct clk_init_data){
2291 .name = "camss_jpeg_dma_clk",
2292 .parent_names = (const char *[]){ "jpeg_dma_clk_src" },
2294 .flags = CLK_SET_RATE_PARENT,
2295 .ops = &clk_branch2_ops,
2300 static struct clk_branch camss_jpeg_ahb_clk = {
2303 .enable_reg = 0x35b4,
2304 .enable_mask = BIT(0),
2305 .hw.init = &(struct clk_init_data){
2306 .name = "camss_jpeg_ahb_clk",
2307 .parent_names = (const char *[]){ "ahb_clk_src" },
2309 .flags = CLK_SET_RATE_PARENT,
2310 .ops = &clk_branch2_ops,
2315 static struct clk_branch camss_jpeg_axi_clk = {
2318 .enable_reg = 0x35b8,
2319 .enable_mask = BIT(0),
2320 .hw.init = &(struct clk_init_data){
2321 .name = "camss_jpeg_axi_clk",
2322 .parent_names = (const char *[]){ "axi_clk_src" },
2324 .flags = CLK_SET_RATE_PARENT,
2325 .ops = &clk_branch2_ops,
2330 static struct clk_branch camss_vfe_ahb_clk = {
2333 .enable_reg = 0x36b8,
2334 .enable_mask = BIT(0),
2335 .hw.init = &(struct clk_init_data){
2336 .name = "camss_vfe_ahb_clk",
2337 .parent_names = (const char *[]){ "ahb_clk_src" },
2339 .flags = CLK_SET_RATE_PARENT,
2340 .ops = &clk_branch2_ops,
2345 static struct clk_branch camss_vfe_axi_clk = {
2348 .enable_reg = 0x36bc,
2349 .enable_mask = BIT(0),
2350 .hw.init = &(struct clk_init_data){
2351 .name = "camss_vfe_axi_clk",
2352 .parent_names = (const char *[]){ "axi_clk_src" },
2354 .flags = CLK_SET_RATE_PARENT,
2355 .ops = &clk_branch2_ops,
2360 static struct clk_branch camss_vfe0_clk = {
2363 .enable_reg = 0x36a8,
2364 .enable_mask = BIT(0),
2365 .hw.init = &(struct clk_init_data){
2366 .name = "camss_vfe0_clk",
2367 .parent_names = (const char *[]){ "vfe0_clk_src" },
2369 .flags = CLK_SET_RATE_PARENT,
2370 .ops = &clk_branch2_ops,
2375 static struct clk_branch camss_vfe0_stream_clk = {
2378 .enable_reg = 0x3720,
2379 .enable_mask = BIT(0),
2380 .hw.init = &(struct clk_init_data){
2381 .name = "camss_vfe0_stream_clk",
2382 .parent_names = (const char *[]){ "vfe0_clk_src" },
2384 .flags = CLK_SET_RATE_PARENT,
2385 .ops = &clk_branch2_ops,
2390 static struct clk_branch camss_vfe0_ahb_clk = {
2393 .enable_reg = 0x3668,
2394 .enable_mask = BIT(0),
2395 .hw.init = &(struct clk_init_data){
2396 .name = "camss_vfe0_ahb_clk",
2397 .parent_names = (const char *[]){ "ahb_clk_src" },
2399 .flags = CLK_SET_RATE_PARENT,
2400 .ops = &clk_branch2_ops,
2405 static struct clk_branch camss_vfe1_clk = {
2408 .enable_reg = 0x36ac,
2409 .enable_mask = BIT(0),
2410 .hw.init = &(struct clk_init_data){
2411 .name = "camss_vfe1_clk",
2412 .parent_names = (const char *[]){ "vfe1_clk_src" },
2414 .flags = CLK_SET_RATE_PARENT,
2415 .ops = &clk_branch2_ops,
2420 static struct clk_branch camss_vfe1_stream_clk = {
2423 .enable_reg = 0x3724,
2424 .enable_mask = BIT(0),
2425 .hw.init = &(struct clk_init_data){
2426 .name = "camss_vfe1_stream_clk",
2427 .parent_names = (const char *[]){ "vfe1_clk_src" },
2429 .flags = CLK_SET_RATE_PARENT,
2430 .ops = &clk_branch2_ops,
2435 static struct clk_branch camss_vfe1_ahb_clk = {
2438 .enable_reg = 0x3678,
2439 .enable_mask = BIT(0),
2440 .hw.init = &(struct clk_init_data){
2441 .name = "camss_vfe1_ahb_clk",
2442 .parent_names = (const char *[]){ "ahb_clk_src" },
2444 .flags = CLK_SET_RATE_PARENT,
2445 .ops = &clk_branch2_ops,
2450 static struct clk_branch camss_csi_vfe0_clk = {
2453 .enable_reg = 0x3704,
2454 .enable_mask = BIT(0),
2455 .hw.init = &(struct clk_init_data){
2456 .name = "camss_csi_vfe0_clk",
2457 .parent_names = (const char *[]){ "vfe0_clk_src" },
2459 .flags = CLK_SET_RATE_PARENT,
2460 .ops = &clk_branch2_ops,
2465 static struct clk_branch camss_csi_vfe1_clk = {
2468 .enable_reg = 0x3714,
2469 .enable_mask = BIT(0),
2470 .hw.init = &(struct clk_init_data){
2471 .name = "camss_csi_vfe1_clk",
2472 .parent_names = (const char *[]){ "vfe1_clk_src" },
2474 .flags = CLK_SET_RATE_PARENT,
2475 .ops = &clk_branch2_ops,
2480 static struct clk_branch camss_cpp_vbif_ahb_clk = {
2483 .enable_reg = 0x36c8,
2484 .enable_mask = BIT(0),
2485 .hw.init = &(struct clk_init_data){
2486 .name = "camss_cpp_vbif_ahb_clk",
2487 .parent_names = (const char *[]){ "ahb_clk_src" },
2489 .flags = CLK_SET_RATE_PARENT,
2490 .ops = &clk_branch2_ops,
2495 static struct clk_branch camss_cpp_axi_clk = {
2498 .enable_reg = 0x36c4,
2499 .enable_mask = BIT(0),
2500 .hw.init = &(struct clk_init_data){
2501 .name = "camss_cpp_axi_clk",
2502 .parent_names = (const char *[]){ "axi_clk_src" },
2504 .flags = CLK_SET_RATE_PARENT,
2505 .ops = &clk_branch2_ops,
2510 static struct clk_branch camss_cpp_clk = {
2513 .enable_reg = 0x36b0,
2514 .enable_mask = BIT(0),
2515 .hw.init = &(struct clk_init_data){
2516 .name = "camss_cpp_clk",
2517 .parent_names = (const char *[]){ "cpp_clk_src" },
2519 .flags = CLK_SET_RATE_PARENT,
2520 .ops = &clk_branch2_ops,
2525 static struct clk_branch camss_cpp_ahb_clk = {
2528 .enable_reg = 0x36b4,
2529 .enable_mask = BIT(0),
2530 .hw.init = &(struct clk_init_data){
2531 .name = "camss_cpp_ahb_clk",
2532 .parent_names = (const char *[]){ "ahb_clk_src" },
2534 .flags = CLK_SET_RATE_PARENT,
2535 .ops = &clk_branch2_ops,
2540 static struct clk_branch camss_csi0_clk = {
2543 .enable_reg = 0x30b4,
2544 .enable_mask = BIT(0),
2545 .hw.init = &(struct clk_init_data){
2546 .name = "camss_csi0_clk",
2547 .parent_names = (const char *[]){ "csi0_clk_src" },
2549 .flags = CLK_SET_RATE_PARENT,
2550 .ops = &clk_branch2_ops,
2555 static struct clk_branch camss_csi0_ahb_clk = {
2558 .enable_reg = 0x30bc,
2559 .enable_mask = BIT(0),
2560 .hw.init = &(struct clk_init_data){
2561 .name = "camss_csi0_ahb_clk",
2562 .parent_names = (const char *[]){ "ahb_clk_src" },
2564 .flags = CLK_SET_RATE_PARENT,
2565 .ops = &clk_branch2_ops,
2570 static struct clk_branch camss_csi0phy_clk = {
2573 .enable_reg = 0x30c4,
2574 .enable_mask = BIT(0),
2575 .hw.init = &(struct clk_init_data){
2576 .name = "camss_csi0phy_clk",
2577 .parent_names = (const char *[]){ "csi0_clk_src" },
2579 .flags = CLK_SET_RATE_PARENT,
2580 .ops = &clk_branch2_ops,
2585 static struct clk_branch camss_csi0rdi_clk = {
2588 .enable_reg = 0x30d4,
2589 .enable_mask = BIT(0),
2590 .hw.init = &(struct clk_init_data){
2591 .name = "camss_csi0rdi_clk",
2592 .parent_names = (const char *[]){ "csi0_clk_src" },
2594 .flags = CLK_SET_RATE_PARENT,
2595 .ops = &clk_branch2_ops,
2600 static struct clk_branch camss_csi0pix_clk = {
2603 .enable_reg = 0x30e4,
2604 .enable_mask = BIT(0),
2605 .hw.init = &(struct clk_init_data){
2606 .name = "camss_csi0pix_clk",
2607 .parent_names = (const char *[]){ "csi0_clk_src" },
2609 .flags = CLK_SET_RATE_PARENT,
2610 .ops = &clk_branch2_ops,
2615 static struct clk_branch camss_csi1_clk = {
2618 .enable_reg = 0x3124,
2619 .enable_mask = BIT(0),
2620 .hw.init = &(struct clk_init_data){
2621 .name = "camss_csi1_clk",
2622 .parent_names = (const char *[]){ "csi1_clk_src" },
2624 .flags = CLK_SET_RATE_PARENT,
2625 .ops = &clk_branch2_ops,
2630 static struct clk_branch camss_csi1_ahb_clk = {
2633 .enable_reg = 0x3128,
2634 .enable_mask = BIT(0),
2635 .hw.init = &(struct clk_init_data){
2636 .name = "camss_csi1_ahb_clk",
2637 .parent_names = (const char *[]){ "ahb_clk_src" },
2639 .flags = CLK_SET_RATE_PARENT,
2640 .ops = &clk_branch2_ops,
2645 static struct clk_branch camss_csi1phy_clk = {
2648 .enable_reg = 0x3134,
2649 .enable_mask = BIT(0),
2650 .hw.init = &(struct clk_init_data){
2651 .name = "camss_csi1phy_clk",
2652 .parent_names = (const char *[]){ "csi1_clk_src" },
2654 .flags = CLK_SET_RATE_PARENT,
2655 .ops = &clk_branch2_ops,
2660 static struct clk_branch camss_csi1rdi_clk = {
2663 .enable_reg = 0x3144,
2664 .enable_mask = BIT(0),
2665 .hw.init = &(struct clk_init_data){
2666 .name = "camss_csi1rdi_clk",
2667 .parent_names = (const char *[]){ "csi1_clk_src" },
2669 .flags = CLK_SET_RATE_PARENT,
2670 .ops = &clk_branch2_ops,
2675 static struct clk_branch camss_csi1pix_clk = {
2678 .enable_reg = 0x3154,
2679 .enable_mask = BIT(0),
2680 .hw.init = &(struct clk_init_data){
2681 .name = "camss_csi1pix_clk",
2682 .parent_names = (const char *[]){ "csi1_clk_src" },
2684 .flags = CLK_SET_RATE_PARENT,
2685 .ops = &clk_branch2_ops,
2690 static struct clk_branch camss_csi2_clk = {
2693 .enable_reg = 0x3184,
2694 .enable_mask = BIT(0),
2695 .hw.init = &(struct clk_init_data){
2696 .name = "camss_csi2_clk",
2697 .parent_names = (const char *[]){ "csi2_clk_src" },
2699 .flags = CLK_SET_RATE_PARENT,
2700 .ops = &clk_branch2_ops,
2705 static struct clk_branch camss_csi2_ahb_clk = {
2708 .enable_reg = 0x3188,
2709 .enable_mask = BIT(0),
2710 .hw.init = &(struct clk_init_data){
2711 .name = "camss_csi2_ahb_clk",
2712 .parent_names = (const char *[]){ "ahb_clk_src" },
2714 .flags = CLK_SET_RATE_PARENT,
2715 .ops = &clk_branch2_ops,
2720 static struct clk_branch camss_csi2phy_clk = {
2723 .enable_reg = 0x3194,
2724 .enable_mask = BIT(0),
2725 .hw.init = &(struct clk_init_data){
2726 .name = "camss_csi2phy_clk",
2727 .parent_names = (const char *[]){ "csi2_clk_src" },
2729 .flags = CLK_SET_RATE_PARENT,
2730 .ops = &clk_branch2_ops,
2735 static struct clk_branch camss_csi2rdi_clk = {
2738 .enable_reg = 0x31a4,
2739 .enable_mask = BIT(0),
2740 .hw.init = &(struct clk_init_data){
2741 .name = "camss_csi2rdi_clk",
2742 .parent_names = (const char *[]){ "csi2_clk_src" },
2744 .flags = CLK_SET_RATE_PARENT,
2745 .ops = &clk_branch2_ops,
2750 static struct clk_branch camss_csi2pix_clk = {
2753 .enable_reg = 0x31b4,
2754 .enable_mask = BIT(0),
2755 .hw.init = &(struct clk_init_data){
2756 .name = "camss_csi2pix_clk",
2757 .parent_names = (const char *[]){ "csi2_clk_src" },
2759 .flags = CLK_SET_RATE_PARENT,
2760 .ops = &clk_branch2_ops,
2765 static struct clk_branch camss_csi3_clk = {
2768 .enable_reg = 0x31e4,
2769 .enable_mask = BIT(0),
2770 .hw.init = &(struct clk_init_data){
2771 .name = "camss_csi3_clk",
2772 .parent_names = (const char *[]){ "csi3_clk_src" },
2774 .flags = CLK_SET_RATE_PARENT,
2775 .ops = &clk_branch2_ops,
2780 static struct clk_branch camss_csi3_ahb_clk = {
2783 .enable_reg = 0x31e8,
2784 .enable_mask = BIT(0),
2785 .hw.init = &(struct clk_init_data){
2786 .name = "camss_csi3_ahb_clk",
2787 .parent_names = (const char *[]){ "ahb_clk_src" },
2789 .flags = CLK_SET_RATE_PARENT,
2790 .ops = &clk_branch2_ops,
2795 static struct clk_branch camss_csi3phy_clk = {
2798 .enable_reg = 0x31f4,
2799 .enable_mask = BIT(0),
2800 .hw.init = &(struct clk_init_data){
2801 .name = "camss_csi3phy_clk",
2802 .parent_names = (const char *[]){ "csi3_clk_src" },
2804 .flags = CLK_SET_RATE_PARENT,
2805 .ops = &clk_branch2_ops,
2810 static struct clk_branch camss_csi3rdi_clk = {
2813 .enable_reg = 0x3204,
2814 .enable_mask = BIT(0),
2815 .hw.init = &(struct clk_init_data){
2816 .name = "camss_csi3rdi_clk",
2817 .parent_names = (const char *[]){ "csi3_clk_src" },
2819 .flags = CLK_SET_RATE_PARENT,
2820 .ops = &clk_branch2_ops,
2825 static struct clk_branch camss_csi3pix_clk = {
2828 .enable_reg = 0x3214,
2829 .enable_mask = BIT(0),
2830 .hw.init = &(struct clk_init_data){
2831 .name = "camss_csi3pix_clk",
2832 .parent_names = (const char *[]){ "csi3_clk_src" },
2834 .flags = CLK_SET_RATE_PARENT,
2835 .ops = &clk_branch2_ops,
2840 static struct clk_branch camss_ispif_ahb_clk = {
2843 .enable_reg = 0x3224,
2844 .enable_mask = BIT(0),
2845 .hw.init = &(struct clk_init_data){
2846 .name = "camss_ispif_ahb_clk",
2847 .parent_names = (const char *[]){ "ahb_clk_src" },
2849 .flags = CLK_SET_RATE_PARENT,
2850 .ops = &clk_branch2_ops,
2855 static struct clk_branch fd_core_clk = {
2858 .enable_reg = 0x3b68,
2859 .enable_mask = BIT(0),
2860 .hw.init = &(struct clk_init_data){
2861 .name = "fd_core_clk",
2862 .parent_names = (const char *[]){ "fd_core_clk_src" },
2864 .flags = CLK_SET_RATE_PARENT,
2865 .ops = &clk_branch2_ops,
2870 static struct clk_branch fd_core_uar_clk = {
2873 .enable_reg = 0x3b6c,
2874 .enable_mask = BIT(0),
2875 .hw.init = &(struct clk_init_data){
2876 .name = "fd_core_uar_clk",
2877 .parent_names = (const char *[]){ "fd_core_clk_src" },
2879 .flags = CLK_SET_RATE_PARENT,
2880 .ops = &clk_branch2_ops,
2885 static struct clk_branch fd_ahb_clk = {
2886 .halt_reg = 0x3ba74,
2888 .enable_reg = 0x3ba74,
2889 .enable_mask = BIT(0),
2890 .hw.init = &(struct clk_init_data){
2891 .name = "fd_ahb_clk",
2892 .parent_names = (const char *[]){ "ahb_clk_src" },
2894 .flags = CLK_SET_RATE_PARENT,
2895 .ops = &clk_branch2_ops,
2900 static struct clk_hw *mmcc_msm8996_hws[] = {
2904 static struct gdsc mmagic_bimc_gdsc = {
2907 .name = "mmagic_bimc",
2909 .pwrsts = PWRSTS_OFF_ON,
2913 static struct gdsc mmagic_video_gdsc = {
2915 .gds_hw_ctrl = 0x120c,
2917 .name = "mmagic_video",
2919 .pwrsts = PWRSTS_OFF_ON,
2920 .flags = VOTABLE | ALWAYS_ON,
2923 static struct gdsc mmagic_mdss_gdsc = {
2925 .gds_hw_ctrl = 0x2480,
2927 .name = "mmagic_mdss",
2929 .pwrsts = PWRSTS_OFF_ON,
2930 .flags = VOTABLE | ALWAYS_ON,
2933 static struct gdsc mmagic_camss_gdsc = {
2935 .gds_hw_ctrl = 0x3c50,
2937 .name = "mmagic_camss",
2939 .pwrsts = PWRSTS_OFF_ON,
2940 .flags = VOTABLE | ALWAYS_ON,
2943 static struct gdsc venus_gdsc = {
2945 .cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
2950 .parent = &mmagic_video_gdsc.pd,
2951 .pwrsts = PWRSTS_OFF_ON,
2954 static struct gdsc venus_core0_gdsc = {
2956 .cxcs = (unsigned int []){ 0x1048 },
2959 .name = "venus_core0",
2961 .parent = &venus_gdsc.pd,
2962 .pwrsts = PWRSTS_OFF_ON,
2966 static struct gdsc venus_core1_gdsc = {
2968 .cxcs = (unsigned int []){ 0x104c },
2971 .name = "venus_core1",
2973 .parent = &venus_gdsc.pd,
2974 .pwrsts = PWRSTS_OFF_ON,
2978 static struct gdsc camss_gdsc = {
2980 .cxcs = (unsigned int []){ 0x36bc, 0x36c4 },
2985 .parent = &mmagic_camss_gdsc.pd,
2986 .pwrsts = PWRSTS_OFF_ON,
2989 static struct gdsc vfe0_gdsc = {
2991 .cxcs = (unsigned int []){ 0x36a8 },
2996 .parent = &camss_gdsc.pd,
2997 .pwrsts = PWRSTS_OFF_ON,
3000 static struct gdsc vfe1_gdsc = {
3002 .cxcs = (unsigned int []){ 0x36ac },
3007 .parent = &camss_gdsc.pd,
3008 .pwrsts = PWRSTS_OFF_ON,
3011 static struct gdsc jpeg_gdsc = {
3013 .cxcs = (unsigned int []){ 0x35a8, 0x35b0, 0x35c0, 0x35b8 },
3018 .parent = &camss_gdsc.pd,
3019 .pwrsts = PWRSTS_OFF_ON,
3022 static struct gdsc cpp_gdsc = {
3024 .cxcs = (unsigned int []){ 0x36b0 },
3029 .parent = &camss_gdsc.pd,
3030 .pwrsts = PWRSTS_OFF_ON,
3033 static struct gdsc fd_gdsc = {
3035 .cxcs = (unsigned int []){ 0x3b68, 0x3b6c },
3040 .parent = &camss_gdsc.pd,
3041 .pwrsts = PWRSTS_OFF_ON,
3044 static struct gdsc mdss_gdsc = {
3046 .cxcs = (unsigned int []){ 0x2310, 0x231c },
3051 .parent = &mmagic_mdss_gdsc.pd,
3052 .pwrsts = PWRSTS_OFF_ON,
3055 static struct gdsc gpu_gdsc = {
3057 .gds_hw_ctrl = 0x4038,
3061 .pwrsts = PWRSTS_OFF_ON,
3065 static struct gdsc gpu_gx_gdsc = {
3067 .clamp_io_ctrl = 0x4300,
3068 .cxcs = (unsigned int []){ 0x4028 },
3073 .pwrsts = PWRSTS_OFF_ON,
3074 .parent = &gpu_gdsc.pd,
3076 .supply = "vdd-gfx",
3079 static struct clk_regmap *mmcc_msm8996_clocks[] = {
3080 [MMPLL0_EARLY] = &mmpll0_early.clkr,
3081 [MMPLL0_PLL] = &mmpll0.clkr,
3082 [MMPLL1_EARLY] = &mmpll1_early.clkr,
3083 [MMPLL1_PLL] = &mmpll1.clkr,
3084 [MMPLL2_EARLY] = &mmpll2_early.clkr,
3085 [MMPLL2_PLL] = &mmpll2.clkr,
3086 [MMPLL3_EARLY] = &mmpll3_early.clkr,
3087 [MMPLL3_PLL] = &mmpll3.clkr,
3088 [MMPLL4_EARLY] = &mmpll4_early.clkr,
3089 [MMPLL4_PLL] = &mmpll4.clkr,
3090 [MMPLL5_EARLY] = &mmpll5_early.clkr,
3091 [MMPLL5_PLL] = &mmpll5.clkr,
3092 [MMPLL8_EARLY] = &mmpll8_early.clkr,
3093 [MMPLL8_PLL] = &mmpll8.clkr,
3094 [MMPLL9_EARLY] = &mmpll9_early.clkr,
3095 [MMPLL9_PLL] = &mmpll9.clkr,
3096 [AHB_CLK_SRC] = &ahb_clk_src.clkr,
3097 [AXI_CLK_SRC] = &axi_clk_src.clkr,
3098 [MAXI_CLK_SRC] = &maxi_clk_src.clkr,
3099 [GFX3D_CLK_SRC] = &gfx3d_clk_src.rcg.clkr,
3100 [RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,
3101 [ISENSE_CLK_SRC] = &isense_clk_src.clkr,
3102 [RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,
3103 [VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
3104 [VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr,
3105 [VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr,
3106 [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
3107 [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
3108 [MDP_CLK_SRC] = &mdp_clk_src.clkr,
3109 [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
3110 [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
3111 [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
3112 [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
3113 [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
3114 [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
3115 [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
3116 [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
3117 [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
3118 [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
3119 [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
3120 [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
3121 [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
3122 [CCI_CLK_SRC] = &cci_clk_src.clkr,
3123 [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
3124 [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
3125 [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
3126 [CSIPHY0_3P_CLK_SRC] = &csiphy0_3p_clk_src.clkr,
3127 [CSIPHY1_3P_CLK_SRC] = &csiphy1_3p_clk_src.clkr,
3128 [CSIPHY2_3P_CLK_SRC] = &csiphy2_3p_clk_src.clkr,
3129 [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
3130 [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
3131 [JPEG_DMA_CLK_SRC] = &jpeg_dma_clk_src.clkr,
3132 [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
3133 [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
3134 [CPP_CLK_SRC] = &cpp_clk_src.clkr,
3135 [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
3136 [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
3137 [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
3138 [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
3139 [FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
3140 [MMSS_MMAGIC_AHB_CLK] = &mmss_mmagic_ahb_clk.clkr,
3141 [MMSS_MMAGIC_CFG_AHB_CLK] = &mmss_mmagic_cfg_ahb_clk.clkr,
3142 [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
3143 [MMSS_MISC_CXO_CLK] = &mmss_misc_cxo_clk.clkr,
3144 [MMSS_MMAGIC_MAXI_CLK] = &mmss_mmagic_maxi_clk.clkr,
3145 [MMAGIC_CAMSS_AXI_CLK] = &mmagic_camss_axi_clk.clkr,
3146 [MMAGIC_CAMSS_NOC_CFG_AHB_CLK] = &mmagic_camss_noc_cfg_ahb_clk.clkr,
3147 [SMMU_VFE_AHB_CLK] = &smmu_vfe_ahb_clk.clkr,
3148 [SMMU_VFE_AXI_CLK] = &smmu_vfe_axi_clk.clkr,
3149 [SMMU_CPP_AHB_CLK] = &smmu_cpp_ahb_clk.clkr,
3150 [SMMU_CPP_AXI_CLK] = &smmu_cpp_axi_clk.clkr,
3151 [SMMU_JPEG_AHB_CLK] = &smmu_jpeg_ahb_clk.clkr,
3152 [SMMU_JPEG_AXI_CLK] = &smmu_jpeg_axi_clk.clkr,
3153 [MMAGIC_MDSS_AXI_CLK] = &mmagic_mdss_axi_clk.clkr,
3154 [MMAGIC_MDSS_NOC_CFG_AHB_CLK] = &mmagic_mdss_noc_cfg_ahb_clk.clkr,
3155 [SMMU_ROT_AHB_CLK] = &smmu_rot_ahb_clk.clkr,
3156 [SMMU_ROT_AXI_CLK] = &smmu_rot_axi_clk.clkr,
3157 [SMMU_MDP_AHB_CLK] = &smmu_mdp_ahb_clk.clkr,
3158 [SMMU_MDP_AXI_CLK] = &smmu_mdp_axi_clk.clkr,
3159 [MMAGIC_VIDEO_AXI_CLK] = &mmagic_video_axi_clk.clkr,
3160 [MMAGIC_VIDEO_NOC_CFG_AHB_CLK] = &mmagic_video_noc_cfg_ahb_clk.clkr,
3161 [SMMU_VIDEO_AHB_CLK] = &smmu_video_ahb_clk.clkr,
3162 [SMMU_VIDEO_AXI_CLK] = &smmu_video_axi_clk.clkr,
3163 [MMAGIC_BIMC_NOC_CFG_AHB_CLK] = &mmagic_bimc_noc_cfg_ahb_clk.clkr,
3164 [GPU_GX_GFX3D_CLK] = &gpu_gx_gfx3d_clk.clkr,
3165 [GPU_GX_RBBMTIMER_CLK] = &gpu_gx_rbbmtimer_clk.clkr,
3166 [GPU_AHB_CLK] = &gpu_ahb_clk.clkr,
3167 [GPU_AON_ISENSE_CLK] = &gpu_aon_isense_clk.clkr,
3168 [VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr,
3169 [VMEM_AHB_CLK] = &vmem_ahb_clk.clkr,
3170 [MMSS_RBCPR_CLK] = &mmss_rbcpr_clk.clkr,
3171 [MMSS_RBCPR_AHB_CLK] = &mmss_rbcpr_ahb_clk.clkr,
3172 [VIDEO_CORE_CLK] = &video_core_clk.clkr,
3173 [VIDEO_AXI_CLK] = &video_axi_clk.clkr,
3174 [VIDEO_MAXI_CLK] = &video_maxi_clk.clkr,
3175 [VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
3176 [VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
3177 [VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr,
3178 [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
3179 [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
3180 [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
3181 [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
3182 [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
3183 [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
3184 [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
3185 [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
3186 [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
3187 [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
3188 [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
3189 [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
3190 [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
3191 [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
3192 [CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
3193 [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
3194 [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
3195 [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
3196 [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
3197 [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
3198 [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
3199 [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
3200 [CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
3201 [CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
3202 [CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
3203 [CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
3204 [CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
3205 [CAMSS_CSIPHY0_3P_CLK] = &camss_csiphy0_3p_clk.clkr,
3206 [CAMSS_CSIPHY1_3P_CLK] = &camss_csiphy1_3p_clk.clkr,
3207 [CAMSS_CSIPHY2_3P_CLK] = &camss_csiphy2_3p_clk.clkr,
3208 [CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
3209 [CAMSS_JPEG2_CLK] = &camss_jpeg2_clk.clkr,
3210 [CAMSS_JPEG_DMA_CLK] = &camss_jpeg_dma_clk.clkr,
3211 [CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
3212 [CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
3213 [CAMSS_VFE_AHB_CLK] = &camss_vfe_ahb_clk.clkr,
3214 [CAMSS_VFE_AXI_CLK] = &camss_vfe_axi_clk.clkr,
3215 [CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
3216 [CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
3217 [CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
3218 [CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
3219 [CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
3220 [CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
3221 [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
3222 [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
3223 [CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
3224 [CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
3225 [CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
3226 [CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
3227 [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
3228 [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
3229 [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
3230 [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
3231 [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
3232 [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
3233 [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
3234 [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
3235 [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
3236 [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
3237 [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
3238 [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
3239 [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
3240 [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
3241 [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
3242 [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
3243 [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
3244 [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
3245 [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
3246 [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
3247 [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
3248 [FD_CORE_CLK] = &fd_core_clk.clkr,
3249 [FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
3250 [FD_AHB_CLK] = &fd_ahb_clk.clkr,
3253 static struct gdsc *mmcc_msm8996_gdscs[] = {
3254 [MMAGIC_BIMC_GDSC] = &mmagic_bimc_gdsc,
3255 [MMAGIC_VIDEO_GDSC] = &mmagic_video_gdsc,
3256 [MMAGIC_MDSS_GDSC] = &mmagic_mdss_gdsc,
3257 [MMAGIC_CAMSS_GDSC] = &mmagic_camss_gdsc,
3258 [VENUS_GDSC] = &venus_gdsc,
3259 [VENUS_CORE0_GDSC] = &venus_core0_gdsc,
3260 [VENUS_CORE1_GDSC] = &venus_core1_gdsc,
3261 [CAMSS_GDSC] = &camss_gdsc,
3262 [VFE0_GDSC] = &vfe0_gdsc,
3263 [VFE1_GDSC] = &vfe1_gdsc,
3264 [JPEG_GDSC] = &jpeg_gdsc,
3265 [CPP_GDSC] = &cpp_gdsc,
3266 [FD_GDSC] = &fd_gdsc,
3267 [MDSS_GDSC] = &mdss_gdsc,
3268 [GPU_GDSC] = &gpu_gdsc,
3269 [GPU_GX_GDSC] = &gpu_gx_gdsc,
3272 static const struct qcom_reset_map mmcc_msm8996_resets[] = {
3273 [MMAGICAHB_BCR] = { 0x5020 },
3274 [MMAGIC_CFG_BCR] = { 0x5050 },
3275 [MISC_BCR] = { 0x5010 },
3276 [BTO_BCR] = { 0x5030 },
3277 [MMAGICAXI_BCR] = { 0x5060 },
3278 [MMAGICMAXI_BCR] = { 0x5070 },
3279 [DSA_BCR] = { 0x50a0 },
3280 [MMAGIC_CAMSS_BCR] = { 0x3c40 },
3281 [THROTTLE_CAMSS_BCR] = { 0x3c30 },
3282 [SMMU_VFE_BCR] = { 0x3c00 },
3283 [SMMU_CPP_BCR] = { 0x3c10 },
3284 [SMMU_JPEG_BCR] = { 0x3c20 },
3285 [MMAGIC_MDSS_BCR] = { 0x2470 },
3286 [THROTTLE_MDSS_BCR] = { 0x2460 },
3287 [SMMU_ROT_BCR] = { 0x2440 },
3288 [SMMU_MDP_BCR] = { 0x2450 },
3289 [MMAGIC_VIDEO_BCR] = { 0x1190 },
3290 [THROTTLE_VIDEO_BCR] = { 0x1180 },
3291 [SMMU_VIDEO_BCR] = { 0x1170 },
3292 [MMAGIC_BIMC_BCR] = { 0x5290 },
3293 [GPU_GX_BCR] = { 0x4020 },
3294 [GPU_BCR] = { 0x4030 },
3295 [GPU_AON_BCR] = { 0x4040 },
3296 [VMEM_BCR] = { 0x1200 },
3297 [MMSS_RBCPR_BCR] = { 0x4080 },
3298 [VIDEO_BCR] = { 0x1020 },
3299 [MDSS_BCR] = { 0x2300 },
3300 [CAMSS_TOP_BCR] = { 0x3480 },
3301 [CAMSS_AHB_BCR] = { 0x3488 },
3302 [CAMSS_MICRO_BCR] = { 0x3490 },
3303 [CAMSS_CCI_BCR] = { 0x3340 },
3304 [CAMSS_PHY0_BCR] = { 0x3020 },
3305 [CAMSS_PHY1_BCR] = { 0x3050 },
3306 [CAMSS_PHY2_BCR] = { 0x3080 },
3307 [CAMSS_CSIPHY0_3P_BCR] = { 0x3230 },
3308 [CAMSS_CSIPHY1_3P_BCR] = { 0x3250 },
3309 [CAMSS_CSIPHY2_3P_BCR] = { 0x3270 },
3310 [CAMSS_JPEG_BCR] = { 0x35a0 },
3311 [CAMSS_VFE_BCR] = { 0x36a0 },
3312 [CAMSS_VFE0_BCR] = { 0x3660 },
3313 [CAMSS_VFE1_BCR] = { 0x3670 },
3314 [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
3315 [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
3316 [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
3317 [CAMSS_CPP_BCR] = { 0x36d0 },
3318 [CAMSS_CSI0_BCR] = { 0x30b0 },
3319 [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
3320 [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
3321 [CAMSS_CSI1_BCR] = { 0x3120 },
3322 [CAMSS_CSI1RDI_BCR] = { 0x3140 },
3323 [CAMSS_CSI1PIX_BCR] = { 0x3150 },
3324 [CAMSS_CSI2_BCR] = { 0x3180 },
3325 [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
3326 [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
3327 [CAMSS_CSI3_BCR] = { 0x31e0 },
3328 [CAMSS_CSI3RDI_BCR] = { 0x3200 },
3329 [CAMSS_CSI3PIX_BCR] = { 0x3210 },
3330 [CAMSS_ISPIF_BCR] = { 0x3220 },
3331 [FD_BCR] = { 0x3b60 },
3332 [MMSS_SPDM_RM_BCR] = { 0x300 },
3335 static const struct regmap_config mmcc_msm8996_regmap_config = {
3339 .max_register = 0xb008,
3343 static const struct qcom_cc_desc mmcc_msm8996_desc = {
3344 .config = &mmcc_msm8996_regmap_config,
3345 .clks = mmcc_msm8996_clocks,
3346 .num_clks = ARRAY_SIZE(mmcc_msm8996_clocks),
3347 .resets = mmcc_msm8996_resets,
3348 .num_resets = ARRAY_SIZE(mmcc_msm8996_resets),
3349 .gdscs = mmcc_msm8996_gdscs,
3350 .num_gdscs = ARRAY_SIZE(mmcc_msm8996_gdscs),
3351 .clk_hws = mmcc_msm8996_hws,
3352 .num_clk_hws = ARRAY_SIZE(mmcc_msm8996_hws),
3355 static const struct of_device_id mmcc_msm8996_match_table[] = {
3356 { .compatible = "qcom,mmcc-msm8996" },
3359 MODULE_DEVICE_TABLE(of, mmcc_msm8996_match_table);
3361 static int mmcc_msm8996_probe(struct platform_device *pdev)
3363 struct regmap *regmap;
3365 regmap = qcom_cc_map(pdev, &mmcc_msm8996_desc);
3367 return PTR_ERR(regmap);
3369 /* Disable the AHB DCD */
3370 regmap_update_bits(regmap, 0x50d8, BIT(31), 0);
3371 /* Disable the NoC FSM for mmss_mmagic_cfg_ahb_clk */
3372 regmap_update_bits(regmap, 0x5054, BIT(15), 0);
3374 return qcom_cc_really_probe(pdev, &mmcc_msm8996_desc, regmap);
3377 static struct platform_driver mmcc_msm8996_driver = {
3378 .probe = mmcc_msm8996_probe,
3380 .name = "mmcc-msm8996",
3381 .of_match_table = mmcc_msm8996_match_table,
3384 module_platform_driver(mmcc_msm8996_driver);
3386 MODULE_DESCRIPTION("QCOM MMCC MSM8996 Driver");
3387 MODULE_LICENSE("GPL v2");
3388 MODULE_ALIAS("platform:mmcc-msm8996");