1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
18 #include "clk-regmap.h"
21 #define CX_GMU_CBCR_SLEEP_MASK 0xf
22 #define CX_GMU_CBCR_SLEEP_SHIFT 4
23 #define CX_GMU_CBCR_WAKE_MASK 0xf
24 #define CX_GMU_CBCR_WAKE_SHIFT 8
25 #define CLK_DIS_WAIT_SHIFT 12
26 #define CLK_DIS_WAIT_MASK (0xf << CLK_DIS_WAIT_SHIFT)
32 P_GPU_CC_PLL1_OUT_MAIN,
35 static const struct alpha_pll_config gpu_cc_pll1_config = {
40 static struct clk_alpha_pll gpu_cc_pll1 = {
42 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
44 .hw.init = &(struct clk_init_data){
45 .name = "gpu_cc_pll1",
46 .parent_data = &(const struct clk_parent_data){
47 .fw_name = "bi_tcxo", .name = "bi_tcxo",
50 .ops = &clk_alpha_pll_fabia_ops,
55 static const struct parent_map gpu_cc_parent_map_0[] = {
57 { P_GPU_CC_PLL1_OUT_MAIN, 3 },
58 { P_GPLL0_OUT_MAIN, 5 },
59 { P_GPLL0_OUT_MAIN_DIV, 6 },
62 static const struct clk_parent_data gpu_cc_parent_data_0[] = {
63 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
64 { .hw = &gpu_cc_pll1.clkr.hw },
65 { .fw_name = "gcc_gpu_gpll0_clk_src", .name = "gcc_gpu_gpll0_clk_src" },
66 { .fw_name = "gcc_gpu_gpll0_div_clk_src", .name = "gcc_gpu_gpll0_div_clk_src" },
69 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
70 F(19200000, P_BI_TCXO, 1, 0, 0),
71 F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
72 F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
76 static struct clk_rcg2 gpu_cc_gmu_clk_src = {
80 .parent_map = gpu_cc_parent_map_0,
81 .freq_tbl = ftbl_gpu_cc_gmu_clk_src,
82 .clkr.hw.init = &(struct clk_init_data){
83 .name = "gpu_cc_gmu_clk_src",
84 .parent_data = gpu_cc_parent_data_0,
85 .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
86 .ops = &clk_rcg2_shared_ops,
90 static struct clk_branch gpu_cc_cx_gmu_clk = {
92 .halt_check = BRANCH_HALT,
95 .enable_mask = BIT(0),
96 .hw.init = &(struct clk_init_data){
97 .name = "gpu_cc_cx_gmu_clk",
98 .parent_hws = (const struct clk_hw*[]){
99 &gpu_cc_gmu_clk_src.clkr.hw,
102 .flags = CLK_SET_RATE_PARENT,
103 .ops = &clk_branch2_ops,
108 static struct clk_branch gpu_cc_cxo_clk = {
110 .halt_check = BRANCH_HALT,
112 .enable_reg = 0x109c,
113 .enable_mask = BIT(0),
114 .hw.init = &(struct clk_init_data){
115 .name = "gpu_cc_cxo_clk",
116 .ops = &clk_branch2_ops,
121 static struct gdsc gpu_cx_gdsc = {
123 .gds_hw_ctrl = 0x1540,
125 .name = "gpu_cx_gdsc",
127 .pwrsts = PWRSTS_OFF_ON,
131 static struct gdsc gpu_gx_gdsc = {
133 .clamp_io_ctrl = 0x1508,
135 .name = "gpu_gx_gdsc",
136 .power_on = gdsc_gx_do_nothing_enable,
138 .pwrsts = PWRSTS_OFF_ON,
139 .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
142 static struct clk_regmap *gpu_cc_sdm845_clocks[] = {
143 [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
144 [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
145 [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
146 [GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
149 static struct gdsc *gpu_cc_sdm845_gdscs[] = {
150 [GPU_CX_GDSC] = &gpu_cx_gdsc,
151 [GPU_GX_GDSC] = &gpu_gx_gdsc,
154 static const struct regmap_config gpu_cc_sdm845_regmap_config = {
158 .max_register = 0x8008,
162 static const struct qcom_cc_desc gpu_cc_sdm845_desc = {
163 .config = &gpu_cc_sdm845_regmap_config,
164 .clks = gpu_cc_sdm845_clocks,
165 .num_clks = ARRAY_SIZE(gpu_cc_sdm845_clocks),
166 .gdscs = gpu_cc_sdm845_gdscs,
167 .num_gdscs = ARRAY_SIZE(gpu_cc_sdm845_gdscs),
170 static const struct of_device_id gpu_cc_sdm845_match_table[] = {
171 { .compatible = "qcom,sdm845-gpucc" },
174 MODULE_DEVICE_TABLE(of, gpu_cc_sdm845_match_table);
176 static int gpu_cc_sdm845_probe(struct platform_device *pdev)
178 struct regmap *regmap;
179 unsigned int value, mask;
181 regmap = qcom_cc_map(pdev, &gpu_cc_sdm845_desc);
183 return PTR_ERR(regmap);
185 clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
188 * Configure gpu_cc_cx_gmu_clk with recommended
189 * wakeup/sleep settings
191 mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
192 mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
193 value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
194 regmap_update_bits(regmap, 0x1098, mask, value);
196 /* Configure clk_dis_wait for gpu_cx_gdsc */
197 regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK,
198 8 << CLK_DIS_WAIT_SHIFT);
200 return qcom_cc_really_probe(pdev, &gpu_cc_sdm845_desc, regmap);
203 static struct platform_driver gpu_cc_sdm845_driver = {
204 .probe = gpu_cc_sdm845_probe,
206 .name = "sdm845-gpucc",
207 .of_match_table = gpu_cc_sdm845_match_table,
211 static int __init gpu_cc_sdm845_init(void)
213 return platform_driver_register(&gpu_cc_sdm845_driver);
215 subsys_initcall(gpu_cc_sdm845_init);
217 static void __exit gpu_cc_sdm845_exit(void)
219 platform_driver_unregister(&gpu_cc_sdm845_driver);
221 module_exit(gpu_cc_sdm845_exit);
223 MODULE_DESCRIPTION("QTI GPUCC SDM845 Driver");
224 MODULE_LICENSE("GPL v2");