1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
6 #include <linux/bitops.h>
7 #include <linux/delay.h>
9 #include <linux/export.h>
10 #include <linux/jiffies.h>
11 #include <linux/kernel.h>
12 #include <linux/ktime.h>
13 #include <linux/pm_domain.h>
14 #include <linux/regmap.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/reset-controller.h>
17 #include <linux/slab.h>
20 #define PWR_ON_MASK BIT(31)
21 #define EN_REST_WAIT_MASK GENMASK_ULL(23, 20)
22 #define EN_FEW_WAIT_MASK GENMASK_ULL(19, 16)
23 #define CLK_DIS_WAIT_MASK GENMASK_ULL(15, 12)
24 #define SW_OVERRIDE_MASK BIT(2)
25 #define HW_CONTROL_MASK BIT(1)
26 #define SW_COLLAPSE_MASK BIT(0)
27 #define GMEM_CLAMP_IO_MASK BIT(0)
28 #define GMEM_RESET_MASK BIT(4)
31 #define GDSC_POWER_UP_COMPLETE BIT(16)
32 #define GDSC_POWER_DOWN_COMPLETE BIT(15)
33 #define GDSC_RETAIN_FF_ENABLE BIT(11)
34 #define CFG_GDSCR_OFFSET 0x4
36 /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
37 #define EN_REST_WAIT_VAL (0x2 << 20)
38 #define EN_FEW_WAIT_VAL (0x8 << 16)
39 #define CLK_DIS_WAIT_VAL (0x2 << 12)
41 #define RETAIN_MEM BIT(14)
42 #define RETAIN_PERIPH BIT(13)
44 #define TIMEOUT_US 500
46 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
53 /* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
54 static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
60 if (sc->flags & POLL_CFG_GDSCR)
61 reg = sc->gdscr + CFG_GDSCR_OFFSET;
62 else if (sc->gds_hw_ctrl)
63 reg = sc->gds_hw_ctrl;
67 ret = regmap_read(sc->regmap, reg, &val);
71 if (sc->flags & POLL_CFG_GDSCR) {
74 return !!(val & GDSC_POWER_UP_COMPLETE);
76 return !!(val & GDSC_POWER_DOWN_COMPLETE);
82 return !!(val & PWR_ON_MASK);
84 return !(val & PWR_ON_MASK);
90 static int gdsc_hwctrl(struct gdsc *sc, bool en)
92 u32 val = en ? HW_CONTROL_MASK : 0;
94 return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
97 static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
103 if (gdsc_check_status(sc, status))
105 } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
107 if (gdsc_check_status(sc, status))
113 static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
116 u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK;
118 if (status == GDSC_ON && sc->rsupply) {
119 ret = regulator_enable(sc->rsupply);
124 ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
128 /* If disabling votable gdscs, don't poll on status */
129 if ((sc->flags & VOTABLE) && status == GDSC_OFF) {
131 * Add a short delay here to ensure that an enable
132 * right after it was disabled does not put it in an
139 if (sc->gds_hw_ctrl) {
141 * The gds hw controller asserts/de-asserts the status bit soon
142 * after it receives a power on/off request from a master.
143 * The controller then takes around 8 xo cycles to start its
144 * internal state machine and update the status bit. During
145 * this time, the status bit does not reflect the true status
147 * Add a delay of 1 us between writing to the SW_COLLAPSE bit
148 * and polling the status bit.
153 ret = gdsc_poll_status(sc, status);
154 WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n");
156 if (!ret && status == GDSC_OFF && sc->rsupply) {
157 ret = regulator_disable(sc->rsupply);
165 static inline int gdsc_deassert_reset(struct gdsc *sc)
169 for (i = 0; i < sc->reset_count; i++)
170 sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
174 static inline int gdsc_assert_reset(struct gdsc *sc)
178 for (i = 0; i < sc->reset_count; i++)
179 sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
183 static inline void gdsc_force_mem_on(struct gdsc *sc)
186 u32 mask = RETAIN_MEM;
188 if (!(sc->flags & NO_RET_PERIPH))
189 mask |= RETAIN_PERIPH;
191 for (i = 0; i < sc->cxc_count; i++)
192 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
195 static inline void gdsc_clear_mem_on(struct gdsc *sc)
198 u32 mask = RETAIN_MEM;
200 if (!(sc->flags & NO_RET_PERIPH))
201 mask |= RETAIN_PERIPH;
203 for (i = 0; i < sc->cxc_count; i++)
204 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
207 static inline void gdsc_deassert_clamp_io(struct gdsc *sc)
209 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
210 GMEM_CLAMP_IO_MASK, 0);
213 static inline void gdsc_assert_clamp_io(struct gdsc *sc)
215 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
216 GMEM_CLAMP_IO_MASK, 1);
219 static inline void gdsc_assert_reset_aon(struct gdsc *sc)
221 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
224 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
228 static void gdsc_retain_ff_on(struct gdsc *sc)
230 u32 mask = GDSC_RETAIN_FF_ENABLE;
232 regmap_update_bits(sc->regmap, sc->gdscr, mask, mask);
235 static int gdsc_enable(struct generic_pm_domain *domain)
237 struct gdsc *sc = domain_to_gdsc(domain);
240 if (sc->pwrsts == PWRSTS_ON)
241 return gdsc_deassert_reset(sc);
243 if (sc->flags & SW_RESET) {
244 gdsc_assert_reset(sc);
246 gdsc_deassert_reset(sc);
249 if (sc->flags & CLAMP_IO) {
250 if (sc->flags & AON_RESET)
251 gdsc_assert_reset_aon(sc);
252 gdsc_deassert_clamp_io(sc);
255 ret = gdsc_toggle_logic(sc, GDSC_ON);
259 if (sc->pwrsts & PWRSTS_OFF)
260 gdsc_force_mem_on(sc);
263 * If clocks to this power domain were already on, they will take an
264 * additional 4 clock cycles to re-enable after the power domain is
265 * enabled. Delay to account for this. A delay is also needed to ensure
266 * clocks are not enabled within 400ns of enabling power to the
271 /* Turn on HW trigger mode if supported */
272 if (sc->flags & HW_CTRL) {
273 ret = gdsc_hwctrl(sc, true);
277 * Wait for the GDSC to go through a power down and
278 * up cycle. In case a firmware ends up polling status
279 * bits for the gdsc, it might read an 'on' status before
280 * the GDSC can finish the power cycle.
281 * We wait 1us before returning to ensure the firmware
282 * can't immediately poll the status bits.
287 if (sc->flags & RETAIN_FF_ENABLE)
288 gdsc_retain_ff_on(sc);
293 static int gdsc_disable(struct generic_pm_domain *domain)
295 struct gdsc *sc = domain_to_gdsc(domain);
298 if (sc->pwrsts == PWRSTS_ON)
299 return gdsc_assert_reset(sc);
301 /* Turn off HW trigger mode if supported */
302 if (sc->flags & HW_CTRL) {
303 ret = gdsc_hwctrl(sc, false);
307 * Wait for the GDSC to go through a power down and
308 * up cycle. In case we end up polling status
309 * bits for the gdsc before the power cycle is completed
310 * it might read an 'on' status wrongly.
314 ret = gdsc_poll_status(sc, GDSC_ON);
319 if (sc->pwrsts & PWRSTS_OFF)
320 gdsc_clear_mem_on(sc);
322 ret = gdsc_toggle_logic(sc, GDSC_OFF);
326 if (sc->flags & CLAMP_IO)
327 gdsc_assert_clamp_io(sc);
332 static int gdsc_init(struct gdsc *sc)
338 * Disable HW trigger: collapse/restore occur based on registers writes.
339 * Disable SW override: Use hardware state-machine for sequencing.
340 * Configure wait time between states.
342 mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
343 EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
344 val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
345 ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
349 /* Force gdsc ON if only ON state is supported */
350 if (sc->pwrsts == PWRSTS_ON) {
351 ret = gdsc_toggle_logic(sc, GDSC_ON);
356 on = gdsc_check_status(sc, GDSC_ON);
361 * Votable GDSCs can be ON due to Vote from other masters.
362 * If a Votable GDSC is ON, make sure we have a Vote.
364 if ((sc->flags & VOTABLE) && on)
365 gdsc_enable(&sc->pd);
368 * Make sure the retain bit is set if the GDSC is already on, otherwise
369 * we end up turning off the GDSC and destroying all the register
370 * contents that we thought we were saving.
372 if ((sc->flags & RETAIN_FF_ENABLE) && on)
373 gdsc_retain_ff_on(sc);
375 /* If ALWAYS_ON GDSCs are not ON, turn them ON */
376 if (sc->flags & ALWAYS_ON) {
378 gdsc_enable(&sc->pd);
380 sc->pd.flags |= GENPD_FLAG_ALWAYS_ON;
383 if (on || (sc->pwrsts & PWRSTS_RET))
384 gdsc_force_mem_on(sc);
386 gdsc_clear_mem_on(sc);
388 if (!sc->pd.power_off)
389 sc->pd.power_off = gdsc_disable;
390 if (!sc->pd.power_on)
391 sc->pd.power_on = gdsc_enable;
392 pm_genpd_init(&sc->pd, NULL, !on);
397 int gdsc_register(struct gdsc_desc *desc,
398 struct reset_controller_dev *rcdev, struct regmap *regmap)
401 struct genpd_onecell_data *data;
402 struct device *dev = desc->dev;
403 struct gdsc **scs = desc->scs;
404 size_t num = desc->num;
406 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
410 data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
415 for (i = 0; i < num; i++) {
416 if (!scs[i] || !scs[i]->supply)
419 scs[i]->rsupply = devm_regulator_get(dev, scs[i]->supply);
420 if (IS_ERR(scs[i]->rsupply))
421 return PTR_ERR(scs[i]->rsupply);
424 data->num_domains = num;
425 for (i = 0; i < num; i++) {
428 scs[i]->regmap = regmap;
429 scs[i]->rcdev = rcdev;
430 ret = gdsc_init(scs[i]);
433 data->domains[i] = &scs[i]->pd;
437 for (i = 0; i < num; i++) {
441 pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
444 return of_genpd_add_provider_onecell(dev->of_node, data);
447 void gdsc_unregister(struct gdsc_desc *desc)
450 struct device *dev = desc->dev;
451 struct gdsc **scs = desc->scs;
452 size_t num = desc->num;
454 /* Remove subdomains */
455 for (i = 0; i < num; i++) {
459 pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
461 of_genpd_del_provider(dev->of_node);
465 * On SDM845+ the GPU GX domain is *almost* entirely controlled by the GMU
466 * running in the CX domain so the CPU doesn't need to know anything about the
467 * GX domain EXCEPT....
469 * Hardware constraints dictate that the GX be powered down before the CX. If
470 * the GMU crashes it could leave the GX on. In order to successfully bring back
471 * the device the CPU needs to disable the GX headswitch. There being no sane
472 * way to reach in and touch that register from deep inside the GPU driver we
473 * need to set up the infrastructure to be able to ensure that the GPU can
474 * ensure that the GX is off during this super special case. We do this by
475 * defining a GX gdsc with a dummy enable function and a "default" disable
478 * This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU
479 * driver. During power up, nothing will happen from the CPU (and the GMU will
480 * power up normally but during power down this will ensure that the GX domain
481 * is *really* off - this gives us a semi standard way of doing what we need.
483 int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain)
485 /* Do nothing but give genpd the impression that we were successful */
488 EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable);