1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015, 2017-2018, 2022, The Linux Foundation. All rights reserved.
6 #include <linux/bitops.h>
7 #include <linux/delay.h>
9 #include <linux/export.h>
10 #include <linux/jiffies.h>
11 #include <linux/kernel.h>
12 #include <linux/ktime.h>
13 #include <linux/pm_domain.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regmap.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/reset-controller.h>
18 #include <linux/slab.h>
21 #define PWR_ON_MASK BIT(31)
22 #define EN_REST_WAIT_MASK GENMASK_ULL(23, 20)
23 #define EN_FEW_WAIT_MASK GENMASK_ULL(19, 16)
24 #define CLK_DIS_WAIT_MASK GENMASK_ULL(15, 12)
25 #define SW_OVERRIDE_MASK BIT(2)
26 #define HW_CONTROL_MASK BIT(1)
27 #define SW_COLLAPSE_MASK BIT(0)
28 #define GMEM_CLAMP_IO_MASK BIT(0)
29 #define GMEM_RESET_MASK BIT(4)
32 #define GDSC_POWER_UP_COMPLETE BIT(16)
33 #define GDSC_POWER_DOWN_COMPLETE BIT(15)
34 #define GDSC_RETAIN_FF_ENABLE BIT(11)
35 #define CFG_GDSCR_OFFSET 0x4
37 /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
38 #define EN_REST_WAIT_VAL 0x2
39 #define EN_FEW_WAIT_VAL 0x8
40 #define CLK_DIS_WAIT_VAL 0x2
42 /* Transition delay shifts */
43 #define EN_REST_WAIT_SHIFT 20
44 #define EN_FEW_WAIT_SHIFT 16
45 #define CLK_DIS_WAIT_SHIFT 12
47 #define RETAIN_MEM BIT(14)
48 #define RETAIN_PERIPH BIT(13)
50 #define TIMEOUT_US 500
52 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
59 static int gdsc_pm_runtime_get(struct gdsc *sc)
64 return pm_runtime_resume_and_get(sc->dev);
67 static int gdsc_pm_runtime_put(struct gdsc *sc)
72 return pm_runtime_put_sync(sc->dev);
75 /* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
76 static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
82 if (sc->flags & POLL_CFG_GDSCR)
83 reg = sc->gdscr + CFG_GDSCR_OFFSET;
84 else if (sc->gds_hw_ctrl)
85 reg = sc->gds_hw_ctrl;
89 ret = regmap_read(sc->regmap, reg, &val);
93 if (sc->flags & POLL_CFG_GDSCR) {
96 return !!(val & GDSC_POWER_UP_COMPLETE);
98 return !!(val & GDSC_POWER_DOWN_COMPLETE);
104 return !!(val & PWR_ON_MASK);
106 return !(val & PWR_ON_MASK);
112 static int gdsc_hwctrl(struct gdsc *sc, bool en)
114 u32 val = en ? HW_CONTROL_MASK : 0;
116 return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
119 static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
125 if (gdsc_check_status(sc, status))
127 } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
129 if (gdsc_check_status(sc, status))
135 static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
138 u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK;
140 if (status == GDSC_ON && sc->rsupply) {
141 ret = regulator_enable(sc->rsupply);
146 ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
150 /* If disabling votable gdscs, don't poll on status */
151 if ((sc->flags & VOTABLE) && status == GDSC_OFF) {
153 * Add a short delay here to ensure that an enable
154 * right after it was disabled does not put it in an
161 if (sc->gds_hw_ctrl) {
163 * The gds hw controller asserts/de-asserts the status bit soon
164 * after it receives a power on/off request from a master.
165 * The controller then takes around 8 xo cycles to start its
166 * internal state machine and update the status bit. During
167 * this time, the status bit does not reflect the true status
169 * Add a delay of 1 us between writing to the SW_COLLAPSE bit
170 * and polling the status bit.
175 ret = gdsc_poll_status(sc, status);
176 WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n");
178 if (!ret && status == GDSC_OFF && sc->rsupply) {
179 ret = regulator_disable(sc->rsupply);
187 static inline int gdsc_deassert_reset(struct gdsc *sc)
191 for (i = 0; i < sc->reset_count; i++)
192 sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
196 static inline int gdsc_assert_reset(struct gdsc *sc)
200 for (i = 0; i < sc->reset_count; i++)
201 sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
205 static inline void gdsc_force_mem_on(struct gdsc *sc)
208 u32 mask = RETAIN_MEM;
210 if (!(sc->flags & NO_RET_PERIPH))
211 mask |= RETAIN_PERIPH;
213 for (i = 0; i < sc->cxc_count; i++)
214 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
217 static inline void gdsc_clear_mem_on(struct gdsc *sc)
220 u32 mask = RETAIN_MEM;
222 if (!(sc->flags & NO_RET_PERIPH))
223 mask |= RETAIN_PERIPH;
225 for (i = 0; i < sc->cxc_count; i++)
226 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
229 static inline void gdsc_deassert_clamp_io(struct gdsc *sc)
231 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
232 GMEM_CLAMP_IO_MASK, 0);
235 static inline void gdsc_assert_clamp_io(struct gdsc *sc)
237 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
238 GMEM_CLAMP_IO_MASK, 1);
241 static inline void gdsc_assert_reset_aon(struct gdsc *sc)
243 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
246 regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
250 static void gdsc_retain_ff_on(struct gdsc *sc)
252 u32 mask = GDSC_RETAIN_FF_ENABLE;
254 regmap_update_bits(sc->regmap, sc->gdscr, mask, mask);
257 static int _gdsc_enable(struct gdsc *sc)
261 if (sc->pwrsts == PWRSTS_ON)
262 return gdsc_deassert_reset(sc);
264 if (sc->flags & SW_RESET) {
265 gdsc_assert_reset(sc);
267 gdsc_deassert_reset(sc);
270 if (sc->flags & CLAMP_IO) {
271 if (sc->flags & AON_RESET)
272 gdsc_assert_reset_aon(sc);
273 gdsc_deassert_clamp_io(sc);
276 ret = gdsc_toggle_logic(sc, GDSC_ON);
280 if (sc->pwrsts & PWRSTS_OFF)
281 gdsc_force_mem_on(sc);
284 * If clocks to this power domain were already on, they will take an
285 * additional 4 clock cycles to re-enable after the power domain is
286 * enabled. Delay to account for this. A delay is also needed to ensure
287 * clocks are not enabled within 400ns of enabling power to the
292 /* Turn on HW trigger mode if supported */
293 if (sc->flags & HW_CTRL) {
294 ret = gdsc_hwctrl(sc, true);
298 * Wait for the GDSC to go through a power down and
299 * up cycle. In case a firmware ends up polling status
300 * bits for the gdsc, it might read an 'on' status before
301 * the GDSC can finish the power cycle.
302 * We wait 1us before returning to ensure the firmware
303 * can't immediately poll the status bits.
308 if (sc->flags & RETAIN_FF_ENABLE)
309 gdsc_retain_ff_on(sc);
314 static int gdsc_enable(struct generic_pm_domain *domain)
316 struct gdsc *sc = domain_to_gdsc(domain);
319 ret = gdsc_pm_runtime_get(sc);
323 return _gdsc_enable(sc);
326 static int _gdsc_disable(struct gdsc *sc)
330 if (sc->pwrsts == PWRSTS_ON)
331 return gdsc_assert_reset(sc);
333 /* Turn off HW trigger mode if supported */
334 if (sc->flags & HW_CTRL) {
335 ret = gdsc_hwctrl(sc, false);
339 * Wait for the GDSC to go through a power down and
340 * up cycle. In case we end up polling status
341 * bits for the gdsc before the power cycle is completed
342 * it might read an 'on' status wrongly.
346 ret = gdsc_poll_status(sc, GDSC_ON);
351 if (sc->pwrsts & PWRSTS_OFF)
352 gdsc_clear_mem_on(sc);
354 ret = gdsc_toggle_logic(sc, GDSC_OFF);
358 if (sc->flags & CLAMP_IO)
359 gdsc_assert_clamp_io(sc);
364 static int gdsc_disable(struct generic_pm_domain *domain)
366 struct gdsc *sc = domain_to_gdsc(domain);
369 ret = _gdsc_disable(sc);
371 gdsc_pm_runtime_put(sc);
376 static int gdsc_init(struct gdsc *sc)
382 * Disable HW trigger: collapse/restore occur based on registers writes.
383 * Disable SW override: Use hardware state-machine for sequencing.
384 * Configure wait time between states.
386 mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
387 EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
389 if (!sc->en_rest_wait_val)
390 sc->en_rest_wait_val = EN_REST_WAIT_VAL;
391 if (!sc->en_few_wait_val)
392 sc->en_few_wait_val = EN_FEW_WAIT_VAL;
393 if (!sc->clk_dis_wait_val)
394 sc->clk_dis_wait_val = CLK_DIS_WAIT_VAL;
396 val = sc->en_rest_wait_val << EN_REST_WAIT_SHIFT |
397 sc->en_few_wait_val << EN_FEW_WAIT_SHIFT |
398 sc->clk_dis_wait_val << CLK_DIS_WAIT_SHIFT;
400 ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
404 /* Force gdsc ON if only ON state is supported */
405 if (sc->pwrsts == PWRSTS_ON) {
406 ret = gdsc_toggle_logic(sc, GDSC_ON);
411 on = gdsc_check_status(sc, GDSC_ON);
416 /* The regulator must be on, sync the kernel state */
418 ret = regulator_enable(sc->rsupply);
424 * Votable GDSCs can be ON due to Vote from other masters.
425 * If a Votable GDSC is ON, make sure we have a Vote.
427 if (sc->flags & VOTABLE) {
428 ret = regmap_update_bits(sc->regmap, sc->gdscr,
429 SW_COLLAPSE_MASK, val);
434 /* Turn on HW trigger mode if supported */
435 if (sc->flags & HW_CTRL) {
436 ret = gdsc_hwctrl(sc, true);
442 * Make sure the retain bit is set if the GDSC is already on,
443 * otherwise we end up turning off the GDSC and destroying all
444 * the register contents that we thought we were saving.
446 if (sc->flags & RETAIN_FF_ENABLE)
447 gdsc_retain_ff_on(sc);
448 } else if (sc->flags & ALWAYS_ON) {
449 /* If ALWAYS_ON GDSCs are not ON, turn them ON */
450 gdsc_enable(&sc->pd);
454 if (on || (sc->pwrsts & PWRSTS_RET))
455 gdsc_force_mem_on(sc);
457 gdsc_clear_mem_on(sc);
459 if (sc->flags & ALWAYS_ON)
460 sc->pd.flags |= GENPD_FLAG_ALWAYS_ON;
461 if (!sc->pd.power_off)
462 sc->pd.power_off = gdsc_disable;
463 if (!sc->pd.power_on)
464 sc->pd.power_on = gdsc_enable;
465 pm_genpd_init(&sc->pd, NULL, !on);
470 int gdsc_register(struct gdsc_desc *desc,
471 struct reset_controller_dev *rcdev, struct regmap *regmap)
474 struct genpd_onecell_data *data;
475 struct device *dev = desc->dev;
476 struct gdsc **scs = desc->scs;
477 size_t num = desc->num;
479 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
483 data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
488 for (i = 0; i < num; i++) {
489 if (!scs[i] || !scs[i]->supply)
492 scs[i]->rsupply = devm_regulator_get(dev, scs[i]->supply);
493 if (IS_ERR(scs[i]->rsupply))
494 return PTR_ERR(scs[i]->rsupply);
497 data->num_domains = num;
498 for (i = 0; i < num; i++) {
501 if (pm_runtime_enabled(dev))
503 scs[i]->regmap = regmap;
504 scs[i]->rcdev = rcdev;
505 ret = gdsc_init(scs[i]);
508 data->domains[i] = &scs[i]->pd;
512 for (i = 0; i < num; i++) {
516 pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
517 else if (!IS_ERR_OR_NULL(dev->pm_domain))
518 pm_genpd_add_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd);
521 return of_genpd_add_provider_onecell(dev->of_node, data);
524 void gdsc_unregister(struct gdsc_desc *desc)
527 struct device *dev = desc->dev;
528 struct gdsc **scs = desc->scs;
529 size_t num = desc->num;
531 /* Remove subdomains */
532 for (i = 0; i < num; i++) {
536 pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
537 else if (!IS_ERR_OR_NULL(dev->pm_domain))
538 pm_genpd_remove_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd);
540 of_genpd_del_provider(dev->of_node);
544 * On SDM845+ the GPU GX domain is *almost* entirely controlled by the GMU
545 * running in the CX domain so the CPU doesn't need to know anything about the
546 * GX domain EXCEPT....
548 * Hardware constraints dictate that the GX be powered down before the CX. If
549 * the GMU crashes it could leave the GX on. In order to successfully bring back
550 * the device the CPU needs to disable the GX headswitch. There being no sane
551 * way to reach in and touch that register from deep inside the GPU driver we
552 * need to set up the infrastructure to be able to ensure that the GPU can
553 * ensure that the GX is off during this super special case. We do this by
554 * defining a GX gdsc with a dummy enable function and a "default" disable
557 * This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU
558 * driver. During power up, nothing will happen from the CPU (and the GMU will
559 * power up normally but during power down this will ensure that the GX domain
560 * is *really* off - this gives us a semi standard way of doing what we need.
562 int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain)
564 /* Do nothing but give genpd the impression that we were successful */
567 EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable);