1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021, Linaro Limited
7 #include <linux/clk-provider.h>
8 #include <linux/module.h>
9 #include <linux/of_device.h>
10 #include <linux/regmap.h>
12 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
17 #include "clk-regmap.h"
18 #include "clk-regmap-divider.h"
19 #include "clk-regmap-mux.h"
33 P_UFS_PHY_RX_SYMBOL_0_CLK,
34 P_UFS_PHY_RX_SYMBOL_1_CLK,
35 P_UFS_PHY_TX_SYMBOL_0_CLK,
36 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
39 static struct clk_alpha_pll gcc_gpll0 = {
41 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
43 .enable_reg = 0x62018,
44 .enable_mask = BIT(0),
45 .hw.init = &(struct clk_init_data){
47 .parent_data = &(const struct clk_parent_data){
51 .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
56 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
61 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
64 .post_div_table = post_div_table_gcc_gpll0_out_even,
65 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
67 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
68 .clkr.hw.init = &(struct clk_init_data){
69 .name = "gcc_gpll0_out_even",
70 .parent_data = &(const struct clk_parent_data){
71 .hw = &gcc_gpll0.clkr.hw,
74 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
78 static struct clk_alpha_pll gcc_gpll4 = {
80 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
82 .enable_reg = 0x62018,
83 .enable_mask = BIT(4),
84 .hw.init = &(struct clk_init_data){
86 .parent_data = &(const struct clk_parent_data){
90 .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
95 static struct clk_alpha_pll gcc_gpll9 = {
97 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
99 .enable_reg = 0x62018,
100 .enable_mask = BIT(9),
101 .hw.init = &(struct clk_init_data){
103 .parent_data = &(const struct clk_parent_data){
104 .fw_name = "bi_tcxo",
107 .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
112 static const struct parent_map gcc_parent_map_0[] = {
114 { P_GCC_GPLL0_OUT_MAIN, 1 },
115 { P_GCC_GPLL0_OUT_EVEN, 6 },
118 static const struct clk_parent_data gcc_parent_data_0[] = {
119 { .fw_name = "bi_tcxo" },
120 { .hw = &gcc_gpll0.clkr.hw },
121 { .hw = &gcc_gpll0_out_even.clkr.hw },
124 static const struct parent_map gcc_parent_map_1[] = {
126 { P_GCC_GPLL0_OUT_MAIN, 1 },
128 { P_GCC_GPLL0_OUT_EVEN, 6 },
131 static const struct clk_parent_data gcc_parent_data_1[] = {
132 { .fw_name = "bi_tcxo" },
133 { .hw = &gcc_gpll0.clkr.hw },
134 { .fw_name = "sleep_clk" },
135 { .hw = &gcc_gpll0_out_even.clkr.hw },
138 static const struct parent_map gcc_parent_map_2[] = {
143 static const struct clk_parent_data gcc_parent_data_2[] = {
144 { .fw_name = "bi_tcxo" },
145 { .fw_name = "sleep_clk" },
148 static const struct parent_map gcc_parent_map_3[] = {
152 static const struct clk_parent_data gcc_parent_data_3[] = {
153 { .fw_name = "bi_tcxo" },
156 static const struct parent_map gcc_parent_map_4[] = {
157 { P_PCIE_0_PIPE_CLK, 0 },
161 static const struct clk_parent_data gcc_parent_data_4[] = {
162 { .fw_name = "pcie_0_pipe_clk", },
163 { .fw_name = "bi_tcxo", },
166 static const struct parent_map gcc_parent_map_5[] = {
167 { P_PCIE_1_PHY_AUX_CLK, 0 },
171 static const struct clk_parent_data gcc_parent_data_5[] = {
172 { .fw_name = "pcie_1_phy_aux_clk" },
173 { .fw_name = "bi_tcxo" },
176 static const struct parent_map gcc_parent_map_6[] = {
177 { P_PCIE_1_PIPE_CLK, 0 },
181 static const struct clk_parent_data gcc_parent_data_6[] = {
182 { .fw_name = "pcie_1_pipe_clk" },
183 { .fw_name = "bi_tcxo" },
186 static const struct parent_map gcc_parent_map_7[] = {
188 { P_GCC_GPLL0_OUT_MAIN, 1 },
189 { P_GCC_GPLL9_OUT_MAIN, 2 },
190 { P_GCC_GPLL4_OUT_MAIN, 5 },
191 { P_GCC_GPLL0_OUT_EVEN, 6 },
194 static const struct clk_parent_data gcc_parent_data_7[] = {
195 { .fw_name = "bi_tcxo" },
196 { .hw = &gcc_gpll0.clkr.hw },
197 { .hw = &gcc_gpll9.clkr.hw },
198 { .hw = &gcc_gpll4.clkr.hw },
199 { .hw = &gcc_gpll0_out_even.clkr.hw },
202 static const struct parent_map gcc_parent_map_8[] = {
203 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
207 static const struct clk_parent_data gcc_parent_data_8[] = {
208 { .fw_name = "ufs_phy_rx_symbol_0_clk" },
209 { .fw_name = "bi_tcxo" },
212 static const struct parent_map gcc_parent_map_9[] = {
213 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
217 static const struct clk_parent_data gcc_parent_data_9[] = {
218 { .fw_name = "ufs_phy_rx_symbol_1_clk" },
219 { .fw_name = "bi_tcxo" },
222 static const struct parent_map gcc_parent_map_10[] = {
223 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
227 static const struct clk_parent_data gcc_parent_data_10[] = {
228 { .fw_name = "ufs_phy_tx_symbol_0_clk" },
229 { .fw_name = "bi_tcxo" },
232 static const struct parent_map gcc_parent_map_11[] = {
233 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
237 static const struct clk_parent_data gcc_parent_data_11[] = {
238 { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
239 { .fw_name = "bi_tcxo" },
242 static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
246 .parent_map = gcc_parent_map_4,
248 .hw.init = &(struct clk_init_data){
249 .name = "gcc_pcie_0_pipe_clk_src",
250 .parent_data = gcc_parent_data_4,
251 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
252 .ops = &clk_regmap_mux_closest_ops,
257 static struct clk_regmap_mux gcc_pcie_1_phy_aux_clk_src = {
261 .parent_map = gcc_parent_map_5,
263 .hw.init = &(struct clk_init_data){
264 .name = "gcc_pcie_1_phy_aux_clk_src",
265 .parent_data = gcc_parent_data_5,
266 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
267 .ops = &clk_regmap_mux_closest_ops,
272 static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
276 .parent_map = gcc_parent_map_6,
278 .hw.init = &(struct clk_init_data){
279 .name = "gcc_pcie_1_pipe_clk_src",
280 .parent_data = gcc_parent_data_6,
281 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
282 .ops = &clk_regmap_mux_closest_ops,
287 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
291 .parent_map = gcc_parent_map_8,
293 .hw.init = &(struct clk_init_data){
294 .name = "gcc_ufs_phy_rx_symbol_0_clk_src",
295 .parent_data = gcc_parent_data_8,
296 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
297 .ops = &clk_regmap_mux_closest_ops,
302 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
306 .parent_map = gcc_parent_map_9,
308 .hw.init = &(struct clk_init_data){
309 .name = "gcc_ufs_phy_rx_symbol_1_clk_src",
310 .parent_data = gcc_parent_data_9,
311 .num_parents = ARRAY_SIZE(gcc_parent_data_9),
312 .ops = &clk_regmap_mux_closest_ops,
317 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
321 .parent_map = gcc_parent_map_10,
323 .hw.init = &(struct clk_init_data){
324 .name = "gcc_ufs_phy_tx_symbol_0_clk_src",
325 .parent_data = gcc_parent_data_10,
326 .num_parents = ARRAY_SIZE(gcc_parent_data_10),
327 .ops = &clk_regmap_mux_closest_ops,
332 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
336 .parent_map = gcc_parent_map_11,
338 .hw.init = &(struct clk_init_data){
339 .name = "gcc_usb3_prim_phy_pipe_clk_src",
340 .parent_data = gcc_parent_data_11,
341 .num_parents = ARRAY_SIZE(gcc_parent_data_11),
342 .ops = &clk_regmap_mux_closest_ops,
347 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
348 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
349 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
350 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
354 static struct clk_rcg2 gcc_gp1_clk_src = {
358 .parent_map = gcc_parent_map_1,
359 .freq_tbl = ftbl_gcc_gp1_clk_src,
360 .clkr.hw.init = &(struct clk_init_data){
361 .name = "gcc_gp1_clk_src",
362 .parent_data = gcc_parent_data_1,
363 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
364 .flags = CLK_SET_RATE_PARENT,
365 .ops = &clk_rcg2_ops,
369 static struct clk_rcg2 gcc_gp2_clk_src = {
373 .parent_map = gcc_parent_map_1,
374 .freq_tbl = ftbl_gcc_gp1_clk_src,
375 .clkr.hw.init = &(struct clk_init_data){
376 .name = "gcc_gp2_clk_src",
377 .parent_data = gcc_parent_data_1,
378 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
379 .flags = CLK_SET_RATE_PARENT,
380 .ops = &clk_rcg2_ops,
384 static struct clk_rcg2 gcc_gp3_clk_src = {
388 .parent_map = gcc_parent_map_1,
389 .freq_tbl = ftbl_gcc_gp1_clk_src,
390 .clkr.hw.init = &(struct clk_init_data){
391 .name = "gcc_gp3_clk_src",
392 .parent_data = gcc_parent_data_1,
393 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
394 .flags = CLK_SET_RATE_PARENT,
395 .ops = &clk_rcg2_ops,
399 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
400 F(19200000, P_BI_TCXO, 1, 0, 0),
404 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
408 .parent_map = gcc_parent_map_2,
409 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
410 .clkr.hw.init = &(struct clk_init_data){
411 .name = "gcc_pcie_0_aux_clk_src",
412 .parent_data = gcc_parent_data_2,
413 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
414 .flags = CLK_SET_RATE_PARENT,
415 .ops = &clk_rcg2_ops,
419 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
420 F(19200000, P_BI_TCXO, 1, 0, 0),
421 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
425 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
429 .parent_map = gcc_parent_map_0,
430 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
431 .clkr.hw.init = &(struct clk_init_data){
432 .name = "gcc_pcie_0_phy_rchng_clk_src",
433 .parent_data = gcc_parent_data_0,
434 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
435 .flags = CLK_SET_RATE_PARENT,
436 .ops = &clk_rcg2_ops,
440 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
444 .parent_map = gcc_parent_map_2,
445 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
446 .clkr.hw.init = &(struct clk_init_data){
447 .name = "gcc_pcie_1_aux_clk_src",
448 .parent_data = gcc_parent_data_2,
449 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
450 .flags = CLK_SET_RATE_PARENT,
451 .ops = &clk_rcg2_ops,
455 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
459 .parent_map = gcc_parent_map_0,
460 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
461 .clkr.hw.init = &(struct clk_init_data){
462 .name = "gcc_pcie_1_phy_rchng_clk_src",
463 .parent_data = gcc_parent_data_0,
464 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
465 .flags = CLK_SET_RATE_PARENT,
466 .ops = &clk_rcg2_ops,
470 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
471 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
475 static struct clk_rcg2 gcc_pdm2_clk_src = {
479 .parent_map = gcc_parent_map_0,
480 .freq_tbl = ftbl_gcc_pdm2_clk_src,
481 .clkr.hw.init = &(struct clk_init_data){
482 .name = "gcc_pdm2_clk_src",
483 .parent_data = gcc_parent_data_0,
484 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
485 .flags = CLK_SET_RATE_PARENT,
486 .ops = &clk_rcg2_ops,
490 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
491 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
492 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
493 F(19200000, P_BI_TCXO, 1, 0, 0),
494 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
495 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
496 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
497 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
498 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
499 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
500 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
501 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
505 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
506 .name = "gcc_qupv3_wrap0_s0_clk_src",
507 .parent_data = gcc_parent_data_0,
508 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
509 .flags = CLK_SET_RATE_PARENT,
510 .ops = &clk_rcg2_ops,
513 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
517 .parent_map = gcc_parent_map_0,
518 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
519 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
522 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
523 .name = "gcc_qupv3_wrap0_s1_clk_src",
524 .parent_data = gcc_parent_data_0,
525 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
526 .flags = CLK_SET_RATE_PARENT,
527 .ops = &clk_rcg2_ops,
530 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
534 .parent_map = gcc_parent_map_0,
535 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
536 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
539 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
540 .name = "gcc_qupv3_wrap0_s2_clk_src",
541 .parent_data = gcc_parent_data_0,
542 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
543 .flags = CLK_SET_RATE_PARENT,
544 .ops = &clk_rcg2_ops,
547 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
551 .parent_map = gcc_parent_map_0,
552 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
553 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
556 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
557 .name = "gcc_qupv3_wrap0_s3_clk_src",
558 .parent_data = gcc_parent_data_0,
559 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
560 .flags = CLK_SET_RATE_PARENT,
561 .ops = &clk_rcg2_ops,
564 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
568 .parent_map = gcc_parent_map_0,
569 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
570 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
573 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
574 .name = "gcc_qupv3_wrap0_s4_clk_src",
575 .parent_data = gcc_parent_data_0,
576 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
577 .flags = CLK_SET_RATE_PARENT,
578 .ops = &clk_rcg2_ops,
581 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
585 .parent_map = gcc_parent_map_0,
586 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
587 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
590 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s5_clk_src[] = {
591 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
592 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
593 F(19200000, P_BI_TCXO, 1, 0, 0),
594 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
595 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
596 F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
597 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
598 F(50000000, P_GCC_GPLL0_OUT_MAIN, 12, 0, 0),
602 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
603 .name = "gcc_qupv3_wrap0_s5_clk_src",
604 .parent_data = gcc_parent_data_0,
605 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
606 .flags = CLK_SET_RATE_PARENT,
607 .ops = &clk_rcg2_ops,
610 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
614 .parent_map = gcc_parent_map_0,
615 .freq_tbl = ftbl_gcc_qupv3_wrap0_s5_clk_src,
616 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
619 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
620 .name = "gcc_qupv3_wrap0_s6_clk_src",
621 .parent_data = gcc_parent_data_0,
622 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
623 .flags = CLK_SET_RATE_PARENT,
624 .ops = &clk_rcg2_ops,
627 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
631 .parent_map = gcc_parent_map_0,
632 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
633 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
636 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
637 .name = "gcc_qupv3_wrap0_s7_clk_src",
638 .parent_data = gcc_parent_data_0,
639 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
640 .flags = CLK_SET_RATE_PARENT,
641 .ops = &clk_rcg2_ops,
644 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
648 .parent_map = gcc_parent_map_0,
649 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
650 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
653 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = {
654 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
655 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
656 F(19200000, P_BI_TCXO, 1, 0, 0),
657 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
658 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
659 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
660 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
661 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
662 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
663 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
664 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
665 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
666 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
667 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
668 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
672 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
673 .name = "gcc_qupv3_wrap1_s0_clk_src",
674 .parent_data = gcc_parent_data_0,
675 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
676 .flags = CLK_SET_RATE_PARENT,
677 .ops = &clk_rcg2_ops,
680 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
684 .parent_map = gcc_parent_map_0,
685 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
686 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
689 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
690 .name = "gcc_qupv3_wrap1_s1_clk_src",
691 .parent_data = gcc_parent_data_0,
692 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
693 .flags = CLK_SET_RATE_PARENT,
694 .ops = &clk_rcg2_ops,
697 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
701 .parent_map = gcc_parent_map_0,
702 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
703 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
706 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
707 .name = "gcc_qupv3_wrap1_s2_clk_src",
708 .parent_data = gcc_parent_data_0,
709 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
710 .flags = CLK_SET_RATE_PARENT,
711 .ops = &clk_rcg2_ops,
714 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
718 .parent_map = gcc_parent_map_0,
719 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
720 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
723 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
724 .name = "gcc_qupv3_wrap1_s3_clk_src",
725 .parent_data = gcc_parent_data_0,
726 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
727 .flags = CLK_SET_RATE_PARENT,
728 .ops = &clk_rcg2_ops,
731 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
735 .parent_map = gcc_parent_map_0,
736 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
737 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
740 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
741 .name = "gcc_qupv3_wrap1_s4_clk_src",
742 .parent_data = gcc_parent_data_0,
743 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
744 .flags = CLK_SET_RATE_PARENT,
745 .ops = &clk_rcg2_ops,
748 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
752 .parent_map = gcc_parent_map_0,
753 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
754 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
757 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
758 .name = "gcc_qupv3_wrap1_s5_clk_src",
759 .parent_data = gcc_parent_data_0,
760 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
761 .flags = CLK_SET_RATE_PARENT,
762 .ops = &clk_rcg2_ops,
765 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
769 .parent_map = gcc_parent_map_0,
770 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
771 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
774 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
775 .name = "gcc_qupv3_wrap1_s6_clk_src",
776 .parent_data = gcc_parent_data_0,
777 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
778 .flags = CLK_SET_RATE_PARENT,
779 .ops = &clk_rcg2_ops,
782 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
786 .parent_map = gcc_parent_map_0,
787 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
788 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
791 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
792 .name = "gcc_qupv3_wrap2_s0_clk_src",
793 .parent_data = gcc_parent_data_0,
794 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
795 .flags = CLK_SET_RATE_PARENT,
796 .ops = &clk_rcg2_ops,
799 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
803 .parent_map = gcc_parent_map_0,
804 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
805 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
808 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
809 .name = "gcc_qupv3_wrap2_s1_clk_src",
810 .parent_data = gcc_parent_data_0,
811 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
812 .flags = CLK_SET_RATE_PARENT,
813 .ops = &clk_rcg2_ops,
816 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
820 .parent_map = gcc_parent_map_0,
821 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
822 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
825 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
826 .name = "gcc_qupv3_wrap2_s2_clk_src",
827 .parent_data = gcc_parent_data_0,
828 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
829 .flags = CLK_SET_RATE_PARENT,
830 .ops = &clk_rcg2_ops,
833 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
837 .parent_map = gcc_parent_map_0,
838 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
839 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
842 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
843 .name = "gcc_qupv3_wrap2_s3_clk_src",
844 .parent_data = gcc_parent_data_0,
845 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
846 .flags = CLK_SET_RATE_PARENT,
847 .ops = &clk_rcg2_ops,
850 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
854 .parent_map = gcc_parent_map_0,
855 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
856 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
859 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
860 .name = "gcc_qupv3_wrap2_s4_clk_src",
861 .parent_data = gcc_parent_data_0,
862 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
863 .flags = CLK_SET_RATE_PARENT,
864 .ops = &clk_rcg2_ops,
867 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
871 .parent_map = gcc_parent_map_0,
872 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
873 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
876 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
877 .name = "gcc_qupv3_wrap2_s5_clk_src",
878 .parent_data = gcc_parent_data_0,
879 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
880 .flags = CLK_SET_RATE_PARENT,
881 .ops = &clk_rcg2_ops,
884 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
888 .parent_map = gcc_parent_map_0,
889 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
890 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
893 static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
894 .name = "gcc_qupv3_wrap2_s6_clk_src",
895 .parent_data = gcc_parent_data_0,
896 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
897 .flags = CLK_SET_RATE_PARENT,
898 .ops = &clk_rcg2_ops,
901 static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
905 .parent_map = gcc_parent_map_0,
906 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
907 .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
910 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
911 F(400000, P_BI_TCXO, 12, 1, 4),
912 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
913 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
914 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
915 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
919 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
923 .parent_map = gcc_parent_map_7,
924 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
925 .clkr.hw.init = &(struct clk_init_data){
926 .name = "gcc_sdcc2_apps_clk_src",
927 .parent_data = gcc_parent_data_7,
928 .num_parents = ARRAY_SIZE(gcc_parent_data_7),
929 .flags = CLK_SET_RATE_PARENT,
930 .ops = &clk_rcg2_ops,
934 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
935 F(400000, P_BI_TCXO, 12, 1, 4),
936 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
937 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
941 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
945 .parent_map = gcc_parent_map_0,
946 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
947 .clkr.hw.init = &(struct clk_init_data){
948 .name = "gcc_sdcc4_apps_clk_src",
949 .parent_data = gcc_parent_data_0,
950 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
951 .flags = CLK_SET_RATE_PARENT,
952 .ops = &clk_rcg2_ops,
956 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
957 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
958 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
959 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
960 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
964 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
968 .parent_map = gcc_parent_map_0,
969 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
970 .clkr.hw.init = &(struct clk_init_data){
971 .name = "gcc_ufs_phy_axi_clk_src",
972 .parent_data = gcc_parent_data_0,
973 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
974 .flags = CLK_SET_RATE_PARENT,
975 .ops = &clk_rcg2_ops,
979 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
980 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
981 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
982 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
986 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
990 .parent_map = gcc_parent_map_0,
991 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
992 .clkr.hw.init = &(struct clk_init_data){
993 .name = "gcc_ufs_phy_ice_core_clk_src",
994 .parent_data = gcc_parent_data_0,
995 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
996 .flags = CLK_SET_RATE_PARENT,
997 .ops = &clk_rcg2_ops,
1001 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
1002 F(9600000, P_BI_TCXO, 2, 0, 0),
1003 F(19200000, P_BI_TCXO, 1, 0, 0),
1007 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1008 .cmd_rcgr = 0x870a8,
1011 .parent_map = gcc_parent_map_3,
1012 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
1013 .clkr.hw.init = &(struct clk_init_data){
1014 .name = "gcc_ufs_phy_phy_aux_clk_src",
1015 .parent_data = gcc_parent_data_3,
1016 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1017 .flags = CLK_SET_RATE_PARENT,
1018 .ops = &clk_rcg2_ops,
1022 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1023 .cmd_rcgr = 0x8708c,
1026 .parent_map = gcc_parent_map_0,
1027 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1028 .clkr.hw.init = &(struct clk_init_data){
1029 .name = "gcc_ufs_phy_unipro_core_clk_src",
1030 .parent_data = gcc_parent_data_0,
1031 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1032 .flags = CLK_SET_RATE_PARENT,
1033 .ops = &clk_rcg2_ops,
1037 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1038 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1039 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1040 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1041 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1045 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1046 .cmd_rcgr = 0x49028,
1049 .parent_map = gcc_parent_map_0,
1050 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1051 .clkr.hw.init = &(struct clk_init_data){
1052 .name = "gcc_usb30_prim_master_clk_src",
1053 .parent_data = gcc_parent_data_0,
1054 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1055 .flags = CLK_SET_RATE_PARENT,
1056 .ops = &clk_rcg2_ops,
1060 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1061 .cmd_rcgr = 0x49040,
1064 .parent_map = gcc_parent_map_0,
1065 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1066 .clkr.hw.init = &(struct clk_init_data){
1067 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1068 .parent_data = gcc_parent_data_0,
1069 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1070 .flags = CLK_SET_RATE_PARENT,
1071 .ops = &clk_rcg2_ops,
1075 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1076 .cmd_rcgr = 0x4906c,
1079 .parent_map = gcc_parent_map_2,
1080 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1081 .clkr.hw.init = &(struct clk_init_data){
1082 .name = "gcc_usb3_prim_phy_aux_clk_src",
1083 .parent_data = gcc_parent_data_2,
1084 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1085 .flags = CLK_SET_RATE_PARENT,
1086 .ops = &clk_rcg2_ops,
1090 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1094 .clkr.hw.init = &(struct clk_init_data) {
1095 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1096 .parent_data = &(const struct clk_parent_data){
1097 .hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1100 .flags = CLK_SET_RATE_PARENT,
1101 .ops = &clk_regmap_div_ro_ops,
1105 static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = {
1106 .halt_reg = 0x7b08c,
1107 .halt_check = BRANCH_HALT_SKIP,
1108 .hwcg_reg = 0x7b08c,
1111 .enable_reg = 0x62000,
1112 .enable_mask = BIT(12),
1113 .hw.init = &(struct clk_init_data){
1114 .name = "gcc_aggre_noc_pcie_0_axi_clk",
1115 .ops = &clk_branch2_ops,
1120 static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = {
1121 .halt_reg = 0x9d098,
1122 .halt_check = BRANCH_HALT_SKIP,
1123 .hwcg_reg = 0x9d098,
1126 .enable_reg = 0x62000,
1127 .enable_mask = BIT(11),
1128 .hw.init = &(struct clk_init_data){
1129 .name = "gcc_aggre_noc_pcie_1_axi_clk",
1130 .ops = &clk_branch2_ops,
1135 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1136 .halt_reg = 0x870d4,
1137 .halt_check = BRANCH_HALT_VOTED,
1138 .hwcg_reg = 0x870d4,
1141 .enable_reg = 0x870d4,
1142 .enable_mask = BIT(0),
1143 .hw.init = &(struct clk_init_data){
1144 .name = "gcc_aggre_ufs_phy_axi_clk",
1145 .parent_data = &(const struct clk_parent_data){
1146 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
1149 .flags = CLK_SET_RATE_PARENT,
1150 .ops = &clk_branch2_ops,
1155 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1156 .halt_reg = 0x870d4,
1157 .halt_check = BRANCH_HALT_VOTED,
1158 .hwcg_reg = 0x870d4,
1161 .enable_reg = 0x870d4,
1162 .enable_mask = BIT(1),
1163 .hw.init = &(struct clk_init_data){
1164 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1165 .parent_data = &(const struct clk_parent_data){
1166 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
1169 .flags = CLK_SET_RATE_PARENT,
1170 .ops = &clk_branch2_ops,
1175 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1176 .halt_reg = 0x49088,
1177 .halt_check = BRANCH_HALT_VOTED,
1178 .hwcg_reg = 0x49088,
1181 .enable_reg = 0x49088,
1182 .enable_mask = BIT(0),
1183 .hw.init = &(struct clk_init_data){
1184 .name = "gcc_aggre_usb3_prim_axi_clk",
1185 .parent_data = &(const struct clk_parent_data){
1186 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
1189 .flags = CLK_SET_RATE_PARENT,
1190 .ops = &clk_branch2_ops,
1195 static struct clk_branch gcc_boot_rom_ahb_clk = {
1196 .halt_reg = 0x48004,
1197 .halt_check = BRANCH_HALT_VOTED,
1198 .hwcg_reg = 0x48004,
1201 .enable_reg = 0x62000,
1202 .enable_mask = BIT(10),
1203 .hw.init = &(struct clk_init_data){
1204 .name = "gcc_boot_rom_ahb_clk",
1205 .ops = &clk_branch2_ops,
1210 static struct clk_branch gcc_camera_hf_axi_clk = {
1211 .halt_reg = 0x36010,
1212 .halt_check = BRANCH_HALT_SKIP,
1213 .hwcg_reg = 0x36010,
1216 .enable_reg = 0x36010,
1217 .enable_mask = BIT(0),
1218 .hw.init = &(struct clk_init_data){
1219 .name = "gcc_camera_hf_axi_clk",
1220 .ops = &clk_branch2_ops,
1225 static struct clk_branch gcc_camera_sf_axi_clk = {
1226 .halt_reg = 0x36018,
1227 .halt_check = BRANCH_HALT_SKIP,
1228 .hwcg_reg = 0x36018,
1231 .enable_reg = 0x36018,
1232 .enable_mask = BIT(0),
1233 .hw.init = &(struct clk_init_data){
1234 .name = "gcc_camera_sf_axi_clk",
1235 .ops = &clk_branch2_ops,
1240 static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {
1241 .halt_reg = 0x20030,
1242 .halt_check = BRANCH_HALT_VOTED,
1243 .hwcg_reg = 0x20030,
1246 .enable_reg = 0x62000,
1247 .enable_mask = BIT(20),
1248 .hw.init = &(struct clk_init_data){
1249 .name = "gcc_cfg_noc_pcie_anoc_ahb_clk",
1250 .ops = &clk_branch2_ops,
1255 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1256 .halt_reg = 0x49084,
1257 .halt_check = BRANCH_HALT_VOTED,
1258 .hwcg_reg = 0x49084,
1261 .enable_reg = 0x49084,
1262 .enable_mask = BIT(0),
1263 .hw.init = &(struct clk_init_data){
1264 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1265 .parent_data = &(const struct clk_parent_data){
1266 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
1269 .flags = CLK_SET_RATE_PARENT,
1270 .ops = &clk_branch2_ops,
1275 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1276 .halt_reg = 0x81154,
1277 .halt_check = BRANCH_HALT_SKIP,
1278 .hwcg_reg = 0x81154,
1281 .enable_reg = 0x81154,
1282 .enable_mask = BIT(0),
1283 .hw.init = &(struct clk_init_data){
1284 .name = "gcc_ddrss_gpu_axi_clk",
1285 .ops = &clk_branch2_aon_ops,
1290 static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = {
1291 .halt_reg = 0x9d094,
1292 .halt_check = BRANCH_HALT_SKIP,
1293 .hwcg_reg = 0x9d094,
1296 .enable_reg = 0x62000,
1297 .enable_mask = BIT(19),
1298 .hw.init = &(struct clk_init_data){
1299 .name = "gcc_ddrss_pcie_sf_tbu_clk",
1300 .ops = &clk_branch2_ops,
1305 static struct clk_branch gcc_disp_hf_axi_clk = {
1306 .halt_reg = 0x3700c,
1307 .halt_check = BRANCH_HALT_SKIP,
1308 .hwcg_reg = 0x3700c,
1311 .enable_reg = 0x3700c,
1312 .enable_mask = BIT(0),
1313 .hw.init = &(struct clk_init_data){
1314 .name = "gcc_disp_hf_axi_clk",
1315 .ops = &clk_branch2_ops,
1320 static struct clk_branch gcc_disp_sf_axi_clk = {
1321 .halt_reg = 0x37014,
1322 .halt_check = BRANCH_HALT_SKIP,
1323 .hwcg_reg = 0x37014,
1326 .enable_reg = 0x37014,
1327 .enable_mask = BIT(0),
1328 .hw.init = &(struct clk_init_data){
1329 .name = "gcc_disp_sf_axi_clk",
1330 .ops = &clk_branch2_ops,
1335 static struct clk_branch gcc_eusb3_0_clkref_en = {
1336 .halt_reg = 0x9c00c,
1337 .halt_check = BRANCH_HALT,
1339 .enable_reg = 0x9c00c,
1340 .enable_mask = BIT(0),
1341 .hw.init = &(struct clk_init_data){
1342 .name = "gcc_eusb3_0_clkref_en",
1343 .ops = &clk_branch2_ops,
1348 static struct clk_branch gcc_gp1_clk = {
1349 .halt_reg = 0x74000,
1350 .halt_check = BRANCH_HALT,
1352 .enable_reg = 0x74000,
1353 .enable_mask = BIT(0),
1354 .hw.init = &(struct clk_init_data){
1355 .name = "gcc_gp1_clk",
1356 .parent_data = &(const struct clk_parent_data){
1357 .hw = &gcc_gp1_clk_src.clkr.hw,
1360 .flags = CLK_SET_RATE_PARENT,
1361 .ops = &clk_branch2_ops,
1366 static struct clk_branch gcc_gp2_clk = {
1367 .halt_reg = 0x75000,
1368 .halt_check = BRANCH_HALT,
1370 .enable_reg = 0x75000,
1371 .enable_mask = BIT(0),
1372 .hw.init = &(struct clk_init_data){
1373 .name = "gcc_gp2_clk",
1374 .parent_data = &(const struct clk_parent_data){
1375 .hw = &gcc_gp2_clk_src.clkr.hw,
1378 .flags = CLK_SET_RATE_PARENT,
1379 .ops = &clk_branch2_ops,
1384 static struct clk_branch gcc_gp3_clk = {
1385 .halt_reg = 0x76000,
1386 .halt_check = BRANCH_HALT,
1388 .enable_reg = 0x76000,
1389 .enable_mask = BIT(0),
1390 .hw.init = &(struct clk_init_data){
1391 .name = "gcc_gp3_clk",
1392 .parent_data = &(const struct clk_parent_data){
1393 .hw = &gcc_gp3_clk_src.clkr.hw,
1396 .flags = CLK_SET_RATE_PARENT,
1397 .ops = &clk_branch2_ops,
1402 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1403 .halt_check = BRANCH_HALT_DELAY,
1405 .enable_reg = 0x62000,
1406 .enable_mask = BIT(15),
1407 .hw.init = &(struct clk_init_data){
1408 .name = "gcc_gpu_gpll0_clk_src",
1409 .parent_data = &(const struct clk_parent_data){
1410 .hw = &gcc_gpll0.clkr.hw,
1413 .flags = CLK_SET_RATE_PARENT,
1414 .ops = &clk_branch2_ops,
1419 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1420 .halt_check = BRANCH_HALT_DELAY,
1422 .enable_reg = 0x62000,
1423 .enable_mask = BIT(16),
1424 .hw.init = &(struct clk_init_data){
1425 .name = "gcc_gpu_gpll0_div_clk_src",
1426 .parent_data = &(const struct clk_parent_data){
1427 .hw = &gcc_gpll0_out_even.clkr.hw,
1430 .flags = CLK_SET_RATE_PARENT,
1431 .ops = &clk_branch2_ops,
1436 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1437 .halt_reg = 0x81010,
1438 .halt_check = BRANCH_HALT_VOTED,
1439 .hwcg_reg = 0x81010,
1442 .enable_reg = 0x81010,
1443 .enable_mask = BIT(0),
1444 .hw.init = &(struct clk_init_data){
1445 .name = "gcc_gpu_memnoc_gfx_clk",
1446 .ops = &clk_branch2_ops,
1451 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1452 .halt_reg = 0x81018,
1453 .halt_check = BRANCH_HALT_DELAY,
1455 .enable_reg = 0x81018,
1456 .enable_mask = BIT(0),
1457 .hw.init = &(struct clk_init_data){
1458 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1459 .ops = &clk_branch2_ops,
1464 static struct clk_branch gcc_pcie_0_aux_clk = {
1465 .halt_reg = 0x7b034,
1466 .halt_check = BRANCH_HALT_VOTED,
1468 .enable_reg = 0x62008,
1469 .enable_mask = BIT(3),
1470 .hw.init = &(struct clk_init_data){
1471 .name = "gcc_pcie_0_aux_clk",
1472 .parent_data = &(const struct clk_parent_data){
1473 .hw = &gcc_pcie_0_aux_clk_src.clkr.hw,
1476 .flags = CLK_SET_RATE_PARENT,
1477 .ops = &clk_branch2_ops,
1482 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1483 .halt_reg = 0x7b030,
1484 .halt_check = BRANCH_HALT_VOTED,
1485 .hwcg_reg = 0x7b030,
1488 .enable_reg = 0x62008,
1489 .enable_mask = BIT(2),
1490 .hw.init = &(struct clk_init_data){
1491 .name = "gcc_pcie_0_cfg_ahb_clk",
1492 .ops = &clk_branch2_ops,
1497 static struct clk_branch gcc_pcie_0_clkref_en = {
1498 .halt_reg = 0x9c004,
1499 .halt_check = BRANCH_HALT,
1501 .enable_reg = 0x9c004,
1502 .enable_mask = BIT(0),
1503 .hw.init = &(struct clk_init_data){
1504 .name = "gcc_pcie_0_clkref_en",
1505 .ops = &clk_branch2_ops,
1510 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1511 .halt_reg = 0x7b028,
1512 .halt_check = BRANCH_HALT_SKIP,
1514 .enable_reg = 0x62008,
1515 .enable_mask = BIT(1),
1516 .hw.init = &(struct clk_init_data){
1517 .name = "gcc_pcie_0_mstr_axi_clk",
1518 .ops = &clk_branch2_ops,
1523 static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
1524 .halt_reg = 0x7b044,
1525 .halt_check = BRANCH_HALT_VOTED,
1527 .enable_reg = 0x62000,
1528 .enable_mask = BIT(22),
1529 .hw.init = &(struct clk_init_data){
1530 .name = "gcc_pcie_0_phy_rchng_clk",
1531 .parent_data = &(const struct clk_parent_data){
1532 .hw = &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
1535 .flags = CLK_SET_RATE_PARENT,
1536 .ops = &clk_branch2_ops,
1541 static struct clk_branch gcc_pcie_0_pipe_clk = {
1542 .halt_reg = 0x7b03c,
1543 .halt_check = BRANCH_HALT_SKIP,
1545 .enable_reg = 0x62008,
1546 .enable_mask = BIT(4),
1547 .hw.init = &(struct clk_init_data){
1548 .name = "gcc_pcie_0_pipe_clk",
1549 .parent_data = &(const struct clk_parent_data){
1550 .hw = &gcc_pcie_0_pipe_clk_src.clkr.hw,
1553 .flags = CLK_SET_RATE_PARENT,
1554 .ops = &clk_branch2_ops,
1559 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1560 .halt_reg = 0x7b020,
1561 .halt_check = BRANCH_HALT_VOTED,
1562 .hwcg_reg = 0x7b020,
1565 .enable_reg = 0x62008,
1566 .enable_mask = BIT(0),
1567 .hw.init = &(struct clk_init_data){
1568 .name = "gcc_pcie_0_slv_axi_clk",
1569 .ops = &clk_branch2_ops,
1574 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1575 .halt_reg = 0x7b01c,
1576 .halt_check = BRANCH_HALT_VOTED,
1578 .enable_reg = 0x62008,
1579 .enable_mask = BIT(5),
1580 .hw.init = &(struct clk_init_data){
1581 .name = "gcc_pcie_0_slv_q2a_axi_clk",
1582 .ops = &clk_branch2_ops,
1587 static struct clk_branch gcc_pcie_1_aux_clk = {
1588 .halt_reg = 0x9d030,
1589 .halt_check = BRANCH_HALT_VOTED,
1591 .enable_reg = 0x62000,
1592 .enable_mask = BIT(29),
1593 .hw.init = &(struct clk_init_data){
1594 .name = "gcc_pcie_1_aux_clk",
1595 .parent_data = &(const struct clk_parent_data){
1596 .hw = &gcc_pcie_1_aux_clk_src.clkr.hw,
1599 .flags = CLK_SET_RATE_PARENT,
1600 .ops = &clk_branch2_ops,
1605 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1606 .halt_reg = 0x9d02c,
1607 .halt_check = BRANCH_HALT_VOTED,
1608 .hwcg_reg = 0x9d02c,
1611 .enable_reg = 0x62000,
1612 .enable_mask = BIT(28),
1613 .hw.init = &(struct clk_init_data){
1614 .name = "gcc_pcie_1_cfg_ahb_clk",
1615 .ops = &clk_branch2_ops,
1620 static struct clk_branch gcc_pcie_1_clkref_en = {
1621 .halt_reg = 0x9c008,
1622 .halt_check = BRANCH_HALT,
1624 .enable_reg = 0x9c008,
1625 .enable_mask = BIT(0),
1626 .hw.init = &(struct clk_init_data){
1627 .name = "gcc_pcie_1_clkref_en",
1628 .ops = &clk_branch2_ops,
1633 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1634 .halt_reg = 0x9d024,
1635 .halt_check = BRANCH_HALT_SKIP,
1637 .enable_reg = 0x62000,
1638 .enable_mask = BIT(27),
1639 .hw.init = &(struct clk_init_data){
1640 .name = "gcc_pcie_1_mstr_axi_clk",
1641 .ops = &clk_branch2_ops,
1646 static struct clk_branch gcc_pcie_1_phy_aux_clk = {
1647 .halt_reg = 0x9d038,
1648 .halt_check = BRANCH_HALT_VOTED,
1650 .enable_reg = 0x62000,
1651 .enable_mask = BIT(24),
1652 .hw.init = &(struct clk_init_data){
1653 .name = "gcc_pcie_1_phy_aux_clk",
1654 .parent_data = &(const struct clk_parent_data){
1655 .hw = &gcc_pcie_1_phy_aux_clk_src.clkr.hw,
1658 .flags = CLK_SET_RATE_PARENT,
1659 .ops = &clk_branch2_ops,
1664 static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
1665 .halt_reg = 0x9d048,
1666 .halt_check = BRANCH_HALT_VOTED,
1668 .enable_reg = 0x62000,
1669 .enable_mask = BIT(23),
1670 .hw.init = &(struct clk_init_data){
1671 .name = "gcc_pcie_1_phy_rchng_clk",
1672 .parent_data = &(const struct clk_parent_data){
1673 .hw = &gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
1676 .flags = CLK_SET_RATE_PARENT,
1677 .ops = &clk_branch2_ops,
1682 static struct clk_branch gcc_pcie_1_pipe_clk = {
1683 .halt_reg = 0x9d040,
1684 .halt_check = BRANCH_HALT_SKIP,
1686 .enable_reg = 0x62000,
1687 .enable_mask = BIT(30),
1688 .hw.init = &(struct clk_init_data){
1689 .name = "gcc_pcie_1_pipe_clk",
1690 .parent_data = &(const struct clk_parent_data){
1691 .hw = &gcc_pcie_1_pipe_clk_src.clkr.hw,
1694 .flags = CLK_SET_RATE_PARENT,
1695 .ops = &clk_branch2_ops,
1700 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1701 .halt_reg = 0x9d01c,
1702 .halt_check = BRANCH_HALT_VOTED,
1703 .hwcg_reg = 0x9d01c,
1706 .enable_reg = 0x62000,
1707 .enable_mask = BIT(26),
1708 .hw.init = &(struct clk_init_data){
1709 .name = "gcc_pcie_1_slv_axi_clk",
1710 .ops = &clk_branch2_ops,
1715 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1716 .halt_reg = 0x9d018,
1717 .halt_check = BRANCH_HALT_VOTED,
1719 .enable_reg = 0x62000,
1720 .enable_mask = BIT(25),
1721 .hw.init = &(struct clk_init_data){
1722 .name = "gcc_pcie_1_slv_q2a_axi_clk",
1723 .ops = &clk_branch2_ops,
1728 static struct clk_branch gcc_pdm2_clk = {
1729 .halt_reg = 0x4300c,
1730 .halt_check = BRANCH_HALT,
1732 .enable_reg = 0x4300c,
1733 .enable_mask = BIT(0),
1734 .hw.init = &(struct clk_init_data){
1735 .name = "gcc_pdm2_clk",
1736 .parent_data = &(const struct clk_parent_data){
1737 .hw = &gcc_pdm2_clk_src.clkr.hw,
1740 .flags = CLK_SET_RATE_PARENT,
1741 .ops = &clk_branch2_ops,
1746 static struct clk_branch gcc_pdm_ahb_clk = {
1747 .halt_reg = 0x43004,
1748 .halt_check = BRANCH_HALT_VOTED,
1749 .hwcg_reg = 0x43004,
1752 .enable_reg = 0x43004,
1753 .enable_mask = BIT(0),
1754 .hw.init = &(struct clk_init_data){
1755 .name = "gcc_pdm_ahb_clk",
1756 .ops = &clk_branch2_ops,
1761 static struct clk_branch gcc_pdm_xo4_clk = {
1762 .halt_reg = 0x43008,
1763 .halt_check = BRANCH_HALT,
1765 .enable_reg = 0x43008,
1766 .enable_mask = BIT(0),
1767 .hw.init = &(struct clk_init_data){
1768 .name = "gcc_pdm_xo4_clk",
1769 .ops = &clk_branch2_ops,
1774 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
1775 .halt_reg = 0x36008,
1776 .halt_check = BRANCH_HALT_VOTED,
1777 .hwcg_reg = 0x36008,
1780 .enable_reg = 0x36008,
1781 .enable_mask = BIT(0),
1782 .hw.init = &(struct clk_init_data){
1783 .name = "gcc_qmip_camera_nrt_ahb_clk",
1784 .ops = &clk_branch2_ops,
1789 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
1790 .halt_reg = 0x3600c,
1791 .halt_check = BRANCH_HALT_VOTED,
1792 .hwcg_reg = 0x3600c,
1795 .enable_reg = 0x3600c,
1796 .enable_mask = BIT(0),
1797 .hw.init = &(struct clk_init_data){
1798 .name = "gcc_qmip_camera_rt_ahb_clk",
1799 .ops = &clk_branch2_ops,
1804 static struct clk_branch gcc_qmip_disp_ahb_clk = {
1805 .halt_reg = 0x37008,
1806 .halt_check = BRANCH_HALT_VOTED,
1807 .hwcg_reg = 0x37008,
1810 .enable_reg = 0x37008,
1811 .enable_mask = BIT(0),
1812 .hw.init = &(struct clk_init_data){
1813 .name = "gcc_qmip_disp_ahb_clk",
1814 .ops = &clk_branch2_ops,
1819 static struct clk_branch gcc_qmip_gpu_ahb_clk = {
1820 .halt_reg = 0x81008,
1821 .halt_check = BRANCH_HALT_VOTED,
1822 .hwcg_reg = 0x81008,
1825 .enable_reg = 0x81008,
1826 .enable_mask = BIT(0),
1827 .hw.init = &(struct clk_init_data){
1828 .name = "gcc_qmip_gpu_ahb_clk",
1829 .ops = &clk_branch2_ops,
1834 static struct clk_branch gcc_qmip_pcie_ahb_clk = {
1835 .halt_reg = 0x7b018,
1836 .halt_check = BRANCH_HALT_VOTED,
1837 .hwcg_reg = 0x7b018,
1840 .enable_reg = 0x7b018,
1841 .enable_mask = BIT(0),
1842 .hw.init = &(struct clk_init_data){
1843 .name = "gcc_qmip_pcie_ahb_clk",
1844 .ops = &clk_branch2_ops,
1849 static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = {
1850 .halt_reg = 0x42014,
1851 .halt_check = BRANCH_HALT_VOTED,
1852 .hwcg_reg = 0x42014,
1855 .enable_reg = 0x42014,
1856 .enable_mask = BIT(0),
1857 .hw.init = &(struct clk_init_data){
1858 .name = "gcc_qmip_video_cv_cpu_ahb_clk",
1859 .ops = &clk_branch2_ops,
1864 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
1865 .halt_reg = 0x42008,
1866 .halt_check = BRANCH_HALT_VOTED,
1867 .hwcg_reg = 0x42008,
1870 .enable_reg = 0x42008,
1871 .enable_mask = BIT(0),
1872 .hw.init = &(struct clk_init_data){
1873 .name = "gcc_qmip_video_cvp_ahb_clk",
1874 .ops = &clk_branch2_ops,
1879 static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {
1880 .halt_reg = 0x42010,
1881 .halt_check = BRANCH_HALT_VOTED,
1882 .hwcg_reg = 0x42010,
1885 .enable_reg = 0x42010,
1886 .enable_mask = BIT(0),
1887 .hw.init = &(struct clk_init_data){
1888 .name = "gcc_qmip_video_v_cpu_ahb_clk",
1889 .ops = &clk_branch2_ops,
1894 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
1895 .halt_reg = 0x4200c,
1896 .halt_check = BRANCH_HALT_VOTED,
1897 .hwcg_reg = 0x4200c,
1900 .enable_reg = 0x4200c,
1901 .enable_mask = BIT(0),
1902 .hw.init = &(struct clk_init_data){
1903 .name = "gcc_qmip_video_vcodec_ahb_clk",
1904 .ops = &clk_branch2_ops,
1909 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
1910 .halt_reg = 0x3300c,
1911 .halt_check = BRANCH_HALT_VOTED,
1913 .enable_reg = 0x62008,
1914 .enable_mask = BIT(9),
1915 .hw.init = &(struct clk_init_data){
1916 .name = "gcc_qupv3_wrap0_core_2x_clk",
1917 .ops = &clk_branch2_ops,
1922 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
1923 .halt_reg = 0x33000,
1924 .halt_check = BRANCH_HALT_VOTED,
1926 .enable_reg = 0x62008,
1927 .enable_mask = BIT(8),
1928 .hw.init = &(struct clk_init_data){
1929 .name = "gcc_qupv3_wrap0_core_clk",
1930 .ops = &clk_branch2_ops,
1935 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
1936 .halt_reg = 0x2700c,
1937 .halt_check = BRANCH_HALT_VOTED,
1939 .enable_reg = 0x62008,
1940 .enable_mask = BIT(10),
1941 .hw.init = &(struct clk_init_data){
1942 .name = "gcc_qupv3_wrap0_s0_clk",
1943 .parent_data = &(const struct clk_parent_data){
1944 .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
1947 .flags = CLK_SET_RATE_PARENT,
1948 .ops = &clk_branch2_ops,
1953 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
1954 .halt_reg = 0x27140,
1955 .halt_check = BRANCH_HALT_VOTED,
1957 .enable_reg = 0x62008,
1958 .enable_mask = BIT(11),
1959 .hw.init = &(struct clk_init_data){
1960 .name = "gcc_qupv3_wrap0_s1_clk",
1961 .parent_data = &(const struct clk_parent_data){
1962 .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
1965 .flags = CLK_SET_RATE_PARENT,
1966 .ops = &clk_branch2_ops,
1971 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
1972 .halt_reg = 0x27274,
1973 .halt_check = BRANCH_HALT_VOTED,
1975 .enable_reg = 0x62008,
1976 .enable_mask = BIT(12),
1977 .hw.init = &(struct clk_init_data){
1978 .name = "gcc_qupv3_wrap0_s2_clk",
1979 .parent_data = &(const struct clk_parent_data){
1980 .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
1983 .flags = CLK_SET_RATE_PARENT,
1984 .ops = &clk_branch2_ops,
1989 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
1990 .halt_reg = 0x273a8,
1991 .halt_check = BRANCH_HALT_VOTED,
1993 .enable_reg = 0x62008,
1994 .enable_mask = BIT(13),
1995 .hw.init = &(struct clk_init_data){
1996 .name = "gcc_qupv3_wrap0_s3_clk",
1997 .parent_data = &(const struct clk_parent_data){
1998 .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2001 .flags = CLK_SET_RATE_PARENT,
2002 .ops = &clk_branch2_ops,
2007 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2008 .halt_reg = 0x274dc,
2009 .halt_check = BRANCH_HALT_VOTED,
2011 .enable_reg = 0x62008,
2012 .enable_mask = BIT(14),
2013 .hw.init = &(struct clk_init_data){
2014 .name = "gcc_qupv3_wrap0_s4_clk",
2015 .parent_data = &(const struct clk_parent_data){
2016 .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2019 .flags = CLK_SET_RATE_PARENT,
2020 .ops = &clk_branch2_ops,
2025 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2026 .halt_reg = 0x27610,
2027 .halt_check = BRANCH_HALT_VOTED,
2029 .enable_reg = 0x62008,
2030 .enable_mask = BIT(15),
2031 .hw.init = &(struct clk_init_data){
2032 .name = "gcc_qupv3_wrap0_s5_clk",
2033 .parent_data = &(const struct clk_parent_data){
2034 .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2037 .flags = CLK_SET_RATE_PARENT,
2038 .ops = &clk_branch2_ops,
2043 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2044 .halt_reg = 0x27744,
2045 .halt_check = BRANCH_HALT_VOTED,
2047 .enable_reg = 0x62008,
2048 .enable_mask = BIT(16),
2049 .hw.init = &(struct clk_init_data){
2050 .name = "gcc_qupv3_wrap0_s6_clk",
2051 .parent_data = &(const struct clk_parent_data){
2052 .hw = &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
2055 .flags = CLK_SET_RATE_PARENT,
2056 .ops = &clk_branch2_ops,
2061 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2062 .halt_reg = 0x27878,
2063 .halt_check = BRANCH_HALT_VOTED,
2065 .enable_reg = 0x62008,
2066 .enable_mask = BIT(17),
2067 .hw.init = &(struct clk_init_data){
2068 .name = "gcc_qupv3_wrap0_s7_clk",
2069 .parent_data = &(const struct clk_parent_data){
2070 .hw = &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
2073 .flags = CLK_SET_RATE_PARENT,
2074 .ops = &clk_branch2_ops,
2079 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
2080 .halt_reg = 0x3314c,
2081 .halt_check = BRANCH_HALT_VOTED,
2083 .enable_reg = 0x62008,
2084 .enable_mask = BIT(18),
2085 .hw.init = &(struct clk_init_data){
2086 .name = "gcc_qupv3_wrap1_core_2x_clk",
2087 .ops = &clk_branch2_ops,
2092 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
2093 .halt_reg = 0x33140,
2094 .halt_check = BRANCH_HALT_VOTED,
2096 .enable_reg = 0x62008,
2097 .enable_mask = BIT(19),
2098 .hw.init = &(struct clk_init_data){
2099 .name = "gcc_qupv3_wrap1_core_clk",
2100 .ops = &clk_branch2_ops,
2105 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2106 .halt_reg = 0x2800c,
2107 .halt_check = BRANCH_HALT_VOTED,
2109 .enable_reg = 0x62008,
2110 .enable_mask = BIT(22),
2111 .hw.init = &(struct clk_init_data){
2112 .name = "gcc_qupv3_wrap1_s0_clk",
2113 .parent_data = &(const struct clk_parent_data){
2114 .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2117 .flags = CLK_SET_RATE_PARENT,
2118 .ops = &clk_branch2_ops,
2123 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2124 .halt_reg = 0x28140,
2125 .halt_check = BRANCH_HALT_VOTED,
2127 .enable_reg = 0x62008,
2128 .enable_mask = BIT(23),
2129 .hw.init = &(struct clk_init_data){
2130 .name = "gcc_qupv3_wrap1_s1_clk",
2131 .parent_data = &(const struct clk_parent_data){
2132 .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2135 .flags = CLK_SET_RATE_PARENT,
2136 .ops = &clk_branch2_ops,
2141 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2142 .halt_reg = 0x28274,
2143 .halt_check = BRANCH_HALT_VOTED,
2145 .enable_reg = 0x62008,
2146 .enable_mask = BIT(24),
2147 .hw.init = &(struct clk_init_data){
2148 .name = "gcc_qupv3_wrap1_s2_clk",
2149 .parent_data = &(const struct clk_parent_data){
2150 .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2153 .flags = CLK_SET_RATE_PARENT,
2154 .ops = &clk_branch2_ops,
2159 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2160 .halt_reg = 0x283a8,
2161 .halt_check = BRANCH_HALT_VOTED,
2163 .enable_reg = 0x62008,
2164 .enable_mask = BIT(25),
2165 .hw.init = &(struct clk_init_data){
2166 .name = "gcc_qupv3_wrap1_s3_clk",
2167 .parent_data = &(const struct clk_parent_data){
2168 .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2171 .flags = CLK_SET_RATE_PARENT,
2172 .ops = &clk_branch2_ops,
2177 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2178 .halt_reg = 0x284dc,
2179 .halt_check = BRANCH_HALT_VOTED,
2181 .enable_reg = 0x62008,
2182 .enable_mask = BIT(26),
2183 .hw.init = &(struct clk_init_data){
2184 .name = "gcc_qupv3_wrap1_s4_clk",
2185 .parent_data = &(const struct clk_parent_data){
2186 .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2189 .flags = CLK_SET_RATE_PARENT,
2190 .ops = &clk_branch2_ops,
2195 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2196 .halt_reg = 0x28610,
2197 .halt_check = BRANCH_HALT_VOTED,
2199 .enable_reg = 0x62008,
2200 .enable_mask = BIT(27),
2201 .hw.init = &(struct clk_init_data){
2202 .name = "gcc_qupv3_wrap1_s5_clk",
2203 .parent_data = &(const struct clk_parent_data){
2204 .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2207 .flags = CLK_SET_RATE_PARENT,
2208 .ops = &clk_branch2_ops,
2213 static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
2214 .halt_reg = 0x28744,
2215 .halt_check = BRANCH_HALT_VOTED,
2217 .enable_reg = 0x62008,
2218 .enable_mask = BIT(28),
2219 .hw.init = &(struct clk_init_data){
2220 .name = "gcc_qupv3_wrap1_s6_clk",
2221 .parent_data = &(const struct clk_parent_data){
2222 .hw = &gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
2225 .flags = CLK_SET_RATE_PARENT,
2226 .ops = &clk_branch2_ops,
2231 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
2232 .halt_reg = 0x3328c,
2233 .halt_check = BRANCH_HALT_VOTED,
2235 .enable_reg = 0x62010,
2236 .enable_mask = BIT(3),
2237 .hw.init = &(struct clk_init_data){
2238 .name = "gcc_qupv3_wrap2_core_2x_clk",
2239 .ops = &clk_branch2_ops,
2244 static struct clk_branch gcc_qupv3_wrap2_core_clk = {
2245 .halt_reg = 0x33280,
2246 .halt_check = BRANCH_HALT_VOTED,
2248 .enable_reg = 0x62010,
2249 .enable_mask = BIT(0),
2250 .hw.init = &(struct clk_init_data){
2251 .name = "gcc_qupv3_wrap2_core_clk",
2252 .ops = &clk_branch2_ops,
2257 static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2258 .halt_reg = 0x2e00c,
2259 .halt_check = BRANCH_HALT_VOTED,
2261 .enable_reg = 0x62010,
2262 .enable_mask = BIT(4),
2263 .hw.init = &(struct clk_init_data){
2264 .name = "gcc_qupv3_wrap2_s0_clk",
2265 .parent_data = &(const struct clk_parent_data){
2266 .hw = &gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
2269 .flags = CLK_SET_RATE_PARENT,
2270 .ops = &clk_branch2_ops,
2275 static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2276 .halt_reg = 0x2e140,
2277 .halt_check = BRANCH_HALT_VOTED,
2279 .enable_reg = 0x62010,
2280 .enable_mask = BIT(5),
2281 .hw.init = &(struct clk_init_data){
2282 .name = "gcc_qupv3_wrap2_s1_clk",
2283 .parent_data = &(const struct clk_parent_data){
2284 .hw = &gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
2287 .flags = CLK_SET_RATE_PARENT,
2288 .ops = &clk_branch2_ops,
2293 static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2294 .halt_reg = 0x2e274,
2295 .halt_check = BRANCH_HALT_VOTED,
2297 .enable_reg = 0x62010,
2298 .enable_mask = BIT(6),
2299 .hw.init = &(struct clk_init_data){
2300 .name = "gcc_qupv3_wrap2_s2_clk",
2301 .parent_data = &(const struct clk_parent_data){
2302 .hw = &gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
2305 .flags = CLK_SET_RATE_PARENT,
2306 .ops = &clk_branch2_ops,
2311 static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2312 .halt_reg = 0x2e3a8,
2313 .halt_check = BRANCH_HALT_VOTED,
2315 .enable_reg = 0x62010,
2316 .enable_mask = BIT(7),
2317 .hw.init = &(struct clk_init_data){
2318 .name = "gcc_qupv3_wrap2_s3_clk",
2319 .parent_data = &(const struct clk_parent_data){
2320 .hw = &gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
2323 .flags = CLK_SET_RATE_PARENT,
2324 .ops = &clk_branch2_ops,
2329 static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2330 .halt_reg = 0x2e4dc,
2331 .halt_check = BRANCH_HALT_VOTED,
2333 .enable_reg = 0x62010,
2334 .enable_mask = BIT(8),
2335 .hw.init = &(struct clk_init_data){
2336 .name = "gcc_qupv3_wrap2_s4_clk",
2337 .parent_data = &(const struct clk_parent_data){
2338 .hw = &gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
2341 .flags = CLK_SET_RATE_PARENT,
2342 .ops = &clk_branch2_ops,
2347 static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2348 .halt_reg = 0x2e610,
2349 .halt_check = BRANCH_HALT_VOTED,
2351 .enable_reg = 0x62010,
2352 .enable_mask = BIT(9),
2353 .hw.init = &(struct clk_init_data){
2354 .name = "gcc_qupv3_wrap2_s5_clk",
2355 .parent_data = &(const struct clk_parent_data){
2356 .hw = &gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
2359 .flags = CLK_SET_RATE_PARENT,
2360 .ops = &clk_branch2_ops,
2365 static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
2366 .halt_reg = 0x2e744,
2367 .halt_check = BRANCH_HALT_VOTED,
2369 .enable_reg = 0x62010,
2370 .enable_mask = BIT(10),
2371 .hw.init = &(struct clk_init_data){
2372 .name = "gcc_qupv3_wrap2_s6_clk",
2373 .parent_data = &(const struct clk_parent_data){
2374 .hw = &gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
2377 .flags = CLK_SET_RATE_PARENT,
2378 .ops = &clk_branch2_ops,
2383 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2384 .halt_reg = 0x27004,
2385 .halt_check = BRANCH_HALT_VOTED,
2386 .hwcg_reg = 0x27004,
2389 .enable_reg = 0x62008,
2390 .enable_mask = BIT(6),
2391 .hw.init = &(struct clk_init_data){
2392 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2393 .ops = &clk_branch2_ops,
2398 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2399 .halt_reg = 0x27008,
2400 .halt_check = BRANCH_HALT_VOTED,
2401 .hwcg_reg = 0x27008,
2404 .enable_reg = 0x62008,
2405 .enable_mask = BIT(7),
2406 .hw.init = &(struct clk_init_data){
2407 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2408 .ops = &clk_branch2_ops,
2413 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2414 .halt_reg = 0x28004,
2415 .halt_check = BRANCH_HALT_VOTED,
2416 .hwcg_reg = 0x28004,
2419 .enable_reg = 0x62008,
2420 .enable_mask = BIT(20),
2421 .hw.init = &(struct clk_init_data){
2422 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2423 .ops = &clk_branch2_ops,
2428 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2429 .halt_reg = 0x28008,
2430 .halt_check = BRANCH_HALT_VOTED,
2431 .hwcg_reg = 0x28008,
2434 .enable_reg = 0x62008,
2435 .enable_mask = BIT(21),
2436 .hw.init = &(struct clk_init_data){
2437 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2438 .ops = &clk_branch2_ops,
2443 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
2444 .halt_reg = 0x2e004,
2445 .halt_check = BRANCH_HALT_VOTED,
2446 .hwcg_reg = 0x2e004,
2449 .enable_reg = 0x62010,
2450 .enable_mask = BIT(2),
2451 .hw.init = &(struct clk_init_data){
2452 .name = "gcc_qupv3_wrap_2_m_ahb_clk",
2453 .ops = &clk_branch2_ops,
2458 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
2459 .halt_reg = 0x2e008,
2460 .halt_check = BRANCH_HALT_VOTED,
2461 .hwcg_reg = 0x2e008,
2464 .enable_reg = 0x62010,
2465 .enable_mask = BIT(1),
2466 .hw.init = &(struct clk_init_data){
2467 .name = "gcc_qupv3_wrap_2_s_ahb_clk",
2468 .ops = &clk_branch2_ops,
2473 static struct clk_branch gcc_sdcc2_ahb_clk = {
2474 .halt_reg = 0x2400c,
2475 .halt_check = BRANCH_HALT,
2477 .enable_reg = 0x2400c,
2478 .enable_mask = BIT(0),
2479 .hw.init = &(struct clk_init_data){
2480 .name = "gcc_sdcc2_ahb_clk",
2481 .ops = &clk_branch2_ops,
2486 static struct clk_branch gcc_sdcc2_apps_clk = {
2487 .halt_reg = 0x24004,
2488 .halt_check = BRANCH_HALT,
2490 .enable_reg = 0x24004,
2491 .enable_mask = BIT(0),
2492 .hw.init = &(struct clk_init_data){
2493 .name = "gcc_sdcc2_apps_clk",
2494 .parent_data = &(const struct clk_parent_data){
2495 .hw = &gcc_sdcc2_apps_clk_src.clkr.hw,
2498 .flags = CLK_SET_RATE_PARENT,
2499 .ops = &clk_branch2_ops,
2504 static struct clk_branch gcc_sdcc2_at_clk = {
2505 .halt_reg = 0x24010,
2506 .halt_check = BRANCH_HALT_VOTED,
2507 .hwcg_reg = 0x24010,
2510 .enable_reg = 0x24010,
2511 .enable_mask = BIT(0),
2512 .hw.init = &(struct clk_init_data){
2513 .name = "gcc_sdcc2_at_clk",
2514 .ops = &clk_branch2_ops,
2519 static struct clk_branch gcc_sdcc4_ahb_clk = {
2520 .halt_reg = 0x2600c,
2521 .halt_check = BRANCH_HALT,
2523 .enable_reg = 0x2600c,
2524 .enable_mask = BIT(0),
2525 .hw.init = &(struct clk_init_data){
2526 .name = "gcc_sdcc4_ahb_clk",
2527 .ops = &clk_branch2_ops,
2532 static struct clk_branch gcc_sdcc4_apps_clk = {
2533 .halt_reg = 0x26004,
2534 .halt_check = BRANCH_HALT,
2536 .enable_reg = 0x26004,
2537 .enable_mask = BIT(0),
2538 .hw.init = &(struct clk_init_data){
2539 .name = "gcc_sdcc4_apps_clk",
2540 .parent_data = &(const struct clk_parent_data){
2541 .hw = &gcc_sdcc4_apps_clk_src.clkr.hw,
2544 .flags = CLK_SET_RATE_PARENT,
2545 .ops = &clk_branch2_ops,
2550 static struct clk_branch gcc_sdcc4_at_clk = {
2551 .halt_reg = 0x26010,
2552 .halt_check = BRANCH_HALT_VOTED,
2553 .hwcg_reg = 0x26010,
2556 .enable_reg = 0x26010,
2557 .enable_mask = BIT(0),
2558 .hw.init = &(struct clk_init_data){
2559 .name = "gcc_sdcc4_at_clk",
2560 .ops = &clk_branch2_ops,
2565 static struct clk_branch gcc_ufs_0_clkref_en = {
2566 .halt_reg = 0x9c000,
2567 .halt_check = BRANCH_HALT,
2569 .enable_reg = 0x9c000,
2570 .enable_mask = BIT(0),
2571 .hw.init = &(struct clk_init_data){
2572 .name = "gcc_ufs_0_clkref_en",
2573 .ops = &clk_branch2_ops,
2578 static struct clk_branch gcc_ufs_phy_ahb_clk = {
2579 .halt_reg = 0x87020,
2580 .halt_check = BRANCH_HALT_VOTED,
2581 .hwcg_reg = 0x87020,
2584 .enable_reg = 0x87020,
2585 .enable_mask = BIT(0),
2586 .hw.init = &(struct clk_init_data){
2587 .name = "gcc_ufs_phy_ahb_clk",
2588 .ops = &clk_branch2_ops,
2593 static struct clk_branch gcc_ufs_phy_axi_clk = {
2594 .halt_reg = 0x87018,
2595 .halt_check = BRANCH_HALT_VOTED,
2596 .hwcg_reg = 0x87018,
2599 .enable_reg = 0x87018,
2600 .enable_mask = BIT(0),
2601 .hw.init = &(struct clk_init_data){
2602 .name = "gcc_ufs_phy_axi_clk",
2603 .parent_data = &(const struct clk_parent_data){
2604 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
2607 .flags = CLK_SET_RATE_PARENT,
2608 .ops = &clk_branch2_ops,
2613 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
2614 .halt_reg = 0x87018,
2615 .halt_check = BRANCH_HALT_VOTED,
2616 .hwcg_reg = 0x87018,
2619 .enable_reg = 0x87018,
2620 .enable_mask = BIT(1),
2621 .hw.init = &(struct clk_init_data){
2622 .name = "gcc_ufs_phy_axi_hw_ctl_clk",
2623 .parent_data = &(const struct clk_parent_data){
2624 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
2627 .flags = CLK_SET_RATE_PARENT,
2628 .ops = &clk_branch2_ops,
2633 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2634 .halt_reg = 0x8706c,
2635 .halt_check = BRANCH_HALT_VOTED,
2636 .hwcg_reg = 0x8706c,
2639 .enable_reg = 0x8706c,
2640 .enable_mask = BIT(0),
2641 .hw.init = &(struct clk_init_data){
2642 .name = "gcc_ufs_phy_ice_core_clk",
2643 .parent_data = &(const struct clk_parent_data){
2644 .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2647 .flags = CLK_SET_RATE_PARENT,
2648 .ops = &clk_branch2_ops,
2653 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
2654 .halt_reg = 0x8706c,
2655 .halt_check = BRANCH_HALT_VOTED,
2656 .hwcg_reg = 0x8706c,
2659 .enable_reg = 0x8706c,
2660 .enable_mask = BIT(1),
2661 .hw.init = &(struct clk_init_data){
2662 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
2663 .parent_data = &(const struct clk_parent_data){
2664 .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2667 .flags = CLK_SET_RATE_PARENT,
2668 .ops = &clk_branch2_ops,
2673 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2674 .halt_reg = 0x870a4,
2675 .halt_check = BRANCH_HALT_VOTED,
2676 .hwcg_reg = 0x870a4,
2679 .enable_reg = 0x870a4,
2680 .enable_mask = BIT(0),
2681 .hw.init = &(struct clk_init_data){
2682 .name = "gcc_ufs_phy_phy_aux_clk",
2683 .parent_data = &(const struct clk_parent_data){
2684 .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2687 .flags = CLK_SET_RATE_PARENT,
2688 .ops = &clk_branch2_ops,
2693 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
2694 .halt_reg = 0x870a4,
2695 .halt_check = BRANCH_HALT_VOTED,
2696 .hwcg_reg = 0x870a4,
2699 .enable_reg = 0x870a4,
2700 .enable_mask = BIT(1),
2701 .hw.init = &(struct clk_init_data){
2702 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
2703 .parent_data = &(const struct clk_parent_data){
2704 .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2707 .flags = CLK_SET_RATE_PARENT,
2708 .ops = &clk_branch2_ops,
2713 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2714 .halt_reg = 0x87028,
2715 .halt_check = BRANCH_HALT_DELAY,
2717 .enable_reg = 0x87028,
2718 .enable_mask = BIT(0),
2719 .hw.init = &(struct clk_init_data){
2720 .name = "gcc_ufs_phy_rx_symbol_0_clk",
2721 .parent_data = &(const struct clk_parent_data){
2722 .hw = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
2725 .flags = CLK_SET_RATE_PARENT,
2726 .ops = &clk_branch2_ops,
2731 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2732 .halt_reg = 0x870c0,
2733 .halt_check = BRANCH_HALT_DELAY,
2735 .enable_reg = 0x870c0,
2736 .enable_mask = BIT(0),
2737 .hw.init = &(struct clk_init_data){
2738 .name = "gcc_ufs_phy_rx_symbol_1_clk",
2739 .parent_data = &(const struct clk_parent_data){
2740 .hw = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
2743 .flags = CLK_SET_RATE_PARENT,
2744 .ops = &clk_branch2_ops,
2749 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2750 .halt_reg = 0x87024,
2751 .halt_check = BRANCH_HALT_DELAY,
2753 .enable_reg = 0x87024,
2754 .enable_mask = BIT(0),
2755 .hw.init = &(struct clk_init_data){
2756 .name = "gcc_ufs_phy_tx_symbol_0_clk",
2757 .parent_data = &(const struct clk_parent_data){
2758 .hw = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
2761 .flags = CLK_SET_RATE_PARENT,
2762 .ops = &clk_branch2_ops,
2767 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2768 .halt_reg = 0x87064,
2769 .halt_check = BRANCH_HALT_VOTED,
2770 .hwcg_reg = 0x87064,
2773 .enable_reg = 0x87064,
2774 .enable_mask = BIT(0),
2775 .hw.init = &(struct clk_init_data){
2776 .name = "gcc_ufs_phy_unipro_core_clk",
2777 .parent_data = &(const struct clk_parent_data){
2778 .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2781 .flags = CLK_SET_RATE_PARENT,
2782 .ops = &clk_branch2_ops,
2787 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
2788 .halt_reg = 0x87064,
2789 .halt_check = BRANCH_HALT_VOTED,
2790 .hwcg_reg = 0x87064,
2793 .enable_reg = 0x87064,
2794 .enable_mask = BIT(1),
2795 .hw.init = &(struct clk_init_data){
2796 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
2797 .parent_data = &(const struct clk_parent_data){
2798 .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2801 .flags = CLK_SET_RATE_PARENT,
2802 .ops = &clk_branch2_ops,
2807 static struct clk_branch gcc_usb30_prim_master_clk = {
2808 .halt_reg = 0x49018,
2809 .halt_check = BRANCH_HALT,
2811 .enable_reg = 0x49018,
2812 .enable_mask = BIT(0),
2813 .hw.init = &(struct clk_init_data){
2814 .name = "gcc_usb30_prim_master_clk",
2815 .parent_data = &(const struct clk_parent_data){
2816 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
2819 .flags = CLK_SET_RATE_PARENT,
2820 .ops = &clk_branch2_ops,
2825 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2826 .halt_reg = 0x49024,
2827 .halt_check = BRANCH_HALT,
2829 .enable_reg = 0x49024,
2830 .enable_mask = BIT(0),
2831 .hw.init = &(struct clk_init_data){
2832 .name = "gcc_usb30_prim_mock_utmi_clk",
2833 .parent_data = &(const struct clk_parent_data){
2834 .hw = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
2837 .flags = CLK_SET_RATE_PARENT,
2838 .ops = &clk_branch2_ops,
2843 static struct clk_branch gcc_usb30_prim_sleep_clk = {
2844 .halt_reg = 0x49020,
2845 .halt_check = BRANCH_HALT,
2847 .enable_reg = 0x49020,
2848 .enable_mask = BIT(0),
2849 .hw.init = &(struct clk_init_data){
2850 .name = "gcc_usb30_prim_sleep_clk",
2851 .ops = &clk_branch2_ops,
2856 static struct clk_branch gcc_usb3_0_clkref_en = {
2857 .halt_reg = 0x9c010,
2858 .halt_check = BRANCH_HALT,
2860 .enable_reg = 0x9c010,
2861 .enable_mask = BIT(0),
2862 .hw.init = &(struct clk_init_data){
2863 .name = "gcc_usb3_0_clkref_en",
2864 .ops = &clk_branch2_ops,
2869 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2870 .halt_reg = 0x4905c,
2871 .halt_check = BRANCH_HALT,
2873 .enable_reg = 0x4905c,
2874 .enable_mask = BIT(0),
2875 .hw.init = &(struct clk_init_data){
2876 .name = "gcc_usb3_prim_phy_aux_clk",
2877 .parent_data = &(const struct clk_parent_data){
2878 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2881 .flags = CLK_SET_RATE_PARENT,
2882 .ops = &clk_branch2_ops,
2887 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2888 .halt_reg = 0x49060,
2889 .halt_check = BRANCH_HALT,
2891 .enable_reg = 0x49060,
2892 .enable_mask = BIT(0),
2893 .hw.init = &(struct clk_init_data){
2894 .name = "gcc_usb3_prim_phy_com_aux_clk",
2895 .parent_data = &(const struct clk_parent_data){
2896 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2899 .flags = CLK_SET_RATE_PARENT,
2900 .ops = &clk_branch2_ops,
2905 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2906 .halt_reg = 0x49064,
2907 .halt_check = BRANCH_HALT_DELAY,
2908 .hwcg_reg = 0x49064,
2911 .enable_reg = 0x49064,
2912 .enable_mask = BIT(0),
2913 .hw.init = &(struct clk_init_data){
2914 .name = "gcc_usb3_prim_phy_pipe_clk",
2915 .parent_data = &(const struct clk_parent_data){
2916 .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
2919 .flags = CLK_SET_RATE_PARENT,
2920 .ops = &clk_branch2_ops,
2925 static struct clk_branch gcc_video_axi0_clk = {
2926 .halt_reg = 0x42018,
2927 .halt_check = BRANCH_HALT_SKIP,
2928 .hwcg_reg = 0x42018,
2931 .enable_reg = 0x42018,
2932 .enable_mask = BIT(0),
2933 .hw.init = &(struct clk_init_data){
2934 .name = "gcc_video_axi0_clk",
2935 .ops = &clk_branch2_ops,
2940 static struct clk_branch gcc_video_axi1_clk = {
2941 .halt_reg = 0x42020,
2942 .halt_check = BRANCH_HALT_SKIP,
2943 .hwcg_reg = 0x42020,
2946 .enable_reg = 0x42020,
2947 .enable_mask = BIT(0),
2948 .hw.init = &(struct clk_init_data){
2949 .name = "gcc_video_axi1_clk",
2950 .ops = &clk_branch2_ops,
2955 static struct gdsc pcie_0_gdsc = {
2958 .name = "pcie_0_gdsc",
2960 .pwrsts = PWRSTS_OFF_ON,
2963 static struct gdsc pcie_1_gdsc = {
2966 .name = "pcie_1_gdsc",
2968 .pwrsts = PWRSTS_OFF_ON,
2971 static struct gdsc ufs_phy_gdsc = {
2974 .name = "ufs_phy_gdsc",
2976 .pwrsts = PWRSTS_OFF_ON,
2979 static struct gdsc usb30_prim_gdsc = {
2982 .name = "usb30_prim_gdsc",
2984 .pwrsts = PWRSTS_OFF_ON,
2987 static struct clk_regmap *gcc_sm8450_clocks[] = {
2988 [GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr,
2989 [GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr,
2990 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
2991 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
2992 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
2993 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2994 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
2995 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
2996 [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,
2997 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
2998 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
2999 [GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr,
3000 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3001 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
3002 [GCC_EUSB3_0_CLKREF_EN] = &gcc_eusb3_0_clkref_en.clkr,
3003 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3004 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3005 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3006 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3007 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3008 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3009 [GCC_GPLL0] = &gcc_gpll0.clkr,
3010 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
3011 [GCC_GPLL4] = &gcc_gpll4.clkr,
3012 [GCC_GPLL9] = &gcc_gpll9.clkr,
3013 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3014 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3015 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3016 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3017 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3018 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3019 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3020 [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,
3021 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3022 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
3023 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
3024 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3025 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
3026 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3027 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3028 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3029 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3030 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3031 [GCC_PCIE_1_CLKREF_EN] = &gcc_pcie_1_clkref_en.clkr,
3032 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3033 [GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr,
3034 [GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr,
3035 [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
3036 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
3037 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3038 [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
3039 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3040 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3041 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3042 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3043 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3044 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3045 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3046 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3047 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3048 [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,
3049 [GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr,
3050 [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr,
3051 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
3052 [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr,
3053 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3054 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3055 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3056 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3057 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3058 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3059 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3060 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3061 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3062 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3063 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3064 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3065 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3066 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3067 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3068 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3069 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3070 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3071 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3072 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
3073 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
3074 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3075 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3076 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3077 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3078 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3079 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3080 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3081 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3082 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3083 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3084 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3085 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3086 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3087 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3088 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
3089 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
3090 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
3091 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
3092 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
3093 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
3094 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
3095 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
3096 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
3097 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
3098 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
3099 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
3100 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
3101 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
3102 [GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
3103 [GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
3104 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3105 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3106 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3107 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3108 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
3109 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
3110 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3111 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3112 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3113 [GCC_SDCC2_AT_CLK] = &gcc_sdcc2_at_clk.clkr,
3114 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3115 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3116 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3117 [GCC_SDCC4_AT_CLK] = &gcc_sdcc4_at_clk.clkr,
3118 [GCC_UFS_0_CLKREF_EN] = &gcc_ufs_0_clkref_en.clkr,
3119 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3120 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3121 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3122 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
3123 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3124 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3125 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
3126 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3127 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3128 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
3129 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3130 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
3131 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3132 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
3133 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3134 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
3135 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3136 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
3137 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
3138 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3139 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3140 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3141 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3142 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3143 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3144 [GCC_USB3_0_CLKREF_EN] = &gcc_usb3_0_clkref_en.clkr,
3145 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3146 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3147 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3148 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3149 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
3150 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3151 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
3154 static const struct qcom_reset_map gcc_sm8450_resets[] = {
3155 [GCC_CAMERA_BCR] = { 0x36000 },
3156 [GCC_DISPLAY_BCR] = { 0x37000 },
3157 [GCC_GPU_BCR] = { 0x81000 },
3158 [GCC_PCIE_0_BCR] = { 0x7b000 },
3159 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x7c014 },
3160 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x7c020 },
3161 [GCC_PCIE_0_PHY_BCR] = { 0x7c01c },
3162 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x7c028 },
3163 [GCC_PCIE_1_BCR] = { 0x9d000 },
3164 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x9e014 },
3165 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x9e020 },
3166 [GCC_PCIE_1_PHY_BCR] = { 0x9e01c },
3167 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x9e000 },
3168 [GCC_PCIE_PHY_BCR] = { 0x7f000 },
3169 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x7f00c },
3170 [GCC_PCIE_PHY_COM_BCR] = { 0x7f010 },
3171 [GCC_PDM_BCR] = { 0x43000 },
3172 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x27000 },
3173 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x28000 },
3174 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x2e000 },
3175 [GCC_QUSB2PHY_PRIM_BCR] = { 0x22000 },
3176 [GCC_QUSB2PHY_SEC_BCR] = { 0x22004 },
3177 [GCC_SDCC2_BCR] = { 0x24000 },
3178 [GCC_SDCC4_BCR] = { 0x26000 },
3179 [GCC_UFS_PHY_BCR] = { 0x87000 },
3180 [GCC_USB30_PRIM_BCR] = { 0x49000 },
3181 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x60008 },
3182 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x60014 },
3183 [GCC_USB3_PHY_PRIM_BCR] = { 0x60000 },
3184 [GCC_USB3_PHY_SEC_BCR] = { 0x6000c },
3185 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 },
3186 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 },
3187 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 },
3188 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x42018, 2 },
3189 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x42020, 2 },
3190 [GCC_VIDEO_BCR] = { 0x42000 },
3193 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3194 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3195 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3196 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3197 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3198 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3199 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3200 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3201 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
3202 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3203 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3204 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3205 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3206 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3207 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3208 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
3209 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
3210 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
3211 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
3212 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
3213 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
3214 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
3215 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),
3218 static struct gdsc *gcc_sm8450_gdscs[] = {
3219 [PCIE_0_GDSC] = &pcie_0_gdsc,
3220 [PCIE_1_GDSC] = &pcie_1_gdsc,
3221 [UFS_PHY_GDSC] = &ufs_phy_gdsc,
3222 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3225 static const struct regmap_config gcc_sm8450_regmap_config = {
3229 .max_register = 0x1f1030,
3233 static const struct qcom_cc_desc gcc_sm8450_desc = {
3234 .config = &gcc_sm8450_regmap_config,
3235 .clks = gcc_sm8450_clocks,
3236 .num_clks = ARRAY_SIZE(gcc_sm8450_clocks),
3237 .resets = gcc_sm8450_resets,
3238 .num_resets = ARRAY_SIZE(gcc_sm8450_resets),
3239 .gdscs = gcc_sm8450_gdscs,
3240 .num_gdscs = ARRAY_SIZE(gcc_sm8450_gdscs),
3243 static const struct of_device_id gcc_sm8450_match_table[] = {
3244 { .compatible = "qcom,gcc-sm8450" },
3247 MODULE_DEVICE_TABLE(of, gcc_sm8450_match_table);
3249 static int gcc_sm8450_probe(struct platform_device *pdev)
3251 struct regmap *regmap;
3254 regmap = qcom_cc_map(pdev, &gcc_sm8450_desc);
3256 return PTR_ERR(regmap);
3258 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
3259 ARRAY_SIZE(gcc_dfs_clocks));
3263 /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
3264 regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
3267 * Keep the critical clock always-On
3268 * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk,
3269 * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk,
3272 regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0));
3273 regmap_update_bits(regmap, 0x36020, BIT(0), BIT(0));
3274 regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0));
3275 regmap_update_bits(regmap, 0x3701c, BIT(0), BIT(0));
3276 regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0));
3277 regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0));
3278 regmap_update_bits(regmap, 0x42028, BIT(0), BIT(0));
3280 return qcom_cc_really_probe(pdev, &gcc_sm8450_desc, regmap);
3283 static struct platform_driver gcc_sm8450_driver = {
3284 .probe = gcc_sm8450_probe,
3286 .name = "gcc-sm8450",
3287 .of_match_table = gcc_sm8450_match_table,
3291 static int __init gcc_sm8450_init(void)
3293 return platform_driver_register(&gcc_sm8450_driver);
3295 subsys_initcall(gcc_sm8450_init);
3297 static void __exit gcc_sm8450_exit(void)
3299 platform_driver_unregister(&gcc_sm8450_driver);
3301 module_exit(gcc_sm8450_exit);
3303 MODULE_DESCRIPTION("QTI GCC SM8450 Driver");
3304 MODULE_LICENSE("GPL v2");