1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2021, Linaro Limited
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
11 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
13 #include "clk-alpha-pll.h"
14 #include "clk-branch.h"
16 #include "clk-regmap.h"
17 #include "clk-regmap-divider.h"
18 #include "clk-regmap-mux.h"
24 P_CORE_BI_PLL_TEST_SE,
32 P_UFS_CARD_RX_SYMBOL_0_CLK,
33 P_UFS_CARD_RX_SYMBOL_1_CLK,
34 P_UFS_CARD_TX_SYMBOL_0_CLK,
35 P_UFS_PHY_RX_SYMBOL_0_CLK,
36 P_UFS_PHY_RX_SYMBOL_1_CLK,
37 P_UFS_PHY_TX_SYMBOL_0_CLK,
38 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
39 P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK,
42 static struct clk_alpha_pll gcc_gpll0 = {
44 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
46 .enable_reg = 0x52018,
47 .enable_mask = BIT(0),
48 .hw.init = &(struct clk_init_data){
50 .parent_data = &(const struct clk_parent_data){
54 .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
59 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
64 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
67 .post_div_table = post_div_table_gcc_gpll0_out_even,
68 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
70 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
71 .clkr.hw.init = &(struct clk_init_data){
72 .name = "gcc_gpll0_out_even",
73 .parent_data = &(const struct clk_parent_data){
74 .hw = &gcc_gpll0.clkr.hw,
77 .ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops,
81 static struct clk_alpha_pll gcc_gpll4 = {
83 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
85 .enable_reg = 0x52018,
86 .enable_mask = BIT(4),
87 .hw.init = &(struct clk_init_data){
89 .parent_data = &(const struct clk_parent_data){
94 .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
99 static struct clk_alpha_pll gcc_gpll9 = {
101 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
103 .enable_reg = 0x52018,
104 .enable_mask = BIT(9),
105 .hw.init = &(struct clk_init_data){
107 .parent_data = &(const struct clk_parent_data){
108 .fw_name = "bi_tcxo",
112 .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
117 static const struct parent_map gcc_parent_map_0[] = {
119 { P_GCC_GPLL0_OUT_MAIN, 1 },
120 { P_GCC_GPLL0_OUT_EVEN, 6 },
121 { P_CORE_BI_PLL_TEST_SE, 7 },
124 static const struct clk_parent_data gcc_parent_data_0[] = {
125 { .fw_name = "bi_tcxo" },
126 { .hw = &gcc_gpll0.clkr.hw },
127 { .hw = &gcc_gpll0_out_even.clkr.hw },
128 { .fw_name = "core_bi_pll_test_se" },
131 static const struct parent_map gcc_parent_map_1[] = {
133 { P_GCC_GPLL0_OUT_MAIN, 1 },
135 { P_GCC_GPLL0_OUT_EVEN, 6 },
136 { P_CORE_BI_PLL_TEST_SE, 7 },
139 static const struct clk_parent_data gcc_parent_data_1[] = {
140 { .fw_name = "bi_tcxo" },
141 { .hw = &gcc_gpll0.clkr.hw },
142 { .fw_name = "sleep_clk" },
143 { .hw = &gcc_gpll0_out_even.clkr.hw },
144 { .fw_name = "core_bi_pll_test_se" },
147 static const struct parent_map gcc_parent_map_2[] = {
150 { P_CORE_BI_PLL_TEST_SE, 7 },
153 static const struct clk_parent_data gcc_parent_data_2[] = {
154 { .fw_name = "bi_tcxo" },
155 { .fw_name = "sleep_clk" },
156 { .fw_name = "core_bi_pll_test_se" },
159 static const struct parent_map gcc_parent_map_3[] = {
161 { P_CORE_BI_PLL_TEST_SE, 7 },
164 static const struct clk_parent_data gcc_parent_data_3[] = {
165 { .fw_name = "bi_tcxo" },
166 { .fw_name = "core_bi_pll_test_se" },
169 static const struct parent_map gcc_parent_map_4[] = {
170 { P_PCIE_0_PIPE_CLK, 0 },
174 static const struct clk_parent_data gcc_parent_data_4[] = {
175 { .fw_name = "pcie_0_pipe_clk", },
176 { .fw_name = "bi_tcxo" },
179 static const struct parent_map gcc_parent_map_5[] = {
180 { P_PCIE_1_PIPE_CLK, 0 },
184 static const struct clk_parent_data gcc_parent_data_5[] = {
185 { .fw_name = "pcie_1_pipe_clk" },
186 { .fw_name = "bi_tcxo" },
189 static const struct parent_map gcc_parent_map_6[] = {
191 { P_GCC_GPLL0_OUT_MAIN, 1 },
192 { P_GCC_GPLL9_OUT_MAIN, 2 },
193 { P_GCC_GPLL4_OUT_MAIN, 5 },
194 { P_GCC_GPLL0_OUT_EVEN, 6 },
195 { P_CORE_BI_PLL_TEST_SE, 7 },
198 static const struct clk_parent_data gcc_parent_data_6[] = {
199 { .fw_name = "bi_tcxo" },
200 { .hw = &gcc_gpll0.clkr.hw },
201 { .hw = &gcc_gpll9.clkr.hw },
202 { .hw = &gcc_gpll4.clkr.hw },
203 { .hw = &gcc_gpll0_out_even.clkr.hw },
204 { .fw_name = "core_bi_pll_test_se" },
207 static const struct parent_map gcc_parent_map_7[] = {
208 { P_UFS_CARD_RX_SYMBOL_0_CLK, 0 },
212 static const struct clk_parent_data gcc_parent_data_7[] = {
213 { .fw_name = "ufs_card_rx_symbol_0_clk" },
214 { .fw_name = "bi_tcxo" },
217 static const struct parent_map gcc_parent_map_8[] = {
218 { P_UFS_CARD_RX_SYMBOL_1_CLK, 0 },
222 static const struct clk_parent_data gcc_parent_data_8[] = {
223 { .fw_name = "ufs_card_rx_symbol_1_clk" },
224 { .fw_name = "bi_tcxo" },
227 static const struct parent_map gcc_parent_map_9[] = {
228 { P_UFS_CARD_TX_SYMBOL_0_CLK, 0 },
232 static const struct clk_parent_data gcc_parent_data_9[] = {
233 { .fw_name = "ufs_card_tx_symbol_0_clk" },
234 { .fw_name = "bi_tcxo" },
237 static const struct parent_map gcc_parent_map_10[] = {
238 { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
242 static const struct clk_parent_data gcc_parent_data_10[] = {
243 { .fw_name = "ufs_phy_rx_symbol_0_clk" },
244 { .fw_name = "bi_tcxo" },
247 static const struct parent_map gcc_parent_map_11[] = {
248 { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
252 static const struct clk_parent_data gcc_parent_data_11[] = {
253 { .fw_name = "ufs_phy_rx_symbol_1_clk" },
254 { .fw_name = "bi_tcxo" },
257 static const struct parent_map gcc_parent_map_12[] = {
258 { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
262 static const struct clk_parent_data gcc_parent_data_12[] = {
263 { .fw_name = "ufs_phy_tx_symbol_0_clk" },
264 { .fw_name = "bi_tcxo" },
267 static const struct parent_map gcc_parent_map_13[] = {
268 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
269 { P_CORE_BI_PLL_TEST_SE, 1 },
273 static const struct clk_parent_data gcc_parent_data_13[] = {
274 { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
275 { .fw_name = "core_bi_pll_test_se" },
276 { .fw_name = "bi_tcxo" },
279 static const struct parent_map gcc_parent_map_14[] = {
280 { P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK, 0 },
281 { P_CORE_BI_PLL_TEST_SE, 1 },
285 static const struct clk_parent_data gcc_parent_data_14[] = {
286 { .fw_name = "usb3_uni_phy_sec_gcc_usb30_pipe_clk" },
287 { .fw_name = "core_bi_pll_test_se" },
288 { .fw_name = "bi_tcxo" },
291 static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
295 .parent_map = gcc_parent_map_4,
297 .hw.init = &(struct clk_init_data){
298 .name = "gcc_pcie_0_pipe_clk_src",
299 .parent_data = gcc_parent_data_4,
301 .ops = &clk_regmap_mux_closest_ops,
306 static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
310 .parent_map = gcc_parent_map_5,
312 .hw.init = &(struct clk_init_data){
313 .name = "gcc_pcie_1_pipe_clk_src",
314 .parent_data = gcc_parent_data_5,
316 .ops = &clk_regmap_mux_closest_ops,
321 static struct clk_regmap_mux gcc_ufs_card_rx_symbol_0_clk_src = {
325 .parent_map = gcc_parent_map_7,
327 .hw.init = &(struct clk_init_data){
328 .name = "gcc_ufs_card_rx_symbol_0_clk_src",
329 .parent_data = gcc_parent_data_7,
331 .ops = &clk_regmap_mux_closest_ops,
336 static struct clk_regmap_mux gcc_ufs_card_rx_symbol_1_clk_src = {
340 .parent_map = gcc_parent_map_8,
342 .hw.init = &(struct clk_init_data){
343 .name = "gcc_ufs_card_rx_symbol_1_clk_src",
344 .parent_data = gcc_parent_data_8,
346 .ops = &clk_regmap_mux_closest_ops,
351 static struct clk_regmap_mux gcc_ufs_card_tx_symbol_0_clk_src = {
355 .parent_map = gcc_parent_map_9,
357 .hw.init = &(struct clk_init_data){
358 .name = "gcc_ufs_card_tx_symbol_0_clk_src",
359 .parent_data = gcc_parent_data_9,
361 .ops = &clk_regmap_mux_closest_ops,
366 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
370 .parent_map = gcc_parent_map_10,
372 .hw.init = &(struct clk_init_data){
373 .name = "gcc_ufs_phy_rx_symbol_0_clk_src",
374 .parent_data = gcc_parent_data_10,
376 .ops = &clk_regmap_mux_closest_ops,
381 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
385 .parent_map = gcc_parent_map_11,
387 .hw.init = &(struct clk_init_data){
388 .name = "gcc_ufs_phy_rx_symbol_1_clk_src",
389 .parent_data = gcc_parent_data_11,
391 .ops = &clk_regmap_mux_closest_ops,
396 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
400 .parent_map = gcc_parent_map_12,
402 .hw.init = &(struct clk_init_data){
403 .name = "gcc_ufs_phy_tx_symbol_0_clk_src",
404 .parent_data = gcc_parent_data_12,
406 .ops = &clk_regmap_mux_closest_ops,
411 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
415 .parent_map = gcc_parent_map_13,
417 .hw.init = &(struct clk_init_data){
418 .name = "gcc_usb3_prim_phy_pipe_clk_src",
419 .parent_data = gcc_parent_data_13,
421 .ops = &clk_regmap_mux_closest_ops,
426 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
430 .parent_map = gcc_parent_map_14,
432 .hw.init = &(struct clk_init_data){
433 .name = "gcc_usb3_sec_phy_pipe_clk_src",
434 .parent_data = gcc_parent_data_14,
436 .ops = &clk_regmap_mux_closest_ops,
441 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
442 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
443 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
444 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
448 static struct clk_rcg2 gcc_gp1_clk_src = {
452 .parent_map = gcc_parent_map_1,
453 .freq_tbl = ftbl_gcc_gp1_clk_src,
454 .clkr.hw.init = &(struct clk_init_data){
455 .name = "gcc_gp1_clk_src",
456 .parent_data = gcc_parent_data_1,
458 .flags = CLK_SET_RATE_PARENT,
459 .ops = &clk_rcg2_ops,
463 static struct clk_rcg2 gcc_gp2_clk_src = {
467 .parent_map = gcc_parent_map_1,
468 .freq_tbl = ftbl_gcc_gp1_clk_src,
469 .clkr.hw.init = &(struct clk_init_data){
470 .name = "gcc_gp2_clk_src",
471 .parent_data = gcc_parent_data_1,
473 .flags = CLK_SET_RATE_PARENT,
474 .ops = &clk_rcg2_ops,
478 static struct clk_rcg2 gcc_gp3_clk_src = {
482 .parent_map = gcc_parent_map_1,
483 .freq_tbl = ftbl_gcc_gp1_clk_src,
484 .clkr.hw.init = &(struct clk_init_data){
485 .name = "gcc_gp3_clk_src",
486 .parent_data = gcc_parent_data_1,
488 .flags = CLK_SET_RATE_PARENT,
489 .ops = &clk_rcg2_ops,
493 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
494 F(9600000, P_BI_TCXO, 2, 0, 0),
495 F(19200000, P_BI_TCXO, 1, 0, 0),
499 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
503 .parent_map = gcc_parent_map_2,
504 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
505 .clkr.hw.init = &(struct clk_init_data){
506 .name = "gcc_pcie_0_aux_clk_src",
507 .parent_data = gcc_parent_data_2,
509 .flags = CLK_SET_RATE_PARENT,
510 .ops = &clk_rcg2_ops,
514 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
515 F(19200000, P_BI_TCXO, 1, 0, 0),
516 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
520 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
524 .parent_map = gcc_parent_map_0,
525 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
526 .clkr.hw.init = &(struct clk_init_data){
527 .name = "gcc_pcie_0_phy_rchng_clk_src",
528 .parent_data = gcc_parent_data_0,
530 .flags = CLK_SET_RATE_PARENT,
531 .ops = &clk_rcg2_ops,
535 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
539 .parent_map = gcc_parent_map_2,
540 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
541 .clkr.hw.init = &(struct clk_init_data){
542 .name = "gcc_pcie_1_aux_clk_src",
543 .parent_data = gcc_parent_data_2,
545 .flags = CLK_SET_RATE_PARENT,
546 .ops = &clk_rcg2_ops,
550 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
554 .parent_map = gcc_parent_map_0,
555 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
556 .clkr.hw.init = &(struct clk_init_data){
557 .name = "gcc_pcie_1_phy_rchng_clk_src",
558 .parent_data = gcc_parent_data_0,
560 .flags = CLK_SET_RATE_PARENT,
561 .ops = &clk_rcg2_ops,
565 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
566 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
570 static struct clk_rcg2 gcc_pdm2_clk_src = {
574 .parent_map = gcc_parent_map_0,
575 .freq_tbl = ftbl_gcc_pdm2_clk_src,
576 .clkr.hw.init = &(struct clk_init_data){
577 .name = "gcc_pdm2_clk_src",
578 .parent_data = gcc_parent_data_0,
580 .flags = CLK_SET_RATE_PARENT,
581 .ops = &clk_rcg2_ops,
585 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
586 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
587 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
588 F(19200000, P_BI_TCXO, 1, 0, 0),
589 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
590 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
591 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
592 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
593 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
594 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
595 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
596 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
600 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
601 .name = "gcc_qupv3_wrap0_s0_clk_src",
602 .parent_data = gcc_parent_data_0,
604 .flags = CLK_SET_RATE_PARENT,
605 .ops = &clk_rcg2_ops,
608 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
612 .parent_map = gcc_parent_map_0,
613 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
614 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
617 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
618 .name = "gcc_qupv3_wrap0_s1_clk_src",
619 .parent_data = gcc_parent_data_0,
621 .flags = CLK_SET_RATE_PARENT,
622 .ops = &clk_rcg2_ops,
625 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
629 .parent_map = gcc_parent_map_0,
630 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
631 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
634 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
635 .name = "gcc_qupv3_wrap0_s2_clk_src",
636 .parent_data = gcc_parent_data_0,
638 .flags = CLK_SET_RATE_PARENT,
639 .ops = &clk_rcg2_ops,
642 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
646 .parent_map = gcc_parent_map_0,
647 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
648 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
651 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
652 .name = "gcc_qupv3_wrap0_s3_clk_src",
653 .parent_data = gcc_parent_data_0,
655 .flags = CLK_SET_RATE_PARENT,
656 .ops = &clk_rcg2_ops,
659 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
663 .parent_map = gcc_parent_map_0,
664 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
665 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
668 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
669 .name = "gcc_qupv3_wrap0_s4_clk_src",
670 .parent_data = gcc_parent_data_0,
672 .flags = CLK_SET_RATE_PARENT,
673 .ops = &clk_rcg2_ops,
676 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
680 .parent_map = gcc_parent_map_0,
681 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
682 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
685 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
686 .name = "gcc_qupv3_wrap0_s5_clk_src",
687 .parent_data = gcc_parent_data_0,
689 .flags = CLK_SET_RATE_PARENT,
690 .ops = &clk_rcg2_ops,
693 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
697 .parent_map = gcc_parent_map_0,
698 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
699 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
702 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
703 .name = "gcc_qupv3_wrap0_s6_clk_src",
704 .parent_data = gcc_parent_data_0,
706 .flags = CLK_SET_RATE_PARENT,
707 .ops = &clk_rcg2_ops,
710 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
714 .parent_map = gcc_parent_map_0,
715 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
716 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
719 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
720 .name = "gcc_qupv3_wrap0_s7_clk_src",
721 .parent_data = gcc_parent_data_0,
723 .flags = CLK_SET_RATE_PARENT,
724 .ops = &clk_rcg2_ops,
727 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
731 .parent_map = gcc_parent_map_0,
732 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
733 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
736 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = {
737 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
738 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
739 F(19200000, P_BI_TCXO, 1, 0, 0),
740 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
741 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
742 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
743 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
744 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
745 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
746 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
747 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
748 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
749 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
750 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
751 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
755 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
756 .name = "gcc_qupv3_wrap1_s0_clk_src",
757 .parent_data = gcc_parent_data_0,
759 .flags = CLK_SET_RATE_PARENT,
760 .ops = &clk_rcg2_ops,
763 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
767 .parent_map = gcc_parent_map_0,
768 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
769 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
772 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
773 .name = "gcc_qupv3_wrap1_s1_clk_src",
774 .parent_data = gcc_parent_data_0,
776 .flags = CLK_SET_RATE_PARENT,
777 .ops = &clk_rcg2_ops,
780 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
784 .parent_map = gcc_parent_map_0,
785 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
786 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
789 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
790 .name = "gcc_qupv3_wrap1_s2_clk_src",
791 .parent_data = gcc_parent_data_0,
793 .flags = CLK_SET_RATE_PARENT,
794 .ops = &clk_rcg2_ops,
797 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
801 .parent_map = gcc_parent_map_0,
802 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
803 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
806 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
807 .name = "gcc_qupv3_wrap1_s3_clk_src",
808 .parent_data = gcc_parent_data_0,
810 .flags = CLK_SET_RATE_PARENT,
811 .ops = &clk_rcg2_ops,
814 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
818 .parent_map = gcc_parent_map_0,
819 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
820 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
823 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
824 .name = "gcc_qupv3_wrap1_s4_clk_src",
825 .parent_data = gcc_parent_data_0,
827 .flags = CLK_SET_RATE_PARENT,
828 .ops = &clk_rcg2_ops,
831 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
835 .parent_map = gcc_parent_map_0,
836 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
837 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
840 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
841 .name = "gcc_qupv3_wrap1_s5_clk_src",
842 .parent_data = gcc_parent_data_0,
844 .flags = CLK_SET_RATE_PARENT,
845 .ops = &clk_rcg2_ops,
848 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
852 .parent_map = gcc_parent_map_0,
853 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
854 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
857 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
858 .name = "gcc_qupv3_wrap2_s0_clk_src",
859 .parent_data = gcc_parent_data_0,
861 .flags = CLK_SET_RATE_PARENT,
862 .ops = &clk_rcg2_ops,
865 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
869 .parent_map = gcc_parent_map_0,
870 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
871 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
874 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
875 .name = "gcc_qupv3_wrap2_s1_clk_src",
876 .parent_data = gcc_parent_data_0,
878 .flags = CLK_SET_RATE_PARENT,
879 .ops = &clk_rcg2_ops,
882 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
886 .parent_map = gcc_parent_map_0,
887 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
888 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
891 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
892 .name = "gcc_qupv3_wrap2_s2_clk_src",
893 .parent_data = gcc_parent_data_0,
895 .flags = CLK_SET_RATE_PARENT,
896 .ops = &clk_rcg2_ops,
899 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
903 .parent_map = gcc_parent_map_0,
904 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
905 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
908 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
909 .name = "gcc_qupv3_wrap2_s3_clk_src",
910 .parent_data = gcc_parent_data_0,
912 .flags = CLK_SET_RATE_PARENT,
913 .ops = &clk_rcg2_ops,
916 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
920 .parent_map = gcc_parent_map_0,
921 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
922 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
925 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
926 .name = "gcc_qupv3_wrap2_s4_clk_src",
927 .parent_data = gcc_parent_data_0,
929 .flags = CLK_SET_RATE_PARENT,
930 .ops = &clk_rcg2_ops,
933 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
937 .parent_map = gcc_parent_map_0,
938 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
939 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
942 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
943 .name = "gcc_qupv3_wrap2_s5_clk_src",
944 .parent_data = gcc_parent_data_0,
946 .flags = CLK_SET_RATE_PARENT,
947 .ops = &clk_rcg2_ops,
950 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
954 .parent_map = gcc_parent_map_0,
955 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
956 .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
959 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
960 F(400000, P_BI_TCXO, 12, 1, 4),
961 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
962 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
963 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
964 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
968 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
972 .parent_map = gcc_parent_map_6,
973 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
974 .clkr.hw.init = &(struct clk_init_data){
975 .name = "gcc_sdcc2_apps_clk_src",
976 .parent_data = gcc_parent_data_6,
978 .flags = CLK_SET_RATE_PARENT,
979 .ops = &clk_rcg2_floor_ops,
983 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
984 F(400000, P_BI_TCXO, 12, 1, 4),
985 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
986 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
990 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
994 .parent_map = gcc_parent_map_0,
995 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
996 .clkr.hw.init = &(struct clk_init_data){
997 .name = "gcc_sdcc4_apps_clk_src",
998 .parent_data = gcc_parent_data_0,
1000 .flags = CLK_SET_RATE_PARENT,
1001 .ops = &clk_rcg2_floor_ops,
1005 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
1006 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1007 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1008 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1009 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1013 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
1014 .cmd_rcgr = 0x75024,
1017 .parent_map = gcc_parent_map_0,
1018 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
1019 .clkr.hw.init = &(struct clk_init_data){
1020 .name = "gcc_ufs_card_axi_clk_src",
1021 .parent_data = gcc_parent_data_0,
1023 .flags = CLK_SET_RATE_PARENT,
1024 .ops = &clk_rcg2_ops,
1028 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
1029 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1030 F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1031 F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1035 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
1036 .cmd_rcgr = 0x7506c,
1039 .parent_map = gcc_parent_map_0,
1040 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1041 .clkr.hw.init = &(struct clk_init_data){
1042 .name = "gcc_ufs_card_ice_core_clk_src",
1043 .parent_data = gcc_parent_data_0,
1045 .flags = CLK_SET_RATE_PARENT,
1046 .ops = &clk_rcg2_ops,
1050 static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = {
1051 F(19200000, P_BI_TCXO, 1, 0, 0),
1055 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
1056 .cmd_rcgr = 0x750a0,
1059 .parent_map = gcc_parent_map_3,
1060 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1061 .clkr.hw.init = &(struct clk_init_data){
1062 .name = "gcc_ufs_card_phy_aux_clk_src",
1063 .parent_data = gcc_parent_data_3,
1065 .flags = CLK_SET_RATE_PARENT,
1066 .ops = &clk_rcg2_ops,
1070 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
1071 .cmd_rcgr = 0x75084,
1074 .parent_map = gcc_parent_map_0,
1075 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1076 .clkr.hw.init = &(struct clk_init_data){
1077 .name = "gcc_ufs_card_unipro_core_clk_src",
1078 .parent_data = gcc_parent_data_0,
1080 .flags = CLK_SET_RATE_PARENT,
1081 .ops = &clk_rcg2_ops,
1085 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1086 .cmd_rcgr = 0x77024,
1089 .parent_map = gcc_parent_map_0,
1090 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
1091 .clkr.hw.init = &(struct clk_init_data){
1092 .name = "gcc_ufs_phy_axi_clk_src",
1093 .parent_data = gcc_parent_data_0,
1095 .flags = CLK_SET_RATE_PARENT,
1096 .ops = &clk_rcg2_ops,
1100 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1101 .cmd_rcgr = 0x7706c,
1104 .parent_map = gcc_parent_map_0,
1105 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1106 .clkr.hw.init = &(struct clk_init_data){
1107 .name = "gcc_ufs_phy_ice_core_clk_src",
1108 .parent_data = gcc_parent_data_0,
1110 .flags = CLK_SET_RATE_PARENT,
1111 .ops = &clk_rcg2_ops,
1115 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1116 .cmd_rcgr = 0x770a0,
1119 .parent_map = gcc_parent_map_3,
1120 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1121 .clkr.hw.init = &(struct clk_init_data){
1122 .name = "gcc_ufs_phy_phy_aux_clk_src",
1123 .parent_data = gcc_parent_data_3,
1125 .flags = CLK_SET_RATE_PARENT,
1126 .ops = &clk_rcg2_ops,
1130 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1131 .cmd_rcgr = 0x77084,
1134 .parent_map = gcc_parent_map_0,
1135 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1136 .clkr.hw.init = &(struct clk_init_data){
1137 .name = "gcc_ufs_phy_unipro_core_clk_src",
1138 .parent_data = gcc_parent_data_0,
1140 .flags = CLK_SET_RATE_PARENT,
1141 .ops = &clk_rcg2_ops,
1145 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1146 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1147 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1148 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1149 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1153 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1157 .parent_map = gcc_parent_map_0,
1158 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1159 .clkr.hw.init = &(struct clk_init_data){
1160 .name = "gcc_usb30_prim_master_clk_src",
1161 .parent_data = gcc_parent_data_0,
1163 .flags = CLK_SET_RATE_PARENT,
1164 .ops = &clk_rcg2_ops,
1168 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1172 .parent_map = gcc_parent_map_0,
1173 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1174 .clkr.hw.init = &(struct clk_init_data){
1175 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1176 .parent_data = gcc_parent_data_0,
1178 .flags = CLK_SET_RATE_PARENT,
1179 .ops = &clk_rcg2_ops,
1183 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1184 .cmd_rcgr = 0x10020,
1187 .parent_map = gcc_parent_map_0,
1188 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1189 .clkr.hw.init = &(struct clk_init_data){
1190 .name = "gcc_usb30_sec_master_clk_src",
1191 .parent_data = gcc_parent_data_0,
1193 .flags = CLK_SET_RATE_PARENT,
1194 .ops = &clk_rcg2_ops,
1198 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1199 .cmd_rcgr = 0x10038,
1202 .parent_map = gcc_parent_map_0,
1203 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1204 .clkr.hw.init = &(struct clk_init_data){
1205 .name = "gcc_usb30_sec_mock_utmi_clk_src",
1206 .parent_data = gcc_parent_data_0,
1208 .flags = CLK_SET_RATE_PARENT,
1209 .ops = &clk_rcg2_ops,
1213 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1217 .parent_map = gcc_parent_map_2,
1218 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1219 .clkr.hw.init = &(struct clk_init_data){
1220 .name = "gcc_usb3_prim_phy_aux_clk_src",
1221 .parent_data = gcc_parent_data_2,
1223 .flags = CLK_SET_RATE_PARENT,
1224 .ops = &clk_rcg2_ops,
1228 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1229 .cmd_rcgr = 0x10064,
1232 .parent_map = gcc_parent_map_2,
1233 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1234 .clkr.hw.init = &(struct clk_init_data){
1235 .name = "gcc_usb3_sec_phy_aux_clk_src",
1236 .parent_data = gcc_parent_data_2,
1238 .flags = CLK_SET_RATE_PARENT,
1239 .ops = &clk_rcg2_ops,
1243 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1247 .clkr.hw.init = &(struct clk_init_data) {
1248 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1249 .parent_data = &(const struct clk_parent_data){
1250 .hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1253 .flags = CLK_SET_RATE_PARENT,
1254 .ops = &clk_regmap_div_ro_ops,
1258 static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
1262 .clkr.hw.init = &(struct clk_init_data) {
1263 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
1264 .parent_data = &(const struct clk_parent_data){
1265 .hw = &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
1268 .flags = CLK_SET_RATE_PARENT,
1269 .ops = &clk_regmap_div_ro_ops,
1273 /* external clocks so add BRANCH_HALT_SKIP */
1274 static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = {
1275 .halt_reg = 0x6b080,
1276 .halt_check = BRANCH_HALT_SKIP,
1278 .enable_reg = 0x52000,
1279 .enable_mask = BIT(12),
1280 .hw.init = &(struct clk_init_data){
1281 .name = "gcc_aggre_noc_pcie_0_axi_clk",
1282 .ops = &clk_branch2_ops,
1287 /* external clocks so add BRANCH_HALT_SKIP */
1288 static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = {
1289 .halt_reg = 0x8d084,
1290 .halt_check = BRANCH_HALT_SKIP,
1292 .enable_reg = 0x52000,
1293 .enable_mask = BIT(11),
1294 .hw.init = &(struct clk_init_data){
1295 .name = "gcc_aggre_noc_pcie_1_axi_clk",
1296 .ops = &clk_branch2_ops,
1301 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1302 .halt_reg = 0x9000c,
1303 .halt_check = BRANCH_HALT_VOTED,
1304 .hwcg_reg = 0x9000c,
1307 .enable_reg = 0x52000,
1308 .enable_mask = BIT(18),
1309 .hw.init = &(struct clk_init_data){
1310 .name = "gcc_aggre_noc_pcie_tbu_clk",
1311 .ops = &clk_branch2_ops,
1316 static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1317 .halt_reg = 0x750cc,
1318 .halt_check = BRANCH_HALT_VOTED,
1319 .hwcg_reg = 0x750cc,
1322 .enable_reg = 0x750cc,
1323 .enable_mask = BIT(0),
1324 .hw.init = &(struct clk_init_data){
1325 .name = "gcc_aggre_ufs_card_axi_clk",
1326 .parent_data = &(const struct clk_parent_data){
1327 .hw = &gcc_ufs_card_axi_clk_src.clkr.hw,
1330 .flags = CLK_SET_RATE_PARENT,
1331 .ops = &clk_branch2_ops,
1336 static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
1337 .halt_reg = 0x750cc,
1338 .halt_check = BRANCH_HALT_VOTED,
1339 .hwcg_reg = 0x750cc,
1342 .enable_reg = 0x750cc,
1343 .enable_mask = BIT(1),
1344 .hw.init = &(struct clk_init_data){
1345 .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
1346 .parent_data = &(const struct clk_parent_data){
1347 .hw = &gcc_ufs_card_axi_clk_src.clkr.hw,
1350 .flags = CLK_SET_RATE_PARENT,
1351 .ops = &clk_branch2_ops,
1356 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1357 .halt_reg = 0x770cc,
1358 .halt_check = BRANCH_HALT_VOTED,
1359 .hwcg_reg = 0x770cc,
1362 .enable_reg = 0x770cc,
1363 .enable_mask = BIT(0),
1364 .hw.init = &(struct clk_init_data){
1365 .name = "gcc_aggre_ufs_phy_axi_clk",
1366 .parent_data = &(const struct clk_parent_data){
1367 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
1370 .flags = CLK_SET_RATE_PARENT,
1371 .ops = &clk_branch2_ops,
1376 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1377 .halt_reg = 0x770cc,
1378 .halt_check = BRANCH_HALT_VOTED,
1379 .hwcg_reg = 0x770cc,
1382 .enable_reg = 0x770cc,
1383 .enable_mask = BIT(1),
1384 .hw.init = &(struct clk_init_data){
1385 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1386 .parent_data = &(const struct clk_parent_data){
1387 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
1390 .flags = CLK_SET_RATE_PARENT,
1391 .ops = &clk_branch2_ops,
1396 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1398 .halt_check = BRANCH_HALT_VOTED,
1402 .enable_reg = 0xf080,
1403 .enable_mask = BIT(0),
1404 .hw.init = &(struct clk_init_data){
1405 .name = "gcc_aggre_usb3_prim_axi_clk",
1406 .parent_data = &(const struct clk_parent_data){
1407 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
1410 .flags = CLK_SET_RATE_PARENT,
1411 .ops = &clk_branch2_ops,
1416 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1417 .halt_reg = 0x10080,
1418 .halt_check = BRANCH_HALT_VOTED,
1419 .hwcg_reg = 0x10080,
1422 .enable_reg = 0x10080,
1423 .enable_mask = BIT(0),
1424 .hw.init = &(struct clk_init_data){
1425 .name = "gcc_aggre_usb3_sec_axi_clk",
1426 .parent_data = &(const struct clk_parent_data){
1427 .hw = &gcc_usb30_sec_master_clk_src.clkr.hw,
1430 .flags = CLK_SET_RATE_PARENT,
1431 .ops = &clk_branch2_ops,
1436 static struct clk_branch gcc_boot_rom_ahb_clk = {
1437 .halt_reg = 0x38004,
1438 .halt_check = BRANCH_HALT_VOTED,
1439 .hwcg_reg = 0x38004,
1442 .enable_reg = 0x52000,
1443 .enable_mask = BIT(10),
1444 .hw.init = &(struct clk_init_data){
1445 .name = "gcc_boot_rom_ahb_clk",
1446 .ops = &clk_branch2_ops,
1451 /* external clocks so add BRANCH_HALT_SKIP */
1452 static struct clk_branch gcc_camera_hf_axi_clk = {
1453 .halt_reg = 0x26010,
1454 .halt_check = BRANCH_HALT_SKIP,
1455 .hwcg_reg = 0x26010,
1458 .enable_reg = 0x26010,
1459 .enable_mask = BIT(0),
1460 .hw.init = &(struct clk_init_data){
1461 .name = "gcc_camera_hf_axi_clk",
1462 .ops = &clk_branch2_ops,
1467 /* external clocks so add BRANCH_HALT_SKIP */
1468 static struct clk_branch gcc_camera_sf_axi_clk = {
1469 .halt_reg = 0x26014,
1470 .halt_check = BRANCH_HALT_SKIP,
1471 .hwcg_reg = 0x26014,
1474 .enable_reg = 0x26014,
1475 .enable_mask = BIT(0),
1476 .hw.init = &(struct clk_init_data){
1477 .name = "gcc_camera_sf_axi_clk",
1478 .ops = &clk_branch2_ops,
1483 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1485 .halt_check = BRANCH_HALT_VOTED,
1489 .enable_reg = 0xf07c,
1490 .enable_mask = BIT(0),
1491 .hw.init = &(struct clk_init_data){
1492 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1493 .parent_data = &(const struct clk_parent_data){
1494 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
1497 .flags = CLK_SET_RATE_PARENT,
1498 .ops = &clk_branch2_ops,
1503 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1504 .halt_reg = 0x1007c,
1505 .halt_check = BRANCH_HALT_VOTED,
1506 .hwcg_reg = 0x1007c,
1509 .enable_reg = 0x1007c,
1510 .enable_mask = BIT(0),
1511 .hw.init = &(struct clk_init_data){
1512 .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1513 .parent_data = &(const struct clk_parent_data){
1514 .hw = &gcc_usb30_sec_master_clk_src.clkr.hw,
1517 .flags = CLK_SET_RATE_PARENT,
1518 .ops = &clk_branch2_ops,
1523 /* external clocks so add BRANCH_HALT_SKIP */
1524 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1525 .halt_reg = 0x71154,
1526 .halt_check = BRANCH_HALT_SKIP,
1527 .hwcg_reg = 0x71154,
1530 .enable_reg = 0x71154,
1531 .enable_mask = BIT(0),
1532 .hw.init = &(struct clk_init_data){
1533 .name = "gcc_ddrss_gpu_axi_clk",
1534 .ops = &clk_branch2_aon_ops,
1539 /* external clocks so add BRANCH_HALT_SKIP */
1540 static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = {
1541 .halt_reg = 0x8d080,
1542 .halt_check = BRANCH_HALT_SKIP,
1543 .hwcg_reg = 0x8d080,
1546 .enable_reg = 0x52000,
1547 .enable_mask = BIT(19),
1548 .hw.init = &(struct clk_init_data){
1549 .name = "gcc_ddrss_pcie_sf_tbu_clk",
1550 .ops = &clk_branch2_ops,
1555 /* external clocks so add BRANCH_HALT_SKIP */
1556 static struct clk_branch gcc_disp_hf_axi_clk = {
1557 .halt_reg = 0x2700c,
1558 .halt_check = BRANCH_HALT_SKIP,
1559 .hwcg_reg = 0x2700c,
1562 .enable_reg = 0x2700c,
1563 .enable_mask = BIT(0),
1564 .hw.init = &(struct clk_init_data){
1565 .name = "gcc_disp_hf_axi_clk",
1566 .ops = &clk_branch2_ops,
1571 /* external clocks so add BRANCH_HALT_SKIP */
1572 static struct clk_branch gcc_disp_sf_axi_clk = {
1573 .halt_reg = 0x27014,
1574 .halt_check = BRANCH_HALT_SKIP,
1575 .hwcg_reg = 0x27014,
1578 .enable_reg = 0x27014,
1579 .enable_mask = BIT(0),
1580 .hw.init = &(struct clk_init_data){
1581 .name = "gcc_disp_sf_axi_clk",
1582 .ops = &clk_branch2_ops,
1587 static struct clk_branch gcc_gp1_clk = {
1588 .halt_reg = 0x64000,
1589 .halt_check = BRANCH_HALT,
1591 .enable_reg = 0x64000,
1592 .enable_mask = BIT(0),
1593 .hw.init = &(struct clk_init_data){
1594 .name = "gcc_gp1_clk",
1595 .parent_data = &(const struct clk_parent_data){
1596 .hw = &gcc_gp1_clk_src.clkr.hw,
1599 .flags = CLK_SET_RATE_PARENT,
1600 .ops = &clk_branch2_ops,
1605 static struct clk_branch gcc_gp2_clk = {
1606 .halt_reg = 0x65000,
1607 .halt_check = BRANCH_HALT,
1609 .enable_reg = 0x65000,
1610 .enable_mask = BIT(0),
1611 .hw.init = &(struct clk_init_data){
1612 .name = "gcc_gp2_clk",
1613 .parent_data = &(const struct clk_parent_data){
1614 .hw = &gcc_gp2_clk_src.clkr.hw,
1617 .flags = CLK_SET_RATE_PARENT,
1618 .ops = &clk_branch2_ops,
1623 static struct clk_branch gcc_gp3_clk = {
1624 .halt_reg = 0x66000,
1625 .halt_check = BRANCH_HALT,
1627 .enable_reg = 0x66000,
1628 .enable_mask = BIT(0),
1629 .hw.init = &(struct clk_init_data){
1630 .name = "gcc_gp3_clk",
1631 .parent_data = &(const struct clk_parent_data){
1632 .hw = &gcc_gp3_clk_src.clkr.hw,
1635 .flags = CLK_SET_RATE_PARENT,
1636 .ops = &clk_branch2_ops,
1641 /* Clock ON depends on external parent clock, so don't poll */
1642 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1643 .halt_check = BRANCH_HALT_DELAY,
1645 .enable_reg = 0x52000,
1646 .enable_mask = BIT(15),
1647 .hw.init = &(struct clk_init_data){
1648 .name = "gcc_gpu_gpll0_clk_src",
1649 .parent_data = &(const struct clk_parent_data){
1650 .hw = &gcc_gpll0.clkr.hw,
1653 .flags = CLK_SET_RATE_PARENT,
1654 .ops = &clk_branch2_ops,
1659 /* Clock ON depends on external parent clock, so don't poll */
1660 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1661 .halt_check = BRANCH_HALT_DELAY,
1663 .enable_reg = 0x52000,
1664 .enable_mask = BIT(16),
1665 .hw.init = &(struct clk_init_data){
1666 .name = "gcc_gpu_gpll0_div_clk_src",
1667 .parent_data = &(const struct clk_parent_data){
1668 .hw = &gcc_gpll0_out_even.clkr.hw,
1671 .flags = CLK_SET_RATE_PARENT,
1672 .ops = &clk_branch2_ops,
1677 static struct clk_branch gcc_gpu_iref_en = {
1678 .halt_reg = 0x8c014,
1679 .halt_check = BRANCH_HALT,
1681 .enable_reg = 0x8c014,
1682 .enable_mask = BIT(0),
1683 .hw.init = &(struct clk_init_data){
1684 .name = "gcc_gpu_iref_en",
1685 .ops = &clk_branch2_ops,
1690 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1691 .halt_reg = 0x7100c,
1692 .halt_check = BRANCH_HALT_VOTED,
1693 .hwcg_reg = 0x7100c,
1696 .enable_reg = 0x7100c,
1697 .enable_mask = BIT(0),
1698 .hw.init = &(struct clk_init_data){
1699 .name = "gcc_gpu_memnoc_gfx_clk",
1700 .ops = &clk_branch2_aon_ops,
1705 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1706 .halt_reg = 0x71018,
1707 .halt_check = BRANCH_HALT,
1709 .enable_reg = 0x71018,
1710 .enable_mask = BIT(0),
1711 .hw.init = &(struct clk_init_data){
1712 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1713 .ops = &clk_branch2_aon_ops,
1718 static struct clk_branch gcc_pcie0_phy_rchng_clk = {
1719 .halt_reg = 0x6b038,
1720 .halt_check = BRANCH_HALT_VOTED,
1722 .enable_reg = 0x52000,
1723 .enable_mask = BIT(22),
1724 .hw.init = &(struct clk_init_data){
1725 .name = "gcc_pcie0_phy_rchng_clk",
1726 .parent_data = &(const struct clk_parent_data){
1727 .hw = &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
1730 .flags = CLK_SET_RATE_PARENT,
1731 .ops = &clk_branch2_ops,
1736 static struct clk_branch gcc_pcie1_phy_rchng_clk = {
1737 .halt_reg = 0x8d038,
1738 .halt_check = BRANCH_HALT_VOTED,
1740 .enable_reg = 0x52000,
1741 .enable_mask = BIT(23),
1742 .hw.init = &(struct clk_init_data){
1743 .name = "gcc_pcie1_phy_rchng_clk",
1744 .parent_data = &(const struct clk_parent_data){
1745 .hw = &gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
1748 .flags = CLK_SET_RATE_PARENT,
1749 .ops = &clk_branch2_ops,
1754 static struct clk_branch gcc_pcie_0_aux_clk = {
1755 .halt_reg = 0x6b028,
1756 .halt_check = BRANCH_HALT_VOTED,
1758 .enable_reg = 0x52008,
1759 .enable_mask = BIT(3),
1760 .hw.init = &(struct clk_init_data){
1761 .name = "gcc_pcie_0_aux_clk",
1762 .parent_data = &(const struct clk_parent_data){
1763 .hw = &gcc_pcie_0_aux_clk_src.clkr.hw,
1766 .flags = CLK_SET_RATE_PARENT,
1767 .ops = &clk_branch2_ops,
1772 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1773 .halt_reg = 0x6b024,
1774 .halt_check = BRANCH_HALT_VOTED,
1775 .hwcg_reg = 0x6b024,
1778 .enable_reg = 0x52008,
1779 .enable_mask = BIT(2),
1780 .hw.init = &(struct clk_init_data){
1781 .name = "gcc_pcie_0_cfg_ahb_clk",
1782 .ops = &clk_branch2_ops,
1787 static struct clk_branch gcc_pcie_0_clkref_en = {
1788 .halt_reg = 0x8c004,
1789 .halt_check = BRANCH_HALT,
1791 .enable_reg = 0x8c004,
1792 .enable_mask = BIT(0),
1793 .hw.init = &(struct clk_init_data){
1794 .name = "gcc_pcie_0_clkref_en",
1795 .ops = &clk_branch2_ops,
1800 /* external clocks so add BRANCH_HALT_SKIP */
1801 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1802 .halt_reg = 0x6b01c,
1803 .halt_check = BRANCH_HALT_SKIP,
1804 .hwcg_reg = 0x6b01c,
1807 .enable_reg = 0x52008,
1808 .enable_mask = BIT(1),
1809 .hw.init = &(struct clk_init_data){
1810 .name = "gcc_pcie_0_mstr_axi_clk",
1811 .ops = &clk_branch2_ops,
1816 /* external clocks so add BRANCH_HALT_SKIP */
1817 static struct clk_branch gcc_pcie_0_pipe_clk = {
1818 .halt_reg = 0x6b030,
1819 .halt_check = BRANCH_HALT_SKIP,
1821 .enable_reg = 0x52008,
1822 .enable_mask = BIT(4),
1823 .hw.init = &(struct clk_init_data){
1824 .name = "gcc_pcie_0_pipe_clk",
1825 .parent_data = &(const struct clk_parent_data){
1826 .hw = &gcc_pcie_0_pipe_clk_src.clkr.hw,
1829 .flags = CLK_SET_RATE_PARENT,
1830 .ops = &clk_branch2_ops,
1835 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1836 .halt_reg = 0x6b014,
1837 .halt_check = BRANCH_HALT_VOTED,
1838 .hwcg_reg = 0x6b014,
1841 .enable_reg = 0x52008,
1842 .enable_mask = BIT(0),
1843 .hw.init = &(struct clk_init_data){
1844 .name = "gcc_pcie_0_slv_axi_clk",
1845 .ops = &clk_branch2_ops,
1850 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1851 .halt_reg = 0x6b010,
1852 .halt_check = BRANCH_HALT_VOTED,
1854 .enable_reg = 0x52008,
1855 .enable_mask = BIT(5),
1856 .hw.init = &(struct clk_init_data){
1857 .name = "gcc_pcie_0_slv_q2a_axi_clk",
1858 .ops = &clk_branch2_ops,
1863 static struct clk_branch gcc_pcie_1_aux_clk = {
1864 .halt_reg = 0x8d028,
1865 .halt_check = BRANCH_HALT_VOTED,
1867 .enable_reg = 0x52000,
1868 .enable_mask = BIT(29),
1869 .hw.init = &(struct clk_init_data){
1870 .name = "gcc_pcie_1_aux_clk",
1871 .parent_data = &(const struct clk_parent_data){
1872 .hw = &gcc_pcie_1_aux_clk_src.clkr.hw,
1875 .flags = CLK_SET_RATE_PARENT,
1876 .ops = &clk_branch2_ops,
1881 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1882 .halt_reg = 0x8d024,
1883 .halt_check = BRANCH_HALT_VOTED,
1884 .hwcg_reg = 0x8d024,
1887 .enable_reg = 0x52000,
1888 .enable_mask = BIT(28),
1889 .hw.init = &(struct clk_init_data){
1890 .name = "gcc_pcie_1_cfg_ahb_clk",
1891 .ops = &clk_branch2_ops,
1896 static struct clk_branch gcc_pcie_1_clkref_en = {
1897 .halt_reg = 0x8c008,
1898 .halt_check = BRANCH_HALT,
1900 .enable_reg = 0x8c008,
1901 .enable_mask = BIT(0),
1902 .hw.init = &(struct clk_init_data){
1903 .name = "gcc_pcie_1_clkref_en",
1904 .ops = &clk_branch2_ops,
1909 /* external clocks so add BRANCH_HALT_SKIP */
1910 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1911 .halt_reg = 0x8d01c,
1912 .halt_check = BRANCH_HALT_SKIP,
1913 .hwcg_reg = 0x8d01c,
1916 .enable_reg = 0x52000,
1917 .enable_mask = BIT(27),
1918 .hw.init = &(struct clk_init_data){
1919 .name = "gcc_pcie_1_mstr_axi_clk",
1920 .ops = &clk_branch2_ops,
1925 /* external clocks so add BRANCH_HALT_SKIP */
1926 static struct clk_branch gcc_pcie_1_pipe_clk = {
1927 .halt_reg = 0x8d030,
1928 .halt_check = BRANCH_HALT_SKIP,
1930 .enable_reg = 0x52000,
1931 .enable_mask = BIT(30),
1932 .hw.init = &(struct clk_init_data){
1933 .name = "gcc_pcie_1_pipe_clk",
1934 .parent_data = &(const struct clk_parent_data){
1935 .hw = &gcc_pcie_1_pipe_clk_src.clkr.hw,
1938 .flags = CLK_SET_RATE_PARENT,
1939 .ops = &clk_branch2_ops,
1944 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1945 .halt_reg = 0x8d014,
1946 .halt_check = BRANCH_HALT_VOTED,
1947 .hwcg_reg = 0x8d014,
1950 .enable_reg = 0x52000,
1951 .enable_mask = BIT(26),
1952 .hw.init = &(struct clk_init_data){
1953 .name = "gcc_pcie_1_slv_axi_clk",
1954 .ops = &clk_branch2_ops,
1959 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1960 .halt_reg = 0x8d010,
1961 .halt_check = BRANCH_HALT_VOTED,
1963 .enable_reg = 0x52000,
1964 .enable_mask = BIT(25),
1965 .hw.init = &(struct clk_init_data){
1966 .name = "gcc_pcie_1_slv_q2a_axi_clk",
1967 .ops = &clk_branch2_ops,
1972 static struct clk_branch gcc_pdm2_clk = {
1973 .halt_reg = 0x3300c,
1974 .halt_check = BRANCH_HALT,
1976 .enable_reg = 0x3300c,
1977 .enable_mask = BIT(0),
1978 .hw.init = &(struct clk_init_data){
1979 .name = "gcc_pdm2_clk",
1980 .parent_data = &(const struct clk_parent_data){
1981 .hw = &gcc_pdm2_clk_src.clkr.hw,
1984 .flags = CLK_SET_RATE_PARENT,
1985 .ops = &clk_branch2_ops,
1990 static struct clk_branch gcc_pdm_ahb_clk = {
1991 .halt_reg = 0x33004,
1992 .halt_check = BRANCH_HALT_VOTED,
1993 .hwcg_reg = 0x33004,
1996 .enable_reg = 0x33004,
1997 .enable_mask = BIT(0),
1998 .hw.init = &(struct clk_init_data){
1999 .name = "gcc_pdm_ahb_clk",
2000 .ops = &clk_branch2_ops,
2005 static struct clk_branch gcc_pdm_xo4_clk = {
2006 .halt_reg = 0x33008,
2007 .halt_check = BRANCH_HALT,
2009 .enable_reg = 0x33008,
2010 .enable_mask = BIT(0),
2011 .hw.init = &(struct clk_init_data){
2012 .name = "gcc_pdm_xo4_clk",
2013 .ops = &clk_branch2_ops,
2018 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2019 .halt_reg = 0x26008,
2020 .halt_check = BRANCH_HALT_VOTED,
2021 .hwcg_reg = 0x26008,
2024 .enable_reg = 0x26008,
2025 .enable_mask = BIT(0),
2026 .hw.init = &(struct clk_init_data){
2027 .name = "gcc_qmip_camera_nrt_ahb_clk",
2028 .ops = &clk_branch2_ops,
2033 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2034 .halt_reg = 0x2600c,
2035 .halt_check = BRANCH_HALT_VOTED,
2036 .hwcg_reg = 0x2600c,
2039 .enable_reg = 0x2600c,
2040 .enable_mask = BIT(0),
2041 .hw.init = &(struct clk_init_data){
2042 .name = "gcc_qmip_camera_rt_ahb_clk",
2043 .ops = &clk_branch2_ops,
2048 static struct clk_branch gcc_qmip_disp_ahb_clk = {
2049 .halt_reg = 0x27008,
2050 .halt_check = BRANCH_HALT_VOTED,
2051 .hwcg_reg = 0x27008,
2054 .enable_reg = 0x27008,
2055 .enable_mask = BIT(0),
2056 .hw.init = &(struct clk_init_data){
2057 .name = "gcc_qmip_disp_ahb_clk",
2058 .ops = &clk_branch2_ops,
2063 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
2064 .halt_reg = 0x28008,
2065 .halt_check = BRANCH_HALT_VOTED,
2066 .hwcg_reg = 0x28008,
2069 .enable_reg = 0x28008,
2070 .enable_mask = BIT(0),
2071 .hw.init = &(struct clk_init_data){
2072 .name = "gcc_qmip_video_cvp_ahb_clk",
2073 .ops = &clk_branch2_ops,
2078 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2079 .halt_reg = 0x2800c,
2080 .halt_check = BRANCH_HALT_VOTED,
2081 .hwcg_reg = 0x2800c,
2084 .enable_reg = 0x2800c,
2085 .enable_mask = BIT(0),
2086 .hw.init = &(struct clk_init_data){
2087 .name = "gcc_qmip_video_vcodec_ahb_clk",
2088 .ops = &clk_branch2_ops,
2093 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2094 .halt_reg = 0x23008,
2095 .halt_check = BRANCH_HALT_VOTED,
2097 .enable_reg = 0x52008,
2098 .enable_mask = BIT(9),
2099 .hw.init = &(struct clk_init_data){
2100 .name = "gcc_qupv3_wrap0_core_2x_clk",
2101 .ops = &clk_branch2_ops,
2106 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2107 .halt_reg = 0x23000,
2108 .halt_check = BRANCH_HALT_VOTED,
2110 .enable_reg = 0x52008,
2111 .enable_mask = BIT(8),
2112 .hw.init = &(struct clk_init_data){
2113 .name = "gcc_qupv3_wrap0_core_clk",
2114 .ops = &clk_branch2_ops,
2119 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2120 .halt_reg = 0x1700c,
2121 .halt_check = BRANCH_HALT_VOTED,
2123 .enable_reg = 0x52008,
2124 .enable_mask = BIT(10),
2125 .hw.init = &(struct clk_init_data){
2126 .name = "gcc_qupv3_wrap0_s0_clk",
2127 .parent_data = &(const struct clk_parent_data){
2128 .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2131 .flags = CLK_SET_RATE_PARENT,
2132 .ops = &clk_branch2_ops,
2137 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2138 .halt_reg = 0x1713c,
2139 .halt_check = BRANCH_HALT_VOTED,
2141 .enable_reg = 0x52008,
2142 .enable_mask = BIT(11),
2143 .hw.init = &(struct clk_init_data){
2144 .name = "gcc_qupv3_wrap0_s1_clk",
2145 .parent_data = &(const struct clk_parent_data){
2146 .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2149 .flags = CLK_SET_RATE_PARENT,
2150 .ops = &clk_branch2_ops,
2155 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2156 .halt_reg = 0x1726c,
2157 .halt_check = BRANCH_HALT_VOTED,
2159 .enable_reg = 0x52008,
2160 .enable_mask = BIT(12),
2161 .hw.init = &(struct clk_init_data){
2162 .name = "gcc_qupv3_wrap0_s2_clk",
2163 .parent_data = &(const struct clk_parent_data){
2164 .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2167 .flags = CLK_SET_RATE_PARENT,
2168 .ops = &clk_branch2_ops,
2173 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2174 .halt_reg = 0x1739c,
2175 .halt_check = BRANCH_HALT_VOTED,
2177 .enable_reg = 0x52008,
2178 .enable_mask = BIT(13),
2179 .hw.init = &(struct clk_init_data){
2180 .name = "gcc_qupv3_wrap0_s3_clk",
2181 .parent_data = &(const struct clk_parent_data){
2182 .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2185 .flags = CLK_SET_RATE_PARENT,
2186 .ops = &clk_branch2_ops,
2191 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2192 .halt_reg = 0x174cc,
2193 .halt_check = BRANCH_HALT_VOTED,
2195 .enable_reg = 0x52008,
2196 .enable_mask = BIT(14),
2197 .hw.init = &(struct clk_init_data){
2198 .name = "gcc_qupv3_wrap0_s4_clk",
2199 .parent_data = &(const struct clk_parent_data){
2200 .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2203 .flags = CLK_SET_RATE_PARENT,
2204 .ops = &clk_branch2_ops,
2209 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2210 .halt_reg = 0x175fc,
2211 .halt_check = BRANCH_HALT_VOTED,
2213 .enable_reg = 0x52008,
2214 .enable_mask = BIT(15),
2215 .hw.init = &(struct clk_init_data){
2216 .name = "gcc_qupv3_wrap0_s5_clk",
2217 .parent_data = &(const struct clk_parent_data){
2218 .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2221 .flags = CLK_SET_RATE_PARENT,
2222 .ops = &clk_branch2_ops,
2227 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2228 .halt_reg = 0x1772c,
2229 .halt_check = BRANCH_HALT_VOTED,
2231 .enable_reg = 0x52008,
2232 .enable_mask = BIT(16),
2233 .hw.init = &(struct clk_init_data){
2234 .name = "gcc_qupv3_wrap0_s6_clk",
2235 .parent_data = &(const struct clk_parent_data){
2236 .hw = &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
2239 .flags = CLK_SET_RATE_PARENT,
2240 .ops = &clk_branch2_ops,
2245 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2246 .halt_reg = 0x1785c,
2247 .halt_check = BRANCH_HALT_VOTED,
2249 .enable_reg = 0x52008,
2250 .enable_mask = BIT(17),
2251 .hw.init = &(struct clk_init_data){
2252 .name = "gcc_qupv3_wrap0_s7_clk",
2253 .parent_data = &(const struct clk_parent_data){
2254 .hw = &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
2257 .flags = CLK_SET_RATE_PARENT,
2258 .ops = &clk_branch2_ops,
2263 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
2264 .halt_reg = 0x23140,
2265 .halt_check = BRANCH_HALT_VOTED,
2267 .enable_reg = 0x52008,
2268 .enable_mask = BIT(18),
2269 .hw.init = &(struct clk_init_data){
2270 .name = "gcc_qupv3_wrap1_core_2x_clk",
2271 .ops = &clk_branch2_ops,
2276 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
2277 .halt_reg = 0x23138,
2278 .halt_check = BRANCH_HALT_VOTED,
2280 .enable_reg = 0x52008,
2281 .enable_mask = BIT(19),
2282 .hw.init = &(struct clk_init_data){
2283 .name = "gcc_qupv3_wrap1_core_clk",
2284 .ops = &clk_branch2_ops,
2289 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2290 .halt_reg = 0x18004,
2291 .halt_check = BRANCH_HALT_VOTED,
2292 .hwcg_reg = 0x18004,
2295 .enable_reg = 0x52008,
2296 .enable_mask = BIT(20),
2297 .hw.init = &(struct clk_init_data){
2298 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2299 .ops = &clk_branch2_ops,
2304 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2305 .halt_reg = 0x18008,
2306 .halt_check = BRANCH_HALT_VOTED,
2307 .hwcg_reg = 0x18008,
2310 .enable_reg = 0x52008,
2311 .enable_mask = BIT(21),
2312 .hw.init = &(struct clk_init_data){
2313 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2314 .ops = &clk_branch2_ops,
2319 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2320 .halt_reg = 0x1800c,
2321 .halt_check = BRANCH_HALT_VOTED,
2323 .enable_reg = 0x52008,
2324 .enable_mask = BIT(22),
2325 .hw.init = &(struct clk_init_data){
2326 .name = "gcc_qupv3_wrap1_s0_clk",
2327 .parent_data = &(const struct clk_parent_data){
2328 .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2331 .flags = CLK_SET_RATE_PARENT,
2332 .ops = &clk_branch2_ops,
2337 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2338 .halt_reg = 0x1813c,
2339 .halt_check = BRANCH_HALT_VOTED,
2341 .enable_reg = 0x52008,
2342 .enable_mask = BIT(23),
2343 .hw.init = &(struct clk_init_data){
2344 .name = "gcc_qupv3_wrap1_s1_clk",
2345 .parent_data = &(const struct clk_parent_data){
2346 .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2349 .flags = CLK_SET_RATE_PARENT,
2350 .ops = &clk_branch2_ops,
2355 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2356 .halt_reg = 0x1826c,
2357 .halt_check = BRANCH_HALT_VOTED,
2359 .enable_reg = 0x52008,
2360 .enable_mask = BIT(24),
2361 .hw.init = &(struct clk_init_data){
2362 .name = "gcc_qupv3_wrap1_s2_clk",
2363 .parent_data = &(const struct clk_parent_data){
2364 .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2367 .flags = CLK_SET_RATE_PARENT,
2368 .ops = &clk_branch2_ops,
2373 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2374 .halt_reg = 0x1839c,
2375 .halt_check = BRANCH_HALT_VOTED,
2377 .enable_reg = 0x52008,
2378 .enable_mask = BIT(25),
2379 .hw.init = &(struct clk_init_data){
2380 .name = "gcc_qupv3_wrap1_s3_clk",
2381 .parent_data = &(const struct clk_parent_data){
2382 .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2385 .flags = CLK_SET_RATE_PARENT,
2386 .ops = &clk_branch2_ops,
2391 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2392 .halt_reg = 0x184cc,
2393 .halt_check = BRANCH_HALT_VOTED,
2395 .enable_reg = 0x52008,
2396 .enable_mask = BIT(26),
2397 .hw.init = &(struct clk_init_data){
2398 .name = "gcc_qupv3_wrap1_s4_clk",
2399 .parent_data = &(const struct clk_parent_data){
2400 .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2403 .flags = CLK_SET_RATE_PARENT,
2404 .ops = &clk_branch2_ops,
2409 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2410 .halt_reg = 0x185fc,
2411 .halt_check = BRANCH_HALT_VOTED,
2413 .enable_reg = 0x52008,
2414 .enable_mask = BIT(27),
2415 .hw.init = &(struct clk_init_data){
2416 .name = "gcc_qupv3_wrap1_s5_clk",
2417 .parent_data = &(const struct clk_parent_data){
2418 .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2421 .flags = CLK_SET_RATE_PARENT,
2422 .ops = &clk_branch2_ops,
2427 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
2428 .halt_reg = 0x23278,
2429 .halt_check = BRANCH_HALT_VOTED,
2431 .enable_reg = 0x52010,
2432 .enable_mask = BIT(3),
2433 .hw.init = &(struct clk_init_data){
2434 .name = "gcc_qupv3_wrap2_core_2x_clk",
2435 .ops = &clk_branch2_ops,
2440 static struct clk_branch gcc_qupv3_wrap2_core_clk = {
2441 .halt_reg = 0x23270,
2442 .halt_check = BRANCH_HALT_VOTED,
2444 .enable_reg = 0x52010,
2445 .enable_mask = BIT(0),
2446 .hw.init = &(struct clk_init_data){
2447 .name = "gcc_qupv3_wrap2_core_clk",
2448 .ops = &clk_branch2_ops,
2453 static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2454 .halt_reg = 0x1e00c,
2455 .halt_check = BRANCH_HALT_VOTED,
2457 .enable_reg = 0x52010,
2458 .enable_mask = BIT(4),
2459 .hw.init = &(struct clk_init_data){
2460 .name = "gcc_qupv3_wrap2_s0_clk",
2461 .parent_data = &(const struct clk_parent_data){
2462 .hw = &gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
2465 .flags = CLK_SET_RATE_PARENT,
2466 .ops = &clk_branch2_ops,
2471 static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2472 .halt_reg = 0x1e13c,
2473 .halt_check = BRANCH_HALT_VOTED,
2475 .enable_reg = 0x52010,
2476 .enable_mask = BIT(5),
2477 .hw.init = &(struct clk_init_data){
2478 .name = "gcc_qupv3_wrap2_s1_clk",
2479 .parent_data = &(const struct clk_parent_data){
2480 .hw = &gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
2483 .flags = CLK_SET_RATE_PARENT,
2484 .ops = &clk_branch2_ops,
2489 static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2490 .halt_reg = 0x1e26c,
2491 .halt_check = BRANCH_HALT_VOTED,
2493 .enable_reg = 0x52010,
2494 .enable_mask = BIT(6),
2495 .hw.init = &(struct clk_init_data){
2496 .name = "gcc_qupv3_wrap2_s2_clk",
2497 .parent_data = &(const struct clk_parent_data){
2498 .hw = &gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
2501 .flags = CLK_SET_RATE_PARENT,
2502 .ops = &clk_branch2_ops,
2507 static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2508 .halt_reg = 0x1e39c,
2509 .halt_check = BRANCH_HALT_VOTED,
2511 .enable_reg = 0x52010,
2512 .enable_mask = BIT(7),
2513 .hw.init = &(struct clk_init_data){
2514 .name = "gcc_qupv3_wrap2_s3_clk",
2515 .parent_data = &(const struct clk_parent_data){
2516 .hw = &gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
2519 .flags = CLK_SET_RATE_PARENT,
2520 .ops = &clk_branch2_ops,
2525 static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2526 .halt_reg = 0x1e4cc,
2527 .halt_check = BRANCH_HALT_VOTED,
2529 .enable_reg = 0x52010,
2530 .enable_mask = BIT(8),
2531 .hw.init = &(struct clk_init_data){
2532 .name = "gcc_qupv3_wrap2_s4_clk",
2533 .parent_data = &(const struct clk_parent_data){
2534 .hw = &gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
2537 .flags = CLK_SET_RATE_PARENT,
2538 .ops = &clk_branch2_ops,
2543 static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2544 .halt_reg = 0x1e5fc,
2545 .halt_check = BRANCH_HALT_VOTED,
2547 .enable_reg = 0x52010,
2548 .enable_mask = BIT(9),
2549 .hw.init = &(struct clk_init_data){
2550 .name = "gcc_qupv3_wrap2_s5_clk",
2551 .parent_data = &(const struct clk_parent_data){
2552 .hw = &gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
2555 .flags = CLK_SET_RATE_PARENT,
2556 .ops = &clk_branch2_ops,
2561 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2562 .halt_reg = 0x17004,
2563 .halt_check = BRANCH_HALT_VOTED,
2564 .hwcg_reg = 0x17004,
2567 .enable_reg = 0x52008,
2568 .enable_mask = BIT(6),
2569 .hw.init = &(struct clk_init_data){
2570 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2571 .ops = &clk_branch2_ops,
2576 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2577 .halt_reg = 0x17008,
2578 .halt_check = BRANCH_HALT_VOTED,
2579 .hwcg_reg = 0x17008,
2582 .enable_reg = 0x52008,
2583 .enable_mask = BIT(7),
2584 .hw.init = &(struct clk_init_data){
2585 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2586 .ops = &clk_branch2_ops,
2591 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
2592 .halt_reg = 0x1e004,
2593 .halt_check = BRANCH_HALT_VOTED,
2594 .hwcg_reg = 0x1e004,
2597 .enable_reg = 0x52010,
2598 .enable_mask = BIT(2),
2599 .hw.init = &(struct clk_init_data){
2600 .name = "gcc_qupv3_wrap_2_m_ahb_clk",
2601 .ops = &clk_branch2_ops,
2606 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
2607 .halt_reg = 0x1e008,
2608 .halt_check = BRANCH_HALT_VOTED,
2609 .hwcg_reg = 0x1e008,
2612 .enable_reg = 0x52010,
2613 .enable_mask = BIT(1),
2614 .hw.init = &(struct clk_init_data){
2615 .name = "gcc_qupv3_wrap_2_s_ahb_clk",
2616 .ops = &clk_branch2_ops,
2621 static struct clk_branch gcc_sdcc2_ahb_clk = {
2622 .halt_reg = 0x14008,
2623 .halt_check = BRANCH_HALT,
2625 .enable_reg = 0x14008,
2626 .enable_mask = BIT(0),
2627 .hw.init = &(struct clk_init_data){
2628 .name = "gcc_sdcc2_ahb_clk",
2629 .ops = &clk_branch2_ops,
2634 static struct clk_branch gcc_sdcc2_apps_clk = {
2635 .halt_reg = 0x14004,
2636 .halt_check = BRANCH_HALT,
2638 .enable_reg = 0x14004,
2639 .enable_mask = BIT(0),
2640 .hw.init = &(struct clk_init_data){
2641 .name = "gcc_sdcc2_apps_clk",
2642 .parent_data = &(const struct clk_parent_data){
2643 .hw = &gcc_sdcc2_apps_clk_src.clkr.hw,
2646 .flags = CLK_SET_RATE_PARENT,
2647 .ops = &clk_branch2_ops,
2652 static struct clk_branch gcc_sdcc4_ahb_clk = {
2653 .halt_reg = 0x16008,
2654 .halt_check = BRANCH_HALT,
2656 .enable_reg = 0x16008,
2657 .enable_mask = BIT(0),
2658 .hw.init = &(struct clk_init_data){
2659 .name = "gcc_sdcc4_ahb_clk",
2660 .ops = &clk_branch2_ops,
2665 static struct clk_branch gcc_sdcc4_apps_clk = {
2666 .halt_reg = 0x16004,
2667 .halt_check = BRANCH_HALT,
2669 .enable_reg = 0x16004,
2670 .enable_mask = BIT(0),
2671 .hw.init = &(struct clk_init_data){
2672 .name = "gcc_sdcc4_apps_clk",
2673 .parent_data = &(const struct clk_parent_data){
2674 .hw = &gcc_sdcc4_apps_clk_src.clkr.hw,
2677 .flags = CLK_SET_RATE_PARENT,
2678 .ops = &clk_branch2_ops,
2683 static struct clk_branch gcc_throttle_pcie_ahb_clk = {
2685 .halt_check = BRANCH_HALT,
2687 .enable_reg = 0x9044,
2688 .enable_mask = BIT(0),
2689 .hw.init = &(struct clk_init_data){
2690 .name = "gcc_throttle_pcie_ahb_clk",
2691 .ops = &clk_branch2_ops,
2696 static struct clk_branch gcc_ufs_1_clkref_en = {
2697 .halt_reg = 0x8c000,
2698 .halt_check = BRANCH_HALT,
2700 .enable_reg = 0x8c000,
2701 .enable_mask = BIT(0),
2702 .hw.init = &(struct clk_init_data){
2703 .name = "gcc_ufs_1_clkref_en",
2704 .ops = &clk_branch2_ops,
2709 static struct clk_branch gcc_ufs_card_ahb_clk = {
2710 .halt_reg = 0x75018,
2711 .halt_check = BRANCH_HALT_VOTED,
2712 .hwcg_reg = 0x75018,
2715 .enable_reg = 0x75018,
2716 .enable_mask = BIT(0),
2717 .hw.init = &(struct clk_init_data){
2718 .name = "gcc_ufs_card_ahb_clk",
2719 .ops = &clk_branch2_ops,
2724 static struct clk_branch gcc_ufs_card_axi_clk = {
2725 .halt_reg = 0x75010,
2726 .halt_check = BRANCH_HALT_VOTED,
2727 .hwcg_reg = 0x75010,
2730 .enable_reg = 0x75010,
2731 .enable_mask = BIT(0),
2732 .hw.init = &(struct clk_init_data){
2733 .name = "gcc_ufs_card_axi_clk",
2734 .parent_data = &(const struct clk_parent_data){
2735 .hw = &gcc_ufs_card_axi_clk_src.clkr.hw,
2738 .flags = CLK_SET_RATE_PARENT,
2739 .ops = &clk_branch2_ops,
2744 static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
2745 .halt_reg = 0x75010,
2746 .halt_check = BRANCH_HALT_VOTED,
2747 .hwcg_reg = 0x75010,
2750 .enable_reg = 0x75010,
2751 .enable_mask = BIT(1),
2752 .hw.init = &(struct clk_init_data){
2753 .name = "gcc_ufs_card_axi_hw_ctl_clk",
2754 .parent_data = &(const struct clk_parent_data){
2755 .hw = &gcc_ufs_card_axi_clk_src.clkr.hw,
2758 .flags = CLK_SET_RATE_PARENT,
2759 .ops = &clk_branch2_ops,
2764 static struct clk_branch gcc_ufs_card_ice_core_clk = {
2765 .halt_reg = 0x75064,
2766 .halt_check = BRANCH_HALT_VOTED,
2767 .hwcg_reg = 0x75064,
2770 .enable_reg = 0x75064,
2771 .enable_mask = BIT(0),
2772 .hw.init = &(struct clk_init_data){
2773 .name = "gcc_ufs_card_ice_core_clk",
2774 .parent_data = &(const struct clk_parent_data){
2775 .hw = &gcc_ufs_card_ice_core_clk_src.clkr.hw,
2778 .flags = CLK_SET_RATE_PARENT,
2779 .ops = &clk_branch2_ops,
2784 static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
2785 .halt_reg = 0x75064,
2786 .halt_check = BRANCH_HALT_VOTED,
2787 .hwcg_reg = 0x75064,
2790 .enable_reg = 0x75064,
2791 .enable_mask = BIT(1),
2792 .hw.init = &(struct clk_init_data){
2793 .name = "gcc_ufs_card_ice_core_hw_ctl_clk",
2794 .parent_data = &(const struct clk_parent_data){
2795 .hw = &gcc_ufs_card_ice_core_clk_src.clkr.hw,
2798 .flags = CLK_SET_RATE_PARENT,
2799 .ops = &clk_branch2_ops,
2804 static struct clk_branch gcc_ufs_card_phy_aux_clk = {
2805 .halt_reg = 0x7509c,
2806 .halt_check = BRANCH_HALT_VOTED,
2807 .hwcg_reg = 0x7509c,
2810 .enable_reg = 0x7509c,
2811 .enable_mask = BIT(0),
2812 .hw.init = &(struct clk_init_data){
2813 .name = "gcc_ufs_card_phy_aux_clk",
2814 .parent_data = &(const struct clk_parent_data){
2815 .hw = &gcc_ufs_card_phy_aux_clk_src.clkr.hw,
2818 .flags = CLK_SET_RATE_PARENT,
2819 .ops = &clk_branch2_ops,
2824 static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
2825 .halt_reg = 0x7509c,
2826 .halt_check = BRANCH_HALT_VOTED,
2827 .hwcg_reg = 0x7509c,
2830 .enable_reg = 0x7509c,
2831 .enable_mask = BIT(1),
2832 .hw.init = &(struct clk_init_data){
2833 .name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
2834 .parent_data = &(const struct clk_parent_data){
2835 .hw = &gcc_ufs_card_phy_aux_clk_src.clkr.hw,
2838 .flags = CLK_SET_RATE_PARENT,
2839 .ops = &clk_branch2_ops,
2844 /* Clock ON depends on external parent clock, so don't poll */
2845 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
2846 .halt_reg = 0x75020,
2847 .halt_check = BRANCH_HALT_DELAY,
2849 .enable_reg = 0x75020,
2850 .enable_mask = BIT(0),
2851 .hw.init = &(struct clk_init_data){
2852 .name = "gcc_ufs_card_rx_symbol_0_clk",
2853 .parent_data = &(const struct clk_parent_data){
2854 .hw = &gcc_ufs_card_rx_symbol_0_clk_src.clkr.hw,
2857 .flags = CLK_SET_RATE_PARENT,
2858 .ops = &clk_branch2_ops,
2863 /* Clock ON depends on external parent clock, so don't poll */
2864 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
2865 .halt_reg = 0x750b8,
2866 .halt_check = BRANCH_HALT_DELAY,
2868 .enable_reg = 0x750b8,
2869 .enable_mask = BIT(0),
2870 .hw.init = &(struct clk_init_data){
2871 .name = "gcc_ufs_card_rx_symbol_1_clk",
2872 .parent_data = &(const struct clk_parent_data){
2873 .hw = &gcc_ufs_card_rx_symbol_1_clk_src.clkr.hw,
2876 .flags = CLK_SET_RATE_PARENT,
2877 .ops = &clk_branch2_ops,
2882 /* Clock ON depends on external parent clock, so don't poll */
2883 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
2884 .halt_reg = 0x7501c,
2885 .halt_check = BRANCH_HALT_DELAY,
2887 .enable_reg = 0x7501c,
2888 .enable_mask = BIT(0),
2889 .hw.init = &(struct clk_init_data){
2890 .name = "gcc_ufs_card_tx_symbol_0_clk",
2891 .parent_data = &(const struct clk_parent_data){
2892 .hw = &gcc_ufs_card_tx_symbol_0_clk_src.clkr.hw,
2895 .flags = CLK_SET_RATE_PARENT,
2896 .ops = &clk_branch2_ops,
2901 static struct clk_branch gcc_ufs_card_unipro_core_clk = {
2902 .halt_reg = 0x7505c,
2903 .halt_check = BRANCH_HALT_VOTED,
2904 .hwcg_reg = 0x7505c,
2907 .enable_reg = 0x7505c,
2908 .enable_mask = BIT(0),
2909 .hw.init = &(struct clk_init_data){
2910 .name = "gcc_ufs_card_unipro_core_clk",
2911 .parent_data = &(const struct clk_parent_data){
2912 .hw = &gcc_ufs_card_unipro_core_clk_src.clkr.hw,
2915 .flags = CLK_SET_RATE_PARENT,
2916 .ops = &clk_branch2_ops,
2921 static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
2922 .halt_reg = 0x7505c,
2923 .halt_check = BRANCH_HALT_VOTED,
2924 .hwcg_reg = 0x7505c,
2927 .enable_reg = 0x7505c,
2928 .enable_mask = BIT(1),
2929 .hw.init = &(struct clk_init_data){
2930 .name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
2931 .parent_data = &(const struct clk_parent_data){
2932 .hw = &gcc_ufs_card_unipro_core_clk_src.clkr.hw,
2935 .flags = CLK_SET_RATE_PARENT,
2936 .ops = &clk_branch2_ops,
2941 static struct clk_branch gcc_ufs_phy_ahb_clk = {
2942 .halt_reg = 0x77018,
2943 .halt_check = BRANCH_HALT_VOTED,
2944 .hwcg_reg = 0x77018,
2947 .enable_reg = 0x77018,
2948 .enable_mask = BIT(0),
2949 .hw.init = &(struct clk_init_data){
2950 .name = "gcc_ufs_phy_ahb_clk",
2951 .ops = &clk_branch2_ops,
2956 static struct clk_branch gcc_ufs_phy_axi_clk = {
2957 .halt_reg = 0x77010,
2958 .halt_check = BRANCH_HALT_VOTED,
2959 .hwcg_reg = 0x77010,
2962 .enable_reg = 0x77010,
2963 .enable_mask = BIT(0),
2964 .hw.init = &(struct clk_init_data){
2965 .name = "gcc_ufs_phy_axi_clk",
2966 .parent_data = &(const struct clk_parent_data){
2967 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
2970 .flags = CLK_SET_RATE_PARENT,
2971 .ops = &clk_branch2_ops,
2976 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
2977 .halt_reg = 0x77010,
2978 .halt_check = BRANCH_HALT_VOTED,
2979 .hwcg_reg = 0x77010,
2982 .enable_reg = 0x77010,
2983 .enable_mask = BIT(1),
2984 .hw.init = &(struct clk_init_data){
2985 .name = "gcc_ufs_phy_axi_hw_ctl_clk",
2986 .parent_data = &(const struct clk_parent_data){
2987 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
2990 .flags = CLK_SET_RATE_PARENT,
2991 .ops = &clk_branch2_ops,
2996 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2997 .halt_reg = 0x77064,
2998 .halt_check = BRANCH_HALT_VOTED,
2999 .hwcg_reg = 0x77064,
3002 .enable_reg = 0x77064,
3003 .enable_mask = BIT(0),
3004 .hw.init = &(struct clk_init_data){
3005 .name = "gcc_ufs_phy_ice_core_clk",
3006 .parent_data = &(const struct clk_parent_data){
3007 .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
3010 .flags = CLK_SET_RATE_PARENT,
3011 .ops = &clk_branch2_ops,
3016 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
3017 .halt_reg = 0x77064,
3018 .halt_check = BRANCH_HALT_VOTED,
3019 .hwcg_reg = 0x77064,
3022 .enable_reg = 0x77064,
3023 .enable_mask = BIT(1),
3024 .hw.init = &(struct clk_init_data){
3025 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
3026 .parent_data = &(const struct clk_parent_data){
3027 .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
3030 .flags = CLK_SET_RATE_PARENT,
3031 .ops = &clk_branch2_ops,
3036 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
3037 .halt_reg = 0x7709c,
3038 .halt_check = BRANCH_HALT_VOTED,
3039 .hwcg_reg = 0x7709c,
3042 .enable_reg = 0x7709c,
3043 .enable_mask = BIT(0),
3044 .hw.init = &(struct clk_init_data){
3045 .name = "gcc_ufs_phy_phy_aux_clk",
3046 .parent_data = &(const struct clk_parent_data){
3047 .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
3050 .flags = CLK_SET_RATE_PARENT,
3051 .ops = &clk_branch2_ops,
3056 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
3057 .halt_reg = 0x7709c,
3058 .halt_check = BRANCH_HALT_VOTED,
3059 .hwcg_reg = 0x7709c,
3062 .enable_reg = 0x7709c,
3063 .enable_mask = BIT(1),
3064 .hw.init = &(struct clk_init_data){
3065 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
3066 .parent_data = &(const struct clk_parent_data){
3067 .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
3070 .flags = CLK_SET_RATE_PARENT,
3071 .ops = &clk_branch2_ops,
3076 /* Clock ON depends on external parent clock, so don't poll */
3077 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
3078 .halt_reg = 0x77020,
3079 .halt_check = BRANCH_HALT_DELAY,
3081 .enable_reg = 0x77020,
3082 .enable_mask = BIT(0),
3083 .hw.init = &(struct clk_init_data){
3084 .name = "gcc_ufs_phy_rx_symbol_0_clk",
3085 .parent_data = &(const struct clk_parent_data){
3086 .hw = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
3089 .flags = CLK_SET_RATE_PARENT,
3090 .ops = &clk_branch2_ops,
3095 /* Clock ON depends on external parent clock, so don't poll */
3096 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
3097 .halt_reg = 0x770b8,
3098 .halt_check = BRANCH_HALT_DELAY,
3100 .enable_reg = 0x770b8,
3101 .enable_mask = BIT(0),
3102 .hw.init = &(struct clk_init_data){
3103 .name = "gcc_ufs_phy_rx_symbol_1_clk",
3104 .parent_data = &(const struct clk_parent_data){
3105 .hw = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
3108 .flags = CLK_SET_RATE_PARENT,
3109 .ops = &clk_branch2_ops,
3114 /* Clock ON depends on external parent clock, so don't poll */
3115 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
3116 .halt_reg = 0x7701c,
3117 .halt_check = BRANCH_HALT_DELAY,
3119 .enable_reg = 0x7701c,
3120 .enable_mask = BIT(0),
3121 .hw.init = &(struct clk_init_data){
3122 .name = "gcc_ufs_phy_tx_symbol_0_clk",
3123 .parent_data = &(const struct clk_parent_data){
3124 .hw = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
3127 .flags = CLK_SET_RATE_PARENT,
3128 .ops = &clk_branch2_ops,
3133 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
3134 .halt_reg = 0x7705c,
3135 .halt_check = BRANCH_HALT_VOTED,
3136 .hwcg_reg = 0x7705c,
3139 .enable_reg = 0x7705c,
3140 .enable_mask = BIT(0),
3141 .hw.init = &(struct clk_init_data){
3142 .name = "gcc_ufs_phy_unipro_core_clk",
3143 .parent_data = &(const struct clk_parent_data){
3144 .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
3147 .flags = CLK_SET_RATE_PARENT,
3148 .ops = &clk_branch2_ops,
3153 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
3154 .halt_reg = 0x7705c,
3155 .halt_check = BRANCH_HALT_VOTED,
3156 .hwcg_reg = 0x7705c,
3159 .enable_reg = 0x7705c,
3160 .enable_mask = BIT(1),
3161 .hw.init = &(struct clk_init_data){
3162 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
3163 .parent_data = &(const struct clk_parent_data){
3164 .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
3167 .flags = CLK_SET_RATE_PARENT,
3168 .ops = &clk_branch2_ops,
3173 static struct clk_branch gcc_usb30_prim_master_clk = {
3175 .halt_check = BRANCH_HALT,
3177 .enable_reg = 0xf010,
3178 .enable_mask = BIT(0),
3179 .hw.init = &(struct clk_init_data){
3180 .name = "gcc_usb30_prim_master_clk",
3181 .parent_data = &(const struct clk_parent_data){
3182 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
3185 .flags = CLK_SET_RATE_PARENT,
3186 .ops = &clk_branch2_ops,
3191 static struct clk_branch gcc_usb30_prim_master_clk__force_mem_core_on = {
3193 .halt_check = BRANCH_HALT,
3195 .enable_reg = 0xf010,
3196 .enable_mask = BIT(14),
3197 .hw.init = &(struct clk_init_data){
3198 .name = "gcc_usb30_prim_master_clk__force_mem_core_on",
3199 .ops = &clk_branch_simple_ops,
3204 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3206 .halt_check = BRANCH_HALT,
3208 .enable_reg = 0xf01c,
3209 .enable_mask = BIT(0),
3210 .hw.init = &(struct clk_init_data){
3211 .name = "gcc_usb30_prim_mock_utmi_clk",
3212 .parent_data = &(const struct clk_parent_data){
3214 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
3217 .flags = CLK_SET_RATE_PARENT,
3218 .ops = &clk_branch2_ops,
3223 static struct clk_branch gcc_usb30_prim_sleep_clk = {
3225 .halt_check = BRANCH_HALT,
3227 .enable_reg = 0xf018,
3228 .enable_mask = BIT(0),
3229 .hw.init = &(struct clk_init_data){
3230 .name = "gcc_usb30_prim_sleep_clk",
3231 .ops = &clk_branch2_ops,
3236 static struct clk_branch gcc_usb30_sec_master_clk = {
3237 .halt_reg = 0x10010,
3238 .halt_check = BRANCH_HALT,
3240 .enable_reg = 0x10010,
3241 .enable_mask = BIT(0),
3242 .hw.init = &(struct clk_init_data){
3243 .name = "gcc_usb30_sec_master_clk",
3244 .parent_data = &(const struct clk_parent_data){
3245 .hw = &gcc_usb30_sec_master_clk_src.clkr.hw,
3248 .flags = CLK_SET_RATE_PARENT,
3249 .ops = &clk_branch2_ops,
3254 static struct clk_branch gcc_usb30_sec_master_clk__force_mem_core_on = {
3255 .halt_reg = 0x10010,
3256 .halt_check = BRANCH_HALT,
3258 .enable_reg = 0x10010,
3259 .enable_mask = BIT(14),
3260 .hw.init = &(struct clk_init_data){
3261 .name = "gcc_usb30_sec_master_clk__force_mem_core_on",
3262 .ops = &clk_branch_simple_ops,
3267 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
3268 .halt_reg = 0x1001c,
3269 .halt_check = BRANCH_HALT,
3271 .enable_reg = 0x1001c,
3272 .enable_mask = BIT(0),
3273 .hw.init = &(struct clk_init_data){
3274 .name = "gcc_usb30_sec_mock_utmi_clk",
3275 .parent_data = &(const struct clk_parent_data){
3277 &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
3280 .flags = CLK_SET_RATE_PARENT,
3281 .ops = &clk_branch2_ops,
3286 static struct clk_branch gcc_usb30_sec_sleep_clk = {
3287 .halt_reg = 0x10018,
3288 .halt_check = BRANCH_HALT,
3290 .enable_reg = 0x10018,
3291 .enable_mask = BIT(0),
3292 .hw.init = &(struct clk_init_data){
3293 .name = "gcc_usb30_sec_sleep_clk",
3294 .ops = &clk_branch2_ops,
3299 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
3301 .halt_check = BRANCH_HALT,
3303 .enable_reg = 0xf054,
3304 .enable_mask = BIT(0),
3305 .hw.init = &(struct clk_init_data){
3306 .name = "gcc_usb3_prim_phy_aux_clk",
3307 .parent_data = &(const struct clk_parent_data){
3308 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3311 .flags = CLK_SET_RATE_PARENT,
3312 .ops = &clk_branch2_ops,
3317 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3319 .halt_check = BRANCH_HALT,
3321 .enable_reg = 0xf058,
3322 .enable_mask = BIT(0),
3323 .hw.init = &(struct clk_init_data){
3324 .name = "gcc_usb3_prim_phy_com_aux_clk",
3325 .parent_data = &(const struct clk_parent_data){
3326 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3329 .flags = CLK_SET_RATE_PARENT,
3330 .ops = &clk_branch2_ops,
3335 /* Clock ON depends on external parent clock, so don't poll */
3336 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
3338 .halt_check = BRANCH_HALT_DELAY,
3342 .enable_reg = 0xf05c,
3343 .enable_mask = BIT(0),
3344 .hw.init = &(struct clk_init_data){
3345 .name = "gcc_usb3_prim_phy_pipe_clk",
3346 .parent_data = &(const struct clk_parent_data){
3347 .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
3350 .flags = CLK_SET_RATE_PARENT,
3351 .ops = &clk_branch2_ops,
3356 static struct clk_branch gcc_usb3_sec_clkref_en = {
3357 .halt_reg = 0x8c010,
3358 .halt_check = BRANCH_HALT,
3360 .enable_reg = 0x8c010,
3361 .enable_mask = BIT(0),
3362 .hw.init = &(struct clk_init_data){
3363 .name = "gcc_usb3_sec_clkref_en",
3364 .ops = &clk_branch2_ops,
3369 static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
3370 .halt_reg = 0x10054,
3371 .halt_check = BRANCH_HALT,
3373 .enable_reg = 0x10054,
3374 .enable_mask = BIT(0),
3375 .hw.init = &(struct clk_init_data){
3376 .name = "gcc_usb3_sec_phy_aux_clk",
3377 .parent_data = &(const struct clk_parent_data){
3378 .hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3381 .flags = CLK_SET_RATE_PARENT,
3382 .ops = &clk_branch2_ops,
3387 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
3388 .halt_reg = 0x10058,
3389 .halt_check = BRANCH_HALT,
3391 .enable_reg = 0x10058,
3392 .enable_mask = BIT(0),
3393 .hw.init = &(struct clk_init_data){
3394 .name = "gcc_usb3_sec_phy_com_aux_clk",
3395 .parent_data = &(const struct clk_parent_data){
3396 .hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3399 .flags = CLK_SET_RATE_PARENT,
3400 .ops = &clk_branch2_ops,
3405 /* Clock ON depends on external parent clock, so don't poll */
3406 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
3407 .halt_reg = 0x1005c,
3408 .halt_check = BRANCH_HALT_DELAY,
3410 .enable_reg = 0x1005c,
3411 .enable_mask = BIT(0),
3412 .hw.init = &(struct clk_init_data){
3413 .name = "gcc_usb3_sec_phy_pipe_clk",
3414 .parent_data = &(const struct clk_parent_data){
3415 .hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
3418 .flags = CLK_SET_RATE_PARENT,
3419 .ops = &clk_branch2_ops,
3424 /* external clocks so add BRANCH_HALT_SKIP */
3425 static struct clk_branch gcc_video_axi0_clk = {
3426 .halt_reg = 0x28010,
3427 .halt_check = BRANCH_HALT_SKIP,
3428 .hwcg_reg = 0x28010,
3431 .enable_reg = 0x28010,
3432 .enable_mask = BIT(0),
3433 .hw.init = &(struct clk_init_data){
3434 .name = "gcc_video_axi0_clk",
3435 .ops = &clk_branch2_ops,
3440 /* external clocks so add BRANCH_HALT_SKIP */
3441 static struct clk_branch gcc_video_axi1_clk = {
3442 .halt_reg = 0x28018,
3443 .halt_check = BRANCH_HALT_SKIP,
3444 .hwcg_reg = 0x28018,
3447 .enable_reg = 0x28018,
3448 .enable_mask = BIT(0),
3449 .hw.init = &(struct clk_init_data){
3450 .name = "gcc_video_axi1_clk",
3451 .ops = &clk_branch2_ops,
3456 static struct gdsc pcie_0_gdsc = {
3459 .name = "pcie_0_gdsc",
3461 .pwrsts = PWRSTS_OFF_ON,
3464 static struct gdsc pcie_1_gdsc = {
3467 .name = "pcie_1_gdsc",
3469 .pwrsts = PWRSTS_OFF_ON,
3472 static struct gdsc ufs_card_gdsc = {
3475 .name = "ufs_card_gdsc",
3477 .pwrsts = PWRSTS_OFF_ON,
3480 static struct gdsc ufs_phy_gdsc = {
3483 .name = "ufs_phy_gdsc",
3485 .pwrsts = PWRSTS_OFF_ON,
3488 static struct gdsc usb30_prim_gdsc = {
3491 .name = "usb30_prim_gdsc",
3493 .pwrsts = PWRSTS_OFF_ON,
3496 static struct gdsc usb30_sec_gdsc = {
3499 .name = "usb30_sec_gdsc",
3501 .pwrsts = PWRSTS_OFF_ON,
3504 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
3507 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
3509 .pwrsts = PWRSTS_OFF_ON,
3513 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
3516 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
3518 .pwrsts = PWRSTS_OFF_ON,
3522 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = {
3525 .name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc",
3527 .pwrsts = PWRSTS_OFF_ON,
3531 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc = {
3534 .name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc",
3536 .pwrsts = PWRSTS_OFF_ON,
3540 static struct clk_regmap *gcc_sm8350_clocks[] = {
3541 [GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr,
3542 [GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr,
3543 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3544 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
3545 [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
3546 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3547 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
3548 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3549 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3550 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3551 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3552 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3553 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3554 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3555 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3556 [GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr,
3557 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3558 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
3559 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3560 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3561 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3562 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3563 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3564 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3565 [GCC_GPLL0] = &gcc_gpll0.clkr,
3566 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
3567 [GCC_GPLL4] = &gcc_gpll4.clkr,
3568 [GCC_GPLL9] = &gcc_gpll9.clkr,
3569 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3570 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3571 [GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr,
3572 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3573 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3574 [GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr,
3575 [GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr,
3576 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3577 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3578 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3579 [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,
3580 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3581 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
3582 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3583 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
3584 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3585 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3586 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3587 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3588 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3589 [GCC_PCIE_1_CLKREF_EN] = &gcc_pcie_1_clkref_en.clkr,
3590 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3591 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
3592 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3593 [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
3594 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3595 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3596 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3597 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3598 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3599 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3600 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3601 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3602 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3603 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
3604 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3605 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3606 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3607 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3608 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3609 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3610 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3611 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3612 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3613 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3614 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3615 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3616 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3617 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3618 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3619 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3620 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3621 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3622 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3623 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
3624 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
3625 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3626 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3627 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3628 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3629 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3630 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3631 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3632 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3633 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3634 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3635 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3636 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3637 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
3638 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
3639 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
3640 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
3641 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
3642 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
3643 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
3644 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
3645 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
3646 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
3647 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
3648 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
3649 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
3650 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
3651 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3652 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3653 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3654 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3655 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
3656 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
3657 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3658 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3659 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3660 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3661 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3662 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3663 [GCC_THROTTLE_PCIE_AHB_CLK] = &gcc_throttle_pcie_ahb_clk.clkr,
3664 [GCC_UFS_1_CLKREF_EN] = &gcc_ufs_1_clkref_en.clkr,
3665 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
3666 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
3667 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
3668 [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
3669 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
3670 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
3671 [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
3672 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
3673 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
3674 [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
3675 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
3676 [GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_rx_symbol_0_clk_src.clkr,
3677 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
3678 [GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_card_rx_symbol_1_clk_src.clkr,
3679 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
3680 [GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_tx_symbol_0_clk_src.clkr,
3681 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
3682 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr,
3683 [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
3684 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3685 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3686 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3687 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
3688 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3689 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3690 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
3691 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3692 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3693 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
3694 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3695 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
3696 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3697 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
3698 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3699 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
3700 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3701 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
3702 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
3703 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3704 [GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON] =
3705 &gcc_usb30_prim_master_clk__force_mem_core_on.clkr,
3706 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3707 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3708 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3709 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3710 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3711 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3712 [GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON] =
3713 &gcc_usb30_sec_master_clk__force_mem_core_on.clkr,
3714 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3715 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3716 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3717 [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
3718 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3719 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3720 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3721 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3722 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3723 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
3724 [GCC_USB3_SEC_CLKREF_EN] = &gcc_usb3_sec_clkref_en.clkr,
3725 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3726 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3727 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3728 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
3729 [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
3730 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3731 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
3734 static struct gdsc *gcc_sm8350_gdscs[] = {
3735 [PCIE_0_GDSC] = &pcie_0_gdsc,
3736 [PCIE_1_GDSC] = &pcie_1_gdsc,
3737 [UFS_CARD_GDSC] = &ufs_card_gdsc,
3738 [UFS_PHY_GDSC] = &ufs_phy_gdsc,
3739 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3740 [USB30_SEC_GDSC] = &usb30_sec_gdsc,
3741 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
3742 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
3743 [HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc,
3744 [HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc,
3747 static const struct qcom_reset_map gcc_sm8350_resets[] = {
3748 [GCC_CAMERA_BCR] = { 0x26000 },
3749 [GCC_DISPLAY_BCR] = { 0x27000 },
3750 [GCC_GPU_BCR] = { 0x71000 },
3751 [GCC_MMSS_BCR] = { 0xb000 },
3752 [GCC_PCIE_0_BCR] = { 0x6b000 },
3753 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3754 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3755 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3756 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
3757 [GCC_PCIE_1_BCR] = { 0x8d000 },
3758 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
3759 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
3760 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3761 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 },
3762 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
3763 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
3764 [GCC_PDM_BCR] = { 0x33000 },
3765 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3766 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3767 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3768 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3769 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3770 [GCC_SDCC2_BCR] = { 0x14000 },
3771 [GCC_SDCC4_BCR] = { 0x16000 },
3772 [GCC_UFS_CARD_BCR] = { 0x75000 },
3773 [GCC_UFS_PHY_BCR] = { 0x77000 },
3774 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3775 [GCC_USB30_SEC_BCR] = { 0x10000 },
3776 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3777 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3778 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3779 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3780 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3781 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3782 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3783 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x28010, 2 },
3784 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x28018, 2 },
3785 [GCC_VIDEO_BCR] = { 0x28000 },
3788 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3789 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3790 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3791 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3792 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3793 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3794 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3795 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3796 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
3797 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3798 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3799 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3800 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3801 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3802 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3803 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
3804 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
3805 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
3806 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
3807 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
3808 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
3811 static const struct regmap_config gcc_sm8350_regmap_config = {
3815 .max_register = 0x9c100,
3819 static const struct qcom_cc_desc gcc_sm8350_desc = {
3820 .config = &gcc_sm8350_regmap_config,
3821 .clks = gcc_sm8350_clocks,
3822 .num_clks = ARRAY_SIZE(gcc_sm8350_clocks),
3823 .resets = gcc_sm8350_resets,
3824 .num_resets = ARRAY_SIZE(gcc_sm8350_resets),
3825 .gdscs = gcc_sm8350_gdscs,
3826 .num_gdscs = ARRAY_SIZE(gcc_sm8350_gdscs),
3829 static const struct of_device_id gcc_sm8350_match_table[] = {
3830 { .compatible = "qcom,gcc-sm8350" },
3833 MODULE_DEVICE_TABLE(of, gcc_sm8350_match_table);
3835 static int gcc_sm8350_probe(struct platform_device *pdev)
3837 struct regmap *regmap;
3840 regmap = qcom_cc_map(pdev, &gcc_sm8350_desc);
3841 if (IS_ERR(regmap)) {
3842 dev_err(&pdev->dev, "Failed to map gcc registers\n");
3843 return PTR_ERR(regmap);
3847 * Keep the critical clock always-On
3848 * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK,
3849 * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK
3851 regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0));
3852 regmap_update_bits(regmap, 0x26018, BIT(0), BIT(0));
3853 regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0));
3854 regmap_update_bits(regmap, 0x2701c, BIT(0), BIT(0));
3855 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
3856 regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0));
3857 regmap_update_bits(regmap, 0x28020, BIT(0), BIT(0));
3859 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
3863 /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
3864 regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
3866 return qcom_cc_really_probe(pdev, &gcc_sm8350_desc, regmap);
3869 static struct platform_driver gcc_sm8350_driver = {
3870 .probe = gcc_sm8350_probe,
3872 .name = "sm8350-gcc",
3873 .of_match_table = gcc_sm8350_match_table,
3877 static int __init gcc_sm8350_init(void)
3879 return platform_driver_register(&gcc_sm8350_driver);
3881 subsys_initcall(gcc_sm8350_init);
3883 static void __exit gcc_sm8350_exit(void)
3885 platform_driver_unregister(&gcc_sm8350_driver);
3887 module_exit(gcc_sm8350_exit);
3889 MODULE_DESCRIPTION("QTI GCC SM8350 Driver");
3890 MODULE_LICENSE("GPL v2");