drivers/clk/qcom/gcc-sm8350.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2020-2021, Linaro Limited
   5  */
   6
   7 #include <linux/module.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/regmap.h>
  10
  11 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
  12
  13 #include "clk-alpha-pll.h"
  14 #include "clk-branch.h"
  15 #include "clk-rcg.h"
  16 #include "clk-regmap.h"
  17 #include "clk-regmap-divider.h"
  18 #include "clk-regmap-mux.h"
  19 #include "gdsc.h"
  20 #include "reset.h"
  21
  22 enum {
  23         P_BI_TCXO,
  24         P_CORE_BI_PLL_TEST_SE,
  25         P_GCC_GPLL0_OUT_EVEN,
  26         P_GCC_GPLL0_OUT_MAIN,
  27         P_GCC_GPLL4_OUT_MAIN,
  28         P_GCC_GPLL9_OUT_MAIN,
  29         P_PCIE_0_PIPE_CLK,
  30         P_PCIE_1_PIPE_CLK,
  31         P_SLEEP_CLK,
  32         P_UFS_CARD_RX_SYMBOL_0_CLK,
  33         P_UFS_CARD_RX_SYMBOL_1_CLK,
  34         P_UFS_CARD_TX_SYMBOL_0_CLK,
  35         P_UFS_PHY_RX_SYMBOL_0_CLK,
  36         P_UFS_PHY_RX_SYMBOL_1_CLK,
  37         P_UFS_PHY_TX_SYMBOL_0_CLK,
  38         P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
  39         P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK,
  40 };
  41
  42 static struct clk_alpha_pll gcc_gpll0 = {
  43         .offset = 0x0,
  44         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  45         .clkr = {
  46                 .enable_reg = 0x52018,
  47                 .enable_mask = BIT(0),
  48                 .hw.init = &(struct clk_init_data){
  49                         .name = "gcc_gpll0",
  50                         .parent_data = &(const struct clk_parent_data){
  51                                 .fw_name = "bi_tcxo",
  52                         },
  53                         .num_parents = 1,
  54                         .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
  55                 },
  56         },
  57 };
  58
  59 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
  60         { 0x1, 2 },
  61         { }
  62 };
  63
  64 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
  65         .offset = 0x0,
  66         .post_div_shift = 8,
  67         .post_div_table = post_div_table_gcc_gpll0_out_even,
  68         .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
  69         .width = 4,
  70         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  71         .clkr.hw.init = &(struct clk_init_data){
  72                 .name = "gcc_gpll0_out_even",
  73                 .parent_data = &(const struct clk_parent_data){
  74                         .hw = &gcc_gpll0.clkr.hw,
  75                 },
  76                 .num_parents = 1,
  77                 .ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops,
  78         },
  79 };
  80
  81 static struct clk_alpha_pll gcc_gpll4 = {
  82         .offset = 0x76000,
  83         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  84         .clkr = {
  85                 .enable_reg = 0x52018,
  86                 .enable_mask = BIT(4),
  87                 .hw.init = &(struct clk_init_data){
  88                         .name = "gcc_gpll4",
  89                         .parent_data = &(const struct clk_parent_data){
  90                                 .fw_name = "bi_tcxo",
  91                                 .name = "bi_tcxo",
  92                         },
  93                         .num_parents = 1,
  94                         .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
  95                 },
  96         },
  97 };
  98
  99 static struct clk_alpha_pll gcc_gpll9 = {
 100         .offset = 0x1c000,
 101         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 102         .clkr = {
 103                 .enable_reg = 0x52018,
 104                 .enable_mask = BIT(9),
 105                 .hw.init = &(struct clk_init_data){
 106                         .name = "gcc_gpll9",
 107                         .parent_data = &(const struct clk_parent_data){
 108                                 .fw_name = "bi_tcxo",
 109                                 .name = "bi_tcxo",
 110                         },
 111                         .num_parents = 1,
 112                         .ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
 113                 },
 114         },
 115 };
 116
 117 static const struct parent_map gcc_parent_map_0[] = {
 118         { P_BI_TCXO, 0 },
 119         { P_GCC_GPLL0_OUT_MAIN, 1 },
 120         { P_GCC_GPLL0_OUT_EVEN, 6 },
 121         { P_CORE_BI_PLL_TEST_SE, 7 },
 122 };
 123
 124 static const struct clk_parent_data gcc_parent_data_0[] = {
 125         { .fw_name = "bi_tcxo" },
 126         { .hw = &gcc_gpll0.clkr.hw },
 127         { .hw = &gcc_gpll0_out_even.clkr.hw },
 128         { .fw_name = "core_bi_pll_test_se" },
 129 };
 130
 131 static const struct parent_map gcc_parent_map_1[] = {
 132         { P_BI_TCXO, 0 },
 133         { P_GCC_GPLL0_OUT_MAIN, 1 },
 134         { P_SLEEP_CLK, 5 },
 135         { P_GCC_GPLL0_OUT_EVEN, 6 },
 136         { P_CORE_BI_PLL_TEST_SE, 7 },
 137 };
 138
 139 static const struct clk_parent_data gcc_parent_data_1[] = {
 140         { .fw_name = "bi_tcxo" },
 141         { .hw = &gcc_gpll0.clkr.hw },
 142         { .fw_name = "sleep_clk" },
 143         { .hw = &gcc_gpll0_out_even.clkr.hw },
 144         { .fw_name = "core_bi_pll_test_se" },
 145 };
 146
 147 static const struct parent_map gcc_parent_map_2[] = {
 148         { P_BI_TCXO, 0 },
 149         { P_SLEEP_CLK, 5 },
 150         { P_CORE_BI_PLL_TEST_SE, 7 },
 151 };
 152
 153 static const struct clk_parent_data gcc_parent_data_2[] = {
 154         { .fw_name = "bi_tcxo" },
 155         { .fw_name = "sleep_clk" },
 156         { .fw_name = "core_bi_pll_test_se" },
 157 };
 158
 159 static const struct parent_map gcc_parent_map_3[] = {
 160         { P_BI_TCXO, 0 },
 161         { P_CORE_BI_PLL_TEST_SE, 7 },
 162 };
 163
 164 static const struct clk_parent_data gcc_parent_data_3[] = {
 165         { .fw_name = "bi_tcxo" },
 166         { .fw_name = "core_bi_pll_test_se" },
 167 };
 168
 169 static const struct parent_map gcc_parent_map_4[] = {
 170         { P_PCIE_0_PIPE_CLK, 0 },
 171         { P_BI_TCXO, 2 },
 172 };
 173
 174 static const struct clk_parent_data gcc_parent_data_4[] = {
 175         { .fw_name = "pcie_0_pipe_clk", },
 176         { .fw_name = "bi_tcxo" },
 177 };
 178
 179 static const struct parent_map gcc_parent_map_5[] = {
 180         { P_PCIE_1_PIPE_CLK, 0 },
 181         { P_BI_TCXO, 2 },
 182 };
 183
 184 static const struct clk_parent_data gcc_parent_data_5[] = {
 185         { .fw_name = "pcie_1_pipe_clk" },
 186         { .fw_name = "bi_tcxo" },
 187 };
 188
 189 static const struct parent_map gcc_parent_map_6[] = {
 190         { P_BI_TCXO, 0 },
 191         { P_GCC_GPLL0_OUT_MAIN, 1 },
 192         { P_GCC_GPLL9_OUT_MAIN, 2 },
 193         { P_GCC_GPLL4_OUT_MAIN, 5 },
 194         { P_GCC_GPLL0_OUT_EVEN, 6 },
 195         { P_CORE_BI_PLL_TEST_SE, 7 },
 196 };
 197
 198 static const struct clk_parent_data gcc_parent_data_6[] = {
 199         { .fw_name = "bi_tcxo" },
 200         { .hw = &gcc_gpll0.clkr.hw },
 201         { .hw = &gcc_gpll9.clkr.hw },
 202         { .hw = &gcc_gpll4.clkr.hw },
 203         { .hw = &gcc_gpll0_out_even.clkr.hw },
 204         { .fw_name = "core_bi_pll_test_se" },
 205 };
 206
 207 static const struct parent_map gcc_parent_map_7[] = {
 208         { P_UFS_CARD_RX_SYMBOL_0_CLK, 0 },
 209         { P_BI_TCXO, 2 },
 210 };
 211
 212 static const struct clk_parent_data gcc_parent_data_7[] = {
 213         { .fw_name = "ufs_card_rx_symbol_0_clk" },
 214         { .fw_name = "bi_tcxo" },
 215 };
 216
 217 static const struct parent_map gcc_parent_map_8[] = {
 218         { P_UFS_CARD_RX_SYMBOL_1_CLK, 0 },
 219         { P_BI_TCXO, 2 },
 220 };
 221
 222 static const struct clk_parent_data gcc_parent_data_8[] = {
 223         { .fw_name = "ufs_card_rx_symbol_1_clk" },
 224         { .fw_name = "bi_tcxo" },
 225 };
 226
 227 static const struct parent_map gcc_parent_map_9[] = {
 228         { P_UFS_CARD_TX_SYMBOL_0_CLK, 0 },
 229         { P_BI_TCXO, 2 },
 230 };
 231
 232 static const struct clk_parent_data gcc_parent_data_9[] = {
 233         { .fw_name = "ufs_card_tx_symbol_0_clk" },
 234         { .fw_name = "bi_tcxo" },
 235 };
 236
 237 static const struct parent_map gcc_parent_map_10[] = {
 238         { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
 239         { P_BI_TCXO, 2 },
 240 };
 241
 242 static const struct clk_parent_data gcc_parent_data_10[] = {
 243         { .fw_name = "ufs_phy_rx_symbol_0_clk" },
 244         { .fw_name = "bi_tcxo" },
 245 };
 246
 247 static const struct parent_map gcc_parent_map_11[] = {
 248         { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
 249         { P_BI_TCXO, 2 },
 250 };
 251
 252 static const struct clk_parent_data gcc_parent_data_11[] = {
 253         { .fw_name = "ufs_phy_rx_symbol_1_clk" },
 254         { .fw_name = "bi_tcxo" },
 255 };
 256
 257 static const struct parent_map gcc_parent_map_12[] = {
 258         { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
 259         { P_BI_TCXO, 2 },
 260 };
 261
 262 static const struct clk_parent_data gcc_parent_data_12[] = {
 263         { .fw_name = "ufs_phy_tx_symbol_0_clk" },
 264         { .fw_name = "bi_tcxo" },
 265 };
 266
 267 static const struct parent_map gcc_parent_map_13[] = {
 268         { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
 269         { P_CORE_BI_PLL_TEST_SE, 1 },
 270         { P_BI_TCXO, 2 },
 271 };
 272
 273 static const struct clk_parent_data gcc_parent_data_13[] = {
 274         { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
 275         { .fw_name = "core_bi_pll_test_se" },
 276         { .fw_name = "bi_tcxo" },
 277 };
 278
 279 static const struct parent_map gcc_parent_map_14[] = {
 280         { P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK, 0 },
 281         { P_CORE_BI_PLL_TEST_SE, 1 },
 282         { P_BI_TCXO, 2 },
 283 };
 284
 285 static const struct clk_parent_data gcc_parent_data_14[] = {
 286         { .fw_name = "usb3_uni_phy_sec_gcc_usb30_pipe_clk" },
 287         { .fw_name = "core_bi_pll_test_se" },
 288         { .fw_name = "bi_tcxo" },
 289 };
 290
 291 static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
 292         .reg = 0x6b054,
 293         .shift = 0,
 294         .width = 2,
 295         .parent_map = gcc_parent_map_4,
 296         .clkr = {
 297                 .hw.init = &(struct clk_init_data){
 298                         .name = "gcc_pcie_0_pipe_clk_src",
 299                         .parent_data = gcc_parent_data_4,
 300                         .num_parents = 2,
 301                         .ops = &clk_regmap_mux_closest_ops,
 302                 },
 303         },
 304 };
 305
 306 static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
 307         .reg = 0x8d054,
 308         .shift = 0,
 309         .width = 2,
 310         .parent_map = gcc_parent_map_5,
 311         .clkr = {
 312                 .hw.init = &(struct clk_init_data){
 313                         .name = "gcc_pcie_1_pipe_clk_src",
 314                         .parent_data = gcc_parent_data_5,
 315                         .num_parents = 2,
 316                         .ops = &clk_regmap_mux_closest_ops,
 317                 },
 318         },
 319 };
 320
 321 static struct clk_regmap_mux gcc_ufs_card_rx_symbol_0_clk_src = {
 322         .reg = 0x75058,
 323         .shift = 0,
 324         .width = 2,
 325         .parent_map = gcc_parent_map_7,
 326         .clkr = {
 327                 .hw.init = &(struct clk_init_data){
 328                         .name = "gcc_ufs_card_rx_symbol_0_clk_src",
 329                         .parent_data = gcc_parent_data_7,
 330                         .num_parents = 2,
 331                         .ops = &clk_regmap_mux_closest_ops,
 332                 },
 333         },
 334 };
 335
 336 static struct clk_regmap_mux gcc_ufs_card_rx_symbol_1_clk_src = {
 337         .reg = 0x750c8,
 338         .shift = 0,
 339         .width = 2,
 340         .parent_map = gcc_parent_map_8,
 341         .clkr = {
 342                 .hw.init = &(struct clk_init_data){
 343                         .name = "gcc_ufs_card_rx_symbol_1_clk_src",
 344                         .parent_data = gcc_parent_data_8,
 345                         .num_parents = 2,
 346                         .ops = &clk_regmap_mux_closest_ops,
 347                 },
 348         },
 349 };
 350
 351 static struct clk_regmap_mux gcc_ufs_card_tx_symbol_0_clk_src = {
 352         .reg = 0x75048,
 353         .shift = 0,
 354         .width = 2,
 355         .parent_map = gcc_parent_map_9,
 356         .clkr = {
 357                 .hw.init = &(struct clk_init_data){
 358                         .name = "gcc_ufs_card_tx_symbol_0_clk_src",
 359                         .parent_data = gcc_parent_data_9,
 360                         .num_parents = 2,
 361                         .ops = &clk_regmap_mux_closest_ops,
 362                 },
 363         },
 364 };
 365
 366 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
 367         .reg = 0x77058,
 368         .shift = 0,
 369         .width = 2,
 370         .parent_map = gcc_parent_map_10,
 371         .clkr = {
 372                 .hw.init = &(struct clk_init_data){
 373                         .name = "gcc_ufs_phy_rx_symbol_0_clk_src",
 374                         .parent_data = gcc_parent_data_10,
 375                         .num_parents = 2,
 376                         .ops = &clk_regmap_mux_closest_ops,
 377                 },
 378         },
 379 };
 380
 381 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
 382         .reg = 0x770c8,
 383         .shift = 0,
 384         .width = 2,
 385         .parent_map = gcc_parent_map_11,
 386         .clkr = {
 387                 .hw.init = &(struct clk_init_data){
 388                         .name = "gcc_ufs_phy_rx_symbol_1_clk_src",
 389                         .parent_data = gcc_parent_data_11,
 390                         .num_parents = 2,
 391                         .ops = &clk_regmap_mux_closest_ops,
 392                 },
 393         },
 394 };
 395
 396 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
 397         .reg = 0x77048,
 398         .shift = 0,
 399         .width = 2,
 400         .parent_map = gcc_parent_map_12,
 401         .clkr = {
 402                 .hw.init = &(struct clk_init_data){
 403                         .name = "gcc_ufs_phy_tx_symbol_0_clk_src",
 404                         .parent_data = gcc_parent_data_12,
 405                         .num_parents = 2,
 406                         .ops = &clk_regmap_mux_closest_ops,
 407                 },
 408         },
 409 };
 410
 411 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
 412         .reg = 0xf060,
 413         .shift = 0,
 414         .width = 2,
 415         .parent_map = gcc_parent_map_13,
 416         .clkr = {
 417                 .hw.init = &(struct clk_init_data){
 418                         .name = "gcc_usb3_prim_phy_pipe_clk_src",
 419                         .parent_data = gcc_parent_data_13,
 420                         .num_parents = 3,
 421                         .ops = &clk_regmap_mux_closest_ops,
 422                 },
 423         },
 424 };
 425
 426 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
 427         .reg = 0x10060,
 428         .shift = 0,
 429         .width = 2,
 430         .parent_map = gcc_parent_map_14,
 431         .clkr = {
 432                 .hw.init = &(struct clk_init_data){
 433                         .name = "gcc_usb3_sec_phy_pipe_clk_src",
 434                         .parent_data = gcc_parent_data_14,
 435                         .num_parents = 3,
 436                         .ops = &clk_regmap_mux_closest_ops,
 437                 },
 438         },
 439 };
 440
 441 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 442         F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
 443         F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 444         F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
 445         { }
 446 };
 447
 448 static struct clk_rcg2 gcc_gp1_clk_src = {
 449         .cmd_rcgr = 0x64004,
 450         .mnd_width = 8,
 451         .hid_width = 5,
 452         .parent_map = gcc_parent_map_1,
 453         .freq_tbl = ftbl_gcc_gp1_clk_src,
 454         .clkr.hw.init = &(struct clk_init_data){
 455                 .name = "gcc_gp1_clk_src",
 456                 .parent_data = gcc_parent_data_1,
 457                 .num_parents = 5,
 458                 .flags = CLK_SET_RATE_PARENT,
 459                 .ops = &clk_rcg2_ops,
 460         },
 461 };
 462
 463 static struct clk_rcg2 gcc_gp2_clk_src = {
 464         .cmd_rcgr = 0x65004,
 465         .mnd_width = 8,
 466         .hid_width = 5,
 467         .parent_map = gcc_parent_map_1,
 468         .freq_tbl = ftbl_gcc_gp1_clk_src,
 469         .clkr.hw.init = &(struct clk_init_data){
 470                 .name = "gcc_gp2_clk_src",
 471                 .parent_data = gcc_parent_data_1,
 472                 .num_parents = 5,
 473                 .flags = CLK_SET_RATE_PARENT,
 474                 .ops = &clk_rcg2_ops,
 475         },
 476 };
 477
 478 static struct clk_rcg2 gcc_gp3_clk_src = {
 479         .cmd_rcgr = 0x66004,
 480         .mnd_width = 8,
 481         .hid_width = 5,
 482         .parent_map = gcc_parent_map_1,
 483         .freq_tbl = ftbl_gcc_gp1_clk_src,
 484         .clkr.hw.init = &(struct clk_init_data){
 485                 .name = "gcc_gp3_clk_src",
 486                 .parent_data = gcc_parent_data_1,
 487                 .num_parents = 5,
 488                 .flags = CLK_SET_RATE_PARENT,
 489                 .ops = &clk_rcg2_ops,
 490         },
 491 };
 492
 493 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
 494         F(9600000, P_BI_TCXO, 2, 0, 0),
 495         F(19200000, P_BI_TCXO, 1, 0, 0),
 496         { }
 497 };
 498
 499 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
 500         .cmd_rcgr = 0x6b058,
 501         .mnd_width = 16,
 502         .hid_width = 5,
 503         .parent_map = gcc_parent_map_2,
 504         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 505         .clkr.hw.init = &(struct clk_init_data){
 506                 .name = "gcc_pcie_0_aux_clk_src",
 507                 .parent_data = gcc_parent_data_2,
 508                 .num_parents = 3,
 509                 .flags = CLK_SET_RATE_PARENT,
 510                 .ops = &clk_rcg2_ops,
 511         },
 512 };
 513
 514 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
 515         F(19200000, P_BI_TCXO, 1, 0, 0),
 516         F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 517         { }
 518 };
 519
 520 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
 521         .cmd_rcgr = 0x6b03c,
 522         .mnd_width = 0,
 523         .hid_width = 5,
 524         .parent_map = gcc_parent_map_0,
 525         .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 526         .clkr.hw.init = &(struct clk_init_data){
 527                 .name = "gcc_pcie_0_phy_rchng_clk_src",
 528                 .parent_data = gcc_parent_data_0,
 529                 .num_parents = 4,
 530                 .flags = CLK_SET_RATE_PARENT,
 531                 .ops = &clk_rcg2_ops,
 532         },
 533 };
 534
 535 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
 536         .cmd_rcgr = 0x8d058,
 537         .mnd_width = 16,
 538         .hid_width = 5,
 539         .parent_map = gcc_parent_map_2,
 540         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 541         .clkr.hw.init = &(struct clk_init_data){
 542                 .name = "gcc_pcie_1_aux_clk_src",
 543                 .parent_data = gcc_parent_data_2,
 544                 .num_parents = 3,
 545                 .flags = CLK_SET_RATE_PARENT,
 546                 .ops = &clk_rcg2_ops,
 547         },
 548 };
 549
 550 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
 551         .cmd_rcgr = 0x8d03c,
 552         .mnd_width = 0,
 553         .hid_width = 5,
 554         .parent_map = gcc_parent_map_0,
 555         .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 556         .clkr.hw.init = &(struct clk_init_data){
 557                 .name = "gcc_pcie_1_phy_rchng_clk_src",
 558                 .parent_data = gcc_parent_data_0,
 559                 .num_parents = 4,
 560                 .flags = CLK_SET_RATE_PARENT,
 561                 .ops = &clk_rcg2_ops,
 562         },
 563 };
 564
 565 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
 566         F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
 567         { }
 568 };
 569
 570 static struct clk_rcg2 gcc_pdm2_clk_src = {
 571         .cmd_rcgr = 0x33010,
 572         .mnd_width = 0,
 573         .hid_width = 5,
 574         .parent_map = gcc_parent_map_0,
 575         .freq_tbl = ftbl_gcc_pdm2_clk_src,
 576         .clkr.hw.init = &(struct clk_init_data){
 577                 .name = "gcc_pdm2_clk_src",
 578                 .parent_data = gcc_parent_data_0,
 579                 .num_parents = 4,
 580                 .flags = CLK_SET_RATE_PARENT,
 581                 .ops = &clk_rcg2_ops,
 582         },
 583 };
 584
 585 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
 586         F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 587         F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 588         F(19200000, P_BI_TCXO, 1, 0, 0),
 589         F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 590         F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 591         F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 592         F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 593         F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
 594         F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 595         F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 596         F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 597         { }
 598 };
 599
 600 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
 601         .name = "gcc_qupv3_wrap0_s0_clk_src",
 602         .parent_data = gcc_parent_data_0,
 603         .num_parents = 4,
 604         .flags = CLK_SET_RATE_PARENT,
 605         .ops = &clk_rcg2_ops,
 606 };
 607
 608 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
 609         .cmd_rcgr = 0x17010,
 610         .mnd_width = 16,
 611         .hid_width = 5,
 612         .parent_map = gcc_parent_map_0,
 613         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 614         .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
 615 };
 616
 617 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
 618         .name = "gcc_qupv3_wrap0_s1_clk_src",
 619         .parent_data = gcc_parent_data_0,
 620         .num_parents = 4,
 621         .flags = CLK_SET_RATE_PARENT,
 622         .ops = &clk_rcg2_ops,
 623 };
 624
 625 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
 626         .cmd_rcgr = 0x17140,
 627         .mnd_width = 16,
 628         .hid_width = 5,
 629         .parent_map = gcc_parent_map_0,
 630         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 631         .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
 632 };
 633
 634 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
 635         .name = "gcc_qupv3_wrap0_s2_clk_src",
 636         .parent_data = gcc_parent_data_0,
 637         .num_parents = 4,
 638         .flags = CLK_SET_RATE_PARENT,
 639         .ops = &clk_rcg2_ops,
 640 };
 641
 642 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
 643         .cmd_rcgr = 0x17270,
 644         .mnd_width = 16,
 645         .hid_width = 5,
 646         .parent_map = gcc_parent_map_0,
 647         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 648         .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
 649 };
 650
 651 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
 652         .name = "gcc_qupv3_wrap0_s3_clk_src",
 653         .parent_data = gcc_parent_data_0,
 654         .num_parents = 4,
 655         .flags = CLK_SET_RATE_PARENT,
 656         .ops = &clk_rcg2_ops,
 657 };
 658
 659 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
 660         .cmd_rcgr = 0x173a0,
 661         .mnd_width = 16,
 662         .hid_width = 5,
 663         .parent_map = gcc_parent_map_0,
 664         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 665         .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
 666 };
 667
 668 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
 669         .name = "gcc_qupv3_wrap0_s4_clk_src",
 670         .parent_data = gcc_parent_data_0,
 671         .num_parents = 4,
 672         .flags = CLK_SET_RATE_PARENT,
 673         .ops = &clk_rcg2_ops,
 674 };
 675
 676 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
 677         .cmd_rcgr = 0x174d0,
 678         .mnd_width = 16,
 679         .hid_width = 5,
 680         .parent_map = gcc_parent_map_0,
 681         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 682         .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
 683 };
 684
 685 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
 686         .name = "gcc_qupv3_wrap0_s5_clk_src",
 687         .parent_data = gcc_parent_data_0,
 688         .num_parents = 4,
 689         .flags = CLK_SET_RATE_PARENT,
 690         .ops = &clk_rcg2_ops,
 691 };
 692
 693 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
 694         .cmd_rcgr = 0x17600,
 695         .mnd_width = 16,
 696         .hid_width = 5,
 697         .parent_map = gcc_parent_map_0,
 698         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 699         .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
 700 };
 701
 702 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
 703         .name = "gcc_qupv3_wrap0_s6_clk_src",
 704         .parent_data = gcc_parent_data_0,
 705         .num_parents = 4,
 706         .flags = CLK_SET_RATE_PARENT,
 707         .ops = &clk_rcg2_ops,
 708 };
 709
 710 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
 711         .cmd_rcgr = 0x17730,
 712         .mnd_width = 16,
 713         .hid_width = 5,
 714         .parent_map = gcc_parent_map_0,
 715         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 716         .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
 717 };
 718
 719 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
 720         .name = "gcc_qupv3_wrap0_s7_clk_src",
 721         .parent_data = gcc_parent_data_0,
 722         .num_parents = 4,
 723         .flags = CLK_SET_RATE_PARENT,
 724         .ops = &clk_rcg2_ops,
 725 };
 726
 727 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
 728         .cmd_rcgr = 0x17860,
 729         .mnd_width = 16,
 730         .hid_width = 5,
 731         .parent_map = gcc_parent_map_0,
 732         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 733         .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
 734 };
 735
 736 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = {
 737         F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 738         F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 739         F(19200000, P_BI_TCXO, 1, 0, 0),
 740         F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 741         F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 742         F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 743         F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 744         F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
 745         F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 746         F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 747         F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 748         F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
 749         F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
 750         F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
 751         F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
 752         { }
 753 };
 754
 755 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
 756         .name = "gcc_qupv3_wrap1_s0_clk_src",
 757         .parent_data = gcc_parent_data_0,
 758         .num_parents = 4,
 759         .flags = CLK_SET_RATE_PARENT,
 760         .ops = &clk_rcg2_ops,
 761 };
 762
 763 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
 764         .cmd_rcgr = 0x18010,
 765         .mnd_width = 16,
 766         .hid_width = 5,
 767         .parent_map = gcc_parent_map_0,
 768         .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
 769         .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
 770 };
 771
 772 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
 773         .name = "gcc_qupv3_wrap1_s1_clk_src",
 774         .parent_data = gcc_parent_data_0,
 775         .num_parents = 4,
 776         .flags = CLK_SET_RATE_PARENT,
 777         .ops = &clk_rcg2_ops,
 778 };
 779
 780 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
 781         .cmd_rcgr = 0x18140,
 782         .mnd_width = 16,
 783         .hid_width = 5,
 784         .parent_map = gcc_parent_map_0,
 785         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 786         .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
 787 };
 788
 789 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
 790         .name = "gcc_qupv3_wrap1_s2_clk_src",
 791         .parent_data = gcc_parent_data_0,
 792         .num_parents = 4,
 793         .flags = CLK_SET_RATE_PARENT,
 794         .ops = &clk_rcg2_ops,
 795 };
 796
 797 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
 798         .cmd_rcgr = 0x18270,
 799         .mnd_width = 16,
 800         .hid_width = 5,
 801         .parent_map = gcc_parent_map_0,
 802         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 803         .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
 804 };
 805
 806 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
 807         .name = "gcc_qupv3_wrap1_s3_clk_src",
 808         .parent_data = gcc_parent_data_0,
 809         .num_parents = 4,
 810         .flags = CLK_SET_RATE_PARENT,
 811         .ops = &clk_rcg2_ops,
 812 };
 813
 814 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
 815         .cmd_rcgr = 0x183a0,
 816         .mnd_width = 16,
 817         .hid_width = 5,
 818         .parent_map = gcc_parent_map_0,
 819         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 820         .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
 821 };
 822
 823 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
 824         .name = "gcc_qupv3_wrap1_s4_clk_src",
 825         .parent_data = gcc_parent_data_0,
 826         .num_parents = 4,
 827         .flags = CLK_SET_RATE_PARENT,
 828         .ops = &clk_rcg2_ops,
 829 };
 830
 831 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
 832         .cmd_rcgr = 0x184d0,
 833         .mnd_width = 16,
 834         .hid_width = 5,
 835         .parent_map = gcc_parent_map_0,
 836         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 837         .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
 838 };
 839
 840 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
 841         .name = "gcc_qupv3_wrap1_s5_clk_src",
 842         .parent_data = gcc_parent_data_0,
 843         .num_parents = 4,
 844         .flags = CLK_SET_RATE_PARENT,
 845         .ops = &clk_rcg2_ops,
 846 };
 847
 848 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
 849         .cmd_rcgr = 0x18600,
 850         .mnd_width = 16,
 851         .hid_width = 5,
 852         .parent_map = gcc_parent_map_0,
 853         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 854         .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
 855 };
 856
 857 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
 858         .name = "gcc_qupv3_wrap2_s0_clk_src",
 859         .parent_data = gcc_parent_data_0,
 860         .num_parents = 4,
 861         .flags = CLK_SET_RATE_PARENT,
 862         .ops = &clk_rcg2_ops,
 863 };
 864
 865 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
 866         .cmd_rcgr = 0x1e010,
 867         .mnd_width = 16,
 868         .hid_width = 5,
 869         .parent_map = gcc_parent_map_0,
 870         .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
 871         .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
 872 };
 873
 874 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
 875         .name = "gcc_qupv3_wrap2_s1_clk_src",
 876         .parent_data = gcc_parent_data_0,
 877         .num_parents = 4,
 878         .flags = CLK_SET_RATE_PARENT,
 879         .ops = &clk_rcg2_ops,
 880 };
 881
 882 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
 883         .cmd_rcgr = 0x1e140,
 884         .mnd_width = 16,
 885         .hid_width = 5,
 886         .parent_map = gcc_parent_map_0,
 887         .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
 888         .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
 889 };
 890
 891 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
 892         .name = "gcc_qupv3_wrap2_s2_clk_src",
 893         .parent_data = gcc_parent_data_0,
 894         .num_parents = 4,
 895         .flags = CLK_SET_RATE_PARENT,
 896         .ops = &clk_rcg2_ops,
 897 };
 898
 899 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
 900         .cmd_rcgr = 0x1e270,
 901         .mnd_width = 16,
 902         .hid_width = 5,
 903         .parent_map = gcc_parent_map_0,
 904         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 905         .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
 906 };
 907
 908 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
 909         .name = "gcc_qupv3_wrap2_s3_clk_src",
 910         .parent_data = gcc_parent_data_0,
 911         .num_parents = 4,
 912         .flags = CLK_SET_RATE_PARENT,
 913         .ops = &clk_rcg2_ops,
 914 };
 915
 916 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
 917         .cmd_rcgr = 0x1e3a0,
 918         .mnd_width = 16,
 919         .hid_width = 5,
 920         .parent_map = gcc_parent_map_0,
 921         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 922         .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
 923 };
 924
 925 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
 926         .name = "gcc_qupv3_wrap2_s4_clk_src",
 927         .parent_data = gcc_parent_data_0,
 928         .num_parents = 4,
 929         .flags = CLK_SET_RATE_PARENT,
 930         .ops = &clk_rcg2_ops,
 931 };
 932
 933 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
 934         .cmd_rcgr = 0x1e4d0,
 935         .mnd_width = 16,
 936         .hid_width = 5,
 937         .parent_map = gcc_parent_map_0,
 938         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 939         .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
 940 };
 941
 942 static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
 943         .name = "gcc_qupv3_wrap2_s5_clk_src",
 944         .parent_data = gcc_parent_data_0,
 945         .num_parents = 4,
 946         .flags = CLK_SET_RATE_PARENT,
 947         .ops = &clk_rcg2_ops,
 948 };
 949
 950 static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
 951         .cmd_rcgr = 0x1e600,
 952         .mnd_width = 16,
 953         .hid_width = 5,
 954         .parent_map = gcc_parent_map_0,
 955         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 956         .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
 957 };
 958
 959 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
 960         F(400000, P_BI_TCXO, 12, 1, 4),
 961         F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
 962         F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
 963         F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 964         F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
 965         { }
 966 };
 967
 968 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
 969         .cmd_rcgr = 0x1400c,
 970         .mnd_width = 8,
 971         .hid_width = 5,
 972         .parent_map = gcc_parent_map_6,
 973         .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
 974         .clkr.hw.init = &(struct clk_init_data){
 975                 .name = "gcc_sdcc2_apps_clk_src",
 976                 .parent_data = gcc_parent_data_6,
 977                 .num_parents = 6,
 978                 .flags = CLK_SET_RATE_PARENT,
 979                 .ops = &clk_rcg2_floor_ops,
 980         },
 981 };
 982
 983 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
 984         F(400000, P_BI_TCXO, 12, 1, 4),
 985         F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
 986         F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 987         { }
 988 };
 989
 990 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
 991         .cmd_rcgr = 0x1600c,
 992         .mnd_width = 8,
 993         .hid_width = 5,
 994         .parent_map = gcc_parent_map_0,
 995         .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
 996         .clkr.hw.init = &(struct clk_init_data){
 997                 .name = "gcc_sdcc4_apps_clk_src",
 998                 .parent_data = gcc_parent_data_0,
 999                 .num_parents = 4,
1000                 .flags = CLK_SET_RATE_PARENT,
1001                 .ops = &clk_rcg2_floor_ops,
1002         },
1003 };
1004
1005 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
1006         F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1007         F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1008         F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1009         F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1010         { }
1011 };
1012
1013 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
1014         .cmd_rcgr = 0x75024,
1015         .mnd_width = 8,
1016         .hid_width = 5,
1017         .parent_map = gcc_parent_map_0,
1018         .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
1019         .clkr.hw.init = &(struct clk_init_data){
1020                 .name = "gcc_ufs_card_axi_clk_src",
1021                 .parent_data = gcc_parent_data_0,
1022                 .num_parents = 4,
1023                 .flags = CLK_SET_RATE_PARENT,
1024                 .ops = &clk_rcg2_ops,
1025         },
1026 };
1027
1028 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
1029         F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1030         F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1031         F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1032         { }
1033 };
1034
1035 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
1036         .cmd_rcgr = 0x7506c,
1037         .mnd_width = 0,
1038         .hid_width = 5,
1039         .parent_map = gcc_parent_map_0,
1040         .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1041         .clkr.hw.init = &(struct clk_init_data){
1042                 .name = "gcc_ufs_card_ice_core_clk_src",
1043                 .parent_data = gcc_parent_data_0,
1044                 .num_parents = 4,
1045                 .flags = CLK_SET_RATE_PARENT,
1046                 .ops = &clk_rcg2_ops,
1047         },
1048 };
1049
1050 static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = {
1051         F(19200000, P_BI_TCXO, 1, 0, 0),
1052         { }
1053 };
1054
1055 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
1056         .cmd_rcgr = 0x750a0,
1057         .mnd_width = 0,
1058         .hid_width = 5,
1059         .parent_map = gcc_parent_map_3,
1060         .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1061         .clkr.hw.init = &(struct clk_init_data){
1062                 .name = "gcc_ufs_card_phy_aux_clk_src",
1063                 .parent_data = gcc_parent_data_3,
1064                 .num_parents = 2,
1065                 .flags = CLK_SET_RATE_PARENT,
1066                 .ops = &clk_rcg2_ops,
1067         },
1068 };
1069
1070 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
1071         .cmd_rcgr = 0x75084,
1072         .mnd_width = 0,
1073         .hid_width = 5,
1074         .parent_map = gcc_parent_map_0,
1075         .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1076         .clkr.hw.init = &(struct clk_init_data){
1077                 .name = "gcc_ufs_card_unipro_core_clk_src",
1078                 .parent_data = gcc_parent_data_0,
1079                 .num_parents = 4,
1080                 .flags = CLK_SET_RATE_PARENT,
1081                 .ops = &clk_rcg2_ops,
1082         },
1083 };
1084
1085 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1086         .cmd_rcgr = 0x77024,
1087         .mnd_width = 8,
1088         .hid_width = 5,
1089         .parent_map = gcc_parent_map_0,
1090         .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
1091         .clkr.hw.init = &(struct clk_init_data){
1092                 .name = "gcc_ufs_phy_axi_clk_src",
1093                 .parent_data = gcc_parent_data_0,
1094                 .num_parents = 4,
1095                 .flags = CLK_SET_RATE_PARENT,
1096                 .ops = &clk_rcg2_ops,
1097         },
1098 };
1099
1100 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1101         .cmd_rcgr = 0x7706c,
1102         .mnd_width = 0,
1103         .hid_width = 5,
1104         .parent_map = gcc_parent_map_0,
1105         .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1106         .clkr.hw.init = &(struct clk_init_data){
1107                 .name = "gcc_ufs_phy_ice_core_clk_src",
1108                 .parent_data = gcc_parent_data_0,
1109                 .num_parents = 4,
1110                 .flags = CLK_SET_RATE_PARENT,
1111                 .ops = &clk_rcg2_ops,
1112         },
1113 };
1114
1115 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1116         .cmd_rcgr = 0x770a0,
1117         .mnd_width = 0,
1118         .hid_width = 5,
1119         .parent_map = gcc_parent_map_3,
1120         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1121         .clkr.hw.init = &(struct clk_init_data){
1122                 .name = "gcc_ufs_phy_phy_aux_clk_src",
1123                 .parent_data = gcc_parent_data_3,
1124                 .num_parents = 2,
1125                 .flags = CLK_SET_RATE_PARENT,
1126                 .ops = &clk_rcg2_ops,
1127         },
1128 };
1129
1130 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1131         .cmd_rcgr = 0x77084,
1132         .mnd_width = 0,
1133         .hid_width = 5,
1134         .parent_map = gcc_parent_map_0,
1135         .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1136         .clkr.hw.init = &(struct clk_init_data){
1137                 .name = "gcc_ufs_phy_unipro_core_clk_src",
1138                 .parent_data = gcc_parent_data_0,
1139                 .num_parents = 4,
1140                 .flags = CLK_SET_RATE_PARENT,
1141                 .ops = &clk_rcg2_ops,
1142         },
1143 };
1144
1145 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1146         F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1147         F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1148         F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1149         F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1150         { }
1151 };
1152
1153 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1154         .cmd_rcgr = 0xf020,
1155         .mnd_width = 8,
1156         .hid_width = 5,
1157         .parent_map = gcc_parent_map_0,
1158         .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1159         .clkr.hw.init = &(struct clk_init_data){
1160                 .name = "gcc_usb30_prim_master_clk_src",
1161                 .parent_data = gcc_parent_data_0,
1162                 .num_parents = 4,
1163                 .flags = CLK_SET_RATE_PARENT,
1164                 .ops = &clk_rcg2_ops,
1165         },
1166 };
1167
1168 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1169         .cmd_rcgr = 0xf038,
1170         .mnd_width = 0,
1171         .hid_width = 5,
1172         .parent_map = gcc_parent_map_0,
1173         .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1174         .clkr.hw.init = &(struct clk_init_data){
1175                 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1176                 .parent_data = gcc_parent_data_0,
1177                 .num_parents = 4,
1178                 .flags = CLK_SET_RATE_PARENT,
1179                 .ops = &clk_rcg2_ops,
1180         },
1181 };
1182
1183 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1184         .cmd_rcgr = 0x10020,
1185         .mnd_width = 8,
1186         .hid_width = 5,
1187         .parent_map = gcc_parent_map_0,
1188         .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1189         .clkr.hw.init = &(struct clk_init_data){
1190                 .name = "gcc_usb30_sec_master_clk_src",
1191                 .parent_data = gcc_parent_data_0,
1192                 .num_parents = 4,
1193                 .flags = CLK_SET_RATE_PARENT,
1194                 .ops = &clk_rcg2_ops,
1195         },
1196 };
1197
1198 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1199         .cmd_rcgr = 0x10038,
1200         .mnd_width = 0,
1201         .hid_width = 5,
1202         .parent_map = gcc_parent_map_0,
1203         .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1204         .clkr.hw.init = &(struct clk_init_data){
1205                 .name = "gcc_usb30_sec_mock_utmi_clk_src",
1206                 .parent_data = gcc_parent_data_0,
1207                 .num_parents = 4,
1208                 .flags = CLK_SET_RATE_PARENT,
1209                 .ops = &clk_rcg2_ops,
1210         },
1211 };
1212
1213 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1214         .cmd_rcgr = 0xf064,
1215         .mnd_width = 0,
1216         .hid_width = 5,
1217         .parent_map = gcc_parent_map_2,
1218         .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1219         .clkr.hw.init = &(struct clk_init_data){
1220                 .name = "gcc_usb3_prim_phy_aux_clk_src",
1221                 .parent_data = gcc_parent_data_2,
1222                 .num_parents = 3,
1223                 .flags = CLK_SET_RATE_PARENT,
1224                 .ops = &clk_rcg2_ops,
1225         },
1226 };
1227
1228 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1229         .cmd_rcgr = 0x10064,
1230         .mnd_width = 0,
1231         .hid_width = 5,
1232         .parent_map = gcc_parent_map_2,
1233         .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1234         .clkr.hw.init = &(struct clk_init_data){
1235                 .name = "gcc_usb3_sec_phy_aux_clk_src",
1236                 .parent_data = gcc_parent_data_2,
1237                 .num_parents = 3,
1238                 .flags = CLK_SET_RATE_PARENT,
1239                 .ops = &clk_rcg2_ops,
1240         },
1241 };
1242
1243 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1244         .reg = 0xf050,
1245         .shift = 0,
1246         .width = 4,
1247         .clkr.hw.init = &(struct clk_init_data) {
1248                 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1249                 .parent_data = &(const struct clk_parent_data){
1250                         .hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1251                 },
1252                 .num_parents = 1,
1253                 .flags = CLK_SET_RATE_PARENT,
1254                 .ops = &clk_regmap_div_ro_ops,
1255         },
1256 };
1257
1258 static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
1259         .reg = 0x10050,
1260         .shift = 0,
1261         .width = 4,
1262         .clkr.hw.init = &(struct clk_init_data) {
1263                 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
1264                 .parent_data = &(const struct clk_parent_data){
1265                         .hw = &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
1266                 },
1267                 .num_parents = 1,
1268                 .flags = CLK_SET_RATE_PARENT,
1269                 .ops = &clk_regmap_div_ro_ops,
1270         },
1271 };
1272
1273 /* external clocks so add BRANCH_HALT_SKIP */
1274 static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = {
1275         .halt_reg = 0x6b080,
1276         .halt_check = BRANCH_HALT_SKIP,
1277         .clkr = {
1278                 .enable_reg = 0x52000,
1279                 .enable_mask = BIT(12),
1280                 .hw.init = &(struct clk_init_data){
1281                         .name = "gcc_aggre_noc_pcie_0_axi_clk",
1282                         .ops = &clk_branch2_ops,
1283                 },
1284         },
1285 };
1286
1287 /* external clocks so add BRANCH_HALT_SKIP */
1288 static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = {
1289         .halt_reg = 0x8d084,
1290         .halt_check = BRANCH_HALT_SKIP,
1291         .clkr = {
1292                 .enable_reg = 0x52000,
1293                 .enable_mask = BIT(11),
1294                 .hw.init = &(struct clk_init_data){
1295                         .name = "gcc_aggre_noc_pcie_1_axi_clk",
1296                         .ops = &clk_branch2_ops,
1297                 },
1298         },
1299 };
1300
1301 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1302         .halt_reg = 0x9000c,
1303         .halt_check = BRANCH_HALT_VOTED,
1304         .hwcg_reg = 0x9000c,
1305         .hwcg_bit = 1,
1306         .clkr = {
1307                 .enable_reg = 0x52000,
1308                 .enable_mask = BIT(18),
1309                 .hw.init = &(struct clk_init_data){
1310                         .name = "gcc_aggre_noc_pcie_tbu_clk",
1311                         .ops = &clk_branch2_ops,
1312                 },
1313         },
1314 };
1315
1316 static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1317         .halt_reg = 0x750cc,
1318         .halt_check = BRANCH_HALT_VOTED,
1319         .hwcg_reg = 0x750cc,
1320         .hwcg_bit = 1,
1321         .clkr = {
1322                 .enable_reg = 0x750cc,
1323                 .enable_mask = BIT(0),
1324                 .hw.init = &(struct clk_init_data){
1325                         .name = "gcc_aggre_ufs_card_axi_clk",
1326                         .parent_data = &(const struct clk_parent_data){
1327                                 .hw = &gcc_ufs_card_axi_clk_src.clkr.hw,
1328                         },
1329                         .num_parents = 1,
1330                         .flags = CLK_SET_RATE_PARENT,
1331                         .ops = &clk_branch2_ops,
1332                 },
1333         },
1334 };
1335
1336 static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
1337         .halt_reg = 0x750cc,
1338         .halt_check = BRANCH_HALT_VOTED,
1339         .hwcg_reg = 0x750cc,
1340         .hwcg_bit = 1,
1341         .clkr = {
1342                 .enable_reg = 0x750cc,
1343                 .enable_mask = BIT(1),
1344                 .hw.init = &(struct clk_init_data){
1345                         .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
1346                         .parent_data = &(const struct clk_parent_data){
1347                                 .hw = &gcc_ufs_card_axi_clk_src.clkr.hw,
1348                         },
1349                         .num_parents = 1,
1350                         .flags = CLK_SET_RATE_PARENT,
1351                         .ops = &clk_branch2_ops,
1352                 },
1353         },
1354 };
1355
1356 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1357         .halt_reg = 0x770cc,
1358         .halt_check = BRANCH_HALT_VOTED,
1359         .hwcg_reg = 0x770cc,
1360         .hwcg_bit = 1,
1361         .clkr = {
1362                 .enable_reg = 0x770cc,
1363                 .enable_mask = BIT(0),
1364                 .hw.init = &(struct clk_init_data){
1365                         .name = "gcc_aggre_ufs_phy_axi_clk",
1366                         .parent_data = &(const struct clk_parent_data){
1367                                 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
1368                         },
1369                         .num_parents = 1,
1370                         .flags = CLK_SET_RATE_PARENT,
1371                         .ops = &clk_branch2_ops,
1372                 },
1373         },
1374 };
1375
1376 static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1377         .halt_reg = 0x770cc,
1378         .halt_check = BRANCH_HALT_VOTED,
1379         .hwcg_reg = 0x770cc,
1380         .hwcg_bit = 1,
1381         .clkr = {
1382                 .enable_reg = 0x770cc,
1383                 .enable_mask = BIT(1),
1384                 .hw.init = &(struct clk_init_data){
1385                         .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1386                         .parent_data = &(const struct clk_parent_data){
1387                                 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
1388                         },
1389                         .num_parents = 1,
1390                         .flags = CLK_SET_RATE_PARENT,
1391                         .ops = &clk_branch2_ops,
1392                 },
1393         },
1394 };
1395
1396 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1397         .halt_reg = 0xf080,
1398         .halt_check = BRANCH_HALT_VOTED,
1399         .hwcg_reg = 0xf080,
1400         .hwcg_bit = 1,
1401         .clkr = {
1402                 .enable_reg = 0xf080,
1403                 .enable_mask = BIT(0),
1404                 .hw.init = &(struct clk_init_data){
1405                         .name = "gcc_aggre_usb3_prim_axi_clk",
1406                         .parent_data = &(const struct clk_parent_data){
1407                                 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
1408                         },
1409                         .num_parents = 1,
1410                         .flags = CLK_SET_RATE_PARENT,
1411                         .ops = &clk_branch2_ops,
1412                 },
1413         },
1414 };
1415
1416 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1417         .halt_reg = 0x10080,
1418         .halt_check = BRANCH_HALT_VOTED,
1419         .hwcg_reg = 0x10080,
1420         .hwcg_bit = 1,
1421         .clkr = {
1422                 .enable_reg = 0x10080,
1423                 .enable_mask = BIT(0),
1424                 .hw.init = &(struct clk_init_data){
1425                         .name = "gcc_aggre_usb3_sec_axi_clk",
1426                         .parent_data = &(const struct clk_parent_data){
1427                                 .hw = &gcc_usb30_sec_master_clk_src.clkr.hw,
1428                         },
1429                         .num_parents = 1,
1430                         .flags = CLK_SET_RATE_PARENT,
1431                         .ops = &clk_branch2_ops,
1432                 },
1433         },
1434 };
1435
1436 static struct clk_branch gcc_boot_rom_ahb_clk = {
1437         .halt_reg = 0x38004,
1438         .halt_check = BRANCH_HALT_VOTED,
1439         .hwcg_reg = 0x38004,
1440         .hwcg_bit = 1,
1441         .clkr = {
1442                 .enable_reg = 0x52000,
1443                 .enable_mask = BIT(10),
1444                 .hw.init = &(struct clk_init_data){
1445                         .name = "gcc_boot_rom_ahb_clk",
1446                         .ops = &clk_branch2_ops,
1447                 },
1448         },
1449 };
1450
1451 /* external clocks so add BRANCH_HALT_SKIP */
1452 static struct clk_branch gcc_camera_hf_axi_clk = {
1453         .halt_reg = 0x26010,
1454         .halt_check = BRANCH_HALT_SKIP,
1455         .hwcg_reg = 0x26010,
1456         .hwcg_bit = 1,
1457         .clkr = {
1458                 .enable_reg = 0x26010,
1459                 .enable_mask = BIT(0),
1460                 .hw.init = &(struct clk_init_data){
1461                         .name = "gcc_camera_hf_axi_clk",
1462                         .ops = &clk_branch2_ops,
1463                 },
1464         },
1465 };
1466
1467 /* external clocks so add BRANCH_HALT_SKIP */
1468 static struct clk_branch gcc_camera_sf_axi_clk = {
1469         .halt_reg = 0x26014,
1470         .halt_check = BRANCH_HALT_SKIP,
1471         .hwcg_reg = 0x26014,
1472         .hwcg_bit = 1,
1473         .clkr = {
1474                 .enable_reg = 0x26014,
1475                 .enable_mask = BIT(0),
1476                 .hw.init = &(struct clk_init_data){
1477                         .name = "gcc_camera_sf_axi_clk",
1478                         .ops = &clk_branch2_ops,
1479                 },
1480         },
1481 };
1482
1483 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1484         .halt_reg = 0xf07c,
1485         .halt_check = BRANCH_HALT_VOTED,
1486         .hwcg_reg = 0xf07c,
1487         .hwcg_bit = 1,
1488         .clkr = {
1489                 .enable_reg = 0xf07c,
1490                 .enable_mask = BIT(0),
1491                 .hw.init = &(struct clk_init_data){
1492                         .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1493                         .parent_data = &(const struct clk_parent_data){
1494                                 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
1495                         },
1496                         .num_parents = 1,
1497                         .flags = CLK_SET_RATE_PARENT,
1498                         .ops = &clk_branch2_ops,
1499                 },
1500         },
1501 };
1502
1503 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1504         .halt_reg = 0x1007c,
1505         .halt_check = BRANCH_HALT_VOTED,
1506         .hwcg_reg = 0x1007c,
1507         .hwcg_bit = 1,
1508         .clkr = {
1509                 .enable_reg = 0x1007c,
1510                 .enable_mask = BIT(0),
1511                 .hw.init = &(struct clk_init_data){
1512                         .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1513                         .parent_data = &(const struct clk_parent_data){
1514                                 .hw = &gcc_usb30_sec_master_clk_src.clkr.hw,
1515                         },
1516                         .num_parents = 1,
1517                         .flags = CLK_SET_RATE_PARENT,
1518                         .ops = &clk_branch2_ops,
1519                 },
1520         },
1521 };
1522
1523 /* external clocks so add BRANCH_HALT_SKIP */
1524 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1525         .halt_reg = 0x71154,
1526         .halt_check = BRANCH_HALT_SKIP,
1527         .hwcg_reg = 0x71154,
1528         .hwcg_bit = 1,
1529         .clkr = {
1530                 .enable_reg = 0x71154,
1531                 .enable_mask = BIT(0),
1532                 .hw.init = &(struct clk_init_data){
1533                         .name = "gcc_ddrss_gpu_axi_clk",
1534                         .ops = &clk_branch2_aon_ops,
1535                 },
1536         },
1537 };
1538
1539 /* external clocks so add BRANCH_HALT_SKIP */
1540 static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = {
1541         .halt_reg = 0x8d080,
1542         .halt_check = BRANCH_HALT_SKIP,
1543         .hwcg_reg = 0x8d080,
1544         .hwcg_bit = 1,
1545         .clkr = {
1546                 .enable_reg = 0x52000,
1547                 .enable_mask = BIT(19),
1548                 .hw.init = &(struct clk_init_data){
1549                         .name = "gcc_ddrss_pcie_sf_tbu_clk",
1550                         .ops = &clk_branch2_ops,
1551                 },
1552         },
1553 };
1554
1555 /* external clocks so add BRANCH_HALT_SKIP */
1556 static struct clk_branch gcc_disp_hf_axi_clk = {
1557         .halt_reg = 0x2700c,
1558         .halt_check = BRANCH_HALT_SKIP,
1559         .hwcg_reg = 0x2700c,
1560         .hwcg_bit = 1,
1561         .clkr = {
1562                 .enable_reg = 0x2700c,
1563                 .enable_mask = BIT(0),
1564                 .hw.init = &(struct clk_init_data){
1565                         .name = "gcc_disp_hf_axi_clk",
1566                         .ops = &clk_branch2_ops,
1567                 },
1568         },
1569 };
1570
1571 /* external clocks so add BRANCH_HALT_SKIP */
1572 static struct clk_branch gcc_disp_sf_axi_clk = {
1573         .halt_reg = 0x27014,
1574         .halt_check = BRANCH_HALT_SKIP,
1575         .hwcg_reg = 0x27014,
1576         .hwcg_bit = 1,
1577         .clkr = {
1578                 .enable_reg = 0x27014,
1579                 .enable_mask = BIT(0),
1580                 .hw.init = &(struct clk_init_data){
1581                         .name = "gcc_disp_sf_axi_clk",
1582                         .ops = &clk_branch2_ops,
1583                 },
1584         },
1585 };
1586
1587 static struct clk_branch gcc_gp1_clk = {
1588         .halt_reg = 0x64000,
1589         .halt_check = BRANCH_HALT,
1590         .clkr = {
1591                 .enable_reg = 0x64000,
1592                 .enable_mask = BIT(0),
1593                 .hw.init = &(struct clk_init_data){
1594                         .name = "gcc_gp1_clk",
1595                         .parent_data = &(const struct clk_parent_data){
1596                                 .hw = &gcc_gp1_clk_src.clkr.hw,
1597                         },
1598                         .num_parents = 1,
1599                         .flags = CLK_SET_RATE_PARENT,
1600                         .ops = &clk_branch2_ops,
1601                 },
1602         },
1603 };
1604
1605 static struct clk_branch gcc_gp2_clk = {
1606         .halt_reg = 0x65000,
1607         .halt_check = BRANCH_HALT,
1608         .clkr = {
1609                 .enable_reg = 0x65000,
1610                 .enable_mask = BIT(0),
1611                 .hw.init = &(struct clk_init_data){
1612                         .name = "gcc_gp2_clk",
1613                         .parent_data = &(const struct clk_parent_data){
1614                                 .hw = &gcc_gp2_clk_src.clkr.hw,
1615                         },
1616                         .num_parents = 1,
1617                         .flags = CLK_SET_RATE_PARENT,
1618                         .ops = &clk_branch2_ops,
1619                 },
1620         },
1621 };
1622
1623 static struct clk_branch gcc_gp3_clk = {
1624         .halt_reg = 0x66000,
1625         .halt_check = BRANCH_HALT,
1626         .clkr = {
1627                 .enable_reg = 0x66000,
1628                 .enable_mask = BIT(0),
1629                 .hw.init = &(struct clk_init_data){
1630                         .name = "gcc_gp3_clk",
1631                         .parent_data = &(const struct clk_parent_data){
1632                                 .hw = &gcc_gp3_clk_src.clkr.hw,
1633                         },
1634                         .num_parents = 1,
1635                         .flags = CLK_SET_RATE_PARENT,
1636                         .ops = &clk_branch2_ops,
1637                 },
1638         },
1639 };
1640
1641 /* Clock ON depends on external parent clock, so don't poll */
1642 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1643         .halt_check = BRANCH_HALT_DELAY,
1644         .clkr = {
1645                 .enable_reg = 0x52000,
1646                 .enable_mask = BIT(15),
1647                 .hw.init = &(struct clk_init_data){
1648                         .name = "gcc_gpu_gpll0_clk_src",
1649                         .parent_data = &(const struct clk_parent_data){
1650                                 .hw = &gcc_gpll0.clkr.hw,
1651                         },
1652                         .num_parents = 1,
1653                         .flags = CLK_SET_RATE_PARENT,
1654                         .ops = &clk_branch2_ops,
1655                 },
1656         },
1657 };
1658
1659 /* Clock ON depends on external parent clock, so don't poll */
1660 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1661         .halt_check = BRANCH_HALT_DELAY,
1662         .clkr = {
1663                 .enable_reg = 0x52000,
1664                 .enable_mask = BIT(16),
1665                 .hw.init = &(struct clk_init_data){
1666                         .name = "gcc_gpu_gpll0_div_clk_src",
1667                         .parent_data = &(const struct clk_parent_data){
1668                                 .hw = &gcc_gpll0_out_even.clkr.hw,
1669                         },
1670                         .num_parents = 1,
1671                         .flags = CLK_SET_RATE_PARENT,
1672                         .ops = &clk_branch2_ops,
1673                 },
1674         },
1675 };
1676
1677 static struct clk_branch gcc_gpu_iref_en = {
1678         .halt_reg = 0x8c014,
1679         .halt_check = BRANCH_HALT,
1680         .clkr = {
1681                 .enable_reg = 0x8c014,
1682                 .enable_mask = BIT(0),
1683                 .hw.init = &(struct clk_init_data){
1684                         .name = "gcc_gpu_iref_en",
1685                         .ops = &clk_branch2_ops,
1686                 },
1687         },
1688 };
1689
1690 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1691         .halt_reg = 0x7100c,
1692         .halt_check = BRANCH_HALT_VOTED,
1693         .hwcg_reg = 0x7100c,
1694         .hwcg_bit = 1,
1695         .clkr = {
1696                 .enable_reg = 0x7100c,
1697                 .enable_mask = BIT(0),
1698                 .hw.init = &(struct clk_init_data){
1699                         .name = "gcc_gpu_memnoc_gfx_clk",
1700                         .ops = &clk_branch2_aon_ops,
1701                 },
1702         },
1703 };
1704
1705 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1706         .halt_reg = 0x71018,
1707         .halt_check = BRANCH_HALT,
1708         .clkr = {
1709                 .enable_reg = 0x71018,
1710                 .enable_mask = BIT(0),
1711                 .hw.init = &(struct clk_init_data){
1712                         .name = "gcc_gpu_snoc_dvm_gfx_clk",
1713                         .ops = &clk_branch2_aon_ops,
1714                 },
1715         },
1716 };
1717
1718 static struct clk_branch gcc_pcie0_phy_rchng_clk = {
1719         .halt_reg = 0x6b038,
1720         .halt_check = BRANCH_HALT_VOTED,
1721         .clkr = {
1722                 .enable_reg = 0x52000,
1723                 .enable_mask = BIT(22),
1724                 .hw.init = &(struct clk_init_data){
1725                         .name = "gcc_pcie0_phy_rchng_clk",
1726                         .parent_data = &(const struct clk_parent_data){
1727                                 .hw = &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
1728                         },
1729                         .num_parents = 1,
1730                         .flags = CLK_SET_RATE_PARENT,
1731                         .ops = &clk_branch2_ops,
1732                 },
1733         },
1734 };
1735
1736 static struct clk_branch gcc_pcie1_phy_rchng_clk = {
1737         .halt_reg = 0x8d038,
1738         .halt_check = BRANCH_HALT_VOTED,
1739         .clkr = {
1740                 .enable_reg = 0x52000,
1741                 .enable_mask = BIT(23),
1742                 .hw.init = &(struct clk_init_data){
1743                         .name = "gcc_pcie1_phy_rchng_clk",
1744                         .parent_data = &(const struct clk_parent_data){
1745                                 .hw = &gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
1746                         },
1747                         .num_parents = 1,
1748                         .flags = CLK_SET_RATE_PARENT,
1749                         .ops = &clk_branch2_ops,
1750                 },
1751         },
1752 };
1753
1754 static struct clk_branch gcc_pcie_0_aux_clk = {
1755         .halt_reg = 0x6b028,
1756         .halt_check = BRANCH_HALT_VOTED,
1757         .clkr = {
1758                 .enable_reg = 0x52008,
1759                 .enable_mask = BIT(3),
1760                 .hw.init = &(struct clk_init_data){
1761                         .name = "gcc_pcie_0_aux_clk",
1762                         .parent_data = &(const struct clk_parent_data){
1763                                 .hw = &gcc_pcie_0_aux_clk_src.clkr.hw,
1764                         },
1765                         .num_parents = 1,
1766                         .flags = CLK_SET_RATE_PARENT,
1767                         .ops = &clk_branch2_ops,
1768                 },
1769         },
1770 };
1771
1772 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1773         .halt_reg = 0x6b024,
1774         .halt_check = BRANCH_HALT_VOTED,
1775         .hwcg_reg = 0x6b024,
1776         .hwcg_bit = 1,
1777         .clkr = {
1778                 .enable_reg = 0x52008,
1779                 .enable_mask = BIT(2),
1780                 .hw.init = &(struct clk_init_data){
1781                         .name = "gcc_pcie_0_cfg_ahb_clk",
1782                         .ops = &clk_branch2_ops,
1783                 },
1784         },
1785 };
1786
1787 static struct clk_branch gcc_pcie_0_clkref_en = {
1788         .halt_reg = 0x8c004,
1789         .halt_check = BRANCH_HALT,
1790         .clkr = {
1791                 .enable_reg = 0x8c004,
1792                 .enable_mask = BIT(0),
1793                 .hw.init = &(struct clk_init_data){
1794                         .name = "gcc_pcie_0_clkref_en",
1795                         .ops = &clk_branch2_ops,
1796                 },
1797         },
1798 };
1799
1800 /* external clocks so add BRANCH_HALT_SKIP */
1801 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1802         .halt_reg = 0x6b01c,
1803         .halt_check = BRANCH_HALT_SKIP,
1804         .hwcg_reg = 0x6b01c,
1805         .hwcg_bit = 1,
1806         .clkr = {
1807                 .enable_reg = 0x52008,
1808                 .enable_mask = BIT(1),
1809                 .hw.init = &(struct clk_init_data){
1810                         .name = "gcc_pcie_0_mstr_axi_clk",
1811                         .ops = &clk_branch2_ops,
1812                 },
1813         },
1814 };
1815
1816 /* external clocks so add BRANCH_HALT_SKIP */
1817 static struct clk_branch gcc_pcie_0_pipe_clk = {
1818         .halt_reg = 0x6b030,
1819         .halt_check = BRANCH_HALT_SKIP,
1820         .clkr = {
1821                 .enable_reg = 0x52008,
1822                 .enable_mask = BIT(4),
1823                 .hw.init = &(struct clk_init_data){
1824                         .name = "gcc_pcie_0_pipe_clk",
1825                         .parent_data = &(const struct clk_parent_data){
1826                                 .hw = &gcc_pcie_0_pipe_clk_src.clkr.hw,
1827                         },
1828                         .num_parents = 1,
1829                         .flags = CLK_SET_RATE_PARENT,
1830                         .ops = &clk_branch2_ops,
1831                 },
1832         },
1833 };
1834
1835 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1836         .halt_reg = 0x6b014,
1837         .halt_check = BRANCH_HALT_VOTED,
1838         .hwcg_reg = 0x6b014,
1839         .hwcg_bit = 1,
1840         .clkr = {
1841                 .enable_reg = 0x52008,
1842                 .enable_mask = BIT(0),
1843                 .hw.init = &(struct clk_init_data){
1844                         .name = "gcc_pcie_0_slv_axi_clk",
1845                         .ops = &clk_branch2_ops,
1846                 },
1847         },
1848 };
1849
1850 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1851         .halt_reg = 0x6b010,
1852         .halt_check = BRANCH_HALT_VOTED,
1853         .clkr = {
1854                 .enable_reg = 0x52008,
1855                 .enable_mask = BIT(5),
1856                 .hw.init = &(struct clk_init_data){
1857                         .name = "gcc_pcie_0_slv_q2a_axi_clk",
1858                         .ops = &clk_branch2_ops,
1859                 },
1860         },
1861 };
1862
1863 static struct clk_branch gcc_pcie_1_aux_clk = {
1864         .halt_reg = 0x8d028,
1865         .halt_check = BRANCH_HALT_VOTED,
1866         .clkr = {
1867                 .enable_reg = 0x52000,
1868                 .enable_mask = BIT(29),
1869                 .hw.init = &(struct clk_init_data){
1870                         .name = "gcc_pcie_1_aux_clk",
1871                         .parent_data = &(const struct clk_parent_data){
1872                                 .hw = &gcc_pcie_1_aux_clk_src.clkr.hw,
1873                         },
1874                         .num_parents = 1,
1875                         .flags = CLK_SET_RATE_PARENT,
1876                         .ops = &clk_branch2_ops,
1877                 },
1878         },
1879 };
1880
1881 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1882         .halt_reg = 0x8d024,
1883         .halt_check = BRANCH_HALT_VOTED,
1884         .hwcg_reg = 0x8d024,
1885         .hwcg_bit = 1,
1886         .clkr = {
1887                 .enable_reg = 0x52000,
1888                 .enable_mask = BIT(28),
1889                 .hw.init = &(struct clk_init_data){
1890                         .name = "gcc_pcie_1_cfg_ahb_clk",
1891                         .ops = &clk_branch2_ops,
1892                 },
1893         },
1894 };
1895
1896 static struct clk_branch gcc_pcie_1_clkref_en = {
1897         .halt_reg = 0x8c008,
1898         .halt_check = BRANCH_HALT,
1899         .clkr = {
1900                 .enable_reg = 0x8c008,
1901                 .enable_mask = BIT(0),
1902                 .hw.init = &(struct clk_init_data){
1903                         .name = "gcc_pcie_1_clkref_en",
1904                         .ops = &clk_branch2_ops,
1905                 },
1906         },
1907 };
1908
1909 /* external clocks so add BRANCH_HALT_SKIP */
1910 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1911         .halt_reg = 0x8d01c,
1912         .halt_check = BRANCH_HALT_SKIP,
1913         .hwcg_reg = 0x8d01c,
1914         .hwcg_bit = 1,
1915         .clkr = {
1916                 .enable_reg = 0x52000,
1917                 .enable_mask = BIT(27),
1918                 .hw.init = &(struct clk_init_data){
1919                         .name = "gcc_pcie_1_mstr_axi_clk",
1920                         .ops = &clk_branch2_ops,
1921                 },
1922         },
1923 };
1924
1925 /* external clocks so add BRANCH_HALT_SKIP */
1926 static struct clk_branch gcc_pcie_1_pipe_clk = {
1927         .halt_reg = 0x8d030,
1928         .halt_check = BRANCH_HALT_SKIP,
1929         .clkr = {
1930                 .enable_reg = 0x52000,
1931                 .enable_mask = BIT(30),
1932                 .hw.init = &(struct clk_init_data){
1933                         .name = "gcc_pcie_1_pipe_clk",
1934                         .parent_data = &(const struct clk_parent_data){
1935                                 .hw = &gcc_pcie_1_pipe_clk_src.clkr.hw,
1936                         },
1937                         .num_parents = 1,
1938                         .flags = CLK_SET_RATE_PARENT,
1939                         .ops = &clk_branch2_ops,
1940                 },
1941         },
1942 };
1943
1944 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1945         .halt_reg = 0x8d014,
1946         .halt_check = BRANCH_HALT_VOTED,
1947         .hwcg_reg = 0x8d014,
1948         .hwcg_bit = 1,
1949         .clkr = {
1950                 .enable_reg = 0x52000,
1951                 .enable_mask = BIT(26),
1952                 .hw.init = &(struct clk_init_data){
1953                         .name = "gcc_pcie_1_slv_axi_clk",
1954                         .ops = &clk_branch2_ops,
1955                 },
1956         },
1957 };
1958
1959 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1960         .halt_reg = 0x8d010,
1961         .halt_check = BRANCH_HALT_VOTED,
1962         .clkr = {
1963                 .enable_reg = 0x52000,
1964                 .enable_mask = BIT(25),
1965                 .hw.init = &(struct clk_init_data){
1966                         .name = "gcc_pcie_1_slv_q2a_axi_clk",
1967                         .ops = &clk_branch2_ops,
1968                 },
1969         },
1970 };
1971
1972 static struct clk_branch gcc_pdm2_clk = {
1973         .halt_reg = 0x3300c,
1974         .halt_check = BRANCH_HALT,
1975         .clkr = {
1976                 .enable_reg = 0x3300c,
1977                 .enable_mask = BIT(0),
1978                 .hw.init = &(struct clk_init_data){
1979                         .name = "gcc_pdm2_clk",
1980                         .parent_data = &(const struct clk_parent_data){
1981                                 .hw = &gcc_pdm2_clk_src.clkr.hw,
1982                         },
1983                         .num_parents = 1,
1984                         .flags = CLK_SET_RATE_PARENT,
1985                         .ops = &clk_branch2_ops,
1986                 },
1987         },
1988 };
1989
1990 static struct clk_branch gcc_pdm_ahb_clk = {
1991         .halt_reg = 0x33004,
1992         .halt_check = BRANCH_HALT_VOTED,
1993         .hwcg_reg = 0x33004,
1994         .hwcg_bit = 1,
1995         .clkr = {
1996                 .enable_reg = 0x33004,
1997                 .enable_mask = BIT(0),
1998                 .hw.init = &(struct clk_init_data){
1999                         .name = "gcc_pdm_ahb_clk",
2000                         .ops = &clk_branch2_ops,
2001                 },
2002         },
2003 };
2004
2005 static struct clk_branch gcc_pdm_xo4_clk = {
2006         .halt_reg = 0x33008,
2007         .halt_check = BRANCH_HALT,
2008         .clkr = {
2009                 .enable_reg = 0x33008,
2010                 .enable_mask = BIT(0),
2011                 .hw.init = &(struct clk_init_data){
2012                         .name = "gcc_pdm_xo4_clk",
2013                         .ops = &clk_branch2_ops,
2014                 },
2015         },
2016 };
2017
2018 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2019         .halt_reg = 0x26008,
2020         .halt_check = BRANCH_HALT_VOTED,
2021         .hwcg_reg = 0x26008,
2022         .hwcg_bit = 1,
2023         .clkr = {
2024                 .enable_reg = 0x26008,
2025                 .enable_mask = BIT(0),
2026                 .hw.init = &(struct clk_init_data){
2027                         .name = "gcc_qmip_camera_nrt_ahb_clk",
2028                         .ops = &clk_branch2_ops,
2029                 },
2030         },
2031 };
2032
2033 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2034         .halt_reg = 0x2600c,
2035         .halt_check = BRANCH_HALT_VOTED,
2036         .hwcg_reg = 0x2600c,
2037         .hwcg_bit = 1,
2038         .clkr = {
2039                 .enable_reg = 0x2600c,
2040                 .enable_mask = BIT(0),
2041                 .hw.init = &(struct clk_init_data){
2042                         .name = "gcc_qmip_camera_rt_ahb_clk",
2043                         .ops = &clk_branch2_ops,
2044                 },
2045         },
2046 };
2047
2048 static struct clk_branch gcc_qmip_disp_ahb_clk = {
2049         .halt_reg = 0x27008,
2050         .halt_check = BRANCH_HALT_VOTED,
2051         .hwcg_reg = 0x27008,
2052         .hwcg_bit = 1,
2053         .clkr = {
2054                 .enable_reg = 0x27008,
2055                 .enable_mask = BIT(0),
2056                 .hw.init = &(struct clk_init_data){
2057                         .name = "gcc_qmip_disp_ahb_clk",
2058                         .ops = &clk_branch2_ops,
2059                 },
2060         },
2061 };
2062
2063 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
2064         .halt_reg = 0x28008,
2065         .halt_check = BRANCH_HALT_VOTED,
2066         .hwcg_reg = 0x28008,
2067         .hwcg_bit = 1,
2068         .clkr = {
2069                 .enable_reg = 0x28008,
2070                 .enable_mask = BIT(0),
2071                 .hw.init = &(struct clk_init_data){
2072                         .name = "gcc_qmip_video_cvp_ahb_clk",
2073                         .ops = &clk_branch2_ops,
2074                 },
2075         },
2076 };
2077
2078 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2079         .halt_reg = 0x2800c,
2080         .halt_check = BRANCH_HALT_VOTED,
2081         .hwcg_reg = 0x2800c,
2082         .hwcg_bit = 1,
2083         .clkr = {
2084                 .enable_reg = 0x2800c,
2085                 .enable_mask = BIT(0),
2086                 .hw.init = &(struct clk_init_data){
2087                         .name = "gcc_qmip_video_vcodec_ahb_clk",
2088                         .ops = &clk_branch2_ops,
2089                 },
2090         },
2091 };
2092
2093 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2094         .halt_reg = 0x23008,
2095         .halt_check = BRANCH_HALT_VOTED,
2096         .clkr = {
2097                 .enable_reg = 0x52008,
2098                 .enable_mask = BIT(9),
2099                 .hw.init = &(struct clk_init_data){
2100                         .name = "gcc_qupv3_wrap0_core_2x_clk",
2101                         .ops = &clk_branch2_ops,
2102                 },
2103         },
2104 };
2105
2106 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2107         .halt_reg = 0x23000,
2108         .halt_check = BRANCH_HALT_VOTED,
2109         .clkr = {
2110                 .enable_reg = 0x52008,
2111                 .enable_mask = BIT(8),
2112                 .hw.init = &(struct clk_init_data){
2113                         .name = "gcc_qupv3_wrap0_core_clk",
2114                         .ops = &clk_branch2_ops,
2115                 },
2116         },
2117 };
2118
2119 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2120         .halt_reg = 0x1700c,
2121         .halt_check = BRANCH_HALT_VOTED,
2122         .clkr = {
2123                 .enable_reg = 0x52008,
2124                 .enable_mask = BIT(10),
2125                 .hw.init = &(struct clk_init_data){
2126                         .name = "gcc_qupv3_wrap0_s0_clk",
2127                         .parent_data = &(const struct clk_parent_data){
2128                                 .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2129                         },
2130                         .num_parents = 1,
2131                         .flags = CLK_SET_RATE_PARENT,
2132                         .ops = &clk_branch2_ops,
2133                 },
2134         },
2135 };
2136
2137 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2138         .halt_reg = 0x1713c,
2139         .halt_check = BRANCH_HALT_VOTED,
2140         .clkr = {
2141                 .enable_reg = 0x52008,
2142                 .enable_mask = BIT(11),
2143                 .hw.init = &(struct clk_init_data){
2144                         .name = "gcc_qupv3_wrap0_s1_clk",
2145                         .parent_data = &(const struct clk_parent_data){
2146                                 .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2147                         },
2148                         .num_parents = 1,
2149                         .flags = CLK_SET_RATE_PARENT,
2150                         .ops = &clk_branch2_ops,
2151                 },
2152         },
2153 };
2154
2155 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2156         .halt_reg = 0x1726c,
2157         .halt_check = BRANCH_HALT_VOTED,
2158         .clkr = {
2159                 .enable_reg = 0x52008,
2160                 .enable_mask = BIT(12),
2161                 .hw.init = &(struct clk_init_data){
2162                         .name = "gcc_qupv3_wrap0_s2_clk",
2163                         .parent_data = &(const struct clk_parent_data){
2164                                 .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2165                         },
2166                         .num_parents = 1,
2167                         .flags = CLK_SET_RATE_PARENT,
2168                         .ops = &clk_branch2_ops,
2169                 },
2170         },
2171 };
2172
2173 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2174         .halt_reg = 0x1739c,
2175         .halt_check = BRANCH_HALT_VOTED,
2176         .clkr = {
2177                 .enable_reg = 0x52008,
2178                 .enable_mask = BIT(13),
2179                 .hw.init = &(struct clk_init_data){
2180                         .name = "gcc_qupv3_wrap0_s3_clk",
2181                         .parent_data = &(const struct clk_parent_data){
2182                                 .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2183                         },
2184                         .num_parents = 1,
2185                         .flags = CLK_SET_RATE_PARENT,
2186                         .ops = &clk_branch2_ops,
2187                 },
2188         },
2189 };
2190
2191 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2192         .halt_reg = 0x174cc,
2193         .halt_check = BRANCH_HALT_VOTED,
2194         .clkr = {
2195                 .enable_reg = 0x52008,
2196                 .enable_mask = BIT(14),
2197                 .hw.init = &(struct clk_init_data){
2198                         .name = "gcc_qupv3_wrap0_s4_clk",
2199                         .parent_data = &(const struct clk_parent_data){
2200                                 .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2201                         },
2202                         .num_parents = 1,
2203                         .flags = CLK_SET_RATE_PARENT,
2204                         .ops = &clk_branch2_ops,
2205                 },
2206         },
2207 };
2208
2209 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2210         .halt_reg = 0x175fc,
2211         .halt_check = BRANCH_HALT_VOTED,
2212         .clkr = {
2213                 .enable_reg = 0x52008,
2214                 .enable_mask = BIT(15),
2215                 .hw.init = &(struct clk_init_data){
2216                         .name = "gcc_qupv3_wrap0_s5_clk",
2217                         .parent_data = &(const struct clk_parent_data){
2218                                 .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2219                         },
2220                         .num_parents = 1,
2221                         .flags = CLK_SET_RATE_PARENT,
2222                         .ops = &clk_branch2_ops,
2223                 },
2224         },
2225 };
2226
2227 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2228         .halt_reg = 0x1772c,
2229         .halt_check = BRANCH_HALT_VOTED,
2230         .clkr = {
2231                 .enable_reg = 0x52008,
2232                 .enable_mask = BIT(16),
2233                 .hw.init = &(struct clk_init_data){
2234                         .name = "gcc_qupv3_wrap0_s6_clk",
2235                         .parent_data = &(const struct clk_parent_data){
2236                                 .hw = &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
2237                         },
2238                         .num_parents = 1,
2239                         .flags = CLK_SET_RATE_PARENT,
2240                         .ops = &clk_branch2_ops,
2241                 },
2242         },
2243 };
2244
2245 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2246         .halt_reg = 0x1785c,
2247         .halt_check = BRANCH_HALT_VOTED,
2248         .clkr = {
2249                 .enable_reg = 0x52008,
2250                 .enable_mask = BIT(17),
2251                 .hw.init = &(struct clk_init_data){
2252                         .name = "gcc_qupv3_wrap0_s7_clk",
2253                         .parent_data = &(const struct clk_parent_data){
2254                                 .hw = &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
2255                         },
2256                         .num_parents = 1,
2257                         .flags = CLK_SET_RATE_PARENT,
2258                         .ops = &clk_branch2_ops,
2259                 },
2260         },
2261 };
2262
2263 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
2264         .halt_reg = 0x23140,
2265         .halt_check = BRANCH_HALT_VOTED,
2266         .clkr = {
2267                 .enable_reg = 0x52008,
2268                 .enable_mask = BIT(18),
2269                 .hw.init = &(struct clk_init_data){
2270                         .name = "gcc_qupv3_wrap1_core_2x_clk",
2271                         .ops = &clk_branch2_ops,
2272                 },
2273         },
2274 };
2275
2276 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
2277         .halt_reg = 0x23138,
2278         .halt_check = BRANCH_HALT_VOTED,
2279         .clkr = {
2280                 .enable_reg = 0x52008,
2281                 .enable_mask = BIT(19),
2282                 .hw.init = &(struct clk_init_data){
2283                         .name = "gcc_qupv3_wrap1_core_clk",
2284                         .ops = &clk_branch2_ops,
2285                 },
2286         },
2287 };
2288
2289 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2290         .halt_reg = 0x18004,
2291         .halt_check = BRANCH_HALT_VOTED,
2292         .hwcg_reg = 0x18004,
2293         .hwcg_bit = 1,
2294         .clkr = {
2295                 .enable_reg = 0x52008,
2296                 .enable_mask = BIT(20),
2297                 .hw.init = &(struct clk_init_data){
2298                         .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2299                         .ops = &clk_branch2_ops,
2300                 },
2301         },
2302 };
2303
2304 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2305         .halt_reg = 0x18008,
2306         .halt_check = BRANCH_HALT_VOTED,
2307         .hwcg_reg = 0x18008,
2308         .hwcg_bit = 1,
2309         .clkr = {
2310                 .enable_reg = 0x52008,
2311                 .enable_mask = BIT(21),
2312                 .hw.init = &(struct clk_init_data){
2313                         .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2314                         .ops = &clk_branch2_ops,
2315                 },
2316         },
2317 };
2318
2319 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2320         .halt_reg = 0x1800c,
2321         .halt_check = BRANCH_HALT_VOTED,
2322         .clkr = {
2323                 .enable_reg = 0x52008,
2324                 .enable_mask = BIT(22),
2325                 .hw.init = &(struct clk_init_data){
2326                         .name = "gcc_qupv3_wrap1_s0_clk",
2327                         .parent_data = &(const struct clk_parent_data){
2328                                 .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2329                         },
2330                         .num_parents = 1,
2331                         .flags = CLK_SET_RATE_PARENT,
2332                         .ops = &clk_branch2_ops,
2333                 },
2334         },
2335 };
2336
2337 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2338         .halt_reg = 0x1813c,
2339         .halt_check = BRANCH_HALT_VOTED,
2340         .clkr = {
2341                 .enable_reg = 0x52008,
2342                 .enable_mask = BIT(23),
2343                 .hw.init = &(struct clk_init_data){
2344                         .name = "gcc_qupv3_wrap1_s1_clk",
2345                         .parent_data = &(const struct clk_parent_data){
2346                                 .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2347                         },
2348                         .num_parents = 1,
2349                         .flags = CLK_SET_RATE_PARENT,
2350                         .ops = &clk_branch2_ops,
2351                 },
2352         },
2353 };
2354
2355 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2356         .halt_reg = 0x1826c,
2357         .halt_check = BRANCH_HALT_VOTED,
2358         .clkr = {
2359                 .enable_reg = 0x52008,
2360                 .enable_mask = BIT(24),
2361                 .hw.init = &(struct clk_init_data){
2362                         .name = "gcc_qupv3_wrap1_s2_clk",
2363                         .parent_data = &(const struct clk_parent_data){
2364                                 .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2365                         },
2366                         .num_parents = 1,
2367                         .flags = CLK_SET_RATE_PARENT,
2368                         .ops = &clk_branch2_ops,
2369                 },
2370         },
2371 };
2372
2373 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2374         .halt_reg = 0x1839c,
2375         .halt_check = BRANCH_HALT_VOTED,
2376         .clkr = {
2377                 .enable_reg = 0x52008,
2378                 .enable_mask = BIT(25),
2379                 .hw.init = &(struct clk_init_data){
2380                         .name = "gcc_qupv3_wrap1_s3_clk",
2381                         .parent_data = &(const struct clk_parent_data){
2382                                 .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2383                         },
2384                         .num_parents = 1,
2385                         .flags = CLK_SET_RATE_PARENT,
2386                         .ops = &clk_branch2_ops,
2387                 },
2388         },
2389 };
2390
2391 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2392         .halt_reg = 0x184cc,
2393         .halt_check = BRANCH_HALT_VOTED,
2394         .clkr = {
2395                 .enable_reg = 0x52008,
2396                 .enable_mask = BIT(26),
2397                 .hw.init = &(struct clk_init_data){
2398                         .name = "gcc_qupv3_wrap1_s4_clk",
2399                         .parent_data = &(const struct clk_parent_data){
2400                                 .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2401                         },
2402                         .num_parents = 1,
2403                         .flags = CLK_SET_RATE_PARENT,
2404                         .ops = &clk_branch2_ops,
2405                 },
2406         },
2407 };
2408
2409 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2410         .halt_reg = 0x185fc,
2411         .halt_check = BRANCH_HALT_VOTED,
2412         .clkr = {
2413                 .enable_reg = 0x52008,
2414                 .enable_mask = BIT(27),
2415                 .hw.init = &(struct clk_init_data){
2416                         .name = "gcc_qupv3_wrap1_s5_clk",
2417                         .parent_data = &(const struct clk_parent_data){
2418                                 .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2419                         },
2420                         .num_parents = 1,
2421                         .flags = CLK_SET_RATE_PARENT,
2422                         .ops = &clk_branch2_ops,
2423                 },
2424         },
2425 };
2426
2427 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
2428         .halt_reg = 0x23278,
2429         .halt_check = BRANCH_HALT_VOTED,
2430         .clkr = {
2431                 .enable_reg = 0x52010,
2432                 .enable_mask = BIT(3),
2433                 .hw.init = &(struct clk_init_data){
2434                         .name = "gcc_qupv3_wrap2_core_2x_clk",
2435                         .ops = &clk_branch2_ops,
2436                 },
2437         },
2438 };
2439
2440 static struct clk_branch gcc_qupv3_wrap2_core_clk = {
2441         .halt_reg = 0x23270,
2442         .halt_check = BRANCH_HALT_VOTED,
2443         .clkr = {
2444                 .enable_reg = 0x52010,
2445                 .enable_mask = BIT(0),
2446                 .hw.init = &(struct clk_init_data){
2447                         .name = "gcc_qupv3_wrap2_core_clk",
2448                         .ops = &clk_branch2_ops,
2449                 },
2450         },
2451 };
2452
2453 static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2454         .halt_reg = 0x1e00c,
2455         .halt_check = BRANCH_HALT_VOTED,
2456         .clkr = {
2457                 .enable_reg = 0x52010,
2458                 .enable_mask = BIT(4),
2459                 .hw.init = &(struct clk_init_data){
2460                         .name = "gcc_qupv3_wrap2_s0_clk",
2461                         .parent_data = &(const struct clk_parent_data){
2462                                 .hw = &gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
2463                         },
2464                         .num_parents = 1,
2465                         .flags = CLK_SET_RATE_PARENT,
2466                         .ops = &clk_branch2_ops,
2467                 },
2468         },
2469 };
2470
2471 static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2472         .halt_reg = 0x1e13c,
2473         .halt_check = BRANCH_HALT_VOTED,
2474         .clkr = {
2475                 .enable_reg = 0x52010,
2476                 .enable_mask = BIT(5),
2477                 .hw.init = &(struct clk_init_data){
2478                         .name = "gcc_qupv3_wrap2_s1_clk",
2479                         .parent_data = &(const struct clk_parent_data){
2480                                 .hw = &gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
2481                         },
2482                         .num_parents = 1,
2483                         .flags = CLK_SET_RATE_PARENT,
2484                         .ops = &clk_branch2_ops,
2485                 },
2486         },
2487 };
2488
2489 static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2490         .halt_reg = 0x1e26c,
2491         .halt_check = BRANCH_HALT_VOTED,
2492         .clkr = {
2493                 .enable_reg = 0x52010,
2494                 .enable_mask = BIT(6),
2495                 .hw.init = &(struct clk_init_data){
2496                         .name = "gcc_qupv3_wrap2_s2_clk",
2497                         .parent_data = &(const struct clk_parent_data){
2498                                 .hw = &gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
2499                         },
2500                         .num_parents = 1,
2501                         .flags = CLK_SET_RATE_PARENT,
2502                         .ops = &clk_branch2_ops,
2503                 },
2504         },
2505 };
2506
2507 static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2508         .halt_reg = 0x1e39c,
2509         .halt_check = BRANCH_HALT_VOTED,
2510         .clkr = {
2511                 .enable_reg = 0x52010,
2512                 .enable_mask = BIT(7),
2513                 .hw.init = &(struct clk_init_data){
2514                         .name = "gcc_qupv3_wrap2_s3_clk",
2515                         .parent_data = &(const struct clk_parent_data){
2516                                 .hw = &gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
2517                         },
2518                         .num_parents = 1,
2519                         .flags = CLK_SET_RATE_PARENT,
2520                         .ops = &clk_branch2_ops,
2521                 },
2522         },
2523 };
2524
2525 static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2526         .halt_reg = 0x1e4cc,
2527         .halt_check = BRANCH_HALT_VOTED,
2528         .clkr = {
2529                 .enable_reg = 0x52010,
2530                 .enable_mask = BIT(8),
2531                 .hw.init = &(struct clk_init_data){
2532                         .name = "gcc_qupv3_wrap2_s4_clk",
2533                         .parent_data = &(const struct clk_parent_data){
2534                                 .hw = &gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
2535                         },
2536                         .num_parents = 1,
2537                         .flags = CLK_SET_RATE_PARENT,
2538                         .ops = &clk_branch2_ops,
2539                 },
2540         },
2541 };
2542
2543 static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2544         .halt_reg = 0x1e5fc,
2545         .halt_check = BRANCH_HALT_VOTED,
2546         .clkr = {
2547                 .enable_reg = 0x52010,
2548                 .enable_mask = BIT(9),
2549                 .hw.init = &(struct clk_init_data){
2550                         .name = "gcc_qupv3_wrap2_s5_clk",
2551                         .parent_data = &(const struct clk_parent_data){
2552                                 .hw = &gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
2553                         },
2554                         .num_parents = 1,
2555                         .flags = CLK_SET_RATE_PARENT,
2556                         .ops = &clk_branch2_ops,
2557                 },
2558         },
2559 };
2560
2561 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2562         .halt_reg = 0x17004,
2563         .halt_check = BRANCH_HALT_VOTED,
2564         .hwcg_reg = 0x17004,
2565         .hwcg_bit = 1,
2566         .clkr = {
2567                 .enable_reg = 0x52008,
2568                 .enable_mask = BIT(6),
2569                 .hw.init = &(struct clk_init_data){
2570                         .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2571                         .ops = &clk_branch2_ops,
2572                 },
2573         },
2574 };
2575
2576 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2577         .halt_reg = 0x17008,
2578         .halt_check = BRANCH_HALT_VOTED,
2579         .hwcg_reg = 0x17008,
2580         .hwcg_bit = 1,
2581         .clkr = {
2582                 .enable_reg = 0x52008,
2583                 .enable_mask = BIT(7),
2584                 .hw.init = &(struct clk_init_data){
2585                         .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2586                         .ops = &clk_branch2_ops,
2587                 },
2588         },
2589 };
2590
2591 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
2592         .halt_reg = 0x1e004,
2593         .halt_check = BRANCH_HALT_VOTED,
2594         .hwcg_reg = 0x1e004,
2595         .hwcg_bit = 1,
2596         .clkr = {
2597                 .enable_reg = 0x52010,
2598                 .enable_mask = BIT(2),
2599                 .hw.init = &(struct clk_init_data){
2600                         .name = "gcc_qupv3_wrap_2_m_ahb_clk",
2601                         .ops = &clk_branch2_ops,
2602                 },
2603         },
2604 };
2605
2606 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
2607         .halt_reg = 0x1e008,
2608         .halt_check = BRANCH_HALT_VOTED,
2609         .hwcg_reg = 0x1e008,
2610         .hwcg_bit = 1,
2611         .clkr = {
2612                 .enable_reg = 0x52010,
2613                 .enable_mask = BIT(1),
2614                 .hw.init = &(struct clk_init_data){
2615                         .name = "gcc_qupv3_wrap_2_s_ahb_clk",
2616                         .ops = &clk_branch2_ops,
2617                 },
2618         },
2619 };
2620
2621 static struct clk_branch gcc_sdcc2_ahb_clk = {
2622         .halt_reg = 0x14008,
2623         .halt_check = BRANCH_HALT,
2624         .clkr = {
2625                 .enable_reg = 0x14008,
2626                 .enable_mask = BIT(0),
2627                 .hw.init = &(struct clk_init_data){
2628                         .name = "gcc_sdcc2_ahb_clk",
2629                         .ops = &clk_branch2_ops,
2630                 },
2631         },
2632 };
2633
2634 static struct clk_branch gcc_sdcc2_apps_clk = {
2635         .halt_reg = 0x14004,
2636         .halt_check = BRANCH_HALT,
2637         .clkr = {
2638                 .enable_reg = 0x14004,
2639                 .enable_mask = BIT(0),
2640                 .hw.init = &(struct clk_init_data){
2641                         .name = "gcc_sdcc2_apps_clk",
2642                         .parent_data = &(const struct clk_parent_data){
2643                                 .hw = &gcc_sdcc2_apps_clk_src.clkr.hw,
2644                         },
2645                         .num_parents = 1,
2646                         .flags = CLK_SET_RATE_PARENT,
2647                         .ops = &clk_branch2_ops,
2648                 },
2649         },
2650 };
2651
2652 static struct clk_branch gcc_sdcc4_ahb_clk = {
2653         .halt_reg = 0x16008,
2654         .halt_check = BRANCH_HALT,
2655         .clkr = {
2656                 .enable_reg = 0x16008,
2657                 .enable_mask = BIT(0),
2658                 .hw.init = &(struct clk_init_data){
2659                         .name = "gcc_sdcc4_ahb_clk",
2660                         .ops = &clk_branch2_ops,
2661                 },
2662         },
2663 };
2664
2665 static struct clk_branch gcc_sdcc4_apps_clk = {
2666         .halt_reg = 0x16004,
2667         .halt_check = BRANCH_HALT,
2668         .clkr = {
2669                 .enable_reg = 0x16004,
2670                 .enable_mask = BIT(0),
2671                 .hw.init = &(struct clk_init_data){
2672                         .name = "gcc_sdcc4_apps_clk",
2673                         .parent_data = &(const struct clk_parent_data){
2674                                 .hw = &gcc_sdcc4_apps_clk_src.clkr.hw,
2675                         },
2676                         .num_parents = 1,
2677                         .flags = CLK_SET_RATE_PARENT,
2678                         .ops = &clk_branch2_ops,
2679                 },
2680         },
2681 };
2682
2683 static struct clk_branch gcc_throttle_pcie_ahb_clk = {
2684         .halt_reg = 0x9044,
2685         .halt_check = BRANCH_HALT,
2686         .clkr = {
2687                 .enable_reg = 0x9044,
2688                 .enable_mask = BIT(0),
2689                 .hw.init = &(struct clk_init_data){
2690                         .name = "gcc_throttle_pcie_ahb_clk",
2691                         .ops = &clk_branch2_ops,
2692                 },
2693         },
2694 };
2695
2696 static struct clk_branch gcc_ufs_1_clkref_en = {
2697         .halt_reg = 0x8c000,
2698         .halt_check = BRANCH_HALT,
2699         .clkr = {
2700                 .enable_reg = 0x8c000,
2701                 .enable_mask = BIT(0),
2702                 .hw.init = &(struct clk_init_data){
2703                         .name = "gcc_ufs_1_clkref_en",
2704                         .ops = &clk_branch2_ops,
2705                 },
2706         },
2707 };
2708
2709 static struct clk_branch gcc_ufs_card_ahb_clk = {
2710         .halt_reg = 0x75018,
2711         .halt_check = BRANCH_HALT_VOTED,
2712         .hwcg_reg = 0x75018,
2713         .hwcg_bit = 1,
2714         .clkr = {
2715                 .enable_reg = 0x75018,
2716                 .enable_mask = BIT(0),
2717                 .hw.init = &(struct clk_init_data){
2718                         .name = "gcc_ufs_card_ahb_clk",
2719                         .ops = &clk_branch2_ops,
2720                 },
2721         },
2722 };
2723
2724 static struct clk_branch gcc_ufs_card_axi_clk = {
2725         .halt_reg = 0x75010,
2726         .halt_check = BRANCH_HALT_VOTED,
2727         .hwcg_reg = 0x75010,
2728         .hwcg_bit = 1,
2729         .clkr = {
2730                 .enable_reg = 0x75010,
2731                 .enable_mask = BIT(0),
2732                 .hw.init = &(struct clk_init_data){
2733                         .name = "gcc_ufs_card_axi_clk",
2734                         .parent_data = &(const struct clk_parent_data){
2735                                 .hw = &gcc_ufs_card_axi_clk_src.clkr.hw,
2736                         },
2737                         .num_parents = 1,
2738                         .flags = CLK_SET_RATE_PARENT,
2739                         .ops = &clk_branch2_ops,
2740                 },
2741         },
2742 };
2743
2744 static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
2745         .halt_reg = 0x75010,
2746         .halt_check = BRANCH_HALT_VOTED,
2747         .hwcg_reg = 0x75010,
2748         .hwcg_bit = 1,
2749         .clkr = {
2750                 .enable_reg = 0x75010,
2751                 .enable_mask = BIT(1),
2752                 .hw.init = &(struct clk_init_data){
2753                         .name = "gcc_ufs_card_axi_hw_ctl_clk",
2754                         .parent_data = &(const struct clk_parent_data){
2755                                 .hw = &gcc_ufs_card_axi_clk_src.clkr.hw,
2756                         },
2757                         .num_parents = 1,
2758                         .flags = CLK_SET_RATE_PARENT,
2759                         .ops = &clk_branch2_ops,
2760                 },
2761         },
2762 };
2763
2764 static struct clk_branch gcc_ufs_card_ice_core_clk = {
2765         .halt_reg = 0x75064,
2766         .halt_check = BRANCH_HALT_VOTED,
2767         .hwcg_reg = 0x75064,
2768         .hwcg_bit = 1,
2769         .clkr = {
2770                 .enable_reg = 0x75064,
2771                 .enable_mask = BIT(0),
2772                 .hw.init = &(struct clk_init_data){
2773                         .name = "gcc_ufs_card_ice_core_clk",
2774                         .parent_data = &(const struct clk_parent_data){
2775                                 .hw = &gcc_ufs_card_ice_core_clk_src.clkr.hw,
2776                         },
2777                         .num_parents = 1,
2778                         .flags = CLK_SET_RATE_PARENT,
2779                         .ops = &clk_branch2_ops,
2780                 },
2781         },
2782 };
2783
2784 static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
2785         .halt_reg = 0x75064,
2786         .halt_check = BRANCH_HALT_VOTED,
2787         .hwcg_reg = 0x75064,
2788         .hwcg_bit = 1,
2789         .clkr = {
2790                 .enable_reg = 0x75064,
2791                 .enable_mask = BIT(1),
2792                 .hw.init = &(struct clk_init_data){
2793                         .name = "gcc_ufs_card_ice_core_hw_ctl_clk",
2794                         .parent_data = &(const struct clk_parent_data){
2795                                 .hw = &gcc_ufs_card_ice_core_clk_src.clkr.hw,
2796                         },
2797                         .num_parents = 1,
2798                         .flags = CLK_SET_RATE_PARENT,
2799                         .ops = &clk_branch2_ops,
2800                 },
2801         },
2802 };
2803
2804 static struct clk_branch gcc_ufs_card_phy_aux_clk = {
2805         .halt_reg = 0x7509c,
2806         .halt_check = BRANCH_HALT_VOTED,
2807         .hwcg_reg = 0x7509c,
2808         .hwcg_bit = 1,
2809         .clkr = {
2810                 .enable_reg = 0x7509c,
2811                 .enable_mask = BIT(0),
2812                 .hw.init = &(struct clk_init_data){
2813                         .name = "gcc_ufs_card_phy_aux_clk",
2814                         .parent_data = &(const struct clk_parent_data){
2815                                 .hw = &gcc_ufs_card_phy_aux_clk_src.clkr.hw,
2816                         },
2817                         .num_parents = 1,
2818                         .flags = CLK_SET_RATE_PARENT,
2819                         .ops = &clk_branch2_ops,
2820                 },
2821         },
2822 };
2823
2824 static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
2825         .halt_reg = 0x7509c,
2826         .halt_check = BRANCH_HALT_VOTED,
2827         .hwcg_reg = 0x7509c,
2828         .hwcg_bit = 1,
2829         .clkr = {
2830                 .enable_reg = 0x7509c,
2831                 .enable_mask = BIT(1),
2832                 .hw.init = &(struct clk_init_data){
2833                         .name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
2834                         .parent_data = &(const struct clk_parent_data){
2835                                 .hw = &gcc_ufs_card_phy_aux_clk_src.clkr.hw,
2836                         },
2837                         .num_parents = 1,
2838                         .flags = CLK_SET_RATE_PARENT,
2839                         .ops = &clk_branch2_ops,
2840                 },
2841         },
2842 };
2843
2844 /* Clock ON depends on external parent clock, so don't poll */
2845 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
2846         .halt_reg = 0x75020,
2847         .halt_check = BRANCH_HALT_DELAY,
2848         .clkr = {
2849                 .enable_reg = 0x75020,
2850                 .enable_mask = BIT(0),
2851                 .hw.init = &(struct clk_init_data){
2852                         .name = "gcc_ufs_card_rx_symbol_0_clk",
2853                         .parent_data = &(const struct clk_parent_data){
2854                                 .hw = &gcc_ufs_card_rx_symbol_0_clk_src.clkr.hw,
2855                         },
2856                         .num_parents = 1,
2857                         .flags = CLK_SET_RATE_PARENT,
2858                         .ops = &clk_branch2_ops,
2859                 },
2860         },
2861 };
2862
2863 /* Clock ON depends on external parent clock, so don't poll */
2864 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
2865         .halt_reg = 0x750b8,
2866         .halt_check = BRANCH_HALT_DELAY,
2867         .clkr = {
2868                 .enable_reg = 0x750b8,
2869                 .enable_mask = BIT(0),
2870                 .hw.init = &(struct clk_init_data){
2871                         .name = "gcc_ufs_card_rx_symbol_1_clk",
2872                         .parent_data = &(const struct clk_parent_data){
2873                                 .hw = &gcc_ufs_card_rx_symbol_1_clk_src.clkr.hw,
2874                         },
2875                         .num_parents = 1,
2876                         .flags = CLK_SET_RATE_PARENT,
2877                         .ops = &clk_branch2_ops,
2878                 },
2879         },
2880 };
2881
2882 /* Clock ON depends on external parent clock, so don't poll */
2883 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
2884         .halt_reg = 0x7501c,
2885         .halt_check = BRANCH_HALT_DELAY,
2886         .clkr = {
2887                 .enable_reg = 0x7501c,
2888                 .enable_mask = BIT(0),
2889                 .hw.init = &(struct clk_init_data){
2890                         .name = "gcc_ufs_card_tx_symbol_0_clk",
2891                         .parent_data = &(const struct clk_parent_data){
2892                                 .hw = &gcc_ufs_card_tx_symbol_0_clk_src.clkr.hw,
2893                         },
2894                         .num_parents = 1,
2895                         .flags = CLK_SET_RATE_PARENT,
2896                         .ops = &clk_branch2_ops,
2897                 },
2898         },
2899 };
2900
2901 static struct clk_branch gcc_ufs_card_unipro_core_clk = {
2902         .halt_reg = 0x7505c,
2903         .halt_check = BRANCH_HALT_VOTED,
2904         .hwcg_reg = 0x7505c,
2905         .hwcg_bit = 1,
2906         .clkr = {
2907                 .enable_reg = 0x7505c,
2908                 .enable_mask = BIT(0),
2909                 .hw.init = &(struct clk_init_data){
2910                         .name = "gcc_ufs_card_unipro_core_clk",
2911                         .parent_data = &(const struct clk_parent_data){
2912                                 .hw = &gcc_ufs_card_unipro_core_clk_src.clkr.hw,
2913                         },
2914                         .num_parents = 1,
2915                         .flags = CLK_SET_RATE_PARENT,
2916                         .ops = &clk_branch2_ops,
2917                 },
2918         },
2919 };
2920
2921 static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
2922         .halt_reg = 0x7505c,
2923         .halt_check = BRANCH_HALT_VOTED,
2924         .hwcg_reg = 0x7505c,
2925         .hwcg_bit = 1,
2926         .clkr = {
2927                 .enable_reg = 0x7505c,
2928                 .enable_mask = BIT(1),
2929                 .hw.init = &(struct clk_init_data){
2930                         .name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
2931                         .parent_data = &(const struct clk_parent_data){
2932                                 .hw = &gcc_ufs_card_unipro_core_clk_src.clkr.hw,
2933                         },
2934                         .num_parents = 1,
2935                         .flags = CLK_SET_RATE_PARENT,
2936                         .ops = &clk_branch2_ops,
2937                 },
2938         },
2939 };
2940
2941 static struct clk_branch gcc_ufs_phy_ahb_clk = {
2942         .halt_reg = 0x77018,
2943         .halt_check = BRANCH_HALT_VOTED,
2944         .hwcg_reg = 0x77018,
2945         .hwcg_bit = 1,
2946         .clkr = {
2947                 .enable_reg = 0x77018,
2948                 .enable_mask = BIT(0),
2949                 .hw.init = &(struct clk_init_data){
2950                         .name = "gcc_ufs_phy_ahb_clk",
2951                         .ops = &clk_branch2_ops,
2952                 },
2953         },
2954 };
2955
2956 static struct clk_branch gcc_ufs_phy_axi_clk = {
2957         .halt_reg = 0x77010,
2958         .halt_check = BRANCH_HALT_VOTED,
2959         .hwcg_reg = 0x77010,
2960         .hwcg_bit = 1,
2961         .clkr = {
2962                 .enable_reg = 0x77010,
2963                 .enable_mask = BIT(0),
2964                 .hw.init = &(struct clk_init_data){
2965                         .name = "gcc_ufs_phy_axi_clk",
2966                         .parent_data = &(const struct clk_parent_data){
2967                                 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
2968                         },
2969                         .num_parents = 1,
2970                         .flags = CLK_SET_RATE_PARENT,
2971                         .ops = &clk_branch2_ops,
2972                 },
2973         },
2974 };
2975
2976 static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
2977         .halt_reg = 0x77010,
2978         .halt_check = BRANCH_HALT_VOTED,
2979         .hwcg_reg = 0x77010,
2980         .hwcg_bit = 1,
2981         .clkr = {
2982                 .enable_reg = 0x77010,
2983                 .enable_mask = BIT(1),
2984                 .hw.init = &(struct clk_init_data){
2985                         .name = "gcc_ufs_phy_axi_hw_ctl_clk",
2986                         .parent_data = &(const struct clk_parent_data){
2987                                 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
2988                         },
2989                         .num_parents = 1,
2990                         .flags = CLK_SET_RATE_PARENT,
2991                         .ops = &clk_branch2_ops,
2992                 },
2993         },
2994 };
2995
2996 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2997         .halt_reg = 0x77064,
2998         .halt_check = BRANCH_HALT_VOTED,
2999         .hwcg_reg = 0x77064,
3000         .hwcg_bit = 1,
3001         .clkr = {
3002                 .enable_reg = 0x77064,
3003                 .enable_mask = BIT(0),
3004                 .hw.init = &(struct clk_init_data){
3005                         .name = "gcc_ufs_phy_ice_core_clk",
3006                         .parent_data = &(const struct clk_parent_data){
3007                                 .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
3008                         },
3009                         .num_parents = 1,
3010                         .flags = CLK_SET_RATE_PARENT,
3011                         .ops = &clk_branch2_ops,
3012                 },
3013         },
3014 };
3015
3016 static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
3017         .halt_reg = 0x77064,
3018         .halt_check = BRANCH_HALT_VOTED,
3019         .hwcg_reg = 0x77064,
3020         .hwcg_bit = 1,
3021         .clkr = {
3022                 .enable_reg = 0x77064,
3023                 .enable_mask = BIT(1),
3024                 .hw.init = &(struct clk_init_data){
3025                         .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
3026                         .parent_data = &(const struct clk_parent_data){
3027                                 .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
3028                         },
3029                         .num_parents = 1,
3030                         .flags = CLK_SET_RATE_PARENT,
3031                         .ops = &clk_branch2_ops,
3032                 },
3033         },
3034 };
3035
3036 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
3037         .halt_reg = 0x7709c,
3038         .halt_check = BRANCH_HALT_VOTED,
3039         .hwcg_reg = 0x7709c,
3040         .hwcg_bit = 1,
3041         .clkr = {
3042                 .enable_reg = 0x7709c,
3043                 .enable_mask = BIT(0),
3044                 .hw.init = &(struct clk_init_data){
3045                         .name = "gcc_ufs_phy_phy_aux_clk",
3046                         .parent_data = &(const struct clk_parent_data){
3047                                 .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
3048                         },
3049                         .num_parents = 1,
3050                         .flags = CLK_SET_RATE_PARENT,
3051                         .ops = &clk_branch2_ops,
3052                 },
3053         },
3054 };
3055
3056 static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
3057         .halt_reg = 0x7709c,
3058         .halt_check = BRANCH_HALT_VOTED,
3059         .hwcg_reg = 0x7709c,
3060         .hwcg_bit = 1,
3061         .clkr = {
3062                 .enable_reg = 0x7709c,
3063                 .enable_mask = BIT(1),
3064                 .hw.init = &(struct clk_init_data){
3065                         .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
3066                         .parent_data = &(const struct clk_parent_data){
3067                                 .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
3068                         },
3069                         .num_parents = 1,
3070                         .flags = CLK_SET_RATE_PARENT,
3071                         .ops = &clk_branch2_ops,
3072                 },
3073         },
3074 };
3075
3076 /* Clock ON depends on external parent clock, so don't poll */
3077 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
3078         .halt_reg = 0x77020,
3079         .halt_check = BRANCH_HALT_DELAY,
3080         .clkr = {
3081                 .enable_reg = 0x77020,
3082                 .enable_mask = BIT(0),
3083                 .hw.init = &(struct clk_init_data){
3084                         .name = "gcc_ufs_phy_rx_symbol_0_clk",
3085                         .parent_data = &(const struct clk_parent_data){
3086                                 .hw = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
3087                         },
3088                         .num_parents = 1,
3089                         .flags = CLK_SET_RATE_PARENT,
3090                         .ops = &clk_branch2_ops,
3091                 },
3092         },
3093 };
3094
3095 /* Clock ON depends on external parent clock, so don't poll */
3096 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
3097         .halt_reg = 0x770b8,
3098         .halt_check = BRANCH_HALT_DELAY,
3099         .clkr = {
3100                 .enable_reg = 0x770b8,
3101                 .enable_mask = BIT(0),
3102                 .hw.init = &(struct clk_init_data){
3103                         .name = "gcc_ufs_phy_rx_symbol_1_clk",
3104                         .parent_data = &(const struct clk_parent_data){
3105                                 .hw = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
3106                         },
3107                         .num_parents = 1,
3108                         .flags = CLK_SET_RATE_PARENT,
3109                         .ops = &clk_branch2_ops,
3110                 },
3111         },
3112 };
3113
3114 /* Clock ON depends on external parent clock, so don't poll */
3115 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
3116         .halt_reg = 0x7701c,
3117         .halt_check = BRANCH_HALT_DELAY,
3118         .clkr = {
3119                 .enable_reg = 0x7701c,
3120                 .enable_mask = BIT(0),
3121                 .hw.init = &(struct clk_init_data){
3122                         .name = "gcc_ufs_phy_tx_symbol_0_clk",
3123                         .parent_data = &(const struct clk_parent_data){
3124                                 .hw = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
3125                         },
3126                         .num_parents = 1,
3127                         .flags = CLK_SET_RATE_PARENT,
3128                         .ops = &clk_branch2_ops,
3129                 },
3130         },
3131 };
3132
3133 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
3134         .halt_reg = 0x7705c,
3135         .halt_check = BRANCH_HALT_VOTED,
3136         .hwcg_reg = 0x7705c,
3137         .hwcg_bit = 1,
3138         .clkr = {
3139                 .enable_reg = 0x7705c,
3140                 .enable_mask = BIT(0),
3141                 .hw.init = &(struct clk_init_data){
3142                         .name = "gcc_ufs_phy_unipro_core_clk",
3143                         .parent_data = &(const struct clk_parent_data){
3144                                 .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
3145                         },
3146                         .num_parents = 1,
3147                         .flags = CLK_SET_RATE_PARENT,
3148                         .ops = &clk_branch2_ops,
3149                 },
3150         },
3151 };
3152
3153 static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
3154         .halt_reg = 0x7705c,
3155         .halt_check = BRANCH_HALT_VOTED,
3156         .hwcg_reg = 0x7705c,
3157         .hwcg_bit = 1,
3158         .clkr = {
3159                 .enable_reg = 0x7705c,
3160                 .enable_mask = BIT(1),
3161                 .hw.init = &(struct clk_init_data){
3162                         .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
3163                         .parent_data = &(const struct clk_parent_data){
3164                                 .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
3165                         },
3166                         .num_parents = 1,
3167                         .flags = CLK_SET_RATE_PARENT,
3168                         .ops = &clk_branch2_ops,
3169                 },
3170         },
3171 };
3172
3173 static struct clk_branch gcc_usb30_prim_master_clk = {
3174         .halt_reg = 0xf010,
3175         .halt_check = BRANCH_HALT,
3176         .clkr = {
3177                 .enable_reg = 0xf010,
3178                 .enable_mask = BIT(0),
3179                 .hw.init = &(struct clk_init_data){
3180                         .name = "gcc_usb30_prim_master_clk",
3181                         .parent_data = &(const struct clk_parent_data){
3182                                 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
3183                         },
3184                         .num_parents = 1,
3185                         .flags = CLK_SET_RATE_PARENT,
3186                         .ops = &clk_branch2_ops,
3187                 },
3188         },
3189 };
3190
3191 static struct clk_branch gcc_usb30_prim_master_clk__force_mem_core_on = {
3192         .halt_reg = 0xf010,
3193         .halt_check = BRANCH_HALT,
3194         .clkr = {
3195                 .enable_reg = 0xf010,
3196                 .enable_mask = BIT(14),
3197                 .hw.init = &(struct clk_init_data){
3198                         .name = "gcc_usb30_prim_master_clk__force_mem_core_on",
3199                         .ops = &clk_branch_simple_ops,
3200                 },
3201         },
3202 };
3203
3204 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3205         .halt_reg = 0xf01c,
3206         .halt_check = BRANCH_HALT,
3207         .clkr = {
3208                 .enable_reg = 0xf01c,
3209                 .enable_mask = BIT(0),
3210                 .hw.init = &(struct clk_init_data){
3211                         .name = "gcc_usb30_prim_mock_utmi_clk",
3212                         .parent_data = &(const struct clk_parent_data){
3213                                 .hw =
3214                         &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
3215                         },
3216                         .num_parents = 1,
3217                         .flags = CLK_SET_RATE_PARENT,
3218                         .ops = &clk_branch2_ops,
3219                 },
3220         },
3221 };
3222
3223 static struct clk_branch gcc_usb30_prim_sleep_clk = {
3224         .halt_reg = 0xf018,
3225         .halt_check = BRANCH_HALT,
3226         .clkr = {
3227                 .enable_reg = 0xf018,
3228                 .enable_mask = BIT(0),
3229                 .hw.init = &(struct clk_init_data){
3230                         .name = "gcc_usb30_prim_sleep_clk",
3231                         .ops = &clk_branch2_ops,
3232                 },
3233         },
3234 };
3235
3236 static struct clk_branch gcc_usb30_sec_master_clk = {
3237         .halt_reg = 0x10010,
3238         .halt_check = BRANCH_HALT,
3239         .clkr = {
3240                 .enable_reg = 0x10010,
3241                 .enable_mask = BIT(0),
3242                 .hw.init = &(struct clk_init_data){
3243                         .name = "gcc_usb30_sec_master_clk",
3244                         .parent_data = &(const struct clk_parent_data){
3245                                 .hw = &gcc_usb30_sec_master_clk_src.clkr.hw,
3246                         },
3247                         .num_parents = 1,
3248                         .flags = CLK_SET_RATE_PARENT,
3249                         .ops = &clk_branch2_ops,
3250                 },
3251         },
3252 };
3253
3254 static struct clk_branch gcc_usb30_sec_master_clk__force_mem_core_on = {
3255         .halt_reg = 0x10010,
3256         .halt_check = BRANCH_HALT,
3257         .clkr = {
3258                 .enable_reg = 0x10010,
3259                 .enable_mask = BIT(14),
3260                 .hw.init = &(struct clk_init_data){
3261                         .name = "gcc_usb30_sec_master_clk__force_mem_core_on",
3262                         .ops = &clk_branch_simple_ops,
3263                 },
3264         },
3265 };
3266
3267 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
3268         .halt_reg = 0x1001c,
3269         .halt_check = BRANCH_HALT,
3270         .clkr = {
3271                 .enable_reg = 0x1001c,
3272                 .enable_mask = BIT(0),
3273                 .hw.init = &(struct clk_init_data){
3274                         .name = "gcc_usb30_sec_mock_utmi_clk",
3275                         .parent_data = &(const struct clk_parent_data){
3276                                 .hw =
3277                         &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
3278                         },
3279                         .num_parents = 1,
3280                         .flags = CLK_SET_RATE_PARENT,
3281                         .ops = &clk_branch2_ops,
3282                 },
3283         },
3284 };
3285
3286 static struct clk_branch gcc_usb30_sec_sleep_clk = {
3287         .halt_reg = 0x10018,
3288         .halt_check = BRANCH_HALT,
3289         .clkr = {
3290                 .enable_reg = 0x10018,
3291                 .enable_mask = BIT(0),
3292                 .hw.init = &(struct clk_init_data){
3293                         .name = "gcc_usb30_sec_sleep_clk",
3294                         .ops = &clk_branch2_ops,
3295                 },
3296         },
3297 };
3298
3299 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
3300         .halt_reg = 0xf054,
3301         .halt_check = BRANCH_HALT,
3302         .clkr = {
3303                 .enable_reg = 0xf054,
3304                 .enable_mask = BIT(0),
3305                 .hw.init = &(struct clk_init_data){
3306                         .name = "gcc_usb3_prim_phy_aux_clk",
3307                         .parent_data = &(const struct clk_parent_data){
3308                                 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3309                         },
3310                         .num_parents = 1,
3311                         .flags = CLK_SET_RATE_PARENT,
3312                         .ops = &clk_branch2_ops,
3313                 },
3314         },
3315 };
3316
3317 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3318         .halt_reg = 0xf058,
3319         .halt_check = BRANCH_HALT,
3320         .clkr = {
3321                 .enable_reg = 0xf058,
3322                 .enable_mask = BIT(0),
3323                 .hw.init = &(struct clk_init_data){
3324                         .name = "gcc_usb3_prim_phy_com_aux_clk",
3325                         .parent_data = &(const struct clk_parent_data){
3326                                 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3327                         },
3328                         .num_parents = 1,
3329                         .flags = CLK_SET_RATE_PARENT,
3330                         .ops = &clk_branch2_ops,
3331                 },
3332         },
3333 };
3334
3335 /* Clock ON depends on external parent clock, so don't poll */
3336 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
3337         .halt_reg = 0xf05c,
3338         .halt_check = BRANCH_HALT_DELAY,
3339         .hwcg_reg = 0xf05c,
3340         .hwcg_bit = 1,
3341         .clkr = {
3342                 .enable_reg = 0xf05c,
3343                 .enable_mask = BIT(0),
3344                 .hw.init = &(struct clk_init_data){
3345                         .name = "gcc_usb3_prim_phy_pipe_clk",
3346                         .parent_data = &(const struct clk_parent_data){
3347                                 .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
3348                         },
3349                         .num_parents = 1,
3350                         .flags = CLK_SET_RATE_PARENT,
3351                         .ops = &clk_branch2_ops,
3352                 },
3353         },
3354 };
3355
3356 static struct clk_branch gcc_usb3_sec_clkref_en = {
3357         .halt_reg = 0x8c010,
3358         .halt_check = BRANCH_HALT,
3359         .clkr = {
3360                 .enable_reg = 0x8c010,
3361                 .enable_mask = BIT(0),
3362                 .hw.init = &(struct clk_init_data){
3363                         .name = "gcc_usb3_sec_clkref_en",
3364                         .ops = &clk_branch2_ops,
3365                 },
3366         },
3367 };
3368
3369 static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
3370         .halt_reg = 0x10054,
3371         .halt_check = BRANCH_HALT,
3372         .clkr = {
3373                 .enable_reg = 0x10054,
3374                 .enable_mask = BIT(0),
3375                 .hw.init = &(struct clk_init_data){
3376                         .name = "gcc_usb3_sec_phy_aux_clk",
3377                         .parent_data = &(const struct clk_parent_data){
3378                                 .hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3379                         },
3380                         .num_parents = 1,
3381                         .flags = CLK_SET_RATE_PARENT,
3382                         .ops = &clk_branch2_ops,
3383                 },
3384         },
3385 };
3386
3387 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
3388         .halt_reg = 0x10058,
3389         .halt_check = BRANCH_HALT,
3390         .clkr = {
3391                 .enable_reg = 0x10058,
3392                 .enable_mask = BIT(0),
3393                 .hw.init = &(struct clk_init_data){
3394                         .name = "gcc_usb3_sec_phy_com_aux_clk",
3395                         .parent_data = &(const struct clk_parent_data){
3396                                 .hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3397                         },
3398                         .num_parents = 1,
3399                         .flags = CLK_SET_RATE_PARENT,
3400                         .ops = &clk_branch2_ops,
3401                 },
3402         },
3403 };
3404
3405 /* Clock ON depends on external parent clock, so don't poll */
3406 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
3407         .halt_reg = 0x1005c,
3408         .halt_check = BRANCH_HALT_DELAY,
3409         .clkr = {
3410                 .enable_reg = 0x1005c,
3411                 .enable_mask = BIT(0),
3412                 .hw.init = &(struct clk_init_data){
3413                         .name = "gcc_usb3_sec_phy_pipe_clk",
3414                         .parent_data = &(const struct clk_parent_data){
3415                                 .hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
3416                         },
3417                         .num_parents = 1,
3418                         .flags = CLK_SET_RATE_PARENT,
3419                         .ops = &clk_branch2_ops,
3420                 },
3421         },
3422 };
3423
3424 /* external clocks so add BRANCH_HALT_SKIP */
3425 static struct clk_branch gcc_video_axi0_clk = {
3426         .halt_reg = 0x28010,
3427         .halt_check = BRANCH_HALT_SKIP,
3428         .hwcg_reg = 0x28010,
3429         .hwcg_bit = 1,
3430         .clkr = {
3431                 .enable_reg = 0x28010,
3432                 .enable_mask = BIT(0),
3433                 .hw.init = &(struct clk_init_data){
3434                         .name = "gcc_video_axi0_clk",
3435                         .ops = &clk_branch2_ops,
3436                 },
3437         },
3438 };
3439
3440 /* external clocks so add BRANCH_HALT_SKIP */
3441 static struct clk_branch gcc_video_axi1_clk = {
3442         .halt_reg = 0x28018,
3443         .halt_check = BRANCH_HALT_SKIP,
3444         .hwcg_reg = 0x28018,
3445         .hwcg_bit = 1,
3446         .clkr = {
3447                 .enable_reg = 0x28018,
3448                 .enable_mask = BIT(0),
3449                 .hw.init = &(struct clk_init_data){
3450                         .name = "gcc_video_axi1_clk",
3451                         .ops = &clk_branch2_ops,
3452                 },
3453         },
3454 };
3455
3456 static struct gdsc pcie_0_gdsc = {
3457         .gdscr = 0x6b004,
3458         .pd = {
3459                 .name = "pcie_0_gdsc",
3460         },
3461         .pwrsts = PWRSTS_OFF_ON,
3462 };
3463
3464 static struct gdsc pcie_1_gdsc = {
3465         .gdscr = 0x8d004,
3466         .pd = {
3467                 .name = "pcie_1_gdsc",
3468         },
3469         .pwrsts = PWRSTS_OFF_ON,
3470 };
3471
3472 static struct gdsc ufs_card_gdsc = {
3473         .gdscr = 0x75004,
3474         .pd = {
3475                 .name = "ufs_card_gdsc",
3476         },
3477         .pwrsts = PWRSTS_OFF_ON,
3478 };
3479
3480 static struct gdsc ufs_phy_gdsc = {
3481         .gdscr = 0x77004,
3482         .pd = {
3483                 .name = "ufs_phy_gdsc",
3484         },
3485         .pwrsts = PWRSTS_OFF_ON,
3486 };
3487
3488 static struct gdsc usb30_prim_gdsc = {
3489         .gdscr = 0xf004,
3490         .pd = {
3491                 .name = "usb30_prim_gdsc",
3492         },
3493         .pwrsts = PWRSTS_OFF_ON,
3494 };
3495
3496 static struct gdsc usb30_sec_gdsc = {
3497         .gdscr = 0x10004,
3498         .pd = {
3499                 .name = "usb30_sec_gdsc",
3500         },
3501         .pwrsts = PWRSTS_OFF_ON,
3502 };
3503
3504 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
3505         .gdscr = 0x7d050,
3506         .pd = {
3507                 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
3508         },
3509         .pwrsts = PWRSTS_OFF_ON,
3510         .flags = VOTABLE,
3511 };
3512
3513 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
3514         .gdscr = 0x7d058,
3515         .pd = {
3516                 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
3517         },
3518         .pwrsts = PWRSTS_OFF_ON,
3519         .flags = VOTABLE,
3520 };
3521
3522 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = {
3523         .gdscr = 0x7d054,
3524         .pd = {
3525                 .name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc",
3526         },
3527         .pwrsts = PWRSTS_OFF_ON,
3528         .flags = VOTABLE,
3529 };
3530
3531 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc = {
3532         .gdscr = 0x7d06c,
3533         .pd = {
3534                 .name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc",
3535         },
3536         .pwrsts = PWRSTS_OFF_ON,
3537         .flags = VOTABLE,
3538 };
3539
3540 static struct clk_regmap *gcc_sm8350_clocks[] = {
3541         [GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr,
3542         [GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr,
3543         [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3544         [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
3545         [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
3546         [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3547         [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
3548         [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3549         [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3550         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3551         [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3552         [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3553         [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3554         [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3555         [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3556         [GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr,
3557         [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3558         [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
3559         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3560         [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3561         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3562         [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3563         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3564         [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3565         [GCC_GPLL0] = &gcc_gpll0.clkr,
3566         [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
3567         [GCC_GPLL4] = &gcc_gpll4.clkr,
3568         [GCC_GPLL9] = &gcc_gpll9.clkr,
3569         [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3570         [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3571         [GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr,
3572         [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3573         [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3574         [GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr,
3575         [GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr,
3576         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3577         [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3578         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3579         [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,
3580         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3581         [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
3582         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3583         [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
3584         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3585         [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3586         [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3587         [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3588         [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3589         [GCC_PCIE_1_CLKREF_EN] = &gcc_pcie_1_clkref_en.clkr,
3590         [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3591         [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
3592         [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3593         [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
3594         [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3595         [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3596         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3597         [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3598         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3599         [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3600         [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3601         [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3602         [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3603         [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
3604         [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3605         [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3606         [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3607         [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3608         [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3609         [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3610         [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3611         [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3612         [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3613         [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3614         [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3615         [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3616         [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3617         [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3618         [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3619         [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3620         [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3621         [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3622         [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3623         [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
3624         [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
3625         [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3626         [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3627         [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3628         [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3629         [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3630         [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3631         [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3632         [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3633         [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3634         [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3635         [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3636         [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3637         [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
3638         [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
3639         [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
3640         [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
3641         [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
3642         [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
3643         [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
3644         [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
3645         [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
3646         [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
3647         [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
3648         [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
3649         [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
3650         [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
3651         [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3652         [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3653         [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3654         [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3655         [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
3656         [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
3657         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3658         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3659         [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3660         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3661         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3662         [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3663         [GCC_THROTTLE_PCIE_AHB_CLK] = &gcc_throttle_pcie_ahb_clk.clkr,
3664         [GCC_UFS_1_CLKREF_EN] = &gcc_ufs_1_clkref_en.clkr,
3665         [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
3666         [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
3667         [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
3668         [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
3669         [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
3670         [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
3671         [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
3672         [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
3673         [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
3674         [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
3675         [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
3676         [GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_rx_symbol_0_clk_src.clkr,
3677         [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
3678         [GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_card_rx_symbol_1_clk_src.clkr,
3679         [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
3680         [GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_tx_symbol_0_clk_src.clkr,
3681         [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
3682         [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr,
3683         [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
3684         [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3685         [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3686         [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3687         [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
3688         [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3689         [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3690         [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
3691         [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3692         [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3693         [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
3694         [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3695         [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
3696         [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3697         [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
3698         [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3699         [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
3700         [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3701         [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
3702         [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
3703         [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3704         [GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON] =
3705                         &gcc_usb30_prim_master_clk__force_mem_core_on.clkr,
3706         [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3707         [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3708         [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3709         [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3710         [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3711         [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3712         [GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON] =
3713                         &gcc_usb30_sec_master_clk__force_mem_core_on.clkr,
3714         [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3715         [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3716         [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3717         [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
3718         [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3719         [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3720         [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3721         [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3722         [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3723         [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
3724         [GCC_USB3_SEC_CLKREF_EN] = &gcc_usb3_sec_clkref_en.clkr,
3725         [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3726         [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3727         [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3728         [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
3729         [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
3730         [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3731         [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
3732 };
3733
3734 static struct gdsc *gcc_sm8350_gdscs[] = {
3735         [PCIE_0_GDSC] = &pcie_0_gdsc,
3736         [PCIE_1_GDSC] = &pcie_1_gdsc,
3737         [UFS_CARD_GDSC] = &ufs_card_gdsc,
3738         [UFS_PHY_GDSC] = &ufs_phy_gdsc,
3739         [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3740         [USB30_SEC_GDSC] = &usb30_sec_gdsc,
3741         [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
3742         [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
3743         [HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc,
3744         [HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc,
3745 };
3746
3747 static const struct qcom_reset_map gcc_sm8350_resets[] = {
3748         [GCC_CAMERA_BCR] = { 0x26000 },
3749         [GCC_DISPLAY_BCR] = { 0x27000 },
3750         [GCC_GPU_BCR] = { 0x71000 },
3751         [GCC_MMSS_BCR] = { 0xb000 },
3752         [GCC_PCIE_0_BCR] = { 0x6b000 },
3753         [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3754         [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3755         [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3756         [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
3757         [GCC_PCIE_1_BCR] = { 0x8d000 },
3758         [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
3759         [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
3760         [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3761         [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 },
3762         [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
3763         [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
3764         [GCC_PDM_BCR] = { 0x33000 },
3765         [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3766         [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3767         [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3768         [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3769         [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3770         [GCC_SDCC2_BCR] = { 0x14000 },
3771         [GCC_SDCC4_BCR] = { 0x16000 },
3772         [GCC_UFS_CARD_BCR] = { 0x75000 },
3773         [GCC_UFS_PHY_BCR] = { 0x77000 },
3774         [GCC_USB30_PRIM_BCR] = { 0xf000 },
3775         [GCC_USB30_SEC_BCR] = { 0x10000 },
3776         [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3777         [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3778         [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3779         [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3780         [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3781         [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3782         [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3783         [GCC_VIDEO_AXI0_CLK_ARES] = { 0x28010, 2 },
3784         [GCC_VIDEO_AXI1_CLK_ARES] = { 0x28018, 2 },
3785         [GCC_VIDEO_BCR] = { 0x28000 },
3786 };
3787
3788 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3789         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3790         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3791         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3792         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3793         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3794         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3795         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3796         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
3797         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3798         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3799         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3800         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3801         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3802         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3803         DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
3804         DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
3805         DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
3806         DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
3807         DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
3808         DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
3809 };
3810
3811 static const struct regmap_config gcc_sm8350_regmap_config = {
3812         .reg_bits = 32,
3813         .reg_stride = 4,
3814         .val_bits = 32,
3815         .max_register = 0x9c100,
3816         .fast_io = true,
3817 };
3818
3819 static const struct qcom_cc_desc gcc_sm8350_desc = {
3820         .config = &gcc_sm8350_regmap_config,
3821         .clks = gcc_sm8350_clocks,
3822         .num_clks = ARRAY_SIZE(gcc_sm8350_clocks),
3823         .resets = gcc_sm8350_resets,
3824         .num_resets = ARRAY_SIZE(gcc_sm8350_resets),
3825         .gdscs = gcc_sm8350_gdscs,
3826         .num_gdscs = ARRAY_SIZE(gcc_sm8350_gdscs),
3827 };
3828
3829 static const struct of_device_id gcc_sm8350_match_table[] = {
3830         { .compatible = "qcom,gcc-sm8350" },
3831         { }
3832 };
3833 MODULE_DEVICE_TABLE(of, gcc_sm8350_match_table);
3834
3835 static int gcc_sm8350_probe(struct platform_device *pdev)
3836 {
3837         struct regmap *regmap;
3838         int ret;
3839
3840         regmap = qcom_cc_map(pdev, &gcc_sm8350_desc);
3841         if (IS_ERR(regmap)) {
3842                 dev_err(&pdev->dev, "Failed to map gcc registers\n");
3843                 return PTR_ERR(regmap);
3844         }
3845
3846         /*
3847          * Keep the critical clock always-On
3848          * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK,
3849          * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK
3850          */
3851         regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0));
3852         regmap_update_bits(regmap, 0x26018, BIT(0), BIT(0));
3853         regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0));
3854         regmap_update_bits(regmap, 0x2701c, BIT(0), BIT(0));
3855         regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
3856         regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0));
3857         regmap_update_bits(regmap, 0x28020, BIT(0), BIT(0));
3858
3859         ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
3860         if (ret)
3861                 return ret;
3862
3863         /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
3864         regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
3865
3866         return qcom_cc_really_probe(pdev, &gcc_sm8350_desc, regmap);
3867 }
3868
3869 static struct platform_driver gcc_sm8350_driver = {
3870         .probe = gcc_sm8350_probe,
3871         .driver = {
3872                 .name = "sm8350-gcc",
3873                 .of_match_table = gcc_sm8350_match_table,
3874         },
3875 };
3876
3877 static int __init gcc_sm8350_init(void)
3878 {
3879         return platform_driver_register(&gcc_sm8350_driver);
3880 }
3881 subsys_initcall(gcc_sm8350_init);
3882
3883 static void __exit gcc_sm8350_exit(void)
3884 {
3885         platform_driver_unregister(&gcc_sm8350_driver);
3886 }
3887 module_exit(gcc_sm8350_exit);
3888
3889 MODULE_DESCRIPTION("QTI GCC SM8350 Driver");
3890 MODULE_LICENSE("GPL v2");