drivers/clk/qcom/gcc-sm6125.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/err.h>
   8 #include <linux/module.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/of.h>
  11 #include <linux/of_device.h>
  12 #include <linux/clk-provider.h>
  13 #include <linux/regmap.h>
  14 #include <linux/reset-controller.h>
  15
  16 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
  17
  18 #include "clk-alpha-pll.h"
  19 #include "clk-branch.h"
  20 #include "clk-rcg.h"
  21 #include "clk-regmap.h"
  22 #include "common.h"
  23 #include "gdsc.h"
  24 #include "reset.h"
  25
  26 enum {
  27         P_BI_TCXO,
  28         P_GPLL0_OUT_AUX2,
  29         P_GPLL0_OUT_EARLY,
  30         P_GPLL3_OUT_EARLY,
  31         P_GPLL4_OUT_MAIN,
  32         P_GPLL5_OUT_MAIN,
  33         P_GPLL6_OUT_EARLY,
  34         P_GPLL6_OUT_MAIN,
  35         P_GPLL7_OUT_MAIN,
  36         P_GPLL8_OUT_EARLY,
  37         P_GPLL8_OUT_MAIN,
  38         P_GPLL9_OUT_MAIN,
  39         P_SLEEP_CLK,
  40 };
  41
  42 static struct clk_alpha_pll gpll0_out_early = {
  43         .offset = 0x0,
  44         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  45         .clkr = {
  46                 .enable_reg = 0x79000,
  47                 .enable_mask = BIT(0),
  48                 .hw.init = &(struct clk_init_data){
  49                         .name = "gpll0_out_early",
  50                         .parent_data = &(const struct clk_parent_data){
  51                                 .fw_name = "bi_tcxo",
  52                         },
  53                         .num_parents = 1,
  54                         .ops = &clk_alpha_pll_ops,
  55                 },
  56         },
  57 };
  58
  59 static struct clk_fixed_factor gpll0_out_aux2 = {
  60         .mult = 1,
  61         .div = 2,
  62         .hw.init = &(struct clk_init_data){
  63                 .name = "gpll0_out_aux2",
  64                 .parent_hws = (const struct clk_hw*[]){
  65                         &gpll0_out_early.clkr.hw,
  66                 },
  67                 .num_parents = 1,
  68                 .ops = &clk_fixed_factor_ops,
  69         },
  70 };
  71
  72 static struct clk_fixed_factor gpll0_out_main = {
  73         .mult = 1,
  74         .div = 2,
  75         .hw.init = &(struct clk_init_data){
  76                 .name = "gpll0_out_main",
  77                 .parent_hws = (const struct clk_hw*[]){
  78                         &gpll0_out_early.clkr.hw,
  79                 },
  80                 .num_parents = 1,
  81                 .ops = &clk_fixed_factor_ops,
  82         },
  83 };
  84
  85 static struct clk_alpha_pll gpll3_out_early = {
  86         .offset = 0x3000,
  87         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  88         .clkr = {
  89                 .enable_reg = 0x79000,
  90                 .enable_mask = BIT(3),
  91                 .hw.init = &(struct clk_init_data){
  92                         .name = "gpll3_out_early",
  93                         .parent_data = &(const struct clk_parent_data){
  94                                 .fw_name = "bi_tcxo",
  95                         },
  96                         .num_parents = 1,
  97                         .ops = &clk_alpha_pll_ops,
  98                 },
  99         },
 100 };
 101
 102 static struct clk_alpha_pll gpll4_out_main = {
 103         .offset = 0x4000,
 104         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 105         .clkr = {
 106                 .enable_reg = 0x79000,
 107                 .enable_mask = BIT(4),
 108                 .hw.init = &(struct clk_init_data){
 109                         .name = "gpll4_out_main",
 110                         .parent_data = &(const struct clk_parent_data){
 111                                 .fw_name = "bi_tcxo",
 112                         },
 113                         .num_parents = 1,
 114                         .ops = &clk_alpha_pll_ops,
 115                 },
 116         },
 117 };
 118
 119 static struct clk_alpha_pll gpll5_out_main = {
 120         .offset = 0x5000,
 121         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 122         .clkr = {
 123                 .enable_reg = 0x79000,
 124                 .enable_mask = BIT(5),
 125                 .hw.init = &(struct clk_init_data){
 126                         .name = "gpll5_out_main",
 127                         .parent_data = &(const struct clk_parent_data){
 128                                 .fw_name = "bi_tcxo",
 129                         },
 130                         .num_parents = 1,
 131                         .ops = &clk_alpha_pll_ops,
 132                 },
 133         },
 134 };
 135
 136 static struct clk_alpha_pll gpll6_out_early = {
 137         .offset = 0x6000,
 138         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 139         .clkr = {
 140                 .enable_reg = 0x79000,
 141                 .enable_mask = BIT(6),
 142                 .hw.init = &(struct clk_init_data){
 143                         .name = "gpll6_out_early",
 144                         .parent_data = &(const struct clk_parent_data){
 145                                 .fw_name = "bi_tcxo",
 146                         },
 147                         .num_parents = 1,
 148                         .ops = &clk_alpha_pll_ops,
 149                 },
 150         },
 151 };
 152
 153 static struct clk_fixed_factor gpll6_out_main = {
 154         .mult = 1,
 155         .div = 2,
 156         .hw.init = &(struct clk_init_data){
 157                 .name = "gpll6_out_main",
 158                 .parent_hws = (const struct clk_hw*[]){
 159                         &gpll6_out_early.clkr.hw,
 160                 },
 161                 .num_parents = 1,
 162                 .ops = &clk_fixed_factor_ops,
 163         },
 164 };
 165
 166 static struct clk_alpha_pll gpll7_out_early = {
 167         .offset = 0x7000,
 168         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 169         .clkr = {
 170                 .enable_reg = 0x79000,
 171                 .enable_mask = BIT(7),
 172                 .hw.init = &(struct clk_init_data){
 173                         .name = "gpll7_out_early",
 174                         .parent_data = &(const struct clk_parent_data){
 175                                 .fw_name = "bi_tcxo",
 176                         },
 177                         .num_parents = 1,
 178                         .ops = &clk_alpha_pll_ops,
 179                 },
 180         },
 181 };
 182
 183 static struct clk_fixed_factor gpll7_out_main = {
 184         .mult = 1,
 185         .div = 2,
 186         .hw.init = &(struct clk_init_data){
 187                 .name = "gpll7_out_main",
 188                 .parent_hws = (const struct clk_hw*[]){
 189                         &gpll7_out_early.clkr.hw,
 190                 },
 191                 .num_parents = 1,
 192                 .ops = &clk_fixed_factor_ops,
 193         },
 194 };
 195
 196 static struct clk_alpha_pll gpll8_out_early = {
 197         .offset = 0x8000,
 198         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 199         .clkr = {
 200                 .enable_reg = 0x79000,
 201                 .enable_mask = BIT(8),
 202                 .hw.init = &(struct clk_init_data){
 203                         .name = "gpll8_out_early",
 204                         .parent_data = &(const struct clk_parent_data){
 205                                 .fw_name = "bi_tcxo",
 206                         },
 207                         .num_parents = 1,
 208                         .ops = &clk_alpha_pll_ops,
 209                 },
 210         },
 211 };
 212
 213 static struct clk_fixed_factor gpll8_out_main = {
 214         .mult = 1,
 215         .div = 2,
 216         .hw.init = &(struct clk_init_data){
 217                 .name = "gpll8_out_main",
 218                 .parent_hws = (const struct clk_hw*[]){
 219                         &gpll8_out_early.clkr.hw,
 220                 },
 221                 .num_parents = 1,
 222                 .ops = &clk_fixed_factor_ops,
 223         },
 224 };
 225
 226 static struct clk_alpha_pll gpll9_out_early = {
 227         .offset = 0x9000,
 228         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 229         .clkr = {
 230                 .enable_reg = 0x79000,
 231                 .enable_mask = BIT(9),
 232                 .hw.init = &(struct clk_init_data){
 233                         .name = "gpll9_out_early",
 234                         .parent_data = &(const struct clk_parent_data){
 235                                 .fw_name = "bi_tcxo",
 236                         },
 237                         .num_parents = 1,
 238                         .ops = &clk_alpha_pll_ops,
 239                 },
 240         },
 241 };
 242
 243 static struct clk_fixed_factor gpll9_out_main = {
 244         .mult = 1,
 245         .div = 2,
 246         .hw.init = &(struct clk_init_data){
 247                 .name = "gpll9_out_main",
 248                 .parent_hws = (const struct clk_hw*[]){
 249                         &gpll9_out_early.clkr.hw,
 250                 },
 251                 .num_parents = 1,
 252                 .ops = &clk_fixed_factor_ops,
 253         },
 254 };
 255
 256 static const struct parent_map gcc_parent_map_0[] = {
 257         { P_BI_TCXO, 0 },
 258         { P_GPLL0_OUT_EARLY, 1 },
 259         { P_GPLL0_OUT_AUX2, 2 },
 260 };
 261
 262 static const struct clk_parent_data gcc_parent_data_0[] = {
 263         { .fw_name = "bi_tcxo" },
 264         { .hw = &gpll0_out_early.clkr.hw },
 265         { .hw = &gpll0_out_aux2.hw },
 266 };
 267
 268 static const struct parent_map gcc_parent_map_1[] = {
 269         { P_BI_TCXO, 0 },
 270         { P_GPLL0_OUT_EARLY, 1 },
 271         { P_GPLL0_OUT_AUX2, 2 },
 272         { P_GPLL6_OUT_MAIN, 4 },
 273 };
 274
 275 static const struct clk_parent_data gcc_parent_data_1[] = {
 276         { .fw_name = "bi_tcxo" },
 277         { .hw = &gpll0_out_early.clkr.hw },
 278         { .hw = &gpll0_out_aux2.hw },
 279         { .hw = &gpll6_out_main.hw },
 280 };
 281
 282 static const struct parent_map gcc_parent_map_2[] = {
 283         { P_BI_TCXO, 0 },
 284         { P_GPLL0_OUT_EARLY, 1 },
 285         { P_GPLL0_OUT_AUX2, 2 },
 286         { P_SLEEP_CLK, 5 },
 287 };
 288
 289 static const struct clk_parent_data gcc_parent_data_2[] = {
 290         { .fw_name = "bi_tcxo" },
 291         { .hw = &gpll0_out_early.clkr.hw },
 292         { .hw = &gpll0_out_aux2.hw },
 293         { .fw_name = "sleep_clk" },
 294 };
 295
 296 static const struct parent_map gcc_parent_map_3[] = {
 297         { P_BI_TCXO, 0 },
 298         { P_GPLL0_OUT_EARLY, 1 },
 299         { P_GPLL5_OUT_MAIN, 3 },
 300         { P_GPLL4_OUT_MAIN, 5 },
 301 };
 302
 303 static const struct clk_parent_data gcc_parent_data_3[] = {
 304         { .fw_name = "bi_tcxo" },
 305         { .hw = &gpll0_out_early.clkr.hw },
 306         { .hw = &gpll5_out_main.clkr.hw },
 307         { .hw = &gpll4_out_main.clkr.hw },
 308 };
 309
 310 static const struct parent_map gcc_parent_map_4[] = {
 311         { P_BI_TCXO, 0 },
 312         { P_GPLL0_OUT_EARLY, 1 },
 313         { P_GPLL9_OUT_MAIN, 2 },
 314 };
 315
 316 static const struct clk_parent_data gcc_parent_data_4[] = {
 317         { .fw_name = "bi_tcxo" },
 318         { .hw = &gpll0_out_early.clkr.hw },
 319         { .hw = &gpll9_out_main.hw },
 320 };
 321
 322 static const struct parent_map gcc_parent_map_5[] = {
 323         { P_BI_TCXO, 0 },
 324         { P_GPLL0_OUT_EARLY, 1 },
 325 };
 326
 327 static const struct clk_parent_data gcc_parent_data_5[] = {
 328         { .fw_name = "bi_tcxo" },
 329         { .hw = &gpll0_out_early.clkr.hw },
 330 };
 331
 332 static const struct parent_map gcc_parent_map_6[] = {
 333         { P_BI_TCXO, 0 },
 334         { P_GPLL0_OUT_EARLY, 1 },
 335         { P_GPLL4_OUT_MAIN, 5 },
 336 };
 337
 338 static const struct clk_parent_data gcc_parent_data_6[] = {
 339         { .fw_name = "bi_tcxo" },
 340         { .hw = &gpll0_out_early.clkr.hw },
 341         { .hw = &gpll4_out_main.clkr.hw },
 342 };
 343
 344 static const struct parent_map gcc_parent_map_7[] = {
 345         { P_BI_TCXO, 0 },
 346         { P_GPLL0_OUT_EARLY, 1 },
 347         { P_SLEEP_CLK, 5 },
 348 };
 349
 350 static const struct clk_parent_data gcc_parent_data_7[] = {
 351         { .fw_name = "bi_tcxo" },
 352         { .hw = &gpll0_out_early.clkr.hw },
 353         { .fw_name = "sleep_clk" },
 354 };
 355
 356 static const struct parent_map gcc_parent_map_8[] = {
 357         { P_BI_TCXO, 0 },
 358         { P_GPLL0_OUT_EARLY, 1 },
 359         { P_GPLL9_OUT_MAIN, 2 },
 360         { P_GPLL6_OUT_EARLY, 3 },
 361         { P_GPLL8_OUT_MAIN, 4 },
 362         { P_GPLL4_OUT_MAIN, 5 },
 363         { P_GPLL3_OUT_EARLY, 6 },
 364 };
 365
 366 static const struct clk_parent_data gcc_parent_data_8[] = {
 367         { .fw_name = "bi_tcxo" },
 368         { .hw = &gpll0_out_early.clkr.hw },
 369         { .hw = &gpll9_out_main.hw },
 370         { .hw = &gpll6_out_early.clkr.hw },
 371         { .hw = &gpll8_out_main.hw },
 372         { .hw = &gpll4_out_main.clkr.hw },
 373         { .hw = &gpll3_out_early.clkr.hw },
 374 };
 375
 376 static const struct parent_map gcc_parent_map_9[] = {
 377         { P_BI_TCXO, 0 },
 378         { P_GPLL0_OUT_EARLY, 1 },
 379         { P_GPLL8_OUT_MAIN, 4 },
 380 };
 381
 382 static const struct clk_parent_data gcc_parent_data_9[] = {
 383         { .fw_name = "bi_tcxo" },
 384         { .hw = &gpll0_out_early.clkr.hw },
 385         { .hw = &gpll8_out_main.hw },
 386 };
 387
 388 static const struct parent_map gcc_parent_map_10[] = {
 389         { P_BI_TCXO, 0 },
 390         { P_GPLL0_OUT_EARLY, 1 },
 391         { P_GPLL9_OUT_MAIN, 2 },
 392         { P_GPLL6_OUT_EARLY, 3 },
 393         { P_GPLL8_OUT_MAIN, 4 },
 394         { P_GPLL3_OUT_EARLY, 6 },
 395 };
 396
 397 static const struct clk_parent_data gcc_parent_data_10[] = {
 398         { .fw_name = "bi_tcxo" },
 399         { .hw = &gpll0_out_early.clkr.hw },
 400         { .hw = &gpll9_out_main.hw },
 401         { .hw = &gpll6_out_early.clkr.hw },
 402         { .hw = &gpll8_out_main.hw },
 403         { .hw = &gpll3_out_early.clkr.hw },
 404 };
 405
 406 static const struct parent_map gcc_parent_map_11[] = {
 407         { P_BI_TCXO, 0 },
 408         { P_GPLL0_OUT_EARLY, 1 },
 409         { P_GPLL8_OUT_EARLY, 4 },
 410         { P_GPLL4_OUT_MAIN, 5 },
 411 };
 412
 413 static const struct clk_parent_data gcc_parent_data_11[] = {
 414         { .fw_name = "bi_tcxo" },
 415         { .hw = &gpll0_out_early.clkr.hw },
 416         { .hw = &gpll8_out_early.clkr.hw },
 417         { .hw = &gpll4_out_main.clkr.hw },
 418 };
 419
 420 static const struct parent_map gcc_parent_map_12[] = {
 421         { P_BI_TCXO, 0 },
 422         { P_GPLL0_OUT_EARLY, 1 },
 423         { P_GPLL6_OUT_EARLY, 3 },
 424         { P_GPLL8_OUT_EARLY, 4 },
 425 };
 426
 427 static const struct clk_parent_data gcc_parent_data_12[] = {
 428         { .fw_name = "bi_tcxo" },
 429         { .hw = &gpll0_out_early.clkr.hw },
 430         { .hw = &gpll6_out_early.clkr.hw },
 431         { .hw = &gpll8_out_early.clkr.hw },
 432 };
 433
 434 static const struct parent_map gcc_parent_map_13[] = {
 435         { P_BI_TCXO, 0 },
 436         { P_GPLL0_OUT_EARLY, 1 },
 437         { P_GPLL0_OUT_AUX2, 2 },
 438         { P_GPLL7_OUT_MAIN, 3 },
 439         { P_GPLL4_OUT_MAIN, 5 },
 440 };
 441
 442 static const struct clk_parent_data gcc_parent_data_13[] = {
 443         { .fw_name = "bi_tcxo" },
 444         { .hw = &gpll0_out_early.clkr.hw },
 445         { .hw = &gpll0_out_aux2.hw },
 446         { .hw = &gpll7_out_main.hw },
 447         { .hw = &gpll4_out_main.clkr.hw },
 448 };
 449
 450 static const struct parent_map gcc_parent_map_14[] = {
 451         { P_BI_TCXO, 0 },
 452         { P_SLEEP_CLK, 5 },
 453 };
 454
 455 static const struct clk_parent_data gcc_parent_data_14[] = {
 456         { .fw_name = "bi_tcxo" },
 457         { .fw_name = "sleep_clk" },
 458 };
 459
 460 static const struct freq_tbl ftbl_gcc_camss_ahb_clk_src[] = {
 461         F(19200000, P_BI_TCXO, 1, 0, 0),
 462         F(40000000, P_GPLL8_OUT_MAIN, 12, 0, 0),
 463         F(80000000, P_GPLL8_OUT_MAIN, 6, 0, 0),
 464         { }
 465 };
 466
 467 static struct clk_rcg2 gcc_camss_ahb_clk_src = {
 468         .cmd_rcgr = 0x56088,
 469         .mnd_width = 0,
 470         .hid_width = 5,
 471         .parent_map = gcc_parent_map_9,
 472         .freq_tbl = ftbl_gcc_camss_ahb_clk_src,
 473         .clkr.hw.init = &(struct clk_init_data){
 474                 .name = "gcc_camss_ahb_clk_src",
 475                 .parent_data = gcc_parent_data_9,
 476                 .num_parents = ARRAY_SIZE(gcc_parent_data_9),
 477                 .ops = &clk_rcg2_ops,
 478         },
 479 };
 480
 481 static const struct freq_tbl ftbl_gcc_camss_cci_clk_src[] = {
 482         F(37500000, P_GPLL0_OUT_EARLY, 16, 0, 0),
 483         F(50000000, P_GPLL0_OUT_EARLY, 12, 0, 0),
 484         F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
 485         { }
 486 };
 487
 488 static struct clk_rcg2 gcc_camss_cci_clk_src = {
 489         .cmd_rcgr = 0x52004,
 490         .mnd_width = 8,
 491         .hid_width = 5,
 492         .parent_map = gcc_parent_map_5,
 493         .freq_tbl = ftbl_gcc_camss_cci_clk_src,
 494         .clkr.hw.init = &(struct clk_init_data){
 495                 .name = "gcc_camss_cci_clk_src",
 496                 .parent_data = gcc_parent_data_5,
 497                 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
 498                 .ops = &clk_rcg2_ops,
 499         },
 500 };
 501
 502 static const struct freq_tbl ftbl_gcc_camss_cpp_clk_src[] = {
 503         F(120000000, P_GPLL8_OUT_MAIN, 4, 0, 0),
 504         F(240000000, P_GPLL8_OUT_MAIN, 2, 0, 0),
 505         F(320000000, P_GPLL8_OUT_MAIN, 1.5, 0, 0),
 506         F(480000000, P_GPLL8_OUT_MAIN, 1, 0, 0),
 507         F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0),
 508         { }
 509 };
 510
 511 static struct clk_rcg2 gcc_camss_cpp_clk_src = {
 512         .cmd_rcgr = 0x560c8,
 513         .mnd_width = 0,
 514         .hid_width = 5,
 515         .parent_map = gcc_parent_map_10,
 516         .freq_tbl = ftbl_gcc_camss_cpp_clk_src,
 517         .clkr.hw.init = &(struct clk_init_data){
 518                 .name = "gcc_camss_cpp_clk_src",
 519                 .parent_data = gcc_parent_data_10,
 520                 .num_parents = ARRAY_SIZE(gcc_parent_data_10),
 521                 .ops = &clk_rcg2_ops,
 522         },
 523 };
 524
 525 static const struct freq_tbl ftbl_gcc_camss_csi0_clk_src[] = {
 526         F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
 527         F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
 528         F(311000000, P_GPLL5_OUT_MAIN, 3, 0, 0),
 529         F(403200000, P_GPLL4_OUT_MAIN, 2, 0, 0),
 530         F(466500000, P_GPLL5_OUT_MAIN, 2, 0, 0),
 531         { }
 532 };
 533
 534 static struct clk_rcg2 gcc_camss_csi0_clk_src = {
 535         .cmd_rcgr = 0x55030,
 536         .mnd_width = 0,
 537         .hid_width = 5,
 538         .parent_map = gcc_parent_map_3,
 539         .freq_tbl = ftbl_gcc_camss_csi0_clk_src,
 540         .clkr.hw.init = &(struct clk_init_data){
 541                 .name = "gcc_camss_csi0_clk_src",
 542                 .parent_data = gcc_parent_data_3,
 543                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
 544                 .ops = &clk_rcg2_ops,
 545         },
 546 };
 547
 548 static const struct freq_tbl ftbl_gcc_camss_csi0phytimer_clk_src[] = {
 549         F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
 550         F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
 551         F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0),
 552         { }
 553 };
 554
 555 static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = {
 556         .cmd_rcgr = 0x53004,
 557         .mnd_width = 0,
 558         .hid_width = 5,
 559         .parent_map = gcc_parent_map_6,
 560         .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
 561         .clkr.hw.init = &(struct clk_init_data){
 562                 .name = "gcc_camss_csi0phytimer_clk_src",
 563                 .parent_data = gcc_parent_data_6,
 564                 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
 565                 .ops = &clk_rcg2_ops,
 566         },
 567 };
 568
 569 static struct clk_rcg2 gcc_camss_csi1_clk_src = {
 570         .cmd_rcgr = 0x5506c,
 571         .mnd_width = 0,
 572         .hid_width = 5,
 573         .parent_map = gcc_parent_map_3,
 574         .freq_tbl = ftbl_gcc_camss_csi0_clk_src,
 575         .clkr.hw.init = &(struct clk_init_data){
 576                 .name = "gcc_camss_csi1_clk_src",
 577                 .parent_data = gcc_parent_data_3,
 578                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
 579                 .ops = &clk_rcg2_ops,
 580         },
 581 };
 582
 583 static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = {
 584         .cmd_rcgr = 0x53024,
 585         .mnd_width = 0,
 586         .hid_width = 5,
 587         .parent_map = gcc_parent_map_6,
 588         .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
 589         .clkr.hw.init = &(struct clk_init_data){
 590                 .name = "gcc_camss_csi1phytimer_clk_src",
 591                 .parent_data = gcc_parent_data_6,
 592                 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
 593                 .ops = &clk_rcg2_ops,
 594         },
 595 };
 596
 597 static struct clk_rcg2 gcc_camss_csi2_clk_src = {
 598         .cmd_rcgr = 0x550a4,
 599         .mnd_width = 0,
 600         .hid_width = 5,
 601         .parent_map = gcc_parent_map_3,
 602         .freq_tbl = ftbl_gcc_camss_csi0_clk_src,
 603         .clkr.hw.init = &(struct clk_init_data){
 604                 .name = "gcc_camss_csi2_clk_src",
 605                 .parent_data = gcc_parent_data_3,
 606                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
 607                 .ops = &clk_rcg2_ops,
 608         },
 609 };
 610
 611 static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = {
 612         .cmd_rcgr = 0x53044,
 613         .mnd_width = 0,
 614         .hid_width = 5,
 615         .parent_map = gcc_parent_map_6,
 616         .freq_tbl = ftbl_gcc_camss_csi0phytimer_clk_src,
 617         .clkr.hw.init = &(struct clk_init_data){
 618                 .name = "gcc_camss_csi2phytimer_clk_src",
 619                 .parent_data = gcc_parent_data_6,
 620                 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
 621                 .ops = &clk_rcg2_ops,
 622         },
 623 };
 624
 625 static struct clk_rcg2 gcc_camss_csi3_clk_src = {
 626         .cmd_rcgr = 0x550e0,
 627         .mnd_width = 0,
 628         .hid_width = 5,
 629         .parent_map = gcc_parent_map_3,
 630         .freq_tbl = ftbl_gcc_camss_csi0_clk_src,
 631         .clkr.hw.init = &(struct clk_init_data){
 632                 .name = "gcc_camss_csi3_clk_src",
 633                 .parent_data = gcc_parent_data_3,
 634                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
 635                 .ops = &clk_rcg2_ops,
 636         },
 637 };
 638
 639 static const struct freq_tbl ftbl_gcc_camss_csiphy_clk_src[] = {
 640         F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
 641         F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
 642         F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0),
 643         F(320000000, P_GPLL8_OUT_EARLY, 3, 0, 0),
 644         { }
 645 };
 646
 647 static struct clk_rcg2 gcc_camss_csiphy_clk_src = {
 648         .cmd_rcgr = 0x55000,
 649         .mnd_width = 0,
 650         .hid_width = 5,
 651         .parent_map = gcc_parent_map_11,
 652         .freq_tbl = ftbl_gcc_camss_csiphy_clk_src,
 653         .clkr.hw.init = &(struct clk_init_data){
 654                 .name = "gcc_camss_csiphy_clk_src",
 655                 .parent_data = gcc_parent_data_11,
 656                 .num_parents = ARRAY_SIZE(gcc_parent_data_11),
 657                 .ops = &clk_rcg2_ops,
 658         },
 659 };
 660
 661 static const struct freq_tbl ftbl_gcc_camss_gp0_clk_src[] = {
 662         F(50000000, P_GPLL0_OUT_EARLY, 12, 0, 0),
 663         F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
 664         F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
 665         { }
 666 };
 667
 668 static struct clk_rcg2 gcc_camss_gp0_clk_src = {
 669         .cmd_rcgr = 0x50000,
 670         .mnd_width = 8,
 671         .hid_width = 5,
 672         .parent_map = gcc_parent_map_7,
 673         .freq_tbl = ftbl_gcc_camss_gp0_clk_src,
 674         .clkr.hw.init = &(struct clk_init_data){
 675                 .name = "gcc_camss_gp0_clk_src",
 676                 .parent_data = gcc_parent_data_7,
 677                 .num_parents = ARRAY_SIZE(gcc_parent_data_7),
 678                 .ops = &clk_rcg2_ops,
 679         },
 680 };
 681
 682 static struct clk_rcg2 gcc_camss_gp1_clk_src = {
 683         .cmd_rcgr = 0x5001c,
 684         .mnd_width = 8,
 685         .hid_width = 5,
 686         .parent_map = gcc_parent_map_7,
 687         .freq_tbl = ftbl_gcc_camss_gp0_clk_src,
 688         .clkr.hw.init = &(struct clk_init_data){
 689                 .name = "gcc_camss_gp1_clk_src",
 690                 .parent_data = gcc_parent_data_7,
 691                 .num_parents = ARRAY_SIZE(gcc_parent_data_7),
 692                 .ops = &clk_rcg2_ops,
 693         },
 694 };
 695
 696 static const struct freq_tbl ftbl_gcc_camss_jpeg_clk_src[] = {
 697         F(66666667, P_GPLL0_OUT_EARLY, 9, 0, 0),
 698         F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0),
 699         F(219428571, P_GPLL6_OUT_EARLY, 3.5, 0, 0),
 700         F(320000000, P_GPLL8_OUT_EARLY, 3, 0, 0),
 701         F(480000000, P_GPLL8_OUT_EARLY, 2, 0, 0),
 702         { }
 703 };
 704
 705 static struct clk_rcg2 gcc_camss_jpeg_clk_src = {
 706         .cmd_rcgr = 0x52028,
 707         .mnd_width = 0,
 708         .hid_width = 5,
 709         .parent_map = gcc_parent_map_12,
 710         .freq_tbl = ftbl_gcc_camss_jpeg_clk_src,
 711         .clkr.hw.init = &(struct clk_init_data){
 712                 .name = "gcc_camss_jpeg_clk_src",
 713                 .parent_data = gcc_parent_data_12,
 714                 .num_parents = ARRAY_SIZE(gcc_parent_data_12),
 715                 .ops = &clk_rcg2_ops,
 716         },
 717 };
 718
 719 static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = {
 720         F(19200000, P_BI_TCXO, 1, 0, 0),
 721         F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 24),
 722         F(64000000, P_GPLL9_OUT_MAIN, 1, 1, 9),
 723         { }
 724 };
 725
 726 static struct clk_rcg2 gcc_camss_mclk0_clk_src = {
 727         .cmd_rcgr = 0x51000,
 728         .mnd_width = 8,
 729         .hid_width = 5,
 730         .parent_map = gcc_parent_map_4,
 731         .freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
 732         .clkr.hw.init = &(struct clk_init_data){
 733                 .name = "gcc_camss_mclk0_clk_src",
 734                 .parent_data = gcc_parent_data_4,
 735                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 736                 .ops = &clk_rcg2_ops,
 737         },
 738 };
 739
 740 static struct clk_rcg2 gcc_camss_mclk1_clk_src = {
 741         .cmd_rcgr = 0x5101c,
 742         .mnd_width = 8,
 743         .hid_width = 5,
 744         .parent_map = gcc_parent_map_4,
 745         .freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
 746         .clkr.hw.init = &(struct clk_init_data){
 747                 .name = "gcc_camss_mclk1_clk_src",
 748                 .parent_data = gcc_parent_data_4,
 749                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 750                 .ops = &clk_rcg2_ops,
 751         },
 752 };
 753
 754 static struct clk_rcg2 gcc_camss_mclk2_clk_src = {
 755         .cmd_rcgr = 0x51038,
 756         .mnd_width = 8,
 757         .hid_width = 5,
 758         .parent_map = gcc_parent_map_4,
 759         .freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
 760         .clkr.hw.init = &(struct clk_init_data){
 761                 .name = "gcc_camss_mclk2_clk_src",
 762                 .parent_data = gcc_parent_data_4,
 763                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 764                 .ops = &clk_rcg2_ops,
 765         },
 766 };
 767
 768 static struct clk_rcg2 gcc_camss_mclk3_clk_src = {
 769         .cmd_rcgr = 0x51054,
 770         .mnd_width = 8,
 771         .hid_width = 5,
 772         .parent_map = gcc_parent_map_4,
 773         .freq_tbl = ftbl_gcc_camss_mclk0_clk_src,
 774         .clkr.hw.init = &(struct clk_init_data){
 775                 .name = "gcc_camss_mclk3_clk_src",
 776                 .parent_data = gcc_parent_data_4,
 777                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 778                 .ops = &clk_rcg2_ops,
 779         },
 780 };
 781
 782 static const struct freq_tbl ftbl_gcc_camss_vfe0_clk_src[] = {
 783         F(120000000, P_GPLL8_OUT_MAIN, 4, 0, 0),
 784         F(256000000, P_GPLL6_OUT_EARLY, 3, 0, 0),
 785         F(403200000, P_GPLL4_OUT_MAIN, 2, 0, 0),
 786         F(480000000, P_GPLL8_OUT_MAIN, 1, 0, 0),
 787         F(533000000, P_GPLL3_OUT_EARLY, 2, 0, 0),
 788         F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0),
 789         { }
 790 };
 791
 792 static struct clk_rcg2 gcc_camss_vfe0_clk_src = {
 793         .cmd_rcgr = 0x54010,
 794         .mnd_width = 0,
 795         .hid_width = 5,
 796         .parent_map = gcc_parent_map_8,
 797         .freq_tbl = ftbl_gcc_camss_vfe0_clk_src,
 798         .clkr.hw.init = &(struct clk_init_data){
 799                 .name = "gcc_camss_vfe0_clk_src",
 800                 .parent_data = gcc_parent_data_8,
 801                 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
 802                 .ops = &clk_rcg2_ops,
 803         },
 804 };
 805
 806 static struct clk_rcg2 gcc_camss_vfe1_clk_src = {
 807         .cmd_rcgr = 0x54048,
 808         .mnd_width = 0,
 809         .hid_width = 5,
 810         .parent_map = gcc_parent_map_8,
 811         .freq_tbl = ftbl_gcc_camss_vfe0_clk_src,
 812         .clkr.hw.init = &(struct clk_init_data){
 813                 .name = "gcc_camss_vfe1_clk_src",
 814                 .parent_data = gcc_parent_data_8,
 815                 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
 816                 .ops = &clk_rcg2_ops,
 817         },
 818 };
 819
 820 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 821         F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
 822         F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
 823         F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
 824         F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
 825         { }
 826 };
 827
 828 static struct clk_rcg2 gcc_gp1_clk_src = {
 829         .cmd_rcgr = 0x4d004,
 830         .mnd_width = 8,
 831         .hid_width = 5,
 832         .parent_map = gcc_parent_map_2,
 833         .freq_tbl = ftbl_gcc_gp1_clk_src,
 834         .clkr.hw.init = &(struct clk_init_data){
 835                 .name = "gcc_gp1_clk_src",
 836                 .parent_data = gcc_parent_data_2,
 837                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 838                 .ops = &clk_rcg2_ops,
 839         },
 840 };
 841
 842 static struct clk_rcg2 gcc_gp2_clk_src = {
 843         .cmd_rcgr = 0x4e004,
 844         .mnd_width = 8,
 845         .hid_width = 5,
 846         .parent_map = gcc_parent_map_2,
 847         .freq_tbl = ftbl_gcc_gp1_clk_src,
 848         .clkr.hw.init = &(struct clk_init_data){
 849                 .name = "gcc_gp2_clk_src",
 850                 .parent_data = gcc_parent_data_2,
 851                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 852                 .ops = &clk_rcg2_ops,
 853         },
 854 };
 855
 856 static struct clk_rcg2 gcc_gp3_clk_src = {
 857         .cmd_rcgr = 0x4f004,
 858         .mnd_width = 8,
 859         .hid_width = 5,
 860         .parent_map = gcc_parent_map_2,
 861         .freq_tbl = ftbl_gcc_gp1_clk_src,
 862         .clkr.hw.init = &(struct clk_init_data){
 863                 .name = "gcc_gp3_clk_src",
 864                 .parent_data = gcc_parent_data_2,
 865                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 866                 .ops = &clk_rcg2_ops,
 867         },
 868 };
 869
 870 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
 871         F(19200000, P_BI_TCXO, 1, 0, 0),
 872         F(60000000, P_GPLL0_OUT_EARLY, 10, 0, 0),
 873         { }
 874 };
 875
 876 static struct clk_rcg2 gcc_pdm2_clk_src = {
 877         .cmd_rcgr = 0x20010,
 878         .mnd_width = 0,
 879         .hid_width = 5,
 880         .parent_map = gcc_parent_map_0,
 881         .freq_tbl = ftbl_gcc_pdm2_clk_src,
 882         .clkr.hw.init = &(struct clk_init_data){
 883                 .name = "gcc_pdm2_clk_src",
 884                 .parent_data = gcc_parent_data_0,
 885                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 886                 .ops = &clk_rcg2_ops,
 887         },
 888 };
 889
 890 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
 891         F(7372800, P_GPLL0_OUT_AUX2, 1, 384, 15625),
 892         F(14745600, P_GPLL0_OUT_AUX2, 1, 768, 15625),
 893         F(19200000, P_BI_TCXO, 1, 0, 0),
 894         F(29491200, P_GPLL0_OUT_AUX2, 1, 1536, 15625),
 895         F(32000000, P_GPLL0_OUT_AUX2, 1, 8, 75),
 896         F(48000000, P_GPLL0_OUT_AUX2, 1, 4, 25),
 897         F(64000000, P_GPLL0_OUT_AUX2, 1, 16, 75),
 898         F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
 899         F(80000000, P_GPLL0_OUT_AUX2, 1, 4, 15),
 900         F(96000000, P_GPLL0_OUT_AUX2, 1, 8, 25),
 901         F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
 902         F(102400000, P_GPLL0_OUT_AUX2, 1, 128, 375),
 903         F(112000000, P_GPLL0_OUT_AUX2, 1, 28, 75),
 904         F(117964800, P_GPLL0_OUT_AUX2, 1, 6144, 15625),
 905         F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0),
 906         F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
 907         { }
 908 };
 909
 910 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
 911         .name = "gcc_qupv3_wrap0_s0_clk_src",
 912         .parent_data = gcc_parent_data_1,
 913         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 914         .ops = &clk_rcg2_ops,
 915 };
 916
 917 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
 918         .cmd_rcgr = 0x1f148,
 919         .mnd_width = 16,
 920         .hid_width = 5,
 921         .parent_map = gcc_parent_map_1,
 922         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 923         .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
 924 };
 925
 926 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
 927         .name = "gcc_qupv3_wrap0_s1_clk_src",
 928         .parent_data = gcc_parent_data_1,
 929         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 930         .ops = &clk_rcg2_ops,
 931 };
 932
 933 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
 934         .cmd_rcgr = 0x1f278,
 935         .mnd_width = 16,
 936         .hid_width = 5,
 937         .parent_map = gcc_parent_map_1,
 938         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 939         .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
 940 };
 941
 942 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
 943         .name = "gcc_qupv3_wrap0_s2_clk_src",
 944         .parent_data = gcc_parent_data_1,
 945         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 946         .ops = &clk_rcg2_ops,
 947 };
 948
 949 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
 950         .cmd_rcgr = 0x1f3a8,
 951         .mnd_width = 16,
 952         .hid_width = 5,
 953         .parent_map = gcc_parent_map_1,
 954         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 955         .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
 956 };
 957
 958 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
 959         .name = "gcc_qupv3_wrap0_s3_clk_src",
 960         .parent_data = gcc_parent_data_1,
 961         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 962         .ops = &clk_rcg2_ops,
 963 };
 964
 965 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
 966         .cmd_rcgr = 0x1f4d8,
 967         .mnd_width = 16,
 968         .hid_width = 5,
 969         .parent_map = gcc_parent_map_1,
 970         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 971         .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
 972 };
 973
 974 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
 975         .name = "gcc_qupv3_wrap0_s4_clk_src",
 976         .parent_data = gcc_parent_data_1,
 977         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 978         .ops = &clk_rcg2_ops,
 979 };
 980
 981 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
 982         .cmd_rcgr = 0x1f608,
 983         .mnd_width = 16,
 984         .hid_width = 5,
 985         .parent_map = gcc_parent_map_1,
 986         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 987         .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
 988 };
 989
 990 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
 991         .name = "gcc_qupv3_wrap0_s5_clk_src",
 992         .parent_data = gcc_parent_data_1,
 993         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 994         .ops = &clk_rcg2_ops,
 995 };
 996
 997 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
 998         .cmd_rcgr = 0x1f738,
 999         .mnd_width = 16,
1000         .hid_width = 5,
1001         .parent_map = gcc_parent_map_1,
1002         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1003         .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
1004 };
1005
1006 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
1007         .name = "gcc_qupv3_wrap1_s0_clk_src",
1008         .parent_data = gcc_parent_data_1,
1009         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1010         .ops = &clk_rcg2_ops,
1011 };
1012
1013 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
1014         .cmd_rcgr = 0x39148,
1015         .mnd_width = 16,
1016         .hid_width = 5,
1017         .parent_map = gcc_parent_map_1,
1018         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1019         .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
1020 };
1021
1022 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
1023         .name = "gcc_qupv3_wrap1_s1_clk_src",
1024         .parent_data = gcc_parent_data_1,
1025         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1026         .ops = &clk_rcg2_ops,
1027 };
1028
1029 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
1030         .cmd_rcgr = 0x39278,
1031         .mnd_width = 16,
1032         .hid_width = 5,
1033         .parent_map = gcc_parent_map_1,
1034         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1035         .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
1036 };
1037
1038 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
1039         .name = "gcc_qupv3_wrap1_s2_clk_src",
1040         .parent_data = gcc_parent_data_1,
1041         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1042         .ops = &clk_rcg2_ops,
1043 };
1044
1045 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
1046         .cmd_rcgr = 0x393a8,
1047         .mnd_width = 16,
1048         .hid_width = 5,
1049         .parent_map = gcc_parent_map_1,
1050         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1051         .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
1052 };
1053
1054 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
1055         .name = "gcc_qupv3_wrap1_s3_clk_src",
1056         .parent_data = gcc_parent_data_1,
1057         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1058         .ops = &clk_rcg2_ops,
1059 };
1060
1061 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
1062         .cmd_rcgr = 0x394d8,
1063         .mnd_width = 16,
1064         .hid_width = 5,
1065         .parent_map = gcc_parent_map_1,
1066         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1067         .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
1068 };
1069
1070 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
1071         .name = "gcc_qupv3_wrap1_s4_clk_src",
1072         .parent_data = gcc_parent_data_1,
1073         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1074         .ops = &clk_rcg2_ops,
1075 };
1076
1077 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
1078         .cmd_rcgr = 0x39608,
1079         .mnd_width = 16,
1080         .hid_width = 5,
1081         .parent_map = gcc_parent_map_1,
1082         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1083         .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
1084 };
1085
1086 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
1087         .name = "gcc_qupv3_wrap1_s5_clk_src",
1088         .parent_data = gcc_parent_data_1,
1089         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1090         .ops = &clk_rcg2_ops,
1091 };
1092
1093 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
1094         .cmd_rcgr = 0x39738,
1095         .mnd_width = 16,
1096         .hid_width = 5,
1097         .parent_map = gcc_parent_map_1,
1098         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1099         .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
1100 };
1101
1102 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
1103         F(144000, P_BI_TCXO, 16, 3, 25),
1104         F(400000, P_BI_TCXO, 12, 1, 4),
1105         F(20000000, P_GPLL0_OUT_AUX2, 5, 1, 3),
1106         F(25000000, P_GPLL0_OUT_AUX2, 6, 1, 2),
1107         F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1108         F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1109         F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
1110         F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
1111         { }
1112 };
1113
1114 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
1115         .cmd_rcgr = 0x38028,
1116         .mnd_width = 8,
1117         .hid_width = 5,
1118         .parent_map = gcc_parent_map_1,
1119         .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
1120         .clkr.hw.init = &(struct clk_init_data){
1121                 .name = "gcc_sdcc1_apps_clk_src",
1122                 .parent_data = gcc_parent_data_1,
1123                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1124                 .ops = &clk_rcg2_floor_ops,
1125         },
1126 };
1127
1128 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
1129         F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1130         F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0),
1131         F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1132         F(300000000, P_GPLL0_OUT_EARLY, 2, 0, 0),
1133         { }
1134 };
1135
1136 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
1137         .cmd_rcgr = 0x38010,
1138         .mnd_width = 0,
1139         .hid_width = 5,
1140         .parent_map = gcc_parent_map_0,
1141         .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
1142         .clkr.hw.init = &(struct clk_init_data){
1143                 .name = "gcc_sdcc1_ice_core_clk_src",
1144                 .parent_data = gcc_parent_data_0,
1145                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1146                 .ops = &clk_rcg2_ops,
1147         },
1148 };
1149
1150 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
1151         F(400000, P_BI_TCXO, 12, 1, 4),
1152         F(19200000, P_BI_TCXO, 1, 0, 0),
1153         F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1154         F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1155         F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1156         F(202000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
1157         { }
1158 };
1159
1160 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
1161         .cmd_rcgr = 0x1e00c,
1162         .mnd_width = 8,
1163         .hid_width = 5,
1164         .parent_map = gcc_parent_map_13,
1165         .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
1166         .clkr.hw.init = &(struct clk_init_data){
1167                 .name = "gcc_sdcc2_apps_clk_src",
1168                 .parent_data = gcc_parent_data_13,
1169                 .num_parents = ARRAY_SIZE(gcc_parent_data_13),
1170                 .ops = &clk_rcg2_floor_ops,
1171         },
1172 };
1173
1174 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
1175         F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1176         F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1177         F(100000000, P_GPLL0_OUT_EARLY, 6, 0, 0),
1178         F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1179         F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1180         { }
1181 };
1182
1183 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1184         .cmd_rcgr = 0x45020,
1185         .mnd_width = 8,
1186         .hid_width = 5,
1187         .parent_map = gcc_parent_map_0,
1188         .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
1189         .clkr.hw.init = &(struct clk_init_data){
1190                 .name = "gcc_ufs_phy_axi_clk_src",
1191                 .parent_data = gcc_parent_data_0,
1192                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1193                 .ops = &clk_rcg2_ops,
1194         },
1195 };
1196
1197 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
1198         F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
1199         F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1200         F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0),
1201         F(300000000, P_GPLL0_OUT_EARLY, 2, 0, 0),
1202         { }
1203 };
1204
1205 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1206         .cmd_rcgr = 0x45048,
1207         .mnd_width = 0,
1208         .hid_width = 5,
1209         .parent_map = gcc_parent_map_0,
1210         .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1211         .clkr.hw.init = &(struct clk_init_data){
1212                 .name = "gcc_ufs_phy_ice_core_clk_src",
1213                 .parent_data = gcc_parent_data_0,
1214                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1215                 .ops = &clk_rcg2_ops,
1216         },
1217 };
1218
1219 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
1220         F(9600000, P_BI_TCXO, 2, 0, 0),
1221         F(19200000, P_BI_TCXO, 1, 0, 0),
1222         { }
1223 };
1224
1225 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1226         .cmd_rcgr = 0x4507c,
1227         .mnd_width = 0,
1228         .hid_width = 5,
1229         .parent_map = gcc_parent_map_0,
1230         .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
1231         .clkr.hw.init = &(struct clk_init_data){
1232                 .name = "gcc_ufs_phy_phy_aux_clk_src",
1233                 .parent_data = gcc_parent_data_0,
1234                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1235                 .ops = &clk_rcg2_ops,
1236         },
1237 };
1238
1239 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
1240         F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
1241         F(75000000, P_GPLL0_OUT_EARLY, 8, 0, 0),
1242         F(150000000, P_GPLL0_OUT_EARLY, 4, 0, 0),
1243         { }
1244 };
1245
1246 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1247         .cmd_rcgr = 0x45060,
1248         .mnd_width = 0,
1249         .hid_width = 5,
1250         .parent_map = gcc_parent_map_0,
1251         .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
1252         .clkr.hw.init = &(struct clk_init_data){
1253                 .name = "gcc_ufs_phy_unipro_core_clk_src",
1254                 .parent_data = gcc_parent_data_0,
1255                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1256                 .ops = &clk_rcg2_ops,
1257         },
1258 };
1259
1260 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1261         F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0),
1262         F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0),
1263         F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1264         F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1265         { }
1266 };
1267
1268 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1269         .cmd_rcgr = 0x1a01c,
1270         .mnd_width = 8,
1271         .hid_width = 5,
1272         .parent_map = gcc_parent_map_0,
1273         .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1274         .clkr.hw.init = &(struct clk_init_data){
1275                 .name = "gcc_usb30_prim_master_clk_src",
1276                 .parent_data = gcc_parent_data_0,
1277                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1278                 .ops = &clk_rcg2_ops,
1279         },
1280 };
1281
1282 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
1283         F(19200000, P_BI_TCXO, 1, 0, 0),
1284         F(20000000, P_GPLL0_OUT_AUX2, 15, 0, 0),
1285         F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0),
1286         F(60000000, P_GPLL0_OUT_EARLY, 10, 0, 0),
1287         { }
1288 };
1289
1290 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1291         .cmd_rcgr = 0x1a034,
1292         .mnd_width = 0,
1293         .hid_width = 5,
1294         .parent_map = gcc_parent_map_0,
1295         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1296         .clkr.hw.init = &(struct clk_init_data){
1297                 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1298                 .parent_data = gcc_parent_data_0,
1299                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1300                 .ops = &clk_rcg2_ops,
1301         },
1302 };
1303
1304 static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = {
1305         F(19200000, P_BI_TCXO, 1, 0, 0),
1306         { }
1307 };
1308
1309 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1310         .cmd_rcgr = 0x1a060,
1311         .mnd_width = 0,
1312         .hid_width = 5,
1313         .parent_map = gcc_parent_map_14,
1314         .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src,
1315         .clkr.hw.init = &(struct clk_init_data){
1316                 .name = "gcc_usb3_prim_phy_aux_clk_src",
1317                 .parent_data = gcc_parent_data_14,
1318                 .num_parents = ARRAY_SIZE(gcc_parent_data_14),
1319                 .ops = &clk_rcg2_ops,
1320         },
1321 };
1322
1323 static struct clk_rcg2 gcc_vs_ctrl_clk_src = {
1324         .cmd_rcgr = 0x42030,
1325         .mnd_width = 0,
1326         .hid_width = 5,
1327         .parent_map = gcc_parent_map_5,
1328         .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src,
1329         .clkr.hw.init = &(struct clk_init_data){
1330                 .name = "gcc_vs_ctrl_clk_src",
1331                 .parent_data = gcc_parent_data_5,
1332                 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
1333                 .ops = &clk_rcg2_ops,
1334         },
1335 };
1336
1337 static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = {
1338         F(19200000, P_BI_TCXO, 1, 0, 0),
1339         F(400000000, P_GPLL0_OUT_EARLY, 1.5, 0, 0),
1340         F(600000000, P_GPLL0_OUT_EARLY, 1, 0, 0),
1341         { }
1342 };
1343
1344 static struct clk_rcg2 gcc_vsensor_clk_src = {
1345         .cmd_rcgr = 0x42018,
1346         .mnd_width = 0,
1347         .hid_width = 5,
1348         .parent_map = gcc_parent_map_5,
1349         .freq_tbl = ftbl_gcc_vsensor_clk_src,
1350         .clkr.hw.init = &(struct clk_init_data){
1351                 .name = "gcc_vsensor_clk_src",
1352                 .parent_data = gcc_parent_data_5,
1353                 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
1354                 .ops = &clk_rcg2_ops,
1355         },
1356 };
1357
1358 static struct clk_branch gcc_ahb2phy_csi_clk = {
1359         .halt_reg = 0x1d004,
1360         .halt_check = BRANCH_HALT,
1361         .hwcg_reg = 0x1d004,
1362         .hwcg_bit = 1,
1363         .clkr = {
1364                 .enable_reg = 0x1d004,
1365                 .enable_mask = BIT(0),
1366                 .hw.init = &(struct clk_init_data){
1367                         .name = "gcc_ahb2phy_csi_clk",
1368                         .ops = &clk_branch2_ops,
1369                 },
1370         },
1371 };
1372
1373 static struct clk_branch gcc_ahb2phy_usb_clk = {
1374         .halt_reg = 0x1d008,
1375         .halt_check = BRANCH_HALT,
1376         .hwcg_reg = 0x1d008,
1377         .hwcg_bit = 1,
1378         .clkr = {
1379                 .enable_reg = 0x1d008,
1380                 .enable_mask = BIT(0),
1381                 .hw.init = &(struct clk_init_data){
1382                         .name = "gcc_ahb2phy_usb_clk",
1383                         .ops = &clk_branch2_ops,
1384                 },
1385         },
1386 };
1387
1388 static struct clk_branch gcc_apc_vs_clk = {
1389         .halt_reg = 0x4204c,
1390         .halt_check = BRANCH_HALT,
1391         .clkr = {
1392                 .enable_reg = 0x4204c,
1393                 .enable_mask = BIT(0),
1394                 .hw.init = &(struct clk_init_data){
1395                         .name = "gcc_apc_vs_clk",
1396                         .parent_hws = (const struct clk_hw*[]){
1397                                 &gcc_vsensor_clk_src.clkr.hw,
1398                         },
1399                         .num_parents = 1,
1400                         .flags = CLK_SET_RATE_PARENT,
1401                         .ops = &clk_branch2_ops,
1402                 },
1403         },
1404 };
1405
1406 static struct clk_branch gcc_bimc_gpu_axi_clk = {
1407         .halt_reg = 0x71154,
1408         .halt_check = BRANCH_HALT_DELAY,
1409         .clkr = {
1410                 .enable_reg = 0x71154,
1411                 .enable_mask = BIT(0),
1412                 .hw.init = &(struct clk_init_data){
1413                         .name = "gcc_bimc_gpu_axi_clk",
1414                         .ops = &clk_branch2_ops,
1415                 },
1416         },
1417 };
1418
1419 static struct clk_branch gcc_boot_rom_ahb_clk = {
1420         .halt_reg = 0x23004,
1421         .halt_check = BRANCH_HALT_VOTED,
1422         .hwcg_reg = 0x23004,
1423         .hwcg_bit = 1,
1424         .clkr = {
1425                 .enable_reg = 0x79004,
1426                 .enable_mask = BIT(10),
1427                 .hw.init = &(struct clk_init_data){
1428                         .name = "gcc_boot_rom_ahb_clk",
1429                         .ops = &clk_branch2_ops,
1430                 },
1431         },
1432 };
1433
1434 static struct clk_branch gcc_camera_ahb_clk = {
1435         .halt_reg = 0x17008,
1436         .halt_check = BRANCH_HALT_DELAY,
1437         .hwcg_reg = 0x17008,
1438         .hwcg_bit = 1,
1439         .clkr = {
1440                 .enable_reg = 0x17008,
1441                 .enable_mask = BIT(0),
1442                 .hw.init = &(struct clk_init_data){
1443                         .name = "gcc_camera_ahb_clk",
1444                         .flags = CLK_IS_CRITICAL,
1445                         .ops = &clk_branch2_ops,
1446                 },
1447         },
1448 };
1449
1450 static struct clk_branch gcc_camera_xo_clk = {
1451         .halt_reg = 0x17028,
1452         .halt_check = BRANCH_HALT,
1453         .clkr = {
1454                 .enable_reg = 0x17028,
1455                 .enable_mask = BIT(0),
1456                 .hw.init = &(struct clk_init_data){
1457                         .name = "gcc_camera_xo_clk",
1458                         .flags = CLK_IS_CRITICAL,
1459                         .ops = &clk_branch2_ops,
1460                 },
1461         },
1462 };
1463
1464 static struct clk_branch gcc_camss_cci_ahb_clk = {
1465         .halt_reg = 0x52020,
1466         .halt_check = BRANCH_HALT,
1467         .clkr = {
1468                 .enable_reg = 0x52020,
1469                 .enable_mask = BIT(0),
1470                 .hw.init = &(struct clk_init_data){
1471                         .name = "gcc_camss_cci_ahb_clk",
1472                         .parent_hws = (const struct clk_hw*[]){
1473                                 &gcc_camss_ahb_clk_src.clkr.hw,
1474                         },
1475                         .num_parents = 1,
1476                         .flags = CLK_SET_RATE_PARENT,
1477                         .ops = &clk_branch2_ops,
1478                 },
1479         },
1480 };
1481
1482 static struct clk_branch gcc_camss_cci_clk = {
1483         .halt_reg = 0x5201c,
1484         .halt_check = BRANCH_HALT,
1485         .clkr = {
1486                 .enable_reg = 0x5201c,
1487                 .enable_mask = BIT(0),
1488                 .hw.init = &(struct clk_init_data){
1489                         .name = "gcc_camss_cci_clk",
1490                         .parent_hws = (const struct clk_hw*[]){
1491                                 &gcc_camss_cci_clk_src.clkr.hw,
1492                         },
1493                         .num_parents = 1,
1494                         .flags = CLK_SET_RATE_PARENT,
1495                         .ops = &clk_branch2_ops,
1496                 },
1497         },
1498 };
1499
1500 static struct clk_branch gcc_camss_cphy_csid0_clk = {
1501         .halt_reg = 0x5504c,
1502         .halt_check = BRANCH_HALT,
1503         .clkr = {
1504                 .enable_reg = 0x5504c,
1505                 .enable_mask = BIT(0),
1506                 .hw.init = &(struct clk_init_data){
1507                         .name = "gcc_camss_cphy_csid0_clk",
1508                         .parent_hws = (const struct clk_hw*[]){
1509                                 &gcc_camss_csiphy_clk_src.clkr.hw,
1510                         },
1511                         .num_parents = 1,
1512                         .flags = CLK_SET_RATE_PARENT,
1513                         .ops = &clk_branch2_ops,
1514                 },
1515         },
1516 };
1517
1518 static struct clk_branch gcc_camss_cphy_csid1_clk = {
1519         .halt_reg = 0x55088,
1520         .halt_check = BRANCH_HALT,
1521         .clkr = {
1522                 .enable_reg = 0x55088,
1523                 .enable_mask = BIT(0),
1524                 .hw.init = &(struct clk_init_data){
1525                         .name = "gcc_camss_cphy_csid1_clk",
1526                         .parent_hws = (const struct clk_hw*[]){
1527                                 &gcc_camss_csiphy_clk_src.clkr.hw,
1528                         },
1529                         .num_parents = 1,
1530                         .flags = CLK_SET_RATE_PARENT,
1531                         .ops = &clk_branch2_ops,
1532                 },
1533         },
1534 };
1535
1536 static struct clk_branch gcc_camss_cphy_csid2_clk = {
1537         .halt_reg = 0x550c0,
1538         .halt_check = BRANCH_HALT,
1539         .clkr = {
1540                 .enable_reg = 0x550c0,
1541                 .enable_mask = BIT(0),
1542                 .hw.init = &(struct clk_init_data){
1543                         .name = "gcc_camss_cphy_csid2_clk",
1544                         .parent_hws = (const struct clk_hw*[]){
1545                                 &gcc_camss_csiphy_clk_src.clkr.hw,
1546                         },
1547                         .num_parents = 1,
1548                         .flags = CLK_SET_RATE_PARENT,
1549                         .ops = &clk_branch2_ops,
1550                 },
1551         },
1552 };
1553
1554 static struct clk_branch gcc_camss_cphy_csid3_clk = {
1555         .halt_reg = 0x550fc,
1556         .halt_check = BRANCH_HALT,
1557         .clkr = {
1558                 .enable_reg = 0x550fc,
1559                 .enable_mask = BIT(0),
1560                 .hw.init = &(struct clk_init_data){
1561                         .name = "gcc_camss_cphy_csid3_clk",
1562                         .parent_hws = (const struct clk_hw*[]){
1563                                 &gcc_camss_csiphy_clk_src.clkr.hw,
1564                         },
1565                         .num_parents = 1,
1566                         .flags = CLK_SET_RATE_PARENT,
1567                         .ops = &clk_branch2_ops,
1568                 },
1569         },
1570 };
1571
1572 static struct clk_branch gcc_camss_cpp_ahb_clk = {
1573         .halt_reg = 0x560e8,
1574         .halt_check = BRANCH_HALT,
1575         .clkr = {
1576                 .enable_reg = 0x560e8,
1577                 .enable_mask = BIT(0),
1578                 .hw.init = &(struct clk_init_data){
1579                         .name = "gcc_camss_cpp_ahb_clk",
1580                         .parent_hws = (const struct clk_hw*[]){
1581                                 &gcc_camss_ahb_clk_src.clkr.hw,
1582                         },
1583                         .num_parents = 1,
1584                         .flags = CLK_SET_RATE_PARENT,
1585                         .ops = &clk_branch2_ops,
1586                 },
1587         },
1588 };
1589
1590 static struct clk_branch gcc_camss_cpp_axi_clk = {
1591         .halt_reg = 0x560f4,
1592         .halt_check = BRANCH_HALT,
1593         .clkr = {
1594                 .enable_reg = 0x560f4,
1595                 .enable_mask = BIT(0),
1596                 .hw.init = &(struct clk_init_data){
1597                         .name = "gcc_camss_cpp_axi_clk",
1598                         .ops = &clk_branch2_ops,
1599                 },
1600         },
1601 };
1602
1603 static struct clk_branch gcc_camss_cpp_clk = {
1604         .halt_reg = 0x560e0,
1605         .halt_check = BRANCH_HALT,
1606         .clkr = {
1607                 .enable_reg = 0x560e0,
1608                 .enable_mask = BIT(0),
1609                 .hw.init = &(struct clk_init_data){
1610                         .name = "gcc_camss_cpp_clk",
1611                         .parent_hws = (const struct clk_hw*[]){
1612                                 &gcc_camss_cpp_clk_src.clkr.hw,
1613                         },
1614                         .num_parents = 1,
1615                         .flags = CLK_SET_RATE_PARENT,
1616                         .ops = &clk_branch2_ops,
1617                 },
1618         },
1619 };
1620
1621 static struct clk_branch gcc_camss_cpp_vbif_ahb_clk = {
1622         .halt_reg = 0x560f0,
1623         .halt_check = BRANCH_HALT,
1624         .clkr = {
1625                 .enable_reg = 0x560f0,
1626                 .enable_mask = BIT(0),
1627                 .hw.init = &(struct clk_init_data){
1628                         .name = "gcc_camss_cpp_vbif_ahb_clk",
1629                         .parent_hws = (const struct clk_hw*[]){
1630                                 &gcc_camss_ahb_clk_src.clkr.hw,
1631                         },
1632                         .num_parents = 1,
1633                         .flags = CLK_SET_RATE_PARENT,
1634                         .ops = &clk_branch2_ops,
1635                 },
1636         },
1637 };
1638
1639 static struct clk_branch gcc_camss_csi0_ahb_clk = {
1640         .halt_reg = 0x55050,
1641         .halt_check = BRANCH_HALT,
1642         .clkr = {
1643                 .enable_reg = 0x55050,
1644                 .enable_mask = BIT(0),
1645                 .hw.init = &(struct clk_init_data){
1646                         .name = "gcc_camss_csi0_ahb_clk",
1647                         .parent_hws = (const struct clk_hw*[]){
1648                                 &gcc_camss_ahb_clk_src.clkr.hw,
1649                         },
1650                         .num_parents = 1,
1651                         .flags = CLK_SET_RATE_PARENT,
1652                         .ops = &clk_branch2_ops,
1653                 },
1654         },
1655 };
1656
1657 static struct clk_branch gcc_camss_csi0_clk = {
1658         .halt_reg = 0x55048,
1659         .halt_check = BRANCH_HALT,
1660         .clkr = {
1661                 .enable_reg = 0x55048,
1662                 .enable_mask = BIT(0),
1663                 .hw.init = &(struct clk_init_data){
1664                         .name = "gcc_camss_csi0_clk",
1665                         .parent_hws = (const struct clk_hw*[]){
1666                                 &gcc_camss_csi0_clk_src.clkr.hw,
1667                         },
1668                         .num_parents = 1,
1669                         .flags = CLK_SET_RATE_PARENT,
1670                         .ops = &clk_branch2_ops,
1671                 },
1672         },
1673 };
1674
1675 static struct clk_branch gcc_camss_csi0phytimer_clk = {
1676         .halt_reg = 0x5301c,
1677         .halt_check = BRANCH_HALT,
1678         .clkr = {
1679                 .enable_reg = 0x5301c,
1680                 .enable_mask = BIT(0),
1681                 .hw.init = &(struct clk_init_data){
1682                         .name = "gcc_camss_csi0phytimer_clk",
1683                         .parent_hws = (const struct clk_hw*[]){
1684                                 &gcc_camss_csi0phytimer_clk_src.clkr.hw,
1685                         },
1686                         .num_parents = 1,
1687                         .flags = CLK_SET_RATE_PARENT,
1688                         .ops = &clk_branch2_ops,
1689                 },
1690         },
1691 };
1692
1693 static struct clk_branch gcc_camss_csi0pix_clk = {
1694         .halt_reg = 0x55060,
1695         .halt_check = BRANCH_HALT,
1696         .clkr = {
1697                 .enable_reg = 0x55060,
1698                 .enable_mask = BIT(0),
1699                 .hw.init = &(struct clk_init_data){
1700                         .name = "gcc_camss_csi0pix_clk",
1701                         .parent_hws = (const struct clk_hw*[]){
1702                                 &gcc_camss_csi0_clk_src.clkr.hw,
1703                         },
1704                         .num_parents = 1,
1705                         .flags = CLK_SET_RATE_PARENT,
1706                         .ops = &clk_branch2_ops,
1707                 },
1708         },
1709 };
1710
1711 static struct clk_branch gcc_camss_csi0rdi_clk = {
1712         .halt_reg = 0x55058,
1713         .halt_check = BRANCH_HALT,
1714         .clkr = {
1715                 .enable_reg = 0x55058,
1716                 .enable_mask = BIT(0),
1717                 .hw.init = &(struct clk_init_data){
1718                         .name = "gcc_camss_csi0rdi_clk",
1719                         .parent_hws = (const struct clk_hw*[]){
1720                                 &gcc_camss_csi0_clk_src.clkr.hw,
1721                         },
1722                         .num_parents = 1,
1723                         .flags = CLK_SET_RATE_PARENT,
1724                         .ops = &clk_branch2_ops,
1725                 },
1726         },
1727 };
1728
1729 static struct clk_branch gcc_camss_csi1_ahb_clk = {
1730         .halt_reg = 0x5508c,
1731         .halt_check = BRANCH_HALT,
1732         .clkr = {
1733                 .enable_reg = 0x5508c,
1734                 .enable_mask = BIT(0),
1735                 .hw.init = &(struct clk_init_data){
1736                         .name = "gcc_camss_csi1_ahb_clk",
1737                         .parent_hws = (const struct clk_hw*[]){
1738                                 &gcc_camss_ahb_clk_src.clkr.hw,
1739                         },
1740                         .num_parents = 1,
1741                         .flags = CLK_SET_RATE_PARENT,
1742                         .ops = &clk_branch2_ops,
1743                 },
1744         },
1745 };
1746
1747 static struct clk_branch gcc_camss_csi1_clk = {
1748         .halt_reg = 0x55084,
1749         .halt_check = BRANCH_HALT,
1750         .clkr = {
1751                 .enable_reg = 0x55084,
1752                 .enable_mask = BIT(0),
1753                 .hw.init = &(struct clk_init_data){
1754                         .name = "gcc_camss_csi1_clk",
1755                         .parent_hws = (const struct clk_hw*[]){
1756                                 &gcc_camss_csi1_clk_src.clkr.hw,
1757                         },
1758                         .num_parents = 1,
1759                         .flags = CLK_SET_RATE_PARENT,
1760                         .ops = &clk_branch2_ops,
1761                 },
1762         },
1763 };
1764
1765 static struct clk_branch gcc_camss_csi1phytimer_clk = {
1766         .halt_reg = 0x5303c,
1767         .halt_check = BRANCH_HALT,
1768         .clkr = {
1769                 .enable_reg = 0x5303c,
1770                 .enable_mask = BIT(0),
1771                 .hw.init = &(struct clk_init_data){
1772                         .name = "gcc_camss_csi1phytimer_clk",
1773                         .parent_hws = (const struct clk_hw*[]){
1774                                 &gcc_camss_csi1phytimer_clk_src.clkr.hw,
1775                         },
1776                         .num_parents = 1,
1777                         .flags = CLK_SET_RATE_PARENT,
1778                         .ops = &clk_branch2_ops,
1779                 },
1780         },
1781 };
1782
1783 static struct clk_branch gcc_camss_csi1pix_clk = {
1784         .halt_reg = 0x5509c,
1785         .halt_check = BRANCH_HALT,
1786         .clkr = {
1787                 .enable_reg = 0x5509c,
1788                 .enable_mask = BIT(0),
1789                 .hw.init = &(struct clk_init_data){
1790                         .name = "gcc_camss_csi1pix_clk",
1791                         .parent_hws = (const struct clk_hw*[]){
1792                                 &gcc_camss_csi1_clk_src.clkr.hw,
1793                         },
1794                         .num_parents = 1,
1795                         .flags = CLK_SET_RATE_PARENT,
1796                         .ops = &clk_branch2_ops,
1797                 },
1798         },
1799 };
1800
1801 static struct clk_branch gcc_camss_csi1rdi_clk = {
1802         .halt_reg = 0x55094,
1803         .halt_check = BRANCH_HALT,
1804         .clkr = {
1805                 .enable_reg = 0x55094,
1806                 .enable_mask = BIT(0),
1807                 .hw.init = &(struct clk_init_data){
1808                         .name = "gcc_camss_csi1rdi_clk",
1809                         .parent_hws = (const struct clk_hw*[]){
1810                                 &gcc_camss_csi1_clk_src.clkr.hw,
1811                         },
1812                         .num_parents = 1,
1813                         .flags = CLK_SET_RATE_PARENT,
1814                         .ops = &clk_branch2_ops,
1815                 },
1816         },
1817 };
1818
1819 static struct clk_branch gcc_camss_csi2_ahb_clk = {
1820         .halt_reg = 0x550c4,
1821         .halt_check = BRANCH_HALT,
1822         .clkr = {
1823                 .enable_reg = 0x550c4,
1824                 .enable_mask = BIT(0),
1825                 .hw.init = &(struct clk_init_data){
1826                         .name = "gcc_camss_csi2_ahb_clk",
1827                         .parent_hws = (const struct clk_hw*[]){
1828                                 &gcc_camss_ahb_clk_src.clkr.hw,
1829                         },
1830                         .num_parents = 1,
1831                         .flags = CLK_SET_RATE_PARENT,
1832                         .ops = &clk_branch2_ops,
1833                 },
1834         },
1835 };
1836
1837 static struct clk_branch gcc_camss_csi2_clk = {
1838         .halt_reg = 0x550bc,
1839         .halt_check = BRANCH_HALT,
1840         .clkr = {
1841                 .enable_reg = 0x550bc,
1842                 .enable_mask = BIT(0),
1843                 .hw.init = &(struct clk_init_data){
1844                         .name = "gcc_camss_csi2_clk",
1845                         .parent_hws = (const struct clk_hw*[]){
1846                                 &gcc_camss_csi2_clk_src.clkr.hw,
1847                         },
1848                         .num_parents = 1,
1849                         .flags = CLK_SET_RATE_PARENT,
1850                         .ops = &clk_branch2_ops,
1851                 },
1852         },
1853 };
1854
1855 static struct clk_branch gcc_camss_csi2phytimer_clk = {
1856         .halt_reg = 0x5305c,
1857         .halt_check = BRANCH_HALT,
1858         .clkr = {
1859                 .enable_reg = 0x5305c,
1860                 .enable_mask = BIT(0),
1861                 .hw.init = &(struct clk_init_data){
1862                         .name = "gcc_camss_csi2phytimer_clk",
1863                         .parent_hws = (const struct clk_hw*[]){
1864                                 &gcc_camss_csi2phytimer_clk_src.clkr.hw,
1865                         },
1866                         .num_parents = 1,
1867                         .flags = CLK_SET_RATE_PARENT,
1868                         .ops = &clk_branch2_ops,
1869                 },
1870         },
1871 };
1872
1873 static struct clk_branch gcc_camss_csi2pix_clk = {
1874         .halt_reg = 0x550d4,
1875         .halt_check = BRANCH_HALT,
1876         .clkr = {
1877                 .enable_reg = 0x550d4,
1878                 .enable_mask = BIT(0),
1879                 .hw.init = &(struct clk_init_data){
1880                         .name = "gcc_camss_csi2pix_clk",
1881                         .parent_hws = (const struct clk_hw*[]){
1882                                 &gcc_camss_csi2_clk_src.clkr.hw,
1883                         },
1884                         .num_parents = 1,
1885                         .flags = CLK_SET_RATE_PARENT,
1886                         .ops = &clk_branch2_ops,
1887                 },
1888         },
1889 };
1890
1891 static struct clk_branch gcc_camss_csi2rdi_clk = {
1892         .halt_reg = 0x550cc,
1893         .halt_check = BRANCH_HALT,
1894         .clkr = {
1895                 .enable_reg = 0x550cc,
1896                 .enable_mask = BIT(0),
1897                 .hw.init = &(struct clk_init_data){
1898                         .name = "gcc_camss_csi2rdi_clk",
1899                         .parent_hws = (const struct clk_hw*[]){
1900                                 &gcc_camss_csi2_clk_src.clkr.hw,
1901                         },
1902                         .num_parents = 1,
1903                         .flags = CLK_SET_RATE_PARENT,
1904                         .ops = &clk_branch2_ops,
1905                 },
1906         },
1907 };
1908
1909 static struct clk_branch gcc_camss_csi3_ahb_clk = {
1910         .halt_reg = 0x55100,
1911         .halt_check = BRANCH_HALT,
1912         .clkr = {
1913                 .enable_reg = 0x55100,
1914                 .enable_mask = BIT(0),
1915                 .hw.init = &(struct clk_init_data){
1916                         .name = "gcc_camss_csi3_ahb_clk",
1917                         .parent_hws = (const struct clk_hw*[]){
1918                                 &gcc_camss_ahb_clk_src.clkr.hw,
1919                         },
1920                         .num_parents = 1,
1921                         .flags = CLK_SET_RATE_PARENT,
1922                         .ops = &clk_branch2_ops,
1923                 },
1924         },
1925 };
1926
1927 static struct clk_branch gcc_camss_csi3_clk = {
1928         .halt_reg = 0x550f8,
1929         .halt_check = BRANCH_HALT,
1930         .clkr = {
1931                 .enable_reg = 0x550f8,
1932                 .enable_mask = BIT(0),
1933                 .hw.init = &(struct clk_init_data){
1934                         .name = "gcc_camss_csi3_clk",
1935                         .parent_hws = (const struct clk_hw*[]){
1936                                 &gcc_camss_csi3_clk_src.clkr.hw,
1937                         },
1938                         .num_parents = 1,
1939                         .flags = CLK_SET_RATE_PARENT,
1940                         .ops = &clk_branch2_ops,
1941                 },
1942         },
1943 };
1944
1945 static struct clk_branch gcc_camss_csi3pix_clk = {
1946         .halt_reg = 0x55110,
1947         .halt_check = BRANCH_HALT,
1948         .clkr = {
1949                 .enable_reg = 0x55110,
1950                 .enable_mask = BIT(0),
1951                 .hw.init = &(struct clk_init_data){
1952                         .name = "gcc_camss_csi3pix_clk",
1953                         .parent_hws = (const struct clk_hw*[]){
1954                                 &gcc_camss_csi3_clk_src.clkr.hw,
1955                         },
1956                         .num_parents = 1,
1957                         .flags = CLK_SET_RATE_PARENT,
1958                         .ops = &clk_branch2_ops,
1959                 },
1960         },
1961 };
1962
1963 static struct clk_branch gcc_camss_csi3rdi_clk = {
1964         .halt_reg = 0x55108,
1965         .halt_check = BRANCH_HALT,
1966         .clkr = {
1967                 .enable_reg = 0x55108,
1968                 .enable_mask = BIT(0),
1969                 .hw.init = &(struct clk_init_data){
1970                         .name = "gcc_camss_csi3rdi_clk",
1971                         .parent_hws = (const struct clk_hw*[]){
1972                                 &gcc_camss_csi3_clk_src.clkr.hw,
1973                         },
1974                         .num_parents = 1,
1975                         .flags = CLK_SET_RATE_PARENT,
1976                         .ops = &clk_branch2_ops,
1977                 },
1978         },
1979 };
1980
1981 static struct clk_branch gcc_camss_csi_vfe0_clk = {
1982         .halt_reg = 0x54074,
1983         .halt_check = BRANCH_HALT,
1984         .clkr = {
1985                 .enable_reg = 0x54074,
1986                 .enable_mask = BIT(0),
1987                 .hw.init = &(struct clk_init_data){
1988                         .name = "gcc_camss_csi_vfe0_clk",
1989                         .parent_hws = (const struct clk_hw*[]){
1990                                 &gcc_camss_vfe0_clk_src.clkr.hw,
1991                         },
1992                         .num_parents = 1,
1993                         .flags = CLK_SET_RATE_PARENT,
1994                         .ops = &clk_branch2_ops,
1995                 },
1996         },
1997 };
1998
1999 static struct clk_branch gcc_camss_csi_vfe1_clk = {
2000         .halt_reg = 0x54080,
2001         .halt_check = BRANCH_HALT,
2002         .clkr = {
2003                 .enable_reg = 0x54080,
2004                 .enable_mask = BIT(0),
2005                 .hw.init = &(struct clk_init_data){
2006                         .name = "gcc_camss_csi_vfe1_clk",
2007                         .parent_hws = (const struct clk_hw*[]){
2008                                 &gcc_camss_vfe1_clk_src.clkr.hw,
2009                         },
2010                         .num_parents = 1,
2011                         .flags = CLK_SET_RATE_PARENT,
2012                         .ops = &clk_branch2_ops,
2013                 },
2014         },
2015 };
2016
2017 static struct clk_branch gcc_camss_csiphy0_clk = {
2018         .halt_reg = 0x55018,
2019         .halt_check = BRANCH_HALT,
2020         .clkr = {
2021                 .enable_reg = 0x55018,
2022                 .enable_mask = BIT(0),
2023                 .hw.init = &(struct clk_init_data){
2024                         .name = "gcc_camss_csiphy0_clk",
2025                         .parent_hws = (const struct clk_hw*[]){
2026                                 &gcc_camss_csiphy_clk_src.clkr.hw,
2027                         },
2028                         .num_parents = 1,
2029                         .flags = CLK_SET_RATE_PARENT,
2030                         .ops = &clk_branch2_ops,
2031                 },
2032         },
2033 };
2034
2035 static struct clk_branch gcc_camss_csiphy1_clk = {
2036         .halt_reg = 0x5501c,
2037         .halt_check = BRANCH_HALT,
2038         .clkr = {
2039                 .enable_reg = 0x5501c,
2040                 .enable_mask = BIT(0),
2041                 .hw.init = &(struct clk_init_data){
2042                         .name = "gcc_camss_csiphy1_clk",
2043                         .parent_hws = (const struct clk_hw*[]){
2044                                 &gcc_camss_csiphy_clk_src.clkr.hw,
2045                         },
2046                         .num_parents = 1,
2047                         .flags = CLK_SET_RATE_PARENT,
2048                         .ops = &clk_branch2_ops,
2049                 },
2050         },
2051 };
2052
2053 static struct clk_branch gcc_camss_csiphy2_clk = {
2054         .halt_reg = 0x55020,
2055         .halt_check = BRANCH_HALT,
2056         .clkr = {
2057                 .enable_reg = 0x55020,
2058                 .enable_mask = BIT(0),
2059                 .hw.init = &(struct clk_init_data){
2060                         .name = "gcc_camss_csiphy2_clk",
2061                         .parent_hws = (const struct clk_hw*[]){
2062                                 &gcc_camss_csiphy_clk_src.clkr.hw,
2063                         },
2064                         .num_parents = 1,
2065                         .flags = CLK_SET_RATE_PARENT,
2066                         .ops = &clk_branch2_ops,
2067                 },
2068         },
2069 };
2070
2071 static struct clk_branch gcc_camss_gp0_clk = {
2072         .halt_reg = 0x50018,
2073         .halt_check = BRANCH_HALT,
2074         .clkr = {
2075                 .enable_reg = 0x50018,
2076                 .enable_mask = BIT(0),
2077                 .hw.init = &(struct clk_init_data){
2078                         .name = "gcc_camss_gp0_clk",
2079                         .parent_hws = (const struct clk_hw*[]){
2080                                 &gcc_camss_gp0_clk_src.clkr.hw,
2081                         },
2082                         .num_parents = 1,
2083                         .flags = CLK_SET_RATE_PARENT,
2084                         .ops = &clk_branch2_ops,
2085                 },
2086         },
2087 };
2088
2089 static struct clk_branch gcc_camss_gp1_clk = {
2090         .halt_reg = 0x50034,
2091         .halt_check = BRANCH_HALT,
2092         .clkr = {
2093                 .enable_reg = 0x50034,
2094                 .enable_mask = BIT(0),
2095                 .hw.init = &(struct clk_init_data){
2096                         .name = "gcc_camss_gp1_clk",
2097                         .parent_hws = (const struct clk_hw*[]){
2098                                 &gcc_camss_gp1_clk_src.clkr.hw,
2099                         },
2100                         .num_parents = 1,
2101                         .flags = CLK_SET_RATE_PARENT,
2102                         .ops = &clk_branch2_ops,
2103                 },
2104         },
2105 };
2106
2107 static struct clk_branch gcc_camss_ispif_ahb_clk = {
2108         .halt_reg = 0x540a4,
2109         .halt_check = BRANCH_HALT,
2110         .clkr = {
2111                 .enable_reg = 0x540a4,
2112                 .enable_mask = BIT(0),
2113                 .hw.init = &(struct clk_init_data){
2114                         .name = "gcc_camss_ispif_ahb_clk",
2115                         .parent_hws = (const struct clk_hw*[]){
2116                                 &gcc_camss_ahb_clk_src.clkr.hw,
2117                         },
2118                         .num_parents = 1,
2119                         .flags = CLK_SET_RATE_PARENT,
2120                         .ops = &clk_branch2_ops,
2121                 },
2122         },
2123 };
2124
2125 static struct clk_branch gcc_camss_jpeg_ahb_clk = {
2126         .halt_reg = 0x52048,
2127         .halt_check = BRANCH_HALT,
2128         .clkr = {
2129                 .enable_reg = 0x52048,
2130                 .enable_mask = BIT(0),
2131                 .hw.init = &(struct clk_init_data){
2132                         .name = "gcc_camss_jpeg_ahb_clk",
2133                         .parent_hws = (const struct clk_hw*[]){
2134                                 &gcc_camss_ahb_clk_src.clkr.hw,
2135                         },
2136                         .num_parents = 1,
2137                         .flags = CLK_SET_RATE_PARENT,
2138                         .ops = &clk_branch2_ops,
2139                 },
2140         },
2141 };
2142
2143 static struct clk_branch gcc_camss_jpeg_axi_clk = {
2144         .halt_reg = 0x5204c,
2145         .halt_check = BRANCH_HALT,
2146         .clkr = {
2147                 .enable_reg = 0x5204c,
2148                 .enable_mask = BIT(0),
2149                 .hw.init = &(struct clk_init_data){
2150                         .name = "gcc_camss_jpeg_axi_clk",
2151                         .ops = &clk_branch2_ops,
2152                 },
2153         },
2154 };
2155
2156 static struct clk_branch gcc_camss_jpeg_clk = {
2157         .halt_reg = 0x52040,
2158         .halt_check = BRANCH_HALT,
2159         .clkr = {
2160                 .enable_reg = 0x52040,
2161                 .enable_mask = BIT(0),
2162                 .hw.init = &(struct clk_init_data){
2163                         .name = "gcc_camss_jpeg_clk",
2164                         .parent_hws = (const struct clk_hw*[]){
2165                                 &gcc_camss_jpeg_clk_src.clkr.hw,
2166                         },
2167                         .num_parents = 1,
2168                         .flags = CLK_SET_RATE_PARENT,
2169                         .ops = &clk_branch2_ops,
2170                 },
2171         },
2172 };
2173
2174 static struct clk_branch gcc_camss_mclk0_clk = {
2175         .halt_reg = 0x51018,
2176         .halt_check = BRANCH_HALT,
2177         .clkr = {
2178                 .enable_reg = 0x51018,
2179                 .enable_mask = BIT(0),
2180                 .hw.init = &(struct clk_init_data){
2181                         .name = "gcc_camss_mclk0_clk",
2182                         .parent_hws = (const struct clk_hw*[]){
2183                                 &gcc_camss_mclk0_clk_src.clkr.hw,
2184                         },
2185                         .num_parents = 1,
2186                         .flags = CLK_SET_RATE_PARENT,
2187                         .ops = &clk_branch2_ops,
2188                 },
2189         },
2190 };
2191
2192 static struct clk_branch gcc_camss_mclk1_clk = {
2193         .halt_reg = 0x51034,
2194         .halt_check = BRANCH_HALT,
2195         .clkr = {
2196                 .enable_reg = 0x51034,
2197                 .enable_mask = BIT(0),
2198                 .hw.init = &(struct clk_init_data){
2199                         .name = "gcc_camss_mclk1_clk",
2200                         .parent_hws = (const struct clk_hw*[]){
2201                                 &gcc_camss_mclk1_clk_src.clkr.hw,
2202                         },
2203                         .num_parents = 1,
2204                         .flags = CLK_SET_RATE_PARENT,
2205                         .ops = &clk_branch2_ops,
2206                 },
2207         },
2208 };
2209
2210 static struct clk_branch gcc_camss_mclk2_clk = {
2211         .halt_reg = 0x51050,
2212         .halt_check = BRANCH_HALT,
2213         .clkr = {
2214                 .enable_reg = 0x51050,
2215                 .enable_mask = BIT(0),
2216                 .hw.init = &(struct clk_init_data){
2217                         .name = "gcc_camss_mclk2_clk",
2218                         .parent_hws = (const struct clk_hw*[]){
2219                                 &gcc_camss_mclk2_clk_src.clkr.hw,
2220                         },
2221                         .num_parents = 1,
2222                         .flags = CLK_SET_RATE_PARENT,
2223                         .ops = &clk_branch2_ops,
2224                 },
2225         },
2226 };
2227
2228 static struct clk_branch gcc_camss_mclk3_clk = {
2229         .halt_reg = 0x5106c,
2230         .halt_check = BRANCH_HALT,
2231         .clkr = {
2232                 .enable_reg = 0x5106c,
2233                 .enable_mask = BIT(0),
2234                 .hw.init = &(struct clk_init_data){
2235                         .name = "gcc_camss_mclk3_clk",
2236                         .parent_hws = (const struct clk_hw*[]){
2237                                 &gcc_camss_mclk3_clk_src.clkr.hw,
2238                         },
2239                         .num_parents = 1,
2240                         .flags = CLK_SET_RATE_PARENT,
2241                         .ops = &clk_branch2_ops,
2242                 },
2243         },
2244 };
2245
2246 static struct clk_branch gcc_camss_micro_ahb_clk = {
2247         .halt_reg = 0x560b0,
2248         .halt_check = BRANCH_HALT,
2249         .clkr = {
2250                 .enable_reg = 0x560b0,
2251                 .enable_mask = BIT(0),
2252                 .hw.init = &(struct clk_init_data){
2253                         .name = "gcc_camss_micro_ahb_clk",
2254                         .parent_hws = (const struct clk_hw*[]){
2255                                 &gcc_camss_ahb_clk_src.clkr.hw,
2256                         },
2257                         .num_parents = 1,
2258                         .flags = CLK_SET_RATE_PARENT,
2259                         .ops = &clk_branch2_ops,
2260                 },
2261         },
2262 };
2263
2264 static struct clk_branch gcc_camss_throttle_nrt_axi_clk = {
2265         .halt_reg = 0x560a4,
2266         .halt_check = BRANCH_HALT_VOTED,
2267         .clkr = {
2268                 .enable_reg = 0x79004,
2269                 .enable_mask = BIT(27),
2270                 .hw.init = &(struct clk_init_data){
2271                         .name = "gcc_camss_throttle_nrt_axi_clk",
2272                         .ops = &clk_branch2_ops,
2273                 },
2274         },
2275 };
2276
2277 static struct clk_branch gcc_camss_throttle_rt_axi_clk = {
2278         .halt_reg = 0x560a8,
2279         .halt_check = BRANCH_HALT_VOTED,
2280         .clkr = {
2281                 .enable_reg = 0x79004,
2282                 .enable_mask = BIT(26),
2283                 .hw.init = &(struct clk_init_data){
2284                         .name = "gcc_camss_throttle_rt_axi_clk",
2285                         .ops = &clk_branch2_ops,
2286                 },
2287         },
2288 };
2289
2290 static struct clk_branch gcc_camss_top_ahb_clk = {
2291         .halt_reg = 0x560a0,
2292         .halt_check = BRANCH_HALT,
2293         .clkr = {
2294                 .enable_reg = 0x560a0,
2295                 .enable_mask = BIT(0),
2296                 .hw.init = &(struct clk_init_data){
2297                         .name = "gcc_camss_top_ahb_clk",
2298                         .parent_hws = (const struct clk_hw*[]){
2299                                 &gcc_camss_ahb_clk_src.clkr.hw,
2300                         },
2301                         .num_parents = 1,
2302                         .flags = CLK_SET_RATE_PARENT,
2303                         .ops = &clk_branch2_ops,
2304                 },
2305         },
2306 };
2307
2308 static struct clk_branch gcc_camss_vfe0_ahb_clk = {
2309         .halt_reg = 0x54034,
2310         .halt_check = BRANCH_HALT,
2311         .clkr = {
2312                 .enable_reg = 0x54034,
2313                 .enable_mask = BIT(0),
2314                 .hw.init = &(struct clk_init_data){
2315                         .name = "gcc_camss_vfe0_ahb_clk",
2316                         .parent_hws = (const struct clk_hw*[]){
2317                                 &gcc_camss_ahb_clk_src.clkr.hw,
2318                         },
2319                         .num_parents = 1,
2320                         .flags = CLK_SET_RATE_PARENT,
2321                         .ops = &clk_branch2_ops,
2322                 },
2323         },
2324 };
2325
2326 static struct clk_branch gcc_camss_vfe0_clk = {
2327         .halt_reg = 0x54028,
2328         .halt_check = BRANCH_HALT,
2329         .clkr = {
2330                 .enable_reg = 0x54028,
2331                 .enable_mask = BIT(0),
2332                 .hw.init = &(struct clk_init_data){
2333                         .name = "gcc_camss_vfe0_clk",
2334                         .parent_hws = (const struct clk_hw*[]){
2335                                 &gcc_camss_vfe0_clk_src.clkr.hw,
2336                         },
2337                         .num_parents = 1,
2338                         .flags = CLK_SET_RATE_PARENT,
2339                         .ops = &clk_branch2_ops,
2340                 },
2341         },
2342 };
2343
2344 static struct clk_branch gcc_camss_vfe0_stream_clk = {
2345         .halt_reg = 0x54030,
2346         .halt_check = BRANCH_HALT,
2347         .clkr = {
2348                 .enable_reg = 0x54030,
2349                 .enable_mask = BIT(0),
2350                 .hw.init = &(struct clk_init_data){
2351                         .name = "gcc_camss_vfe0_stream_clk",
2352                         .parent_hws = (const struct clk_hw*[]){
2353                                 &gcc_camss_vfe0_clk_src.clkr.hw,
2354                         },
2355                         .num_parents = 1,
2356                         .flags = CLK_SET_RATE_PARENT,
2357                         .ops = &clk_branch2_ops,
2358                 },
2359         },
2360 };
2361
2362 static struct clk_branch gcc_camss_vfe1_ahb_clk = {
2363         .halt_reg = 0x5406c,
2364         .halt_check = BRANCH_HALT,
2365         .clkr = {
2366                 .enable_reg = 0x5406c,
2367                 .enable_mask = BIT(0),
2368                 .hw.init = &(struct clk_init_data){
2369                         .name = "gcc_camss_vfe1_ahb_clk",
2370                         .parent_hws = (const struct clk_hw*[]){
2371                                 &gcc_camss_ahb_clk_src.clkr.hw,
2372                         },
2373                         .num_parents = 1,
2374                         .flags = CLK_SET_RATE_PARENT,
2375                         .ops = &clk_branch2_ops,
2376                 },
2377         },
2378 };
2379
2380 static struct clk_branch gcc_camss_vfe1_clk = {
2381         .halt_reg = 0x54060,
2382         .halt_check = BRANCH_HALT,
2383         .clkr = {
2384                 .enable_reg = 0x54060,
2385                 .enable_mask = BIT(0),
2386                 .hw.init = &(struct clk_init_data){
2387                         .name = "gcc_camss_vfe1_clk",
2388                         .parent_hws = (const struct clk_hw*[]){
2389                                 &gcc_camss_vfe1_clk_src.clkr.hw,
2390                         },
2391                         .num_parents = 1,
2392                         .flags = CLK_SET_RATE_PARENT,
2393                         .ops = &clk_branch2_ops,
2394                 },
2395         },
2396 };
2397
2398 static struct clk_branch gcc_camss_vfe1_stream_clk = {
2399         .halt_reg = 0x54068,
2400         .halt_check = BRANCH_HALT,
2401         .clkr = {
2402                 .enable_reg = 0x54068,
2403                 .enable_mask = BIT(0),
2404                 .hw.init = &(struct clk_init_data){
2405                         .name = "gcc_camss_vfe1_stream_clk",
2406                         .parent_hws = (const struct clk_hw*[]){
2407                                 &gcc_camss_vfe1_clk_src.clkr.hw,
2408                         },
2409                         .num_parents = 1,
2410                         .flags = CLK_SET_RATE_PARENT,
2411                         .ops = &clk_branch2_ops,
2412                 },
2413         },
2414 };
2415
2416 static struct clk_branch gcc_camss_vfe_tsctr_clk = {
2417         .halt_reg = 0x5409c,
2418         .halt_check = BRANCH_HALT,
2419         .clkr = {
2420                 .enable_reg = 0x5409c,
2421                 .enable_mask = BIT(0),
2422                 .hw.init = &(struct clk_init_data){
2423                         .name = "gcc_camss_vfe_tsctr_clk",
2424                         .ops = &clk_branch2_ops,
2425                 },
2426         },
2427 };
2428
2429 static struct clk_branch gcc_camss_vfe_vbif_ahb_clk = {
2430         .halt_reg = 0x5408c,
2431         .halt_check = BRANCH_HALT,
2432         .clkr = {
2433                 .enable_reg = 0x5408c,
2434                 .enable_mask = BIT(0),
2435                 .hw.init = &(struct clk_init_data){
2436                         .name = "gcc_camss_vfe_vbif_ahb_clk",
2437                         .parent_hws = (const struct clk_hw*[]){
2438                                 &gcc_camss_ahb_clk_src.clkr.hw,
2439                         },
2440                         .num_parents = 1,
2441                         .flags = CLK_SET_RATE_PARENT,
2442                         .ops = &clk_branch2_ops,
2443                 },
2444         },
2445 };
2446
2447 static struct clk_branch gcc_camss_vfe_vbif_axi_clk = {
2448         .halt_reg = 0x54090,
2449         .halt_check = BRANCH_HALT,
2450         .clkr = {
2451                 .enable_reg = 0x54090,
2452                 .enable_mask = BIT(0),
2453                 .hw.init = &(struct clk_init_data){
2454                         .name = "gcc_camss_vfe_vbif_axi_clk",
2455                         .ops = &clk_branch2_ops,
2456                 },
2457         },
2458 };
2459
2460 static struct clk_branch gcc_ce1_ahb_clk = {
2461         .halt_reg = 0x2700c,
2462         .halt_check = BRANCH_HALT_VOTED,
2463         .hwcg_reg = 0x2700c,
2464         .hwcg_bit = 1,
2465         .clkr = {
2466                 .enable_reg = 0x79004,
2467                 .enable_mask = BIT(3),
2468                 .hw.init = &(struct clk_init_data){
2469                         .name = "gcc_ce1_ahb_clk",
2470                         .ops = &clk_branch2_ops,
2471                 },
2472         },
2473 };
2474
2475 static struct clk_branch gcc_ce1_axi_clk = {
2476         .halt_reg = 0x27008,
2477         .halt_check = BRANCH_HALT_VOTED,
2478         .clkr = {
2479                 .enable_reg = 0x79004,
2480                 .enable_mask = BIT(4),
2481                 .hw.init = &(struct clk_init_data){
2482                         .name = "gcc_ce1_axi_clk",
2483                         .ops = &clk_branch2_ops,
2484                 },
2485         },
2486 };
2487
2488 static struct clk_branch gcc_ce1_clk = {
2489         .halt_reg = 0x27004,
2490         .halt_check = BRANCH_HALT_VOTED,
2491         .clkr = {
2492                 .enable_reg = 0x79004,
2493                 .enable_mask = BIT(5),
2494                 .hw.init = &(struct clk_init_data){
2495                         .name = "gcc_ce1_clk",
2496                         .ops = &clk_branch2_ops,
2497                 },
2498         },
2499 };
2500
2501 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
2502         .halt_reg = 0x1a084,
2503         .halt_check = BRANCH_HALT,
2504         .clkr = {
2505                 .enable_reg = 0x1a084,
2506                 .enable_mask = BIT(0),
2507                 .hw.init = &(struct clk_init_data){
2508                         .name = "gcc_cfg_noc_usb3_prim_axi_clk",
2509                         .parent_hws = (const struct clk_hw*[]){
2510                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
2511                         },
2512                         .num_parents = 1,
2513                         .flags = CLK_SET_RATE_PARENT,
2514                         .ops = &clk_branch2_ops,
2515                 },
2516         },
2517 };
2518
2519 static struct clk_branch gcc_cpuss_gnoc_clk = {
2520         .halt_reg = 0x2b004,
2521         .halt_check = BRANCH_HALT_VOTED,
2522         .hwcg_reg = 0x2b004,
2523         .hwcg_bit = 1,
2524         .clkr = {
2525                 .enable_reg = 0x79004,
2526                 .enable_mask = BIT(22),
2527                 .hw.init = &(struct clk_init_data){
2528                         .name = "gcc_cpuss_gnoc_clk",
2529                         .flags = CLK_IS_CRITICAL,
2530                         .ops = &clk_branch2_ops,
2531                 },
2532         },
2533 };
2534
2535 static struct clk_branch gcc_disp_ahb_clk = {
2536         .halt_reg = 0x1700c,
2537         .halt_check = BRANCH_HALT,
2538         .hwcg_reg = 0x1700c,
2539         .hwcg_bit = 1,
2540         .clkr = {
2541                 .enable_reg = 0x1700c,
2542                 .enable_mask = BIT(0),
2543                 .hw.init = &(struct clk_init_data){
2544                         .name = "gcc_disp_ahb_clk",
2545                         .flags = CLK_IS_CRITICAL,
2546                         .ops = &clk_branch2_ops,
2547                 },
2548         },
2549 };
2550
2551 static struct clk_branch gcc_disp_gpll0_div_clk_src = {
2552         .halt_check = BRANCH_HALT_DELAY,
2553         .clkr = {
2554                 .enable_reg = 0x79004,
2555                 .enable_mask = BIT(20),
2556                 .hw.init = &(struct clk_init_data){
2557                         .name = "gcc_disp_gpll0_div_clk_src",
2558                         .parent_hws = (const struct clk_hw*[]){
2559                                 &gpll0_out_early.clkr.hw,
2560                         },
2561                         .num_parents = 1,
2562                         .ops = &clk_branch2_ops,
2563                 },
2564         },
2565 };
2566
2567 static struct clk_branch gcc_disp_hf_axi_clk = {
2568         .halt_reg = 0x17020,
2569         .halt_check = BRANCH_HALT,
2570         .clkr = {
2571                 .enable_reg = 0x17020,
2572                 .enable_mask = BIT(0),
2573                 .hw.init = &(struct clk_init_data){
2574                         .name = "gcc_disp_hf_axi_clk",
2575                         .ops = &clk_branch2_ops,
2576                 },
2577         },
2578 };
2579
2580 static struct clk_branch gcc_disp_throttle_core_clk = {
2581         .halt_reg = 0x17064,
2582         .halt_check = BRANCH_HALT_VOTED,
2583         .clkr = {
2584                 .enable_reg = 0x7900c,
2585                 .enable_mask = BIT(5),
2586                 .hw.init = &(struct clk_init_data){
2587                         .name = "gcc_disp_throttle_core_clk",
2588                         .ops = &clk_branch2_ops,
2589                 },
2590         },
2591 };
2592
2593 static struct clk_branch gcc_disp_xo_clk = {
2594         .halt_reg = 0x1702c,
2595         .halt_check = BRANCH_HALT,
2596         .clkr = {
2597                 .enable_reg = 0x1702c,
2598                 .enable_mask = BIT(0),
2599                 .hw.init = &(struct clk_init_data){
2600                         .name = "gcc_disp_xo_clk",
2601                         .flags = CLK_IS_CRITICAL,
2602                         .ops = &clk_branch2_ops,
2603                 },
2604         },
2605 };
2606
2607 static struct clk_branch gcc_gp1_clk = {
2608         .halt_reg = 0x4d000,
2609         .halt_check = BRANCH_HALT,
2610         .clkr = {
2611                 .enable_reg = 0x4d000,
2612                 .enable_mask = BIT(0),
2613                 .hw.init = &(struct clk_init_data){
2614                         .name = "gcc_gp1_clk",
2615                         .parent_hws = (const struct clk_hw*[]){
2616                                 &gcc_gp1_clk_src.clkr.hw,
2617                         },
2618                         .num_parents = 1,
2619                         .flags = CLK_SET_RATE_PARENT,
2620                         .ops = &clk_branch2_ops,
2621                 },
2622         },
2623 };
2624
2625 static struct clk_branch gcc_gp2_clk = {
2626         .halt_reg = 0x4e000,
2627         .halt_check = BRANCH_HALT,
2628         .clkr = {
2629                 .enable_reg = 0x4e000,
2630                 .enable_mask = BIT(0),
2631                 .hw.init = &(struct clk_init_data){
2632                         .name = "gcc_gp2_clk",
2633                         .parent_hws = (const struct clk_hw*[]){
2634                                 &gcc_gp2_clk_src.clkr.hw,
2635                         },
2636                         .num_parents = 1,
2637                         .flags = CLK_SET_RATE_PARENT,
2638                         .ops = &clk_branch2_ops,
2639                 },
2640         },
2641 };
2642
2643 static struct clk_branch gcc_gp3_clk = {
2644         .halt_reg = 0x4f000,
2645         .halt_check = BRANCH_HALT,
2646         .clkr = {
2647                 .enable_reg = 0x4f000,
2648                 .enable_mask = BIT(0),
2649                 .hw.init = &(struct clk_init_data){
2650                         .name = "gcc_gp3_clk",
2651                         .parent_hws = (const struct clk_hw*[]){
2652                                 &gcc_gp3_clk_src.clkr.hw,
2653                         },
2654                         .num_parents = 1,
2655                         .flags = CLK_SET_RATE_PARENT,
2656                         .ops = &clk_branch2_ops,
2657                 },
2658         },
2659 };
2660
2661 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
2662         .halt_reg = 0x36004,
2663         .halt_check = BRANCH_HALT,
2664         .hwcg_reg = 0x36004,
2665         .hwcg_bit = 1,
2666         .clkr = {
2667                 .enable_reg = 0x36004,
2668                 .enable_mask = BIT(0),
2669                 .hw.init = &(struct clk_init_data){
2670                         .name = "gcc_gpu_cfg_ahb_clk",
2671                         .flags = CLK_IS_CRITICAL,
2672                         .ops = &clk_branch2_ops,
2673                 },
2674         },
2675 };
2676
2677 static struct clk_branch gcc_gpu_gpll0_clk_src = {
2678         .halt_check = BRANCH_HALT_DELAY,
2679         .clkr = {
2680                 .enable_reg = 0x79004,
2681                 .enable_mask = BIT(15),
2682                 .hw.init = &(struct clk_init_data){
2683                         .name = "gcc_gpu_gpll0_clk_src",
2684                         .parent_hws = (const struct clk_hw*[]){
2685                                 &gpll0_out_early.clkr.hw,
2686                         },
2687                         .num_parents = 1,
2688                         .ops = &clk_branch2_ops,
2689                 },
2690         },
2691 };
2692
2693 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
2694         .halt_check = BRANCH_HALT_DELAY,
2695         .clkr = {
2696                 .enable_reg = 0x79004,
2697                 .enable_mask = BIT(16),
2698                 .hw.init = &(struct clk_init_data){
2699                         .name = "gcc_gpu_gpll0_div_clk_src",
2700                         .parent_hws = (const struct clk_hw*[]){
2701                                 &gpll0_out_aux2.hw,
2702                         },
2703                         .num_parents = 1,
2704                         .ops = &clk_branch2_ops,
2705                 },
2706         },
2707 };
2708
2709 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
2710         .halt_reg = 0x3600c,
2711         .halt_check = BRANCH_VOTED,
2712         .clkr = {
2713                 .enable_reg = 0x3600c,
2714                 .enable_mask = BIT(0),
2715                 .hw.init = &(struct clk_init_data){
2716                         .name = "gcc_gpu_memnoc_gfx_clk",
2717                         .ops = &clk_branch2_ops,
2718                 },
2719         },
2720 };
2721
2722 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
2723         .halt_reg = 0x36018,
2724         .halt_check = BRANCH_HALT,
2725         .clkr = {
2726                 .enable_reg = 0x36018,
2727                 .enable_mask = BIT(0),
2728                 .hw.init = &(struct clk_init_data){
2729                         .name = "gcc_gpu_snoc_dvm_gfx_clk",
2730                         .ops = &clk_branch2_ops,
2731                 },
2732         },
2733 };
2734
2735 static struct clk_branch gcc_gpu_throttle_core_clk = {
2736         .halt_reg = 0x36048,
2737         .halt_check = BRANCH_HALT_VOTED,
2738         .clkr = {
2739                 .enable_reg = 0x79004,
2740                 .enable_mask = BIT(31),
2741                 .hw.init = &(struct clk_init_data){
2742                         .name = "gcc_gpu_throttle_core_clk",
2743                         .ops = &clk_branch2_ops,
2744                 },
2745         },
2746 };
2747
2748 static struct clk_branch gcc_gpu_throttle_xo_clk = {
2749         .halt_reg = 0x36044,
2750         .halt_check = BRANCH_HALT,
2751         .clkr = {
2752                 .enable_reg = 0x36044,
2753                 .enable_mask = BIT(0),
2754                 .hw.init = &(struct clk_init_data){
2755                         .name = "gcc_gpu_throttle_xo_clk",
2756                         .ops = &clk_branch2_ops,
2757                 },
2758         },
2759 };
2760
2761 static struct clk_branch gcc_mss_vs_clk = {
2762         .halt_reg = 0x42048,
2763         .halt_check = BRANCH_HALT,
2764         .clkr = {
2765                 .enable_reg = 0x42048,
2766                 .enable_mask = BIT(0),
2767                 .hw.init = &(struct clk_init_data){
2768                         .name = "gcc_mss_vs_clk",
2769                         .parent_hws = (const struct clk_hw*[]){
2770                                 &gcc_vsensor_clk_src.clkr.hw,
2771                         },
2772                         .num_parents = 1,
2773                         .flags = CLK_SET_RATE_PARENT,
2774                         .ops = &clk_branch2_ops,
2775                 },
2776         },
2777 };
2778
2779 static struct clk_branch gcc_pdm2_clk = {
2780         .halt_reg = 0x2000c,
2781         .halt_check = BRANCH_HALT,
2782         .clkr = {
2783                 .enable_reg = 0x2000c,
2784                 .enable_mask = BIT(0),
2785                 .hw.init = &(struct clk_init_data){
2786                         .name = "gcc_pdm2_clk",
2787                         .parent_hws = (const struct clk_hw*[]){
2788                                 &gcc_pdm2_clk_src.clkr.hw,
2789                         },
2790                         .num_parents = 1,
2791                         .flags = CLK_SET_RATE_PARENT,
2792                         .ops = &clk_branch2_ops,
2793                 },
2794         },
2795 };
2796
2797 static struct clk_branch gcc_pdm_ahb_clk = {
2798         .halt_reg = 0x20004,
2799         .halt_check = BRANCH_HALT,
2800         .hwcg_reg = 0x20004,
2801         .hwcg_bit = 1,
2802         .clkr = {
2803                 .enable_reg = 0x20004,
2804                 .enable_mask = BIT(0),
2805                 .hw.init = &(struct clk_init_data){
2806                         .name = "gcc_pdm_ahb_clk",
2807                         .ops = &clk_branch2_ops,
2808                 },
2809         },
2810 };
2811
2812 static struct clk_branch gcc_pdm_xo4_clk = {
2813         .halt_reg = 0x20008,
2814         .halt_check = BRANCH_HALT,
2815         .clkr = {
2816                 .enable_reg = 0x20008,
2817                 .enable_mask = BIT(0),
2818                 .hw.init = &(struct clk_init_data){
2819                         .name = "gcc_pdm_xo4_clk",
2820                         .ops = &clk_branch2_ops,
2821                 },
2822         },
2823 };
2824
2825 static struct clk_branch gcc_prng_ahb_clk = {
2826         .halt_reg = 0x21004,
2827         .halt_check = BRANCH_HALT_VOTED,
2828         .hwcg_reg = 0x21004,
2829         .hwcg_bit = 1,
2830         .clkr = {
2831                 .enable_reg = 0x79004,
2832                 .enable_mask = BIT(13),
2833                 .hw.init = &(struct clk_init_data){
2834                         .name = "gcc_prng_ahb_clk",
2835                         .ops = &clk_branch2_ops,
2836                 },
2837         },
2838 };
2839
2840 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2841         .halt_reg = 0x17014,
2842         .halt_check = BRANCH_HALT,
2843         .hwcg_reg = 0x17014,
2844         .hwcg_bit = 1,
2845         .clkr = {
2846                 .enable_reg = 0x7900c,
2847                 .enable_mask = BIT(0),
2848                 .hw.init = &(struct clk_init_data){
2849                         .name = "gcc_qmip_camera_nrt_ahb_clk",
2850                         .ops = &clk_branch2_ops,
2851                 },
2852         },
2853 };
2854
2855 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2856         .halt_reg = 0x17060,
2857         .halt_check = BRANCH_HALT_VOTED,
2858         .hwcg_reg = 0x17060,
2859         .hwcg_bit = 1,
2860         .clkr = {
2861                 .enable_reg = 0x7900c,
2862                 .enable_mask = BIT(2),
2863                 .hw.init = &(struct clk_init_data){
2864                         .name = "gcc_qmip_camera_rt_ahb_clk",
2865                         .ops = &clk_branch2_ops,
2866                 },
2867         },
2868 };
2869
2870 static struct clk_branch gcc_qmip_disp_ahb_clk = {
2871         .halt_reg = 0x17018,
2872         .halt_check = BRANCH_HALT,
2873         .hwcg_reg = 0x17018,
2874         .hwcg_bit = 1,
2875         .clkr = {
2876                 .enable_reg = 0x7900c,
2877                 .enable_mask = BIT(1),
2878                 .hw.init = &(struct clk_init_data){
2879                         .name = "gcc_qmip_disp_ahb_clk",
2880                         .ops = &clk_branch2_ops,
2881                 },
2882         },
2883 };
2884
2885 static struct clk_branch gcc_qmip_gpu_cfg_ahb_clk = {
2886         .halt_reg = 0x36040,
2887         .halt_check = BRANCH_HALT_VOTED,
2888         .hwcg_reg = 0x36040,
2889         .hwcg_bit = 1,
2890         .clkr = {
2891                 .enable_reg = 0x7900c,
2892                 .enable_mask = BIT(4),
2893                 .hw.init = &(struct clk_init_data){
2894                         .name = "gcc_qmip_gpu_cfg_ahb_clk",
2895                         .ops = &clk_branch2_ops,
2896                 },
2897         },
2898 };
2899
2900 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2901         .halt_reg = 0x17010,
2902         .halt_check = BRANCH_HALT,
2903         .hwcg_reg = 0x17010,
2904         .hwcg_bit = 1,
2905         .clkr = {
2906                 .enable_reg = 0x79004,
2907                 .enable_mask = BIT(25),
2908                 .hw.init = &(struct clk_init_data){
2909                         .name = "gcc_qmip_video_vcodec_ahb_clk",
2910                         .ops = &clk_branch2_ops,
2911                 },
2912         },
2913 };
2914
2915 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2916         .halt_reg = 0x1f014,
2917         .halt_check = BRANCH_HALT_VOTED,
2918         .clkr = {
2919                 .enable_reg = 0x7900c,
2920                 .enable_mask = BIT(9),
2921                 .hw.init = &(struct clk_init_data){
2922                         .name = "gcc_qupv3_wrap0_core_2x_clk",
2923                         .ops = &clk_branch2_ops,
2924                 },
2925         },
2926 };
2927
2928 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2929         .halt_reg = 0x1f00c,
2930         .halt_check = BRANCH_HALT_VOTED,
2931         .clkr = {
2932                 .enable_reg = 0x7900c,
2933                 .enable_mask = BIT(8),
2934                 .hw.init = &(struct clk_init_data){
2935                         .name = "gcc_qupv3_wrap0_core_clk",
2936                         .ops = &clk_branch2_ops,
2937                 },
2938         },
2939 };
2940
2941 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2942         .halt_reg = 0x1f144,
2943         .halt_check = BRANCH_HALT_VOTED,
2944         .clkr = {
2945                 .enable_reg = 0x7900c,
2946                 .enable_mask = BIT(10),
2947                 .hw.init = &(struct clk_init_data){
2948                         .name = "gcc_qupv3_wrap0_s0_clk",
2949                         .parent_hws = (const struct clk_hw*[]){
2950                                 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2951                         },
2952                         .num_parents = 1,
2953                         .flags = CLK_SET_RATE_PARENT,
2954                         .ops = &clk_branch2_ops,
2955                 },
2956         },
2957 };
2958
2959 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2960         .halt_reg = 0x1f274,
2961         .halt_check = BRANCH_HALT_VOTED,
2962         .clkr = {
2963                 .enable_reg = 0x7900c,
2964                 .enable_mask = BIT(11),
2965                 .hw.init = &(struct clk_init_data){
2966                         .name = "gcc_qupv3_wrap0_s1_clk",
2967                         .parent_hws = (const struct clk_hw*[]){
2968                                 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2969                         },
2970                         .num_parents = 1,
2971                         .flags = CLK_SET_RATE_PARENT,
2972                         .ops = &clk_branch2_ops,
2973                 },
2974         },
2975 };
2976
2977 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2978         .halt_reg = 0x1f3a4,
2979         .halt_check = BRANCH_HALT_VOTED,
2980         .clkr = {
2981                 .enable_reg = 0x7900c,
2982                 .enable_mask = BIT(12),
2983                 .hw.init = &(struct clk_init_data){
2984                         .name = "gcc_qupv3_wrap0_s2_clk",
2985                         .parent_hws = (const struct clk_hw*[]){
2986                                 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2987                         },
2988                         .num_parents = 1,
2989                         .flags = CLK_SET_RATE_PARENT,
2990                         .ops = &clk_branch2_ops,
2991                 },
2992         },
2993 };
2994
2995 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2996         .halt_reg = 0x1f4d4,
2997         .halt_check = BRANCH_HALT_VOTED,
2998         .clkr = {
2999                 .enable_reg = 0x7900c,
3000                 .enable_mask = BIT(13),
3001                 .hw.init = &(struct clk_init_data){
3002                         .name = "gcc_qupv3_wrap0_s3_clk",
3003                         .parent_hws = (const struct clk_hw*[]){
3004                                 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
3005                         },
3006                         .num_parents = 1,
3007                         .flags = CLK_SET_RATE_PARENT,
3008                         .ops = &clk_branch2_ops,
3009                 },
3010         },
3011 };
3012
3013 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
3014         .halt_reg = 0x1f604,
3015         .halt_check = BRANCH_HALT_VOTED,
3016         .clkr = {
3017                 .enable_reg = 0x7900c,
3018                 .enable_mask = BIT(14),
3019                 .hw.init = &(struct clk_init_data){
3020                         .name = "gcc_qupv3_wrap0_s4_clk",
3021                         .parent_hws = (const struct clk_hw*[]){
3022                                 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
3023                         },
3024                         .num_parents = 1,
3025                         .flags = CLK_SET_RATE_PARENT,
3026                         .ops = &clk_branch2_ops,
3027                 },
3028         },
3029 };
3030
3031 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
3032         .halt_reg = 0x1f734,
3033         .halt_check = BRANCH_HALT_VOTED,
3034         .clkr = {
3035                 .enable_reg = 0x7900c,
3036                 .enable_mask = BIT(15),
3037                 .hw.init = &(struct clk_init_data){
3038                         .name = "gcc_qupv3_wrap0_s5_clk",
3039                         .parent_hws = (const struct clk_hw*[]){
3040                                 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
3041                         },
3042                         .num_parents = 1,
3043                         .flags = CLK_SET_RATE_PARENT,
3044                         .ops = &clk_branch2_ops,
3045                 },
3046         },
3047 };
3048
3049 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
3050         .halt_reg = 0x39014,
3051         .halt_check = BRANCH_HALT_VOTED,
3052         .clkr = {
3053                 .enable_reg = 0x7900c,
3054                 .enable_mask = BIT(18),
3055                 .hw.init = &(struct clk_init_data){
3056                         .name = "gcc_qupv3_wrap1_core_2x_clk",
3057                         .ops = &clk_branch2_ops,
3058                 },
3059         },
3060 };
3061
3062 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
3063         .halt_reg = 0x3900c,
3064         .halt_check = BRANCH_HALT_VOTED,
3065         .clkr = {
3066                 .enable_reg = 0x7900c,
3067                 .enable_mask = BIT(19),
3068                 .hw.init = &(struct clk_init_data){
3069                         .name = "gcc_qupv3_wrap1_core_clk",
3070                         .ops = &clk_branch2_ops,
3071                 },
3072         },
3073 };
3074
3075 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
3076         .halt_reg = 0x39144,
3077         .halt_check = BRANCH_HALT_VOTED,
3078         .clkr = {
3079                 .enable_reg = 0x7900c,
3080                 .enable_mask = BIT(22),
3081                 .hw.init = &(struct clk_init_data){
3082                         .name = "gcc_qupv3_wrap1_s0_clk",
3083                         .parent_hws = (const struct clk_hw*[]){
3084                                 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
3085                         },
3086                         .num_parents = 1,
3087                         .flags = CLK_SET_RATE_PARENT,
3088                         .ops = &clk_branch2_ops,
3089                 },
3090         },
3091 };
3092
3093 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
3094         .halt_reg = 0x39274,
3095         .halt_check = BRANCH_HALT_VOTED,
3096         .clkr = {
3097                 .enable_reg = 0x7900c,
3098                 .enable_mask = BIT(23),
3099                 .hw.init = &(struct clk_init_data){
3100                         .name = "gcc_qupv3_wrap1_s1_clk",
3101                         .parent_hws = (const struct clk_hw*[]){
3102                                 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
3103                         },
3104                         .num_parents = 1,
3105                         .flags = CLK_SET_RATE_PARENT,
3106                         .ops = &clk_branch2_ops,
3107                 },
3108         },
3109 };
3110
3111 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
3112         .halt_reg = 0x393a4,
3113         .halt_check = BRANCH_HALT_VOTED,
3114         .clkr = {
3115                 .enable_reg = 0x7900c,
3116                 .enable_mask = BIT(24),
3117                 .hw.init = &(struct clk_init_data){
3118                         .name = "gcc_qupv3_wrap1_s2_clk",
3119                         .parent_hws = (const struct clk_hw*[]){
3120                                 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
3121                         },
3122                         .num_parents = 1,
3123                         .flags = CLK_SET_RATE_PARENT,
3124                         .ops = &clk_branch2_ops,
3125                 },
3126         },
3127 };
3128
3129 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
3130         .halt_reg = 0x394d4,
3131         .halt_check = BRANCH_HALT_VOTED,
3132         .clkr = {
3133                 .enable_reg = 0x7900c,
3134                 .enable_mask = BIT(25),
3135                 .hw.init = &(struct clk_init_data){
3136                         .name = "gcc_qupv3_wrap1_s3_clk",
3137                         .parent_hws = (const struct clk_hw*[]){
3138                                 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
3139                         },
3140                         .num_parents = 1,
3141                         .flags = CLK_SET_RATE_PARENT,
3142                         .ops = &clk_branch2_ops,
3143                 },
3144         },
3145 };
3146
3147 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
3148         .halt_reg = 0x39604,
3149         .halt_check = BRANCH_HALT_VOTED,
3150         .clkr = {
3151                 .enable_reg = 0x7900c,
3152                 .enable_mask = BIT(26),
3153                 .hw.init = &(struct clk_init_data){
3154                         .name = "gcc_qupv3_wrap1_s4_clk",
3155                         .parent_hws = (const struct clk_hw*[]){
3156                                 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
3157                         },
3158                         .num_parents = 1,
3159                         .flags = CLK_SET_RATE_PARENT,
3160                         .ops = &clk_branch2_ops,
3161                 },
3162         },
3163 };
3164
3165 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
3166         .halt_reg = 0x39734,
3167         .halt_check = BRANCH_HALT_VOTED,
3168         .clkr = {
3169                 .enable_reg = 0x7900c,
3170                 .enable_mask = BIT(27),
3171                 .hw.init = &(struct clk_init_data){
3172                         .name = "gcc_qupv3_wrap1_s5_clk",
3173                         .parent_hws = (const struct clk_hw*[]){
3174                                 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
3175                         },
3176                         .num_parents = 1,
3177                         .flags = CLK_SET_RATE_PARENT,
3178                         .ops = &clk_branch2_ops,
3179                 },
3180         },
3181 };
3182
3183 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
3184         .halt_reg = 0x1f004,
3185         .halt_check = BRANCH_HALT_VOTED,
3186         .clkr = {
3187                 .enable_reg = 0x7900c,
3188                 .enable_mask = BIT(6),
3189                 .hw.init = &(struct clk_init_data){
3190                         .name = "gcc_qupv3_wrap_0_m_ahb_clk",
3191                         .ops = &clk_branch2_ops,
3192                 },
3193         },
3194 };
3195
3196 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
3197         .halt_reg = 0x1f008,
3198         .halt_check = BRANCH_HALT_VOTED,
3199         .hwcg_reg = 0x1f008,
3200         .hwcg_bit = 1,
3201         .clkr = {
3202                 .enable_reg = 0x7900c,
3203                 .enable_mask = BIT(7),
3204                 .hw.init = &(struct clk_init_data){
3205                         .name = "gcc_qupv3_wrap_0_s_ahb_clk",
3206                         .ops = &clk_branch2_ops,
3207                 },
3208         },
3209 };
3210
3211 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
3212         .halt_reg = 0x39004,
3213         .halt_check = BRANCH_HALT_VOTED,
3214         .clkr = {
3215                 .enable_reg = 0x7900c,
3216                 .enable_mask = BIT(20),
3217                 .hw.init = &(struct clk_init_data){
3218                         .name = "gcc_qupv3_wrap_1_m_ahb_clk",
3219                         .ops = &clk_branch2_ops,
3220                 },
3221         },
3222 };
3223
3224 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
3225         .halt_reg = 0x39008,
3226         .halt_check = BRANCH_HALT_VOTED,
3227         .hwcg_reg = 0x39008,
3228         .hwcg_bit = 1,
3229         .clkr = {
3230                 .enable_reg = 0x7900c,
3231                 .enable_mask = BIT(21),
3232                 .hw.init = &(struct clk_init_data){
3233                         .name = "gcc_qupv3_wrap_1_s_ahb_clk",
3234                         .ops = &clk_branch2_ops,
3235                 },
3236         },
3237 };
3238
3239 static struct clk_branch gcc_sdcc1_ahb_clk = {
3240         .halt_reg = 0x38008,
3241         .halt_check = BRANCH_HALT,
3242         .clkr = {
3243                 .enable_reg = 0x38008,
3244                 .enable_mask = BIT(0),
3245                 .hw.init = &(struct clk_init_data){
3246                         .name = "gcc_sdcc1_ahb_clk",
3247                         .ops = &clk_branch2_ops,
3248                 },
3249         },
3250 };
3251
3252 static struct clk_branch gcc_sdcc1_apps_clk = {
3253         .halt_reg = 0x38004,
3254         .halt_check = BRANCH_HALT,
3255         .clkr = {
3256                 .enable_reg = 0x38004,
3257                 .enable_mask = BIT(0),
3258                 .hw.init = &(struct clk_init_data){
3259                         .name = "gcc_sdcc1_apps_clk",
3260                         .parent_hws = (const struct clk_hw*[]){
3261                                 &gcc_sdcc1_apps_clk_src.clkr.hw,
3262                         },
3263                         .num_parents = 1,
3264                         .flags = CLK_SET_RATE_PARENT,
3265                         .ops = &clk_branch2_ops,
3266                 },
3267         },
3268 };
3269
3270 static struct clk_branch gcc_sdcc1_ice_core_clk = {
3271         .halt_reg = 0x3800c,
3272         .halt_check = BRANCH_HALT,
3273         .clkr = {
3274                 .enable_reg = 0x3800c,
3275                 .enable_mask = BIT(0),
3276                 .hw.init = &(struct clk_init_data){
3277                         .name = "gcc_sdcc1_ice_core_clk",
3278                         .parent_hws = (const struct clk_hw*[]){
3279                                 &gcc_sdcc1_ice_core_clk_src.clkr.hw,
3280                         },
3281                         .num_parents = 1,
3282                         .flags = CLK_SET_RATE_PARENT,
3283                         .ops = &clk_branch2_ops,
3284                 },
3285         },
3286 };
3287
3288 static struct clk_branch gcc_sdcc2_ahb_clk = {
3289         .halt_reg = 0x1e008,
3290         .halt_check = BRANCH_HALT,
3291         .clkr = {
3292                 .enable_reg = 0x1e008,
3293                 .enable_mask = BIT(0),
3294                 .hw.init = &(struct clk_init_data){
3295                         .name = "gcc_sdcc2_ahb_clk",
3296                         .ops = &clk_branch2_ops,
3297                 },
3298         },
3299 };
3300
3301 static struct clk_branch gcc_sdcc2_apps_clk = {
3302         .halt_reg = 0x1e004,
3303         .halt_check = BRANCH_HALT,
3304         .clkr = {
3305                 .enable_reg = 0x1e004,
3306                 .enable_mask = BIT(0),
3307                 .hw.init = &(struct clk_init_data){
3308                         .name = "gcc_sdcc2_apps_clk",
3309                         .parent_hws = (const struct clk_hw*[]){
3310                                 &gcc_sdcc2_apps_clk_src.clkr.hw,
3311                         },
3312                         .num_parents = 1,
3313                         .flags = CLK_SET_RATE_PARENT,
3314                         .ops = &clk_branch2_ops,
3315                 },
3316         },
3317 };
3318
3319 static struct clk_branch gcc_sys_noc_compute_sf_axi_clk = {
3320         .halt_reg = 0x1050c,
3321         .halt_check = BRANCH_HALT,
3322         .clkr = {
3323                 .enable_reg = 0x1050c,
3324                 .enable_mask = BIT(0),
3325                 .hw.init = &(struct clk_init_data){
3326                         .name = "gcc_sys_noc_compute_sf_axi_clk",
3327                         .flags = CLK_IS_CRITICAL,
3328                         .ops = &clk_branch2_ops,
3329                 },
3330         },
3331 };
3332
3333 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
3334         .halt_reg = 0x2b06c,
3335         .halt_check = BRANCH_HALT_VOTED,
3336         .clkr = {
3337                 .enable_reg = 0x79004,
3338                 .enable_mask = BIT(0),
3339                 .hw.init = &(struct clk_init_data){
3340                         .name = "gcc_sys_noc_cpuss_ahb_clk",
3341                         .flags = CLK_IS_CRITICAL,
3342                         .ops = &clk_branch2_ops,
3343                 },
3344         },
3345 };
3346
3347 static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = {
3348         .halt_reg = 0x45098,
3349         .halt_check = BRANCH_HALT,
3350         .clkr = {
3351                 .enable_reg = 0x45098,
3352                 .enable_mask = BIT(0),
3353                 .hw.init = &(struct clk_init_data){
3354                         .name = "gcc_sys_noc_ufs_phy_axi_clk",
3355                         .parent_hws = (const struct clk_hw*[]){
3356                                 &gcc_ufs_phy_axi_clk_src.clkr.hw,
3357                         },
3358                         .num_parents = 1,
3359                         .flags = CLK_SET_RATE_PARENT,
3360                         .ops = &clk_branch2_ops,
3361                 },
3362         },
3363 };
3364
3365 static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = {
3366         .halt_reg = 0x1a080,
3367         .halt_check = BRANCH_HALT,
3368         .clkr = {
3369                 .enable_reg = 0x1a080,
3370                 .enable_mask = BIT(0),
3371                 .hw.init = &(struct clk_init_data){
3372                         .name = "gcc_sys_noc_usb3_prim_axi_clk",
3373                         .parent_hws = (const struct clk_hw*[]){
3374                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
3375                         },
3376                         .num_parents = 1,
3377                         .flags = CLK_SET_RATE_PARENT,
3378                         .ops = &clk_branch2_ops,
3379                 },
3380         },
3381 };
3382
3383 static struct clk_branch gcc_ufs_mem_clkref_clk = {
3384         .halt_reg = 0x8c000,
3385         .halt_check = BRANCH_HALT,
3386         .clkr = {
3387                 .enable_reg = 0x8c000,
3388                 .enable_mask = BIT(0),
3389                 .hw.init = &(struct clk_init_data){
3390                         .name = "gcc_ufs_mem_clkref_clk",
3391                         .ops = &clk_branch2_ops,
3392                 },
3393         },
3394 };
3395
3396 static struct clk_branch gcc_ufs_phy_ahb_clk = {
3397         .halt_reg = 0x45014,
3398         .halt_check = BRANCH_HALT,
3399         .hwcg_reg = 0x45014,
3400         .hwcg_bit = 1,
3401         .clkr = {
3402                 .enable_reg = 0x45014,
3403                 .enable_mask = BIT(0),
3404                 .hw.init = &(struct clk_init_data){
3405                         .name = "gcc_ufs_phy_ahb_clk",
3406                         .ops = &clk_branch2_ops,
3407                 },
3408         },
3409 };
3410
3411 static struct clk_branch gcc_ufs_phy_axi_clk = {
3412         .halt_reg = 0x45010,
3413         .halt_check = BRANCH_HALT,
3414         .hwcg_reg = 0x45010,
3415         .hwcg_bit = 1,
3416         .clkr = {
3417                 .enable_reg = 0x45010,
3418                 .enable_mask = BIT(0),
3419                 .hw.init = &(struct clk_init_data){
3420                         .name = "gcc_ufs_phy_axi_clk",
3421                         .parent_hws = (const struct clk_hw*[]){
3422                                 &gcc_ufs_phy_axi_clk_src.clkr.hw,
3423                         },
3424                         .num_parents = 1,
3425                         .flags = CLK_SET_RATE_PARENT,
3426                         .ops = &clk_branch2_ops,
3427                 },
3428         },
3429 };
3430
3431 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
3432         .halt_reg = 0x45044,
3433         .halt_check = BRANCH_HALT,
3434         .hwcg_reg = 0x45044,
3435         .hwcg_bit = 1,
3436         .clkr = {
3437                 .enable_reg = 0x45044,
3438                 .enable_mask = BIT(0),
3439                 .hw.init = &(struct clk_init_data){
3440                         .name = "gcc_ufs_phy_ice_core_clk",
3441                         .parent_hws = (const struct clk_hw*[]){
3442                                 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
3443                         },
3444                         .num_parents = 1,
3445                         .flags = CLK_SET_RATE_PARENT,
3446                         .ops = &clk_branch2_ops,
3447                 },
3448         },
3449 };
3450
3451 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
3452         .halt_reg = 0x45078,
3453         .halt_check = BRANCH_HALT,
3454         .hwcg_reg = 0x45078,
3455         .hwcg_bit = 1,
3456         .clkr = {
3457                 .enable_reg = 0x45078,
3458                 .enable_mask = BIT(0),
3459                 .hw.init = &(struct clk_init_data){
3460                         .name = "gcc_ufs_phy_phy_aux_clk",
3461                         .parent_hws = (const struct clk_hw*[]){
3462                                 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
3463                         },
3464                         .num_parents = 1,
3465                         .flags = CLK_SET_RATE_PARENT,
3466                         .ops = &clk_branch2_ops,
3467                 },
3468         },
3469 };
3470
3471 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
3472         .halt_reg = 0x4501c,
3473         .halt_check = BRANCH_HALT_SKIP,
3474         .clkr = {
3475                 .enable_reg = 0x4501c,
3476                 .enable_mask = BIT(0),
3477                 .hw.init = &(struct clk_init_data){
3478                         .name = "gcc_ufs_phy_rx_symbol_0_clk",
3479                         .ops = &clk_branch2_ops,
3480                 },
3481         },
3482 };
3483
3484 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
3485         .halt_reg = 0x45018,
3486         .halt_check = BRANCH_HALT_SKIP,
3487         .clkr = {
3488                 .enable_reg = 0x45018,
3489                 .enable_mask = BIT(0),
3490                 .hw.init = &(struct clk_init_data){
3491                         .name = "gcc_ufs_phy_tx_symbol_0_clk",
3492                         .ops = &clk_branch2_ops,
3493                 },
3494         },
3495 };
3496
3497 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
3498         .halt_reg = 0x45040,
3499         .halt_check = BRANCH_HALT,
3500         .hwcg_reg = 0x45040,
3501         .hwcg_bit = 1,
3502         .clkr = {
3503                 .enable_reg = 0x45040,
3504                 .enable_mask = BIT(0),
3505                 .hw.init = &(struct clk_init_data){
3506                         .name = "gcc_ufs_phy_unipro_core_clk",
3507                         .parent_hws = (const struct clk_hw*[]){
3508                                 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
3509                         },
3510                         .num_parents = 1,
3511                         .flags = CLK_SET_RATE_PARENT,
3512                         .ops = &clk_branch2_ops,
3513                 },
3514         },
3515 };
3516
3517 static struct clk_branch gcc_usb30_prim_master_clk = {
3518         .halt_reg = 0x1a010,
3519         .halt_check = BRANCH_HALT,
3520         .clkr = {
3521                 .enable_reg = 0x1a010,
3522                 .enable_mask = BIT(0),
3523                 .hw.init = &(struct clk_init_data){
3524                         .name = "gcc_usb30_prim_master_clk",
3525                         .parent_hws = (const struct clk_hw*[]){
3526                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
3527                         },
3528                         .num_parents = 1,
3529                         .flags = CLK_SET_RATE_PARENT,
3530                         .ops = &clk_branch2_ops,
3531                 },
3532         },
3533 };
3534
3535 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3536         .halt_reg = 0x1a018,
3537         .halt_check = BRANCH_HALT,
3538         .clkr = {
3539                 .enable_reg = 0x1a018,
3540                 .enable_mask = BIT(0),
3541                 .hw.init = &(struct clk_init_data){
3542                         .name = "gcc_usb30_prim_mock_utmi_clk",
3543                         .parent_hws = (const struct clk_hw*[]){
3544                                 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
3545                         },
3546                         .num_parents = 1,
3547                         .flags = CLK_SET_RATE_PARENT,
3548                         .ops = &clk_branch2_ops,
3549                 },
3550         },
3551 };
3552
3553 static struct clk_branch gcc_usb30_prim_sleep_clk = {
3554         .halt_reg = 0x1a014,
3555         .halt_check = BRANCH_HALT,
3556         .clkr = {
3557                 .enable_reg = 0x1a014,
3558                 .enable_mask = BIT(0),
3559                 .hw.init = &(struct clk_init_data){
3560                         .name = "gcc_usb30_prim_sleep_clk",
3561                         .ops = &clk_branch2_ops,
3562                 },
3563         },
3564 };
3565
3566 static struct clk_branch gcc_usb3_prim_clkref_clk = {
3567         .halt_reg = 0x80278,
3568         .halt_check = BRANCH_HALT,
3569         .clkr = {
3570                 .enable_reg = 0x80278,
3571                 .enable_mask = BIT(0),
3572                 .hw.init = &(struct clk_init_data){
3573                         .name = "gcc_usb3_prim_clkref_clk",
3574                         .ops = &clk_branch2_ops,
3575                 },
3576         },
3577 };
3578
3579 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3580         .halt_reg = 0x1a054,
3581         .halt_check = BRANCH_HALT,
3582         .clkr = {
3583                 .enable_reg = 0x1a054,
3584                 .enable_mask = BIT(0),
3585                 .hw.init = &(struct clk_init_data){
3586                         .name = "gcc_usb3_prim_phy_com_aux_clk",
3587                         .parent_hws = (const struct clk_hw*[]){
3588                                 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3589                         },
3590                         .num_parents = 1,
3591                         .flags = CLK_SET_RATE_PARENT,
3592                         .ops = &clk_branch2_ops,
3593                 },
3594         },
3595 };
3596
3597 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
3598         .halt_check = BRANCH_HALT_SKIP,
3599         .clkr = {
3600                 .enable_reg = 0x1a058,
3601                 .enable_mask = BIT(0),
3602                 .hw.init = &(struct clk_init_data){
3603                         .name = "gcc_usb3_prim_phy_pipe_clk",
3604                         .ops = &clk_branch2_ops,
3605                 },
3606         },
3607 };
3608
3609 static struct clk_branch gcc_vdda_vs_clk = {
3610         .halt_reg = 0x4200c,
3611         .halt_check = BRANCH_HALT,
3612         .clkr = {
3613                 .enable_reg = 0x4200c,
3614                 .enable_mask = BIT(0),
3615                 .hw.init = &(struct clk_init_data){
3616                         .name = "gcc_vdda_vs_clk",
3617                         .parent_hws = (const struct clk_hw*[]){
3618                                 &gcc_vsensor_clk_src.clkr.hw,
3619                         },
3620                         .num_parents = 1,
3621                         .flags = CLK_SET_RATE_PARENT,
3622                         .ops = &clk_branch2_ops,
3623                 },
3624         },
3625 };
3626
3627 static struct clk_branch gcc_vddcx_vs_clk = {
3628         .halt_reg = 0x42004,
3629         .halt_check = BRANCH_HALT,
3630         .clkr = {
3631                 .enable_reg = 0x42004,
3632                 .enable_mask = BIT(0),
3633                 .hw.init = &(struct clk_init_data){
3634                         .name = "gcc_vddcx_vs_clk",
3635                         .parent_hws = (const struct clk_hw*[]){
3636                                 &gcc_vsensor_clk_src.clkr.hw,
3637                         },
3638                         .num_parents = 1,
3639                         .flags = CLK_SET_RATE_PARENT,
3640                         .ops = &clk_branch2_ops,
3641                 },
3642         },
3643 };
3644
3645 static struct clk_branch gcc_vddmx_vs_clk = {
3646         .halt_reg = 0x42008,
3647         .halt_check = BRANCH_HALT,
3648         .clkr = {
3649                 .enable_reg = 0x42008,
3650                 .enable_mask = BIT(0),
3651                 .hw.init = &(struct clk_init_data){
3652                         .name = "gcc_vddmx_vs_clk",
3653                         .parent_hws = (const struct clk_hw*[]){
3654                                 &gcc_vsensor_clk_src.clkr.hw,
3655                         },
3656                         .num_parents = 1,
3657                         .flags = CLK_SET_RATE_PARENT,
3658                         .ops = &clk_branch2_ops,
3659                 },
3660         },
3661 };
3662
3663 static struct clk_branch gcc_video_ahb_clk = {
3664         .halt_reg = 0x17004,
3665         .halt_check = BRANCH_HALT,
3666         .hwcg_reg = 0x17004,
3667         .hwcg_bit = 1,
3668         .clkr = {
3669                 .enable_reg = 0x17004,
3670                 .enable_mask = BIT(0),
3671                 .hw.init = &(struct clk_init_data){
3672                         .name = "gcc_video_ahb_clk",
3673                         .flags = CLK_IS_CRITICAL,
3674                         .ops = &clk_branch2_ops,
3675                 },
3676         },
3677 };
3678
3679 static struct clk_branch gcc_video_axi0_clk = {
3680         .halt_reg = 0x1701c,
3681         .halt_check = BRANCH_HALT,
3682         .clkr = {
3683                 .enable_reg = 0x1701c,
3684                 .enable_mask = BIT(0),
3685                 .hw.init = &(struct clk_init_data){
3686                         .name = "gcc_video_axi0_clk",
3687                         .ops = &clk_branch2_ops,
3688                 },
3689         },
3690 };
3691
3692 static struct clk_branch gcc_video_throttle_core_clk = {
3693         .halt_reg = 0x17068,
3694         .halt_check = BRANCH_HALT_VOTED,
3695         .clkr = {
3696                 .enable_reg = 0x79004,
3697                 .enable_mask = BIT(28),
3698                 .hw.init = &(struct clk_init_data){
3699                         .name = "gcc_video_throttle_core_clk",
3700                         .ops = &clk_branch2_ops,
3701                 },
3702         },
3703 };
3704
3705 static struct clk_branch gcc_video_xo_clk = {
3706         .halt_reg = 0x17024,
3707         .halt_check = BRANCH_HALT,
3708         .clkr = {
3709                 .enable_reg = 0x17024,
3710                 .enable_mask = BIT(0),
3711                 .hw.init = &(struct clk_init_data){
3712                         .name = "gcc_video_xo_clk",
3713                         .flags = CLK_IS_CRITICAL,
3714                         .ops = &clk_branch2_ops,
3715                 },
3716         },
3717 };
3718
3719 static struct clk_branch gcc_vs_ctrl_ahb_clk = {
3720         .halt_reg = 0x42014,
3721         .halt_check = BRANCH_HALT,
3722         .hwcg_reg = 0x42014,
3723         .hwcg_bit = 1,
3724         .clkr = {
3725                 .enable_reg = 0x42014,
3726                 .enable_mask = BIT(0),
3727                 .hw.init = &(struct clk_init_data){
3728                         .name = "gcc_vs_ctrl_ahb_clk",
3729                         .ops = &clk_branch2_ops,
3730                 },
3731         },
3732 };
3733
3734 static struct clk_branch gcc_vs_ctrl_clk = {
3735         .halt_reg = 0x42010,
3736         .halt_check = BRANCH_HALT,
3737         .clkr = {
3738                 .enable_reg = 0x42010,
3739                 .enable_mask = BIT(0),
3740                 .hw.init = &(struct clk_init_data){
3741                         .name = "gcc_vs_ctrl_clk",
3742                         .parent_hws = (const struct clk_hw*[]){
3743                                 &gcc_vs_ctrl_clk_src.clkr.hw,
3744                         },
3745                         .num_parents = 1,
3746                         .flags = CLK_SET_RATE_PARENT,
3747                         .ops = &clk_branch2_ops,
3748                 },
3749         },
3750 };
3751
3752 static struct clk_branch gcc_wcss_vs_clk = {
3753         .halt_reg = 0x42050,
3754         .halt_check = BRANCH_HALT,
3755         .clkr = {
3756                 .enable_reg = 0x42050,
3757                 .enable_mask = BIT(0),
3758                 .hw.init = &(struct clk_init_data){
3759                         .name = "gcc_wcss_vs_clk",
3760                         .parent_hws = (const struct clk_hw*[]){
3761                                 &gcc_vsensor_clk_src.clkr.hw,
3762                         },
3763                         .num_parents = 1,
3764                         .flags = CLK_SET_RATE_PARENT,
3765                         .ops = &clk_branch2_ops,
3766                 },
3767         },
3768 };
3769
3770 static struct gdsc usb30_prim_gdsc = {
3771         .gdscr = 0x1a004,
3772         .pd = {
3773                 .name = "usb30_prim_gdsc",
3774         },
3775         .pwrsts = PWRSTS_OFF_ON,
3776 };
3777
3778 static struct gdsc ufs_phy_gdsc = {
3779         .gdscr = 0x45004,
3780         .pd = {
3781                 .name = "ufs_phy_gdsc",
3782         },
3783         .pwrsts = PWRSTS_OFF_ON,
3784 };
3785
3786 static struct gdsc camss_vfe0_gdsc = {
3787         .gdscr = 0x54004,
3788         .pd = {
3789                 .name = "camss_vfe0_gdsc",
3790         },
3791         .pwrsts = PWRSTS_OFF_ON,
3792 };
3793
3794 static struct gdsc camss_vfe1_gdsc = {
3795         .gdscr = 0x5403c,
3796         .pd = {
3797                 .name = "camss_vfe1_gdsc",
3798         },
3799         .pwrsts = PWRSTS_OFF_ON,
3800 };
3801
3802 static struct gdsc camss_top_gdsc = {
3803         .gdscr = 0x5607c,
3804         .pd = {
3805                 .name = "camss_top_gdsc",
3806         },
3807         .pwrsts = PWRSTS_OFF_ON,
3808 };
3809
3810 static struct gdsc cam_cpp_gdsc = {
3811         .gdscr = 0x560bc,
3812         .pd = {
3813                 .name = "cam_cpp_gdsc",
3814         },
3815         .pwrsts = PWRSTS_OFF_ON,
3816 };
3817
3818 static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {
3819         .gdscr = 0x7d060,
3820         .pd = {
3821                 .name = "hlos1_vote_turing_mmu_tbu1_gdsc",
3822         },
3823         .pwrsts = PWRSTS_OFF_ON,
3824         .flags = VOTABLE,
3825 };
3826
3827 static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc = {
3828         .gdscr = 0x80074,
3829         .pd = {
3830                 .name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc",
3831         },
3832         .pwrsts = PWRSTS_OFF_ON,
3833         .flags = VOTABLE,
3834 };
3835
3836 static struct gdsc hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc = {
3837         .gdscr = 0x80084,
3838         .pd = {
3839                 .name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc",
3840         },
3841         .pwrsts = PWRSTS_OFF_ON,
3842         .flags = VOTABLE,
3843 };
3844
3845
3846 static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {
3847         .gdscr = 0x80094,
3848         .pd = {
3849                 .name = "hlos1_vote_turing_mmu_tbu0_gdsc",
3850         },
3851         .pwrsts = PWRSTS_OFF_ON,
3852         .flags = VOTABLE,
3853 };
3854
3855 static struct gdsc *gcc_sm6125_gdscs[] = {
3856         [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3857         [UFS_PHY_GDSC] = &ufs_phy_gdsc,
3858         [CAMSS_VFE0_GDSC] = &camss_vfe0_gdsc,
3859         [CAMSS_VFE1_GDSC] = &camss_vfe1_gdsc,
3860         [CAMSS_TOP_GDSC] = &camss_top_gdsc,
3861         [CAM_CPP_GDSC] = &cam_cpp_gdsc,
3862         [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
3863         [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc,
3864         [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = &hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc,
3865         [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,
3866 };
3867
3868 static struct clk_hw *gcc_sm6125_hws[] = {
3869         [GPLL0_OUT_AUX2] = &gpll0_out_aux2.hw,
3870         [GPLL0_OUT_MAIN] = &gpll0_out_main.hw,
3871         [GPLL6_OUT_MAIN] = &gpll6_out_main.hw,
3872         [GPLL7_OUT_MAIN] = &gpll7_out_main.hw,
3873         [GPLL8_OUT_MAIN] = &gpll8_out_main.hw,
3874         [GPLL9_OUT_MAIN] = &gpll9_out_main.hw,
3875 };
3876
3877 static struct clk_regmap *gcc_sm6125_clocks[] = {
3878         [GCC_AHB2PHY_CSI_CLK] = &gcc_ahb2phy_csi_clk.clkr,
3879         [GCC_AHB2PHY_USB_CLK] = &gcc_ahb2phy_usb_clk.clkr,
3880         [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr,
3881         [GCC_BIMC_GPU_AXI_CLK] = &gcc_bimc_gpu_axi_clk.clkr,
3882         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3883         [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3884         [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3885         [GCC_CAMSS_AHB_CLK_SRC] = &gcc_camss_ahb_clk_src.clkr,
3886         [GCC_CAMSS_CCI_AHB_CLK] = &gcc_camss_cci_ahb_clk.clkr,
3887         [GCC_CAMSS_CCI_CLK] = &gcc_camss_cci_clk.clkr,
3888         [GCC_CAMSS_CCI_CLK_SRC] = &gcc_camss_cci_clk_src.clkr,
3889         [GCC_CAMSS_CPHY_CSID0_CLK] = &gcc_camss_cphy_csid0_clk.clkr,
3890         [GCC_CAMSS_CPHY_CSID1_CLK] = &gcc_camss_cphy_csid1_clk.clkr,
3891         [GCC_CAMSS_CPHY_CSID2_CLK] = &gcc_camss_cphy_csid2_clk.clkr,
3892         [GCC_CAMSS_CPHY_CSID3_CLK] = &gcc_camss_cphy_csid3_clk.clkr,
3893         [GCC_CAMSS_CPP_AHB_CLK] = &gcc_camss_cpp_ahb_clk.clkr,
3894         [GCC_CAMSS_CPP_AXI_CLK] = &gcc_camss_cpp_axi_clk.clkr,
3895         [GCC_CAMSS_CPP_CLK] = &gcc_camss_cpp_clk.clkr,
3896         [GCC_CAMSS_CPP_CLK_SRC] = &gcc_camss_cpp_clk_src.clkr,
3897         [GCC_CAMSS_CPP_VBIF_AHB_CLK] = &gcc_camss_cpp_vbif_ahb_clk.clkr,
3898         [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr,
3899         [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr,
3900         [GCC_CAMSS_CSI0_CLK_SRC] = &gcc_camss_csi0_clk_src.clkr,
3901         [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr,
3902         [GCC_CAMSS_CSI0PHYTIMER_CLK_SRC] = &gcc_camss_csi0phytimer_clk_src.clkr,
3903         [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr,
3904         [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr,
3905         [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr,
3906         [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr,
3907         [GCC_CAMSS_CSI1_CLK_SRC] = &gcc_camss_csi1_clk_src.clkr,
3908         [GCC_CAMSS_CSI1PHYTIMER_CLK] = &gcc_camss_csi1phytimer_clk.clkr,
3909         [GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr,
3910         [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr,
3911         [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr,
3912         [GCC_CAMSS_CSI2_AHB_CLK] = &gcc_camss_csi2_ahb_clk.clkr,
3913         [GCC_CAMSS_CSI2_CLK] = &gcc_camss_csi2_clk.clkr,
3914         [GCC_CAMSS_CSI2_CLK_SRC] = &gcc_camss_csi2_clk_src.clkr,
3915         [GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr,
3916         [GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr,
3917         [GCC_CAMSS_CSI2PIX_CLK] = &gcc_camss_csi2pix_clk.clkr,
3918         [GCC_CAMSS_CSI2RDI_CLK] = &gcc_camss_csi2rdi_clk.clkr,
3919         [GCC_CAMSS_CSI3_AHB_CLK] = &gcc_camss_csi3_ahb_clk.clkr,
3920         [GCC_CAMSS_CSI3_CLK] = &gcc_camss_csi3_clk.clkr,
3921         [GCC_CAMSS_CSI3_CLK_SRC] = &gcc_camss_csi3_clk_src.clkr,
3922         [GCC_CAMSS_CSI3PIX_CLK] = &gcc_camss_csi3pix_clk.clkr,
3923         [GCC_CAMSS_CSI3RDI_CLK] = &gcc_camss_csi3rdi_clk.clkr,
3924         [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr,
3925         [GCC_CAMSS_CSI_VFE1_CLK] = &gcc_camss_csi_vfe1_clk.clkr,
3926         [GCC_CAMSS_CSIPHY0_CLK] = &gcc_camss_csiphy0_clk.clkr,
3927         [GCC_CAMSS_CSIPHY1_CLK] = &gcc_camss_csiphy1_clk.clkr,
3928         [GCC_CAMSS_CSIPHY2_CLK] = &gcc_camss_csiphy2_clk.clkr,
3929         [GCC_CAMSS_CSIPHY_CLK_SRC] = &gcc_camss_csiphy_clk_src.clkr,
3930         [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,
3931         [GCC_CAMSS_GP0_CLK_SRC] = &gcc_camss_gp0_clk_src.clkr,
3932         [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr,
3933         [GCC_CAMSS_GP1_CLK_SRC] = &gcc_camss_gp1_clk_src.clkr,
3934         [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr,
3935         [GCC_CAMSS_JPEG_AHB_CLK] = &gcc_camss_jpeg_ahb_clk.clkr,
3936         [GCC_CAMSS_JPEG_AXI_CLK] = &gcc_camss_jpeg_axi_clk.clkr,
3937         [GCC_CAMSS_JPEG_CLK] = &gcc_camss_jpeg_clk.clkr,
3938         [GCC_CAMSS_JPEG_CLK_SRC] = &gcc_camss_jpeg_clk_src.clkr,
3939         [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
3940         [GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr,
3941         [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
3942         [GCC_CAMSS_MCLK1_CLK_SRC] = &gcc_camss_mclk1_clk_src.clkr,
3943         [GCC_CAMSS_MCLK2_CLK] = &gcc_camss_mclk2_clk.clkr,
3944         [GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr,
3945         [GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr,
3946         [GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr,
3947         [GCC_CAMSS_MICRO_AHB_CLK] = &gcc_camss_micro_ahb_clk.clkr,
3948         [GCC_CAMSS_THROTTLE_NRT_AXI_CLK] = &gcc_camss_throttle_nrt_axi_clk.clkr,
3949         [GCC_CAMSS_THROTTLE_RT_AXI_CLK] = &gcc_camss_throttle_rt_axi_clk.clkr,
3950         [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr,
3951         [GCC_CAMSS_VFE0_AHB_CLK] = &gcc_camss_vfe0_ahb_clk.clkr,
3952         [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr,
3953         [GCC_CAMSS_VFE0_CLK_SRC] = &gcc_camss_vfe0_clk_src.clkr,
3954         [GCC_CAMSS_VFE0_STREAM_CLK] = &gcc_camss_vfe0_stream_clk.clkr,
3955         [GCC_CAMSS_VFE1_AHB_CLK] = &gcc_camss_vfe1_ahb_clk.clkr,
3956         [GCC_CAMSS_VFE1_CLK] = &gcc_camss_vfe1_clk.clkr,
3957         [GCC_CAMSS_VFE1_CLK_SRC] = &gcc_camss_vfe1_clk_src.clkr,
3958         [GCC_CAMSS_VFE1_STREAM_CLK] = &gcc_camss_vfe1_stream_clk.clkr,
3959         [GCC_CAMSS_VFE_TSCTR_CLK] = &gcc_camss_vfe_tsctr_clk.clkr,
3960         [GCC_CAMSS_VFE_VBIF_AHB_CLK] = &gcc_camss_vfe_vbif_ahb_clk.clkr,
3961         [GCC_CAMSS_VFE_VBIF_AXI_CLK] = &gcc_camss_vfe_vbif_axi_clk.clkr,
3962         [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
3963         [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
3964         [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
3965         [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3966         [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3967         [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3968         [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
3969         [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3970         [GCC_DISP_THROTTLE_CORE_CLK] = &gcc_disp_throttle_core_clk.clkr,
3971         [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3972         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3973         [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3974         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3975         [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3976         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3977         [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3978         [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3979         [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3980         [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3981         [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3982         [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3983         [GCC_GPU_THROTTLE_CORE_CLK] = &gcc_gpu_throttle_core_clk.clkr,
3984         [GCC_GPU_THROTTLE_XO_CLK] = &gcc_gpu_throttle_xo_clk.clkr,
3985         [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr,
3986         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3987         [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3988         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3989         [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3990         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3991         [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3992         [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3993         [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3994         [GCC_QMIP_GPU_CFG_AHB_CLK] = &gcc_qmip_gpu_cfg_ahb_clk.clkr,
3995         [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3996         [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3997         [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3998         [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3999         [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
4000         [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
4001         [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
4002         [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
4003         [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
4004         [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
4005         [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
4006         [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
4007         [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
4008         [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
4009         [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
4010         [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
4011         [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
4012         [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
4013         [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
4014         [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
4015         [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
4016         [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
4017         [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
4018         [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
4019         [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
4020         [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
4021         [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
4022         [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
4023         [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
4024         [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
4025         [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
4026         [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
4027         [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
4028         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4029         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4030         [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
4031         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4032         [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
4033         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
4034         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
4035         [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
4036         [GCC_SYS_NOC_COMPUTE_SF_AXI_CLK] = &gcc_sys_noc_compute_sf_axi_clk.clkr,
4037         [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
4038         [GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr,
4039         [GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr,
4040         [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
4041         [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
4042         [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
4043         [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
4044         [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
4045         [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
4046         [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
4047         [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
4048         [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
4049         [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
4050         [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
4051         [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
4052                 &gcc_ufs_phy_unipro_core_clk_src.clkr,
4053         [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
4054         [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
4055         [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
4056         [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
4057                 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
4058         [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
4059         [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
4060         [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
4061         [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
4062         [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr,
4063         [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr,
4064         [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr,
4065         [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
4066         [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
4067         [GCC_VIDEO_THROTTLE_CORE_CLK] = &gcc_video_throttle_core_clk.clkr,
4068         [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
4069         [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr,
4070         [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr,
4071         [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr,
4072         [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
4073         [GCC_WCSS_VS_CLK] = &gcc_wcss_vs_clk.clkr,
4074         [GPLL0_OUT_EARLY] = &gpll0_out_early.clkr,
4075         [GPLL3_OUT_EARLY] = &gpll3_out_early.clkr,
4076         [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
4077         [GPLL5_OUT_MAIN] = &gpll5_out_main.clkr,
4078         [GPLL6_OUT_EARLY] = &gpll6_out_early.clkr,
4079         [GPLL7_OUT_EARLY] = &gpll7_out_early.clkr,
4080         [GPLL8_OUT_EARLY] = &gpll8_out_early.clkr,
4081         [GPLL9_OUT_EARLY] = &gpll9_out_early.clkr,
4082         [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
4083 };
4084
4085 static const struct qcom_reset_map gcc_sm6125_resets[] = {
4086         [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
4087         [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 },
4088         [GCC_UFS_PHY_BCR] = { 0x45000 },
4089         [GCC_USB30_PRIM_BCR] = { 0x1a000 },
4090         [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
4091         [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 },
4092         [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
4093         [GCC_CAMSS_MICRO_BCR] = { 0x560ac },
4094 };
4095
4096 static struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
4097         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
4098         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
4099         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
4100         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
4101         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
4102         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
4103         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
4104         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
4105         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
4106         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
4107         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
4108         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
4109 };
4110
4111 static const struct regmap_config gcc_sm6125_regmap_config = {
4112         .reg_bits = 32,
4113         .reg_stride = 4,
4114         .val_bits = 32,
4115         .max_register = 0xc7000,
4116         .fast_io = true,
4117 };
4118
4119 static const struct qcom_cc_desc gcc_sm6125_desc = {
4120         .config = &gcc_sm6125_regmap_config,
4121         .clks = gcc_sm6125_clocks,
4122         .num_clks = ARRAY_SIZE(gcc_sm6125_clocks),
4123         .clk_hws = gcc_sm6125_hws,
4124         .num_clk_hws = ARRAY_SIZE(gcc_sm6125_hws),
4125         .resets = gcc_sm6125_resets,
4126         .num_resets = ARRAY_SIZE(gcc_sm6125_resets),
4127         .gdscs = gcc_sm6125_gdscs,
4128         .num_gdscs = ARRAY_SIZE(gcc_sm6125_gdscs),
4129 };
4130
4131 static const struct of_device_id gcc_sm6125_match_table[] = {
4132         { .compatible = "qcom,gcc-sm6125" },
4133         { }
4134 };
4135 MODULE_DEVICE_TABLE(of, gcc_sm6125_match_table);
4136
4137 static int gcc_sm6125_probe(struct platform_device *pdev)
4138 {
4139         struct regmap *regmap;
4140         int ret;
4141
4142         regmap = qcom_cc_map(pdev, &gcc_sm6125_desc);
4143         if (IS_ERR(regmap))
4144                 return PTR_ERR(regmap);
4145
4146         /*
4147          * Disable the GPLL0 active input to video block via
4148          * MISC registers.
4149          */
4150         regmap_update_bits(regmap, 0x80258, 0x1, 0x1);
4151
4152         /*
4153          * Enable DUAL_EDGE mode for MCLK RCGs
4154          * This is requierd to enable MND divider mode
4155          */
4156         regmap_update_bits(regmap, 0x51004, 0x3000, 0x2000);
4157         regmap_update_bits(regmap, 0x51020, 0x3000, 0x2000);
4158         regmap_update_bits(regmap, 0x5103c, 0x3000, 0x2000);
4159         regmap_update_bits(regmap, 0x51058, 0x3000, 0x2000);
4160
4161         ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
4162                                                 ARRAY_SIZE(gcc_dfs_clocks));
4163         if (ret)
4164                 return ret;
4165
4166         return qcom_cc_really_probe(pdev, &gcc_sm6125_desc, regmap);
4167 }
4168
4169 static struct platform_driver gcc_sm6125_driver = {
4170         .probe = gcc_sm6125_probe,
4171         .driver = {
4172                 .name = "gcc-sm6125",
4173                 .of_match_table = gcc_sm6125_match_table,
4174         },
4175 };
4176
4177 static int __init gcc_sm6125_init(void)
4178 {
4179         return platform_driver_register(&gcc_sm6125_driver);
4180 }
4181 subsys_initcall(gcc_sm6125_init);
4182
4183 static void __exit gcc_sm6125_exit(void)
4184 {
4185         platform_driver_unregister(&gcc_sm6125_driver);
4186 }
4187 module_exit(gcc_sm6125_exit);
4188
4189 MODULE_DESCRIPTION("QTI GCC SM6125 Driver");
4190 MODULE_LICENSE("GPL v2");