1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
6 #include <linux/clk-provider.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/of_device.h>
12 #include <linux/regmap.h>
14 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
19 #include "clk-regmap.h"
20 #include "clk-regmap-divider.h"
21 #include "clk-regmap-mux.h"
32 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
35 static struct clk_alpha_pll gpll0 = {
37 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
39 .enable_reg = 0x6d000,
40 .enable_mask = BIT(0),
41 .hw.init = &(struct clk_init_data){
43 .parent_data = &(const struct clk_parent_data){
47 .ops = &clk_alpha_pll_fixed_lucid_evo_ops,
52 static const struct clk_div_table post_div_table_gpll0_out_even[] = {
57 static struct clk_alpha_pll_postdiv gpll0_out_even = {
60 .post_div_table = post_div_table_gpll0_out_even,
61 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
63 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
64 .clkr.hw.init = &(struct clk_init_data){
65 .name = "gpll0_out_even",
66 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
68 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
72 static const struct parent_map gcc_parent_map_0[] = {
74 { P_GPLL0_OUT_MAIN, 1 },
75 { P_GPLL0_OUT_EVEN, 6 },
78 static const struct clk_parent_data gcc_parent_data_0[] = {
79 { .fw_name = "bi_tcxo" },
80 { .hw = &gpll0.clkr.hw },
81 { .hw = &gpll0_out_even.clkr.hw },
84 static const struct clk_parent_data gcc_parent_data_0_ao[] = {
85 { .fw_name = "bi_tcxo_ao" },
86 { .hw = &gpll0.clkr.hw },
87 { .hw = &gpll0_out_even.clkr.hw },
90 static const struct parent_map gcc_parent_map_2[] = {
92 { P_GPLL0_OUT_MAIN, 1 },
94 { P_GPLL0_OUT_EVEN, 6 },
97 static const struct clk_parent_data gcc_parent_data_2[] = {
98 { .fw_name = "bi_tcxo" },
99 { .hw = &gpll0.clkr.hw },
100 { .fw_name = "sleep_clk" },
101 { .hw = &gpll0_out_even.clkr.hw },
104 static const struct parent_map gcc_parent_map_3[] = {
109 static const struct clk_parent_data gcc_parent_data_3[] = {
110 { .fw_name = "bi_tcxo" },
111 { .fw_name = "sleep_clk" },
114 static const struct parent_map gcc_parent_map_4[] = {
118 static const struct parent_map gcc_parent_map_5[] = {
119 { P_PCIE_PIPE_CLK, 0 },
123 static const struct clk_parent_data gcc_parent_data_5[] = {
124 { .fw_name = "pcie_pipe_clk"},
125 { .fw_name = "bi_tcxo"},
128 static const struct parent_map gcc_parent_map_6[] = {
129 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
133 static const struct clk_parent_data gcc_parent_data_6[] = {
134 { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk"},
135 { .fw_name = "bi_tcxo"},
138 static struct clk_regmap_mux gcc_pcie_aux_clk_src = {
142 .parent_map = gcc_parent_map_4,
144 .hw.init = &(struct clk_init_data){
145 .name = "gcc_pcie_aux_clk_src",
146 .parent_data = &(const struct clk_parent_data){
147 .fw_name = "bi_tcxo",
150 .ops = &clk_regmap_mux_closest_ops,
155 static struct clk_regmap_mux gcc_pcie_pipe_clk_src = {
159 .parent_map = gcc_parent_map_5,
161 .hw.init = &(struct clk_init_data){
162 .name = "gcc_pcie_pipe_clk_src",
163 .parent_data = gcc_parent_data_5,
165 .ops = &clk_regmap_mux_closest_ops,
170 static struct clk_regmap_mux gcc_usb3_phy_pipe_clk_src = {
174 .parent_map = gcc_parent_map_6,
176 .hw.init = &(struct clk_init_data){
177 .name = "gcc_usb3_phy_pipe_clk_src",
178 .parent_data = gcc_parent_data_6,
180 .ops = &clk_regmap_mux_closest_ops,
185 static const struct freq_tbl ftbl_gcc_blsp1_qup1_i2c_apps_clk_src[] = {
186 F(9600000, P_BI_TCXO, 2, 0, 0),
187 F(19200000, P_BI_TCXO, 1, 0, 0),
188 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
192 static struct clk_rcg2 gcc_blsp1_qup1_i2c_apps_clk_src = {
196 .parent_map = gcc_parent_map_0,
197 .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
198 .clkr.hw.init = &(struct clk_init_data){
199 .name = "gcc_blsp1_qup1_i2c_apps_clk_src",
200 .parent_data = gcc_parent_data_0,
202 .flags = CLK_SET_RATE_PARENT,
203 .ops = &clk_rcg2_ops,
207 static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = {
208 F(960000, P_BI_TCXO, 10, 1, 2),
209 F(4800000, P_BI_TCXO, 4, 0, 0),
210 F(9600000, P_BI_TCXO, 2, 0, 0),
211 F(15000000, P_GPLL0_OUT_EVEN, 5, 1, 4),
212 F(19200000, P_BI_TCXO, 1, 0, 0),
213 F(24000000, P_GPLL0_OUT_MAIN, 12.5, 1, 2),
214 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
215 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
219 static struct clk_rcg2 gcc_blsp1_qup1_spi_apps_clk_src = {
223 .parent_map = gcc_parent_map_0,
224 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
225 .clkr.hw.init = &(struct clk_init_data){
226 .name = "gcc_blsp1_qup1_spi_apps_clk_src",
227 .parent_data = gcc_parent_data_0,
229 .flags = CLK_SET_RATE_PARENT,
230 .ops = &clk_rcg2_ops,
234 static struct clk_rcg2 gcc_blsp1_qup2_i2c_apps_clk_src = {
238 .parent_map = gcc_parent_map_0,
239 .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
240 .clkr.hw.init = &(struct clk_init_data){
241 .name = "gcc_blsp1_qup2_i2c_apps_clk_src",
242 .parent_data = gcc_parent_data_0,
244 .flags = CLK_SET_RATE_PARENT,
245 .ops = &clk_rcg2_ops,
249 static struct clk_rcg2 gcc_blsp1_qup2_spi_apps_clk_src = {
253 .parent_map = gcc_parent_map_0,
254 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
255 .clkr.hw.init = &(struct clk_init_data){
256 .name = "gcc_blsp1_qup2_spi_apps_clk_src",
257 .parent_data = gcc_parent_data_0,
259 .flags = CLK_SET_RATE_PARENT,
260 .ops = &clk_rcg2_ops,
264 static struct clk_rcg2 gcc_blsp1_qup3_i2c_apps_clk_src = {
268 .parent_map = gcc_parent_map_0,
269 .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
270 .clkr.hw.init = &(struct clk_init_data){
271 .name = "gcc_blsp1_qup3_i2c_apps_clk_src",
272 .parent_data = gcc_parent_data_0,
274 .flags = CLK_SET_RATE_PARENT,
275 .ops = &clk_rcg2_ops,
279 static struct clk_rcg2 gcc_blsp1_qup3_spi_apps_clk_src = {
283 .parent_map = gcc_parent_map_0,
284 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
285 .clkr.hw.init = &(struct clk_init_data){
286 .name = "gcc_blsp1_qup3_spi_apps_clk_src",
287 .parent_data = gcc_parent_data_0,
289 .flags = CLK_SET_RATE_PARENT,
290 .ops = &clk_rcg2_ops,
294 static struct clk_rcg2 gcc_blsp1_qup4_i2c_apps_clk_src = {
298 .parent_map = gcc_parent_map_0,
299 .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src,
300 .clkr.hw.init = &(struct clk_init_data){
301 .name = "gcc_blsp1_qup4_i2c_apps_clk_src",
302 .parent_data = gcc_parent_data_0,
304 .flags = CLK_SET_RATE_PARENT,
305 .ops = &clk_rcg2_ops,
309 static struct clk_rcg2 gcc_blsp1_qup4_spi_apps_clk_src = {
313 .parent_map = gcc_parent_map_0,
314 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
315 .clkr.hw.init = &(struct clk_init_data){
316 .name = "gcc_blsp1_qup4_spi_apps_clk_src",
317 .parent_data = gcc_parent_data_0,
319 .flags = CLK_SET_RATE_PARENT,
320 .ops = &clk_rcg2_ops,
324 static const struct freq_tbl ftbl_gcc_blsp1_uart1_apps_clk_src[] = {
325 F(3686400, P_GPLL0_OUT_EVEN, 1, 192, 15625),
326 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
327 F(9600000, P_BI_TCXO, 2, 0, 0),
328 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
329 F(16000000, P_GPLL0_OUT_EVEN, 1, 4, 75),
330 F(19200000, P_BI_TCXO, 1, 0, 0),
331 F(19354839, P_GPLL0_OUT_MAIN, 15.5, 1, 2),
332 F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
333 F(20689655, P_GPLL0_OUT_MAIN, 14.5, 1, 2),
334 F(21428571, P_GPLL0_OUT_MAIN, 14, 1, 2),
335 F(22222222, P_GPLL0_OUT_MAIN, 13.5, 1, 2),
336 F(23076923, P_GPLL0_OUT_MAIN, 13, 1, 2),
337 F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5),
338 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
339 F(26086957, P_GPLL0_OUT_MAIN, 11.5, 1, 2),
340 F(27272727, P_GPLL0_OUT_MAIN, 11, 1, 2),
341 F(28571429, P_GPLL0_OUT_MAIN, 10.5, 1, 2),
342 F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75),
343 F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
344 F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375),
345 F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
346 F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375),
347 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75),
348 F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625),
349 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
350 F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
354 static struct clk_rcg2 gcc_blsp1_uart1_apps_clk_src = {
358 .parent_map = gcc_parent_map_0,
359 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
360 .clkr.hw.init = &(struct clk_init_data){
361 .name = "gcc_blsp1_uart1_apps_clk_src",
362 .parent_data = gcc_parent_data_0,
364 .flags = CLK_SET_RATE_PARENT,
365 .ops = &clk_rcg2_ops,
369 static struct clk_rcg2 gcc_blsp1_uart2_apps_clk_src = {
373 .parent_map = gcc_parent_map_0,
374 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
375 .clkr.hw.init = &(struct clk_init_data){
376 .name = "gcc_blsp1_uart2_apps_clk_src",
377 .parent_data = gcc_parent_data_0,
379 .flags = CLK_SET_RATE_PARENT,
380 .ops = &clk_rcg2_ops,
384 static struct clk_rcg2 gcc_blsp1_uart3_apps_clk_src = {
388 .parent_map = gcc_parent_map_0,
389 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
390 .clkr.hw.init = &(struct clk_init_data){
391 .name = "gcc_blsp1_uart3_apps_clk_src",
392 .parent_data = gcc_parent_data_0,
394 .flags = CLK_SET_RATE_PARENT,
395 .ops = &clk_rcg2_ops,
399 static struct clk_rcg2 gcc_blsp1_uart4_apps_clk_src = {
403 .parent_map = gcc_parent_map_0,
404 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
405 .clkr.hw.init = &(struct clk_init_data){
406 .name = "gcc_blsp1_uart4_apps_clk_src",
407 .parent_data = gcc_parent_data_0,
409 .flags = CLK_SET_RATE_PARENT,
410 .ops = &clk_rcg2_ops,
414 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
415 F(19200000, P_BI_TCXO, 1, 0, 0),
416 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
417 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
418 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
422 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
426 .parent_map = gcc_parent_map_0,
427 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
428 .clkr.hw.init = &(struct clk_init_data){
429 .name = "gcc_cpuss_ahb_clk_src",
430 .parent_data = gcc_parent_data_0_ao,
432 .flags = CLK_SET_RATE_PARENT,
433 .ops = &clk_rcg2_ops,
437 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
438 F(19200000, P_BI_TCXO, 1, 0, 0),
439 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
440 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
441 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
445 static struct clk_rcg2 gcc_gp1_clk_src = {
449 .parent_map = gcc_parent_map_2,
450 .freq_tbl = ftbl_gcc_gp1_clk_src,
451 .clkr.hw.init = &(struct clk_init_data){
452 .name = "gcc_gp1_clk_src",
453 .parent_data = gcc_parent_data_2,
455 .flags = CLK_SET_RATE_PARENT,
456 .ops = &clk_rcg2_ops,
460 static struct clk_rcg2 gcc_gp2_clk_src = {
464 .parent_map = gcc_parent_map_2,
465 .freq_tbl = ftbl_gcc_gp1_clk_src,
466 .clkr.hw.init = &(struct clk_init_data){
467 .name = "gcc_gp2_clk_src",
468 .parent_data = gcc_parent_data_2,
470 .flags = CLK_SET_RATE_PARENT,
471 .ops = &clk_rcg2_ops,
475 static struct clk_rcg2 gcc_gp3_clk_src = {
479 .parent_map = gcc_parent_map_2,
480 .freq_tbl = ftbl_gcc_gp1_clk_src,
481 .clkr.hw.init = &(struct clk_init_data){
482 .name = "gcc_gp3_clk_src",
483 .parent_data = gcc_parent_data_2,
485 .flags = CLK_SET_RATE_PARENT,
486 .ops = &clk_rcg2_ops,
490 static const struct freq_tbl ftbl_gcc_pcie_aux_phy_clk_src[] = {
491 F(19200000, P_BI_TCXO, 1, 0, 0),
495 static struct clk_rcg2 gcc_pcie_aux_phy_clk_src = {
499 .parent_map = gcc_parent_map_3,
500 .freq_tbl = ftbl_gcc_pcie_aux_phy_clk_src,
501 .clkr.hw.init = &(struct clk_init_data){
502 .name = "gcc_pcie_aux_phy_clk_src",
503 .parent_data = gcc_parent_data_3,
505 .flags = CLK_SET_RATE_PARENT,
506 .ops = &clk_rcg2_ops,
510 static const struct freq_tbl ftbl_gcc_pcie_rchng_phy_clk_src[] = {
511 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
515 static struct clk_rcg2 gcc_pcie_rchng_phy_clk_src = {
519 .parent_map = gcc_parent_map_2,
520 .freq_tbl = ftbl_gcc_pcie_rchng_phy_clk_src,
521 .clkr.hw.init = &(struct clk_init_data){
522 .name = "gcc_pcie_rchng_phy_clk_src",
523 .parent_data = gcc_parent_data_2,
525 .flags = CLK_SET_RATE_PARENT,
526 .ops = &clk_rcg2_ops,
530 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
531 F(19200000, P_BI_TCXO, 1, 0, 0),
532 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
536 static struct clk_rcg2 gcc_pdm2_clk_src = {
540 .parent_map = gcc_parent_map_0,
541 .freq_tbl = ftbl_gcc_pdm2_clk_src,
542 .clkr.hw.init = &(struct clk_init_data){
543 .name = "gcc_pdm2_clk_src",
544 .parent_data = gcc_parent_data_0,
546 .flags = CLK_SET_RATE_PARENT,
547 .ops = &clk_rcg2_ops,
551 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
552 F(400000, P_BI_TCXO, 12, 1, 4),
553 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
554 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
555 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
556 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
560 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
564 .parent_map = gcc_parent_map_0,
565 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
566 .clkr.hw.init = &(struct clk_init_data){
567 .name = "gcc_sdcc1_apps_clk_src",
568 .parent_data = gcc_parent_data_0,
570 .flags = CLK_SET_RATE_PARENT,
571 .ops = &clk_rcg2_ops,
575 static const struct freq_tbl ftbl_gcc_usb30_master_clk_src[] = {
576 F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
580 static struct clk_rcg2 gcc_usb30_master_clk_src = {
584 .parent_map = gcc_parent_map_0,
585 .freq_tbl = ftbl_gcc_usb30_master_clk_src,
586 .clkr.hw.init = &(struct clk_init_data){
587 .name = "gcc_usb30_master_clk_src",
588 .parent_data = gcc_parent_data_0,
590 .flags = CLK_SET_RATE_PARENT,
591 .ops = &clk_rcg2_ops,
595 static struct clk_rcg2 gcc_usb30_mock_utmi_clk_src = {
599 .parent_map = gcc_parent_map_0,
600 .freq_tbl = ftbl_gcc_pcie_aux_phy_clk_src,
601 .clkr.hw.init = &(struct clk_init_data){
602 .name = "gcc_usb30_mock_utmi_clk_src",
603 .parent_data = gcc_parent_data_0,
605 .flags = CLK_SET_RATE_PARENT,
606 .ops = &clk_rcg2_ops,
610 static const struct freq_tbl ftbl_gcc_usb3_phy_aux_clk_src[] = {
611 F(1000000, P_BI_TCXO, 1, 5, 96),
612 F(19200000, P_BI_TCXO, 1, 0, 0),
616 static struct clk_rcg2 gcc_usb3_phy_aux_clk_src = {
620 .parent_map = gcc_parent_map_3,
621 .freq_tbl = ftbl_gcc_usb3_phy_aux_clk_src,
622 .clkr.hw.init = &(struct clk_init_data){
623 .name = "gcc_usb3_phy_aux_clk_src",
624 .parent_data = gcc_parent_data_3,
626 .flags = CLK_SET_RATE_PARENT,
627 .ops = &clk_rcg2_ops,
631 static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = {
635 .clkr.hw.init = &(struct clk_init_data) {
636 .name = "gcc_cpuss_ahb_postdiv_clk_src",
637 .parent_data = &(const struct clk_parent_data){
638 .hw = &gcc_cpuss_ahb_clk_src.clkr.hw,
641 .flags = CLK_SET_RATE_PARENT,
642 .ops = &clk_regmap_div_ro_ops,
646 static struct clk_regmap_div gcc_usb30_mock_utmi_postdiv_clk_src = {
650 .clkr.hw.init = &(struct clk_init_data) {
651 .name = "gcc_usb30_mock_utmi_postdiv_clk_src",
652 .parent_data = &(const struct clk_parent_data){
653 .hw = &gcc_usb30_mock_utmi_clk_src.clkr.hw,
656 .flags = CLK_SET_RATE_PARENT,
657 .ops = &clk_regmap_div_ro_ops,
661 static struct clk_branch gcc_ahb_pcie_link_clk = {
663 .halt_check = BRANCH_HALT,
665 .enable_reg = 0x2e004,
666 .enable_mask = BIT(0),
667 .hw.init = &(struct clk_init_data){
668 .name = "gcc_ahb_pcie_link_clk",
669 .ops = &clk_branch2_ops,
674 static struct clk_branch gcc_blsp1_ahb_clk = {
676 .halt_check = BRANCH_HALT_VOTED,
678 .enable_reg = 0x6d008,
679 .enable_mask = BIT(14),
680 .hw.init = &(struct clk_init_data){
681 .name = "gcc_blsp1_ahb_clk",
682 .ops = &clk_branch2_ops,
687 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
689 .halt_check = BRANCH_HALT,
691 .enable_reg = 0x1c008,
692 .enable_mask = BIT(0),
693 .hw.init = &(struct clk_init_data){
694 .name = "gcc_blsp1_qup1_i2c_apps_clk",
695 .parent_data = &(const struct clk_parent_data){
696 .hw = &gcc_blsp1_qup1_i2c_apps_clk_src.clkr.hw,
699 .flags = CLK_SET_RATE_PARENT,
700 .ops = &clk_branch2_ops,
705 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
707 .halt_check = BRANCH_HALT,
709 .enable_reg = 0x1c004,
710 .enable_mask = BIT(0),
711 .hw.init = &(struct clk_init_data){
712 .name = "gcc_blsp1_qup1_spi_apps_clk",
713 .parent_data = &(const struct clk_parent_data){
714 .hw = &gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw,
717 .flags = CLK_SET_RATE_PARENT,
718 .ops = &clk_branch2_ops,
723 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
725 .halt_check = BRANCH_HALT,
727 .enable_reg = 0x1e008,
728 .enable_mask = BIT(0),
729 .hw.init = &(struct clk_init_data){
730 .name = "gcc_blsp1_qup2_i2c_apps_clk",
731 .parent_data = &(const struct clk_parent_data){
732 .hw = &gcc_blsp1_qup2_i2c_apps_clk_src.clkr.hw,
735 .flags = CLK_SET_RATE_PARENT,
736 .ops = &clk_branch2_ops,
741 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
743 .halt_check = BRANCH_HALT,
745 .enable_reg = 0x1e004,
746 .enable_mask = BIT(0),
747 .hw.init = &(struct clk_init_data){
748 .name = "gcc_blsp1_qup2_spi_apps_clk",
749 .parent_data = &(const struct clk_parent_data){
750 .hw = &gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw,
753 .flags = CLK_SET_RATE_PARENT,
754 .ops = &clk_branch2_ops,
759 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
761 .halt_check = BRANCH_HALT,
763 .enable_reg = 0x20008,
764 .enable_mask = BIT(0),
765 .hw.init = &(struct clk_init_data){
766 .name = "gcc_blsp1_qup3_i2c_apps_clk",
767 .parent_data = &(const struct clk_parent_data){
768 .hw = &gcc_blsp1_qup3_i2c_apps_clk_src.clkr.hw,
771 .flags = CLK_SET_RATE_PARENT,
772 .ops = &clk_branch2_ops,
777 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
779 .halt_check = BRANCH_HALT,
781 .enable_reg = 0x20004,
782 .enable_mask = BIT(0),
783 .hw.init = &(struct clk_init_data){
784 .name = "gcc_blsp1_qup3_spi_apps_clk",
785 .parent_data = &(const struct clk_parent_data){
786 .hw = &gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw,
789 .flags = CLK_SET_RATE_PARENT,
790 .ops = &clk_branch2_ops,
795 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
797 .halt_check = BRANCH_HALT,
799 .enable_reg = 0x22008,
800 .enable_mask = BIT(0),
801 .hw.init = &(struct clk_init_data){
802 .name = "gcc_blsp1_qup4_i2c_apps_clk",
803 .parent_data = &(const struct clk_parent_data){
804 .hw = &gcc_blsp1_qup4_i2c_apps_clk_src.clkr.hw,
807 .flags = CLK_SET_RATE_PARENT,
808 .ops = &clk_branch2_ops,
813 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
815 .halt_check = BRANCH_HALT,
817 .enable_reg = 0x22004,
818 .enable_mask = BIT(0),
819 .hw.init = &(struct clk_init_data){
820 .name = "gcc_blsp1_qup4_spi_apps_clk",
821 .parent_data = &(const struct clk_parent_data){
822 .hw = &gcc_blsp1_qup4_spi_apps_clk_src.clkr.hw,
825 .flags = CLK_SET_RATE_PARENT,
826 .ops = &clk_branch2_ops,
831 static struct clk_branch gcc_blsp1_sleep_clk = {
833 .halt_check = BRANCH_HALT_VOTED,
835 .enable_reg = 0x6d008,
836 .enable_mask = BIT(15),
837 .hw.init = &(struct clk_init_data){
838 .name = "gcc_blsp1_sleep_clk",
839 .ops = &clk_branch2_ops,
844 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
846 .halt_check = BRANCH_HALT,
848 .enable_reg = 0x1d004,
849 .enable_mask = BIT(0),
850 .hw.init = &(struct clk_init_data){
851 .name = "gcc_blsp1_uart1_apps_clk",
852 .parent_data = &(const struct clk_parent_data){
853 .hw = &gcc_blsp1_uart1_apps_clk_src.clkr.hw,
856 .flags = CLK_SET_RATE_PARENT,
857 .ops = &clk_branch2_ops,
862 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
864 .halt_check = BRANCH_HALT,
866 .enable_reg = 0x1f004,
867 .enable_mask = BIT(0),
868 .hw.init = &(struct clk_init_data){
869 .name = "gcc_blsp1_uart2_apps_clk",
870 .parent_data = &(const struct clk_parent_data){
871 .hw = &gcc_blsp1_uart2_apps_clk_src.clkr.hw,
874 .flags = CLK_SET_RATE_PARENT,
875 .ops = &clk_branch2_ops,
880 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
882 .halt_check = BRANCH_HALT,
884 .enable_reg = 0x21004,
885 .enable_mask = BIT(0),
886 .hw.init = &(struct clk_init_data){
887 .name = "gcc_blsp1_uart3_apps_clk",
888 .parent_data = &(const struct clk_parent_data){
889 .hw = &gcc_blsp1_uart3_apps_clk_src.clkr.hw,
892 .flags = CLK_SET_RATE_PARENT,
893 .ops = &clk_branch2_ops,
898 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
900 .halt_check = BRANCH_HALT,
902 .enable_reg = 0x23004,
903 .enable_mask = BIT(0),
904 .hw.init = &(struct clk_init_data){
905 .name = "gcc_blsp1_uart4_apps_clk",
906 .parent_data = &(const struct clk_parent_data){
907 .hw = &gcc_blsp1_uart4_apps_clk_src.clkr.hw,
910 .flags = CLK_SET_RATE_PARENT,
911 .ops = &clk_branch2_ops,
916 static struct clk_branch gcc_boot_rom_ahb_clk = {
918 .halt_check = BRANCH_HALT_VOTED,
922 .enable_reg = 0x6d008,
923 .enable_mask = BIT(10),
924 .hw.init = &(struct clk_init_data){
925 .name = "gcc_boot_rom_ahb_clk",
926 .ops = &clk_branch2_ops,
931 static struct clk_branch gcc_gp1_clk = {
933 .halt_check = BRANCH_HALT,
935 .enable_reg = 0x37000,
936 .enable_mask = BIT(0),
937 .hw.init = &(struct clk_init_data){
938 .name = "gcc_gp1_clk",
939 .parent_data = &(const struct clk_parent_data){
940 .hw = &gcc_gp1_clk_src.clkr.hw,
943 .flags = CLK_SET_RATE_PARENT,
944 .ops = &clk_branch2_ops,
949 static struct clk_branch gcc_gp2_clk = {
951 .halt_check = BRANCH_HALT,
953 .enable_reg = 0x38000,
954 .enable_mask = BIT(0),
955 .hw.init = &(struct clk_init_data){
956 .name = "gcc_gp2_clk",
957 .parent_data = &(const struct clk_parent_data){
958 .hw = &gcc_gp2_clk_src.clkr.hw,
961 .flags = CLK_SET_RATE_PARENT,
962 .ops = &clk_branch2_ops,
967 static struct clk_branch gcc_gp3_clk = {
969 .halt_check = BRANCH_HALT,
971 .enable_reg = 0x39000,
972 .enable_mask = BIT(0),
973 .hw.init = &(struct clk_init_data){
974 .name = "gcc_gp3_clk",
975 .parent_data = &(const struct clk_parent_data){
976 .hw = &gcc_gp3_clk_src.clkr.hw,
979 .flags = CLK_SET_RATE_PARENT,
980 .ops = &clk_branch2_ops,
985 static struct clk_branch gcc_pcie_0_clkref_en = {
988 * The clock controller does not handle the status bit for
989 * the clocks with gdscs(powerdomains) in hw controlled mode
990 * and hence avoid checking for the status bit of those clocks
991 * by setting the BRANCH_HALT_DELAY flag
993 .halt_check = BRANCH_HALT_DELAY,
995 .enable_reg = 0x88004,
996 .enable_mask = BIT(0),
997 .hw.init = &(struct clk_init_data){
998 .name = "gcc_pcie_0_clkref_en",
999 .ops = &clk_branch2_ops,
1004 static struct clk_branch gcc_pcie_aux_clk = {
1005 .halt_reg = 0x43034,
1007 * The clock controller does not handle the status bit for
1008 * the clocks with gdscs(powerdomains) in hw controlled mode
1009 * and hence avoid checking for the status bit of those clocks
1010 * by setting the BRANCH_HALT_DELAY flag
1012 .halt_check = BRANCH_HALT_DELAY,
1013 .hwcg_reg = 0x43034,
1016 .enable_reg = 0x6d010,
1017 .enable_mask = BIT(3),
1018 .hw.init = &(struct clk_init_data){
1019 .name = "gcc_pcie_aux_clk",
1020 .parent_data = &(const struct clk_parent_data){
1021 .hw = &gcc_pcie_aux_clk_src.clkr.hw,
1024 .flags = CLK_SET_RATE_PARENT,
1025 .ops = &clk_branch2_ops,
1030 static struct clk_branch gcc_pcie_cfg_ahb_clk = {
1031 .halt_reg = 0x4302c,
1032 .halt_check = BRANCH_HALT_VOTED,
1033 .hwcg_reg = 0x4302c,
1036 .enable_reg = 0x6d010,
1037 .enable_mask = BIT(2),
1038 .hw.init = &(struct clk_init_data){
1039 .name = "gcc_pcie_cfg_ahb_clk",
1040 .ops = &clk_branch2_ops,
1045 static struct clk_branch gcc_pcie_mstr_axi_clk = {
1046 .halt_reg = 0x43024,
1047 .halt_check = BRANCH_HALT_VOTED,
1048 .hwcg_reg = 0x43024,
1051 .enable_reg = 0x6d010,
1052 .enable_mask = BIT(1),
1053 .hw.init = &(struct clk_init_data){
1054 .name = "gcc_pcie_mstr_axi_clk",
1055 .ops = &clk_branch2_ops,
1060 static struct clk_branch gcc_pcie_pipe_clk = {
1061 .halt_reg = 0x4303c,
1063 * The clock controller does not handle the status bit for
1064 * the clocks with gdscs(powerdomains) in hw controlled mode
1065 * and hence avoid checking for the status bit of those clocks
1066 * by setting the BRANCH_HALT_DELAY flag
1068 .halt_check = BRANCH_HALT_DELAY,
1069 .hwcg_reg = 0x4303c,
1072 .enable_reg = 0x6d010,
1073 .enable_mask = BIT(4),
1074 .hw.init = &(struct clk_init_data){
1075 .name = "gcc_pcie_pipe_clk",
1076 .parent_data = &(const struct clk_parent_data){
1077 .hw = &gcc_pcie_pipe_clk_src.clkr.hw,
1080 .flags = CLK_SET_RATE_PARENT,
1081 .ops = &clk_branch2_ops,
1086 static struct clk_branch gcc_pcie_rchng_phy_clk = {
1087 .halt_reg = 0x43030,
1088 .halt_check = BRANCH_HALT_VOTED,
1089 .hwcg_reg = 0x43030,
1092 .enable_reg = 0x6d010,
1093 .enable_mask = BIT(7),
1094 .hw.init = &(struct clk_init_data){
1095 .name = "gcc_pcie_rchng_phy_clk",
1096 .parent_data = &(const struct clk_parent_data){
1097 .hw = &gcc_pcie_rchng_phy_clk_src.clkr.hw,
1100 .flags = CLK_SET_RATE_PARENT,
1101 .ops = &clk_branch2_ops,
1106 static struct clk_branch gcc_pcie_sleep_clk = {
1107 .halt_reg = 0x43038,
1108 .halt_check = BRANCH_HALT_VOTED,
1109 .hwcg_reg = 0x43038,
1112 .enable_reg = 0x6d010,
1113 .enable_mask = BIT(6),
1114 .hw.init = &(struct clk_init_data){
1115 .name = "gcc_pcie_sleep_clk",
1116 .parent_data = &(const struct clk_parent_data){
1117 .hw = &gcc_pcie_aux_phy_clk_src.clkr.hw,
1120 .flags = CLK_SET_RATE_PARENT,
1121 .ops = &clk_branch2_ops,
1126 static struct clk_branch gcc_pcie_slv_axi_clk = {
1127 .halt_reg = 0x4301c,
1128 .halt_check = BRANCH_HALT_VOTED,
1129 .hwcg_reg = 0x4301c,
1132 .enable_reg = 0x6d010,
1133 .enable_mask = BIT(0),
1134 .hw.init = &(struct clk_init_data){
1135 .name = "gcc_pcie_slv_axi_clk",
1136 .ops = &clk_branch2_ops,
1141 static struct clk_branch gcc_pcie_slv_q2a_axi_clk = {
1142 .halt_reg = 0x43018,
1143 .halt_check = BRANCH_HALT_VOTED,
1144 .hwcg_reg = 0x43018,
1147 .enable_reg = 0x6d010,
1148 .enable_mask = BIT(5),
1149 .hw.init = &(struct clk_init_data){
1150 .name = "gcc_pcie_slv_q2a_axi_clk",
1151 .ops = &clk_branch2_ops,
1156 static struct clk_branch gcc_pdm2_clk = {
1157 .halt_reg = 0x2400c,
1158 .halt_check = BRANCH_HALT,
1160 .enable_reg = 0x2400c,
1161 .enable_mask = BIT(0),
1162 .hw.init = &(struct clk_init_data){
1163 .name = "gcc_pdm2_clk",
1164 .parent_data = &(const struct clk_parent_data){
1165 .hw = &gcc_pdm2_clk_src.clkr.hw,
1168 .flags = CLK_SET_RATE_PARENT,
1169 .ops = &clk_branch2_ops,
1174 static struct clk_branch gcc_pdm_ahb_clk = {
1175 .halt_reg = 0x24004,
1176 .halt_check = BRANCH_HALT,
1177 .hwcg_reg = 0x24004,
1180 .enable_reg = 0x24004,
1181 .enable_mask = BIT(0),
1182 .hw.init = &(struct clk_init_data){
1183 .name = "gcc_pdm_ahb_clk",
1184 .ops = &clk_branch2_ops,
1189 static struct clk_branch gcc_pdm_xo4_clk = {
1190 .halt_reg = 0x24008,
1191 .halt_check = BRANCH_HALT,
1193 .enable_reg = 0x24008,
1194 .enable_mask = BIT(0),
1195 .hw.init = &(struct clk_init_data){
1196 .name = "gcc_pdm_xo4_clk",
1197 .ops = &clk_branch2_ops,
1202 static struct clk_branch gcc_rx1_usb2_clkref_en = {
1203 .halt_reg = 0x88008,
1204 .halt_check = BRANCH_HALT,
1206 .enable_reg = 0x88008,
1207 .enable_mask = BIT(0),
1208 .hw.init = &(struct clk_init_data){
1209 .name = "gcc_rx1_usb2_clkref_en",
1210 .ops = &clk_branch2_ops,
1215 static struct clk_branch gcc_sdcc1_ahb_clk = {
1216 .halt_reg = 0x1a00c,
1217 .halt_check = BRANCH_HALT,
1219 .enable_reg = 0x1a00c,
1220 .enable_mask = BIT(0),
1221 .hw.init = &(struct clk_init_data){
1222 .name = "gcc_sdcc1_ahb_clk",
1223 .ops = &clk_branch2_ops,
1228 static struct clk_branch gcc_sdcc1_apps_clk = {
1229 .halt_reg = 0x1a004,
1230 .halt_check = BRANCH_HALT,
1232 .enable_reg = 0x1a004,
1233 .enable_mask = BIT(0),
1234 .hw.init = &(struct clk_init_data){
1235 .name = "gcc_sdcc1_apps_clk",
1236 .parent_data = &(const struct clk_parent_data){
1237 .hw = &gcc_sdcc1_apps_clk_src.clkr.hw,
1240 .flags = CLK_SET_RATE_PARENT,
1241 .ops = &clk_branch2_ops,
1246 static struct clk_branch gcc_usb30_master_clk = {
1247 .halt_reg = 0x17018,
1248 .halt_check = BRANCH_HALT,
1250 .enable_reg = 0x17018,
1251 .enable_mask = BIT(0),
1252 .hw.init = &(struct clk_init_data){
1253 .name = "gcc_usb30_master_clk",
1254 .parent_data = &(const struct clk_parent_data){
1255 .hw = &gcc_usb30_master_clk_src.clkr.hw,
1258 .flags = CLK_SET_RATE_PARENT,
1259 .ops = &clk_branch2_ops,
1264 static struct clk_branch gcc_usb30_mock_utmi_clk = {
1265 .halt_reg = 0x1702c,
1266 .halt_check = BRANCH_HALT,
1268 .enable_reg = 0x1702c,
1269 .enable_mask = BIT(0),
1270 .hw.init = &(struct clk_init_data){
1271 .name = "gcc_usb30_mock_utmi_clk",
1272 .parent_data = &(const struct clk_parent_data){
1274 &gcc_usb30_mock_utmi_postdiv_clk_src.clkr.hw,
1277 .flags = CLK_SET_RATE_PARENT,
1278 .ops = &clk_branch2_ops,
1283 static struct clk_branch gcc_usb30_mstr_axi_clk = {
1284 .halt_reg = 0x17020,
1285 .halt_check = BRANCH_HALT,
1287 .enable_reg = 0x17020,
1288 .enable_mask = BIT(0),
1289 .hw.init = &(struct clk_init_data){
1290 .name = "gcc_usb30_mstr_axi_clk",
1291 .ops = &clk_branch2_ops,
1296 static struct clk_branch gcc_usb30_sleep_clk = {
1297 .halt_reg = 0x17028,
1298 .halt_check = BRANCH_HALT,
1300 .enable_reg = 0x17028,
1301 .enable_mask = BIT(0),
1302 .hw.init = &(struct clk_init_data){
1303 .name = "gcc_usb30_sleep_clk",
1304 .ops = &clk_branch2_ops,
1309 static struct clk_branch gcc_usb30_slv_ahb_clk = {
1310 .halt_reg = 0x17024,
1311 .halt_check = BRANCH_HALT,
1313 .enable_reg = 0x17024,
1314 .enable_mask = BIT(0),
1315 .hw.init = &(struct clk_init_data){
1316 .name = "gcc_usb30_slv_ahb_clk",
1317 .ops = &clk_branch2_ops,
1322 static struct clk_branch gcc_usb3_phy_aux_clk = {
1323 .halt_reg = 0x17064,
1324 .halt_check = BRANCH_HALT,
1326 .enable_reg = 0x17064,
1327 .enable_mask = BIT(0),
1328 .hw.init = &(struct clk_init_data){
1329 .name = "gcc_usb3_phy_aux_clk",
1330 .parent_data = &(const struct clk_parent_data){
1331 .hw = &gcc_usb3_phy_aux_clk_src.clkr.hw,
1334 .flags = CLK_SET_RATE_PARENT,
1335 .ops = &clk_branch2_ops,
1340 static struct gdsc usb30_gdsc = {
1343 .name = "usb30_gdsc",
1345 .pwrsts = PWRSTS_OFF_ON,
1348 static struct gdsc pcie_gdsc = {
1351 .name = "pcie_gdsc",
1353 .pwrsts = PWRSTS_OFF_ON,
1356 static struct clk_branch gcc_usb3_phy_pipe_clk = {
1357 .halt_reg = 0x17068,
1359 * The clock controller does not handle the status bit for
1360 * the clocks with gdscs(powerdomains) in hw controlled mode
1361 * and hence avoid checking for the status bit of those clocks
1362 * by setting the BRANCH_HALT_DELAY flag
1364 .halt_check = BRANCH_HALT_DELAY,
1365 .hwcg_reg = 0x17068,
1368 .enable_reg = 0x17068,
1369 .enable_mask = BIT(0),
1370 .hw.init = &(struct clk_init_data){
1371 .name = "gcc_usb3_phy_pipe_clk",
1372 .parent_data = &(const struct clk_parent_data){
1373 .hw = &gcc_usb3_phy_pipe_clk_src.clkr.hw,
1376 .flags = CLK_SET_RATE_PARENT,
1377 .ops = &clk_branch2_ops,
1382 static struct clk_branch gcc_usb3_prim_clkref_en = {
1383 .halt_reg = 0x88000,
1384 .halt_check = BRANCH_HALT,
1386 .enable_reg = 0x88000,
1387 .enable_mask = BIT(0),
1388 .hw.init = &(struct clk_init_data){
1389 .name = "gcc_usb3_prim_clkref_en",
1390 .ops = &clk_branch2_ops,
1395 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
1396 .halt_reg = 0x19008,
1397 .halt_check = BRANCH_HALT,
1398 .hwcg_reg = 0x19008,
1401 .enable_reg = 0x19008,
1402 .enable_mask = BIT(0),
1403 .hw.init = &(struct clk_init_data){
1404 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
1405 .ops = &clk_branch2_ops,
1410 static struct clk_branch gcc_xo_div4_clk = {
1411 .halt_reg = 0x2e010,
1412 .halt_check = BRANCH_HALT,
1414 .enable_reg = 0x2e010,
1415 .enable_mask = BIT(0),
1416 .hw.init = &(struct clk_init_data){
1417 .name = "gcc_xo_div4_clk",
1418 .ops = &clk_branch2_ops,
1423 static struct clk_branch gcc_xo_pcie_link_clk = {
1424 .halt_reg = 0x2e008,
1425 .halt_check = BRANCH_HALT,
1426 .hwcg_reg = 0x2e008,
1429 .enable_reg = 0x2e008,
1430 .enable_mask = BIT(0),
1431 .hw.init = &(struct clk_init_data){
1432 .name = "gcc_xo_pcie_link_clk",
1433 .ops = &clk_branch2_ops,
1438 static struct clk_regmap *gcc_sdx65_clocks[] = {
1439 [GCC_AHB_PCIE_LINK_CLK] = &gcc_ahb_pcie_link_clk.clkr,
1440 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
1441 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
1442 [GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC] = &gcc_blsp1_qup1_i2c_apps_clk_src.clkr,
1443 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
1444 [GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup1_spi_apps_clk_src.clkr,
1445 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
1446 [GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC] = &gcc_blsp1_qup2_i2c_apps_clk_src.clkr,
1447 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
1448 [GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup2_spi_apps_clk_src.clkr,
1449 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
1450 [GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC] = &gcc_blsp1_qup3_i2c_apps_clk_src.clkr,
1451 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
1452 [GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup3_spi_apps_clk_src.clkr,
1453 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
1454 [GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC] = &gcc_blsp1_qup4_i2c_apps_clk_src.clkr,
1455 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
1456 [GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup4_spi_apps_clk_src.clkr,
1457 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
1458 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
1459 [GCC_BLSP1_UART1_APPS_CLK_SRC] = &gcc_blsp1_uart1_apps_clk_src.clkr,
1460 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
1461 [GCC_BLSP1_UART2_APPS_CLK_SRC] = &gcc_blsp1_uart2_apps_clk_src.clkr,
1462 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
1463 [GCC_BLSP1_UART3_APPS_CLK_SRC] = &gcc_blsp1_uart3_apps_clk_src.clkr,
1464 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
1465 [GCC_BLSP1_UART4_APPS_CLK_SRC] = &gcc_blsp1_uart4_apps_clk_src.clkr,
1466 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
1467 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
1468 [GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr,
1469 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
1470 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
1471 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
1472 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
1473 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
1474 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
1475 [GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,
1476 [GCC_PCIE_AUX_CLK] = &gcc_pcie_aux_clk.clkr,
1477 [GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr,
1478 [GCC_PCIE_AUX_PHY_CLK_SRC] = &gcc_pcie_aux_phy_clk_src.clkr,
1479 [GCC_PCIE_CFG_AHB_CLK] = &gcc_pcie_cfg_ahb_clk.clkr,
1480 [GCC_PCIE_MSTR_AXI_CLK] = &gcc_pcie_mstr_axi_clk.clkr,
1481 [GCC_PCIE_PIPE_CLK] = &gcc_pcie_pipe_clk.clkr,
1482 [GCC_PCIE_PIPE_CLK_SRC] = &gcc_pcie_pipe_clk_src.clkr,
1483 [GCC_PCIE_RCHNG_PHY_CLK] = &gcc_pcie_rchng_phy_clk.clkr,
1484 [GCC_PCIE_RCHNG_PHY_CLK_SRC] = &gcc_pcie_rchng_phy_clk_src.clkr,
1485 [GCC_PCIE_SLEEP_CLK] = &gcc_pcie_sleep_clk.clkr,
1486 [GCC_PCIE_SLV_AXI_CLK] = &gcc_pcie_slv_axi_clk.clkr,
1487 [GCC_PCIE_SLV_Q2A_AXI_CLK] = &gcc_pcie_slv_q2a_axi_clk.clkr,
1488 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
1489 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
1490 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
1491 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
1492 [GCC_RX1_USB2_CLKREF_EN] = &gcc_rx1_usb2_clkref_en.clkr,
1493 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
1494 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
1495 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
1496 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
1497 [GCC_USB30_MASTER_CLK_SRC] = &gcc_usb30_master_clk_src.clkr,
1498 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
1499 [GCC_USB30_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mock_utmi_clk_src.clkr,
1500 [GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mock_utmi_postdiv_clk_src.clkr,
1501 [GCC_USB30_MSTR_AXI_CLK] = &gcc_usb30_mstr_axi_clk.clkr,
1502 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
1503 [GCC_USB30_SLV_AHB_CLK] = &gcc_usb30_slv_ahb_clk.clkr,
1504 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
1505 [GCC_USB3_PHY_AUX_CLK_SRC] = &gcc_usb3_phy_aux_clk_src.clkr,
1506 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
1507 [GCC_USB3_PHY_PIPE_CLK_SRC] = &gcc_usb3_phy_pipe_clk_src.clkr,
1508 [GCC_USB3_PRIM_CLKREF_EN] = &gcc_usb3_prim_clkref_en.clkr,
1509 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
1510 [GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
1511 [GCC_XO_PCIE_LINK_CLK] = &gcc_xo_pcie_link_clk.clkr,
1512 [GPLL0] = &gpll0.clkr,
1513 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
1516 static const struct qcom_reset_map gcc_sdx65_resets[] = {
1517 [GCC_BLSP1_QUP1_BCR] = { 0x1c000 },
1518 [GCC_BLSP1_QUP2_BCR] = { 0x1e000 },
1519 [GCC_BLSP1_QUP3_BCR] = { 0x20000 },
1520 [GCC_BLSP1_QUP4_BCR] = { 0x22000 },
1521 [GCC_BLSP1_UART1_BCR] = { 0x1d000 },
1522 [GCC_BLSP1_UART2_BCR] = { 0x1f000 },
1523 [GCC_BLSP1_UART3_BCR] = { 0x21000 },
1524 [GCC_BLSP1_UART4_BCR] = { 0x23000 },
1525 [GCC_PCIE_BCR] = { 0x43000 },
1526 [GCC_PCIE_LINK_DOWN_BCR] = { 0x77000 },
1527 [GCC_PCIE_NOCSR_COM_PHY_BCR] = { 0x78008 },
1528 [GCC_PCIE_PHY_BCR] = { 0x44000 },
1529 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x78000 },
1530 [GCC_PCIE_PHY_COM_BCR] = { 0x78004 },
1531 [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x7800c },
1532 [GCC_PDM_BCR] = { 0x24000 },
1533 [GCC_QUSB2PHY_BCR] = { 0x19000 },
1534 [GCC_SDCC1_BCR] = { 0x1a000 },
1535 [GCC_TCSR_PCIE_BCR] = { 0x57000 },
1536 [GCC_USB30_BCR] = { 0x17000 },
1537 [GCC_USB3_PHY_BCR] = { 0x18000 },
1538 [GCC_USB3PHY_PHY_BCR] = { 0x18004 },
1539 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x19004 },
1542 static struct gdsc *gcc_sdx65_gdscs[] = {
1543 [USB30_GDSC] = &usb30_gdsc,
1544 [PCIE_GDSC] = &pcie_gdsc,
1547 static const struct regmap_config gcc_sdx65_regmap_config = {
1551 .max_register = 0x1f101c,
1555 static const struct qcom_cc_desc gcc_sdx65_desc = {
1556 .config = &gcc_sdx65_regmap_config,
1557 .clks = gcc_sdx65_clocks,
1558 .num_clks = ARRAY_SIZE(gcc_sdx65_clocks),
1559 .resets = gcc_sdx65_resets,
1560 .num_resets = ARRAY_SIZE(gcc_sdx65_resets),
1561 .gdscs = gcc_sdx65_gdscs,
1562 .num_gdscs = ARRAY_SIZE(gcc_sdx65_gdscs),
1565 static const struct of_device_id gcc_sdx65_match_table[] = {
1566 { .compatible = "qcom,gcc-sdx65" },
1569 MODULE_DEVICE_TABLE(of, gcc_sdx65_match_table);
1571 static int gcc_sdx65_probe(struct platform_device *pdev)
1573 struct regmap *regmap;
1575 regmap = qcom_cc_map(pdev, &gcc_sdx65_desc);
1577 return PTR_ERR(regmap);
1579 * Keep the clocks always-ON as they are critical to the functioning
1581 * GCC_SYS_NOC_CPUSS_AHB_CLK, GCC_CPUSS_AHB_CLK, GCC_CPUSS_GNOC_CLK
1583 regmap_update_bits(regmap, 0x6d008, BIT(0), BIT(0));
1584 regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21));
1585 regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22));
1587 return qcom_cc_really_probe(pdev, &gcc_sdx65_desc, regmap);
1590 static struct platform_driver gcc_sdx65_driver = {
1591 .probe = gcc_sdx65_probe,
1593 .name = "gcc-sdx65",
1594 .of_match_table = gcc_sdx65_match_table,
1598 static int __init gcc_sdx65_init(void)
1600 return platform_driver_register(&gcc_sdx65_driver);
1602 subsys_initcall(gcc_sdx65_init);
1604 static void __exit gcc_sdx65_exit(void)
1606 platform_driver_unregister(&gcc_sdx65_driver);
1608 module_exit(gcc_sdx65_exit);
1610 MODULE_DESCRIPTION("QTI GCC SDX65 Driver");
1611 MODULE_LICENSE("GPL v2");