1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
20 #include "clk-regmap.h"
23 #include "clk-branch.h"
24 #include "clk-alpha-pll.h"
31 P_CORE_BI_PLL_TEST_SE,
38 static const struct parent_map gcc_parent_map_0[] = {
40 { P_GPLL0_OUT_MAIN, 1 },
41 { P_GPLL0_OUT_EVEN, 6 },
42 { P_CORE_BI_PLL_TEST_SE, 7 },
45 static const char * const gcc_parent_names_0[] = {
49 "core_bi_pll_test_se",
52 static const struct parent_map gcc_parent_map_1[] = {
54 { P_GPLL0_OUT_MAIN, 1 },
56 { P_GPLL0_OUT_EVEN, 6 },
57 { P_CORE_BI_PLL_TEST_SE, 7 },
60 static const char * const gcc_parent_names_1[] = {
65 "core_bi_pll_test_se",
68 static const struct parent_map gcc_parent_map_2[] = {
71 { P_CORE_BI_PLL_TEST_SE, 7 },
74 static const char * const gcc_parent_names_2[] = {
77 "core_bi_pll_test_se",
80 static const struct parent_map gcc_parent_map_3[] = {
82 { P_GPLL0_OUT_MAIN, 1 },
83 { P_CORE_BI_PLL_TEST_SE, 7 },
86 static const char * const gcc_parent_names_3[] = {
89 "core_bi_pll_test_se",
92 static const struct parent_map gcc_parent_map_4[] = {
94 { P_CORE_BI_PLL_TEST_SE, 7 },
97 static const char * const gcc_parent_names_4[] = {
99 "core_bi_pll_test_se",
102 static const struct parent_map gcc_parent_map_6[] = {
104 { P_GPLL0_OUT_MAIN, 1 },
105 { P_AUD_REF_CLK, 2 },
106 { P_GPLL0_OUT_EVEN, 6 },
107 { P_CORE_BI_PLL_TEST_SE, 7 },
110 static const char * const gcc_parent_names_6[] = {
115 "core_bi_pll_test_se",
118 static const char * const gcc_parent_names_7[] = {
122 "core_bi_pll_test_se",
125 static const char * const gcc_parent_names_8[] = {
128 "core_bi_pll_test_se",
131 static const struct parent_map gcc_parent_map_10[] = {
133 { P_GPLL0_OUT_MAIN, 1 },
134 { P_GPLL4_OUT_MAIN, 5 },
135 { P_GPLL0_OUT_EVEN, 6 },
136 { P_CORE_BI_PLL_TEST_SE, 7 },
139 static const char * const gcc_parent_names_10[] = {
144 "core_bi_pll_test_se",
147 static struct clk_alpha_pll gpll0 = {
149 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
151 .enable_reg = 0x52000,
152 .enable_mask = BIT(0),
153 .hw.init = &(struct clk_init_data){
155 .parent_names = (const char *[]){ "bi_tcxo" },
157 .ops = &clk_alpha_pll_fixed_fabia_ops,
162 static struct clk_alpha_pll gpll4 = {
164 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
166 .enable_reg = 0x52000,
167 .enable_mask = BIT(4),
168 .hw.init = &(struct clk_init_data){
170 .parent_names = (const char *[]){ "bi_tcxo" },
172 .ops = &clk_alpha_pll_fixed_fabia_ops,
177 static const struct clk_div_table post_div_table_fabia_even[] = {
185 static struct clk_alpha_pll_postdiv gpll0_out_even = {
188 .post_div_table = post_div_table_fabia_even,
189 .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
191 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
192 .clkr.hw.init = &(struct clk_init_data){
193 .name = "gpll0_out_even",
194 .parent_names = (const char *[]){ "gpll0" },
196 .ops = &clk_alpha_pll_postdiv_fabia_ops,
200 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
201 F(19200000, P_BI_TCXO, 1, 0, 0),
205 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
209 .parent_map = gcc_parent_map_0,
210 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
211 .clkr.hw.init = &(struct clk_init_data){
212 .name = "gcc_cpuss_ahb_clk_src",
213 .parent_names = gcc_parent_names_7,
215 .ops = &clk_rcg2_ops,
219 static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = {
220 F(19200000, P_BI_TCXO, 1, 0, 0),
224 static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = {
228 .parent_map = gcc_parent_map_3,
229 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
230 .clkr.hw.init = &(struct clk_init_data){
231 .name = "gcc_cpuss_rbcpr_clk_src",
232 .parent_names = gcc_parent_names_8,
234 .ops = &clk_rcg2_ops,
238 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
239 F(19200000, P_BI_TCXO, 1, 0, 0),
240 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
241 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
242 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
243 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
247 static struct clk_rcg2 gcc_gp1_clk_src = {
251 .parent_map = gcc_parent_map_1,
252 .freq_tbl = ftbl_gcc_gp1_clk_src,
253 .clkr.hw.init = &(struct clk_init_data){
254 .name = "gcc_gp1_clk_src",
255 .parent_names = gcc_parent_names_1,
257 .ops = &clk_rcg2_ops,
261 static struct clk_rcg2 gcc_gp2_clk_src = {
265 .parent_map = gcc_parent_map_1,
266 .freq_tbl = ftbl_gcc_gp1_clk_src,
267 .clkr.hw.init = &(struct clk_init_data){
268 .name = "gcc_gp2_clk_src",
269 .parent_names = gcc_parent_names_1,
271 .ops = &clk_rcg2_ops,
275 static struct clk_rcg2 gcc_gp3_clk_src = {
279 .parent_map = gcc_parent_map_1,
280 .freq_tbl = ftbl_gcc_gp1_clk_src,
281 .clkr.hw.init = &(struct clk_init_data){
282 .name = "gcc_gp3_clk_src",
283 .parent_names = gcc_parent_names_1,
285 .ops = &clk_rcg2_ops,
289 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
290 F(9600000, P_BI_TCXO, 2, 0, 0),
291 F(19200000, P_BI_TCXO, 1, 0, 0),
295 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
299 .parent_map = gcc_parent_map_2,
300 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
301 .clkr.hw.init = &(struct clk_init_data){
302 .name = "gcc_pcie_0_aux_clk_src",
303 .parent_names = gcc_parent_names_2,
305 .ops = &clk_rcg2_ops,
309 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
313 .parent_map = gcc_parent_map_2,
314 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
315 .clkr.hw.init = &(struct clk_init_data){
316 .name = "gcc_pcie_1_aux_clk_src",
317 .parent_names = gcc_parent_names_2,
319 .ops = &clk_rcg2_ops,
323 static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
324 F(19200000, P_BI_TCXO, 1, 0, 0),
325 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
329 static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
333 .parent_map = gcc_parent_map_0,
334 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
335 .clkr.hw.init = &(struct clk_init_data){
336 .name = "gcc_pcie_phy_refgen_clk_src",
337 .parent_names = gcc_parent_names_0,
339 .ops = &clk_rcg2_ops,
343 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
344 F(19200000, P_BI_TCXO, 1, 0, 0),
345 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
346 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
347 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
351 static struct clk_rcg2 gcc_qspi_core_clk_src = {
355 .parent_map = gcc_parent_map_0,
356 .freq_tbl = ftbl_gcc_qspi_core_clk_src,
357 .clkr.hw.init = &(struct clk_init_data){
358 .name = "gcc_qspi_core_clk_src",
359 .parent_names = gcc_parent_names_0,
361 .ops = &clk_rcg2_floor_ops,
365 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
366 F(9600000, P_BI_TCXO, 2, 0, 0),
367 F(19200000, P_BI_TCXO, 1, 0, 0),
368 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
372 static struct clk_rcg2 gcc_pdm2_clk_src = {
376 .parent_map = gcc_parent_map_0,
377 .freq_tbl = ftbl_gcc_pdm2_clk_src,
378 .clkr.hw.init = &(struct clk_init_data){
379 .name = "gcc_pdm2_clk_src",
380 .parent_names = gcc_parent_names_0,
382 .ops = &clk_rcg2_ops,
386 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
387 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
388 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
389 F(19200000, P_BI_TCXO, 1, 0, 0),
390 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
391 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
392 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
393 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
394 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
395 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
396 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
397 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
398 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
399 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
400 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
401 F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
405 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_init = {
406 .name = "gcc_qupv3_wrap0_s0_clk_src",
407 .parent_names = gcc_parent_names_0,
409 .ops = &clk_rcg2_shared_ops,
412 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
416 .parent_map = gcc_parent_map_0,
417 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
418 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_init,
421 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_init = {
422 .name = "gcc_qupv3_wrap0_s1_clk_src",
423 .parent_names = gcc_parent_names_0,
425 .ops = &clk_rcg2_shared_ops,
428 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
432 .parent_map = gcc_parent_map_0,
433 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
434 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_init,
437 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_init = {
438 .name = "gcc_qupv3_wrap0_s2_clk_src",
439 .parent_names = gcc_parent_names_0,
441 .ops = &clk_rcg2_shared_ops,
444 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
448 .parent_map = gcc_parent_map_0,
449 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
450 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_init,
453 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_init = {
454 .name = "gcc_qupv3_wrap0_s3_clk_src",
455 .parent_names = gcc_parent_names_0,
457 .ops = &clk_rcg2_shared_ops,
460 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
464 .parent_map = gcc_parent_map_0,
465 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
466 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_init,
469 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_init = {
470 .name = "gcc_qupv3_wrap0_s4_clk_src",
471 .parent_names = gcc_parent_names_0,
473 .ops = &clk_rcg2_shared_ops,
476 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
480 .parent_map = gcc_parent_map_0,
481 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
482 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_init,
485 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_init = {
486 .name = "gcc_qupv3_wrap0_s5_clk_src",
487 .parent_names = gcc_parent_names_0,
489 .ops = &clk_rcg2_shared_ops,
492 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
496 .parent_map = gcc_parent_map_0,
497 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
498 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_init,
501 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_init = {
502 .name = "gcc_qupv3_wrap0_s6_clk_src",
503 .parent_names = gcc_parent_names_0,
505 .ops = &clk_rcg2_shared_ops,
508 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
512 .parent_map = gcc_parent_map_0,
513 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
514 .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_init,
517 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_init = {
518 .name = "gcc_qupv3_wrap0_s7_clk_src",
519 .parent_names = gcc_parent_names_0,
521 .ops = &clk_rcg2_shared_ops,
524 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
528 .parent_map = gcc_parent_map_0,
529 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
530 .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_init,
533 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_init = {
534 .name = "gcc_qupv3_wrap1_s0_clk_src",
535 .parent_names = gcc_parent_names_0,
537 .ops = &clk_rcg2_shared_ops,
540 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
544 .parent_map = gcc_parent_map_0,
545 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
546 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_init,
549 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_init = {
550 .name = "gcc_qupv3_wrap1_s1_clk_src",
551 .parent_names = gcc_parent_names_0,
553 .ops = &clk_rcg2_shared_ops,
556 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
560 .parent_map = gcc_parent_map_0,
561 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
562 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_init,
565 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_init = {
566 .name = "gcc_qupv3_wrap1_s2_clk_src",
567 .parent_names = gcc_parent_names_0,
569 .ops = &clk_rcg2_shared_ops,
572 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
576 .parent_map = gcc_parent_map_0,
577 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
578 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_init,
581 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_init = {
582 .name = "gcc_qupv3_wrap1_s3_clk_src",
583 .parent_names = gcc_parent_names_0,
585 .ops = &clk_rcg2_shared_ops,
588 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
592 .parent_map = gcc_parent_map_0,
593 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
594 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_init,
597 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_init = {
598 .name = "gcc_qupv3_wrap1_s4_clk_src",
599 .parent_names = gcc_parent_names_0,
601 .ops = &clk_rcg2_shared_ops,
604 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
608 .parent_map = gcc_parent_map_0,
609 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
610 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_init,
613 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_init = {
614 .name = "gcc_qupv3_wrap1_s5_clk_src",
615 .parent_names = gcc_parent_names_0,
617 .ops = &clk_rcg2_shared_ops,
620 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
624 .parent_map = gcc_parent_map_0,
625 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
626 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_init,
629 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_init = {
630 .name = "gcc_qupv3_wrap1_s6_clk_src",
631 .parent_names = gcc_parent_names_0,
633 .ops = &clk_rcg2_shared_ops,
636 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
640 .parent_map = gcc_parent_map_0,
641 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
642 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_init,
645 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_init = {
646 .name = "gcc_qupv3_wrap1_s7_clk_src",
647 .parent_names = gcc_parent_names_0,
649 .ops = &clk_rcg2_shared_ops,
652 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
656 .parent_map = gcc_parent_map_0,
657 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
658 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_init,
661 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
662 F(400000, P_BI_TCXO, 12, 1, 4),
663 F(9600000, P_BI_TCXO, 2, 0, 0),
664 F(19200000, P_BI_TCXO, 1, 0, 0),
665 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
666 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
667 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
668 F(201500000, P_GPLL4_OUT_MAIN, 4, 0, 0),
672 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
676 .parent_map = gcc_parent_map_10,
677 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
678 .clkr.hw.init = &(struct clk_init_data){
679 .name = "gcc_sdcc2_apps_clk_src",
680 .parent_names = gcc_parent_names_10,
682 .ops = &clk_rcg2_ops,
686 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
687 F(400000, P_BI_TCXO, 12, 1, 4),
688 F(9600000, P_BI_TCXO, 2, 0, 0),
689 F(19200000, P_BI_TCXO, 1, 0, 0),
690 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
691 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
692 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
696 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
700 .parent_map = gcc_parent_map_0,
701 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
702 .clkr.hw.init = &(struct clk_init_data){
703 .name = "gcc_sdcc4_apps_clk_src",
704 .parent_names = gcc_parent_names_0,
706 .ops = &clk_rcg2_ops,
710 static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
711 F(105495, P_BI_TCXO, 2, 1, 91),
715 static struct clk_rcg2 gcc_tsif_ref_clk_src = {
719 .parent_map = gcc_parent_map_6,
720 .freq_tbl = ftbl_gcc_tsif_ref_clk_src,
721 .clkr.hw.init = &(struct clk_init_data){
722 .name = "gcc_tsif_ref_clk_src",
723 .parent_names = gcc_parent_names_6,
725 .ops = &clk_rcg2_ops,
729 static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
730 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
731 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
732 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
733 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
734 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
738 static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
742 .parent_map = gcc_parent_map_0,
743 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
744 .clkr.hw.init = &(struct clk_init_data){
745 .name = "gcc_ufs_card_axi_clk_src",
746 .parent_names = gcc_parent_names_0,
748 .ops = &clk_rcg2_shared_ops,
752 static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
753 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
754 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
755 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
756 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
760 static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
764 .parent_map = gcc_parent_map_0,
765 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
766 .clkr.hw.init = &(struct clk_init_data){
767 .name = "gcc_ufs_card_ice_core_clk_src",
768 .parent_names = gcc_parent_names_0,
770 .ops = &clk_rcg2_shared_ops,
774 static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
778 .parent_map = gcc_parent_map_4,
779 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
780 .clkr.hw.init = &(struct clk_init_data){
781 .name = "gcc_ufs_card_phy_aux_clk_src",
782 .parent_names = gcc_parent_names_4,
784 .ops = &clk_rcg2_ops,
788 static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
789 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
790 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
791 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
795 static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
799 .parent_map = gcc_parent_map_0,
800 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
801 .clkr.hw.init = &(struct clk_init_data){
802 .name = "gcc_ufs_card_unipro_core_clk_src",
803 .parent_names = gcc_parent_names_0,
805 .ops = &clk_rcg2_shared_ops,
809 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
810 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
811 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
812 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
813 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
814 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
818 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
822 .parent_map = gcc_parent_map_0,
823 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
824 .clkr.hw.init = &(struct clk_init_data){
825 .name = "gcc_ufs_phy_axi_clk_src",
826 .parent_names = gcc_parent_names_0,
828 .ops = &clk_rcg2_shared_ops,
832 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
836 .parent_map = gcc_parent_map_0,
837 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
838 .clkr.hw.init = &(struct clk_init_data){
839 .name = "gcc_ufs_phy_ice_core_clk_src",
840 .parent_names = gcc_parent_names_0,
842 .ops = &clk_rcg2_shared_ops,
846 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
850 .parent_map = gcc_parent_map_4,
851 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
852 .clkr.hw.init = &(struct clk_init_data){
853 .name = "gcc_ufs_phy_phy_aux_clk_src",
854 .parent_names = gcc_parent_names_4,
856 .ops = &clk_rcg2_shared_ops,
860 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
864 .parent_map = gcc_parent_map_0,
865 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
866 .clkr.hw.init = &(struct clk_init_data){
867 .name = "gcc_ufs_phy_unipro_core_clk_src",
868 .parent_names = gcc_parent_names_0,
870 .ops = &clk_rcg2_shared_ops,
874 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
875 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
876 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
877 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
878 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
879 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
883 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
887 .parent_map = gcc_parent_map_0,
888 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
889 .clkr.hw.init = &(struct clk_init_data){
890 .name = "gcc_usb30_prim_master_clk_src",
891 .parent_names = gcc_parent_names_0,
893 .ops = &clk_rcg2_shared_ops,
897 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
898 F(19200000, P_BI_TCXO, 1, 0, 0),
899 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
900 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
901 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
905 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
909 .parent_map = gcc_parent_map_0,
910 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
911 .clkr.hw.init = &(struct clk_init_data){
912 .name = "gcc_usb30_prim_mock_utmi_clk_src",
913 .parent_names = gcc_parent_names_0,
915 .ops = &clk_rcg2_shared_ops,
919 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
923 .parent_map = gcc_parent_map_0,
924 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
925 .clkr.hw.init = &(struct clk_init_data){
926 .name = "gcc_usb30_sec_master_clk_src",
927 .parent_names = gcc_parent_names_0,
929 .ops = &clk_rcg2_ops,
933 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
937 .parent_map = gcc_parent_map_0,
938 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
939 .clkr.hw.init = &(struct clk_init_data){
940 .name = "gcc_usb30_sec_mock_utmi_clk_src",
941 .parent_names = gcc_parent_names_0,
943 .ops = &clk_rcg2_ops,
947 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
951 .parent_map = gcc_parent_map_2,
952 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
953 .clkr.hw.init = &(struct clk_init_data){
954 .name = "gcc_usb3_prim_phy_aux_clk_src",
955 .parent_names = gcc_parent_names_2,
957 .ops = &clk_rcg2_ops,
961 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
965 .parent_map = gcc_parent_map_2,
966 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
967 .clkr.hw.init = &(struct clk_init_data){
968 .name = "gcc_usb3_sec_phy_aux_clk_src",
969 .parent_names = gcc_parent_names_2,
971 .ops = &clk_rcg2_shared_ops,
975 static struct clk_rcg2 gcc_vs_ctrl_clk_src = {
979 .parent_map = gcc_parent_map_3,
980 .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
981 .clkr.hw.init = &(struct clk_init_data){
982 .name = "gcc_vs_ctrl_clk_src",
983 .parent_names = gcc_parent_names_3,
985 .ops = &clk_rcg2_ops,
989 static const struct freq_tbl ftbl_gcc_vsensor_clk_src[] = {
990 F(19200000, P_BI_TCXO, 1, 0, 0),
991 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
992 F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
996 static struct clk_rcg2 gcc_vsensor_clk_src = {
1000 .parent_map = gcc_parent_map_3,
1001 .freq_tbl = ftbl_gcc_vsensor_clk_src,
1002 .clkr.hw.init = &(struct clk_init_data){
1003 .name = "gcc_vsensor_clk_src",
1004 .parent_names = gcc_parent_names_8,
1006 .ops = &clk_rcg2_ops,
1010 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1011 .halt_reg = 0x90014,
1012 .halt_check = BRANCH_HALT,
1014 .enable_reg = 0x90014,
1015 .enable_mask = BIT(0),
1016 .hw.init = &(struct clk_init_data){
1017 .name = "gcc_aggre_noc_pcie_tbu_clk",
1018 .ops = &clk_branch2_ops,
1023 static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1024 .halt_reg = 0x82028,
1025 .halt_check = BRANCH_HALT,
1026 .hwcg_reg = 0x82028,
1029 .enable_reg = 0x82028,
1030 .enable_mask = BIT(0),
1031 .hw.init = &(struct clk_init_data){
1032 .name = "gcc_aggre_ufs_card_axi_clk",
1033 .parent_names = (const char *[]){
1034 "gcc_ufs_card_axi_clk_src",
1037 .flags = CLK_SET_RATE_PARENT,
1038 .ops = &clk_branch2_ops,
1043 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1044 .halt_reg = 0x82024,
1045 .halt_check = BRANCH_HALT,
1046 .hwcg_reg = 0x82024,
1049 .enable_reg = 0x82024,
1050 .enable_mask = BIT(0),
1051 .hw.init = &(struct clk_init_data){
1052 .name = "gcc_aggre_ufs_phy_axi_clk",
1053 .parent_names = (const char *[]){
1054 "gcc_ufs_phy_axi_clk_src",
1057 .flags = CLK_SET_RATE_PARENT,
1058 .ops = &clk_branch2_ops,
1063 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1064 .halt_reg = 0x8201c,
1065 .halt_check = BRANCH_HALT,
1067 .enable_reg = 0x8201c,
1068 .enable_mask = BIT(0),
1069 .hw.init = &(struct clk_init_data){
1070 .name = "gcc_aggre_usb3_prim_axi_clk",
1071 .parent_names = (const char *[]){
1072 "gcc_usb30_prim_master_clk_src",
1075 .flags = CLK_SET_RATE_PARENT,
1076 .ops = &clk_branch2_ops,
1081 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1082 .halt_reg = 0x82020,
1083 .halt_check = BRANCH_HALT,
1085 .enable_reg = 0x82020,
1086 .enable_mask = BIT(0),
1087 .hw.init = &(struct clk_init_data){
1088 .name = "gcc_aggre_usb3_sec_axi_clk",
1089 .parent_names = (const char *[]){
1090 "gcc_usb30_sec_master_clk_src",
1093 .flags = CLK_SET_RATE_PARENT,
1094 .ops = &clk_branch2_ops,
1099 static struct clk_branch gcc_apc_vs_clk = {
1100 .halt_reg = 0x7a050,
1101 .halt_check = BRANCH_HALT,
1103 .enable_reg = 0x7a050,
1104 .enable_mask = BIT(0),
1105 .hw.init = &(struct clk_init_data){
1106 .name = "gcc_apc_vs_clk",
1107 .parent_names = (const char *[]){
1108 "gcc_vsensor_clk_src",
1111 .flags = CLK_SET_RATE_PARENT,
1112 .ops = &clk_branch2_ops,
1117 static struct clk_branch gcc_boot_rom_ahb_clk = {
1118 .halt_reg = 0x38004,
1119 .halt_check = BRANCH_HALT_VOTED,
1120 .hwcg_reg = 0x38004,
1123 .enable_reg = 0x52004,
1124 .enable_mask = BIT(10),
1125 .hw.init = &(struct clk_init_data){
1126 .name = "gcc_boot_rom_ahb_clk",
1127 .ops = &clk_branch2_ops,
1132 static struct clk_branch gcc_camera_ahb_clk = {
1134 .halt_check = BRANCH_HALT,
1138 .enable_reg = 0xb008,
1139 .enable_mask = BIT(0),
1140 .hw.init = &(struct clk_init_data){
1141 .name = "gcc_camera_ahb_clk",
1142 .flags = CLK_IS_CRITICAL,
1143 .ops = &clk_branch2_ops,
1148 static struct clk_branch gcc_camera_axi_clk = {
1150 .halt_check = BRANCH_VOTED,
1152 .enable_reg = 0xb020,
1153 .enable_mask = BIT(0),
1154 .hw.init = &(struct clk_init_data){
1155 .name = "gcc_camera_axi_clk",
1156 .ops = &clk_branch2_ops,
1161 static struct clk_branch gcc_camera_xo_clk = {
1163 .halt_check = BRANCH_HALT,
1165 .enable_reg = 0xb02c,
1166 .enable_mask = BIT(0),
1167 .hw.init = &(struct clk_init_data){
1168 .name = "gcc_camera_xo_clk",
1169 .flags = CLK_IS_CRITICAL,
1170 .ops = &clk_branch2_ops,
1175 static struct clk_branch gcc_ce1_ahb_clk = {
1176 .halt_reg = 0x4100c,
1177 .halt_check = BRANCH_HALT_VOTED,
1178 .hwcg_reg = 0x4100c,
1181 .enable_reg = 0x52004,
1182 .enable_mask = BIT(3),
1183 .hw.init = &(struct clk_init_data){
1184 .name = "gcc_ce1_ahb_clk",
1185 .ops = &clk_branch2_ops,
1190 static struct clk_branch gcc_ce1_axi_clk = {
1191 .halt_reg = 0x41008,
1192 .halt_check = BRANCH_HALT_VOTED,
1194 .enable_reg = 0x52004,
1195 .enable_mask = BIT(4),
1196 .hw.init = &(struct clk_init_data){
1197 .name = "gcc_ce1_axi_clk",
1198 .ops = &clk_branch2_ops,
1203 static struct clk_branch gcc_ce1_clk = {
1204 .halt_reg = 0x41004,
1205 .halt_check = BRANCH_HALT_VOTED,
1207 .enable_reg = 0x52004,
1208 .enable_mask = BIT(5),
1209 .hw.init = &(struct clk_init_data){
1210 .name = "gcc_ce1_clk",
1211 .ops = &clk_branch2_ops,
1216 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1218 .halt_check = BRANCH_HALT,
1220 .enable_reg = 0x502c,
1221 .enable_mask = BIT(0),
1222 .hw.init = &(struct clk_init_data){
1223 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1224 .parent_names = (const char *[]){
1225 "gcc_usb30_prim_master_clk_src",
1228 .flags = CLK_SET_RATE_PARENT,
1229 .ops = &clk_branch2_ops,
1234 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1236 .halt_check = BRANCH_HALT,
1238 .enable_reg = 0x5030,
1239 .enable_mask = BIT(0),
1240 .hw.init = &(struct clk_init_data){
1241 .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1242 .parent_names = (const char *[]){
1243 "gcc_usb30_sec_master_clk_src",
1246 .flags = CLK_SET_RATE_PARENT,
1247 .ops = &clk_branch2_ops,
1252 static struct clk_branch gcc_cpuss_ahb_clk = {
1253 .halt_reg = 0x48000,
1254 .halt_check = BRANCH_HALT_VOTED,
1256 .enable_reg = 0x52004,
1257 .enable_mask = BIT(21),
1258 .hw.init = &(struct clk_init_data){
1259 .name = "gcc_cpuss_ahb_clk",
1260 .parent_names = (const char *[]){
1261 "gcc_cpuss_ahb_clk_src",
1264 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1265 .ops = &clk_branch2_ops,
1270 static struct clk_branch gcc_cpuss_rbcpr_clk = {
1271 .halt_reg = 0x48008,
1272 .halt_check = BRANCH_HALT,
1274 .enable_reg = 0x48008,
1275 .enable_mask = BIT(0),
1276 .hw.init = &(struct clk_init_data){
1277 .name = "gcc_cpuss_rbcpr_clk",
1278 .parent_names = (const char *[]){
1279 "gcc_cpuss_rbcpr_clk_src",
1282 .flags = CLK_SET_RATE_PARENT,
1283 .ops = &clk_branch2_ops,
1288 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1289 .halt_reg = 0x44038,
1290 .halt_check = BRANCH_VOTED,
1292 .enable_reg = 0x44038,
1293 .enable_mask = BIT(0),
1294 .hw.init = &(struct clk_init_data){
1295 .name = "gcc_ddrss_gpu_axi_clk",
1296 .ops = &clk_branch2_ops,
1301 static struct clk_branch gcc_disp_ahb_clk = {
1303 .halt_check = BRANCH_HALT,
1307 .enable_reg = 0xb00c,
1308 .enable_mask = BIT(0),
1309 .hw.init = &(struct clk_init_data){
1310 .name = "gcc_disp_ahb_clk",
1311 .flags = CLK_IS_CRITICAL,
1312 .ops = &clk_branch2_ops,
1317 static struct clk_branch gcc_disp_axi_clk = {
1319 .halt_check = BRANCH_VOTED,
1321 .enable_reg = 0xb024,
1322 .enable_mask = BIT(0),
1323 .hw.init = &(struct clk_init_data){
1324 .name = "gcc_disp_axi_clk",
1325 .ops = &clk_branch2_ops,
1330 static struct clk_branch gcc_disp_gpll0_clk_src = {
1331 .halt_check = BRANCH_HALT_DELAY,
1333 .enable_reg = 0x52004,
1334 .enable_mask = BIT(18),
1335 .hw.init = &(struct clk_init_data){
1336 .name = "gcc_disp_gpll0_clk_src",
1337 .parent_names = (const char *[]){
1341 .ops = &clk_branch2_ops,
1346 static struct clk_branch gcc_disp_gpll0_div_clk_src = {
1347 .halt_check = BRANCH_HALT_DELAY,
1349 .enable_reg = 0x52004,
1350 .enable_mask = BIT(19),
1351 .hw.init = &(struct clk_init_data){
1352 .name = "gcc_disp_gpll0_div_clk_src",
1353 .parent_names = (const char *[]){
1357 .ops = &clk_branch2_ops,
1362 static struct clk_branch gcc_disp_xo_clk = {
1364 .halt_check = BRANCH_HALT,
1366 .enable_reg = 0xb030,
1367 .enable_mask = BIT(0),
1368 .hw.init = &(struct clk_init_data){
1369 .name = "gcc_disp_xo_clk",
1370 .flags = CLK_IS_CRITICAL,
1371 .ops = &clk_branch2_ops,
1376 static struct clk_branch gcc_gp1_clk = {
1377 .halt_reg = 0x64000,
1378 .halt_check = BRANCH_HALT,
1380 .enable_reg = 0x64000,
1381 .enable_mask = BIT(0),
1382 .hw.init = &(struct clk_init_data){
1383 .name = "gcc_gp1_clk",
1384 .parent_names = (const char *[]){
1388 .flags = CLK_SET_RATE_PARENT,
1389 .ops = &clk_branch2_ops,
1394 static struct clk_branch gcc_gp2_clk = {
1395 .halt_reg = 0x65000,
1396 .halt_check = BRANCH_HALT,
1398 .enable_reg = 0x65000,
1399 .enable_mask = BIT(0),
1400 .hw.init = &(struct clk_init_data){
1401 .name = "gcc_gp2_clk",
1402 .parent_names = (const char *[]){
1406 .flags = CLK_SET_RATE_PARENT,
1407 .ops = &clk_branch2_ops,
1412 static struct clk_branch gcc_gp3_clk = {
1413 .halt_reg = 0x66000,
1414 .halt_check = BRANCH_HALT,
1416 .enable_reg = 0x66000,
1417 .enable_mask = BIT(0),
1418 .hw.init = &(struct clk_init_data){
1419 .name = "gcc_gp3_clk",
1420 .parent_names = (const char *[]){
1424 .flags = CLK_SET_RATE_PARENT,
1425 .ops = &clk_branch2_ops,
1430 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1431 .halt_reg = 0x71004,
1432 .halt_check = BRANCH_HALT,
1433 .hwcg_reg = 0x71004,
1436 .enable_reg = 0x71004,
1437 .enable_mask = BIT(0),
1438 .hw.init = &(struct clk_init_data){
1439 .name = "gcc_gpu_cfg_ahb_clk",
1440 .flags = CLK_IS_CRITICAL,
1441 .ops = &clk_branch2_ops,
1446 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1447 .halt_check = BRANCH_HALT_DELAY,
1449 .enable_reg = 0x52004,
1450 .enable_mask = BIT(15),
1451 .hw.init = &(struct clk_init_data){
1452 .name = "gcc_gpu_gpll0_clk_src",
1453 .parent_names = (const char *[]){
1457 .ops = &clk_branch2_ops,
1462 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1463 .halt_check = BRANCH_HALT_DELAY,
1465 .enable_reg = 0x52004,
1466 .enable_mask = BIT(16),
1467 .hw.init = &(struct clk_init_data){
1468 .name = "gcc_gpu_gpll0_div_clk_src",
1469 .parent_names = (const char *[]){
1473 .ops = &clk_branch2_ops,
1478 static struct clk_branch gcc_gpu_iref_clk = {
1479 .halt_reg = 0x8c010,
1480 .halt_check = BRANCH_HALT,
1482 .enable_reg = 0x8c010,
1483 .enable_mask = BIT(0),
1484 .hw.init = &(struct clk_init_data){
1485 .name = "gcc_gpu_iref_clk",
1486 .ops = &clk_branch2_ops,
1491 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1492 .halt_reg = 0x7100c,
1493 .halt_check = BRANCH_VOTED,
1495 .enable_reg = 0x7100c,
1496 .enable_mask = BIT(0),
1497 .hw.init = &(struct clk_init_data){
1498 .name = "gcc_gpu_memnoc_gfx_clk",
1499 .ops = &clk_branch2_ops,
1504 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1505 .halt_reg = 0x71018,
1506 .halt_check = BRANCH_HALT,
1508 .enable_reg = 0x71018,
1509 .enable_mask = BIT(0),
1510 .hw.init = &(struct clk_init_data){
1511 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1512 .ops = &clk_branch2_ops,
1517 static struct clk_branch gcc_gpu_vs_clk = {
1518 .halt_reg = 0x7a04c,
1519 .halt_check = BRANCH_HALT,
1521 .enable_reg = 0x7a04c,
1522 .enable_mask = BIT(0),
1523 .hw.init = &(struct clk_init_data){
1524 .name = "gcc_gpu_vs_clk",
1525 .parent_names = (const char *[]){
1526 "gcc_vsensor_clk_src",
1529 .flags = CLK_SET_RATE_PARENT,
1530 .ops = &clk_branch2_ops,
1535 static struct clk_branch gcc_mss_axis2_clk = {
1536 .halt_reg = 0x8a008,
1537 .halt_check = BRANCH_HALT,
1539 .enable_reg = 0x8a008,
1540 .enable_mask = BIT(0),
1541 .hw.init = &(struct clk_init_data){
1542 .name = "gcc_mss_axis2_clk",
1543 .ops = &clk_branch2_ops,
1548 static struct clk_branch gcc_mss_cfg_ahb_clk = {
1549 .halt_reg = 0x8a000,
1550 .halt_check = BRANCH_HALT,
1551 .hwcg_reg = 0x8a000,
1554 .enable_reg = 0x8a000,
1555 .enable_mask = BIT(0),
1556 .hw.init = &(struct clk_init_data){
1557 .name = "gcc_mss_cfg_ahb_clk",
1558 .ops = &clk_branch2_ops,
1563 static struct clk_branch gcc_mss_gpll0_div_clk_src = {
1564 .halt_check = BRANCH_HALT_DELAY,
1566 .enable_reg = 0x52004,
1567 .enable_mask = BIT(17),
1568 .hw.init = &(struct clk_init_data){
1569 .name = "gcc_mss_gpll0_div_clk_src",
1570 .ops = &clk_branch2_ops,
1575 static struct clk_branch gcc_mss_mfab_axis_clk = {
1576 .halt_reg = 0x8a004,
1577 .halt_check = BRANCH_VOTED,
1578 .hwcg_reg = 0x8a004,
1581 .enable_reg = 0x8a004,
1582 .enable_mask = BIT(0),
1583 .hw.init = &(struct clk_init_data){
1584 .name = "gcc_mss_mfab_axis_clk",
1585 .ops = &clk_branch2_ops,
1590 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
1591 .halt_reg = 0x8a154,
1592 .halt_check = BRANCH_VOTED,
1594 .enable_reg = 0x8a154,
1595 .enable_mask = BIT(0),
1596 .hw.init = &(struct clk_init_data){
1597 .name = "gcc_mss_q6_memnoc_axi_clk",
1598 .ops = &clk_branch2_ops,
1603 static struct clk_branch gcc_mss_snoc_axi_clk = {
1604 .halt_reg = 0x8a150,
1605 .halt_check = BRANCH_HALT,
1607 .enable_reg = 0x8a150,
1608 .enable_mask = BIT(0),
1609 .hw.init = &(struct clk_init_data){
1610 .name = "gcc_mss_snoc_axi_clk",
1611 .ops = &clk_branch2_ops,
1616 static struct clk_branch gcc_mss_vs_clk = {
1617 .halt_reg = 0x7a048,
1618 .halt_check = BRANCH_HALT,
1620 .enable_reg = 0x7a048,
1621 .enable_mask = BIT(0),
1622 .hw.init = &(struct clk_init_data){
1623 .name = "gcc_mss_vs_clk",
1624 .parent_names = (const char *[]){
1625 "gcc_vsensor_clk_src",
1628 .flags = CLK_SET_RATE_PARENT,
1629 .ops = &clk_branch2_ops,
1634 static struct clk_branch gcc_pcie_0_aux_clk = {
1635 .halt_reg = 0x6b01c,
1636 .halt_check = BRANCH_HALT_VOTED,
1638 .enable_reg = 0x5200c,
1639 .enable_mask = BIT(3),
1640 .hw.init = &(struct clk_init_data){
1641 .name = "gcc_pcie_0_aux_clk",
1642 .parent_names = (const char *[]){
1643 "gcc_pcie_0_aux_clk_src",
1646 .flags = CLK_SET_RATE_PARENT,
1647 .ops = &clk_branch2_ops,
1652 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1653 .halt_reg = 0x6b018,
1654 .halt_check = BRANCH_HALT_VOTED,
1655 .hwcg_reg = 0x6b018,
1658 .enable_reg = 0x5200c,
1659 .enable_mask = BIT(2),
1660 .hw.init = &(struct clk_init_data){
1661 .name = "gcc_pcie_0_cfg_ahb_clk",
1662 .ops = &clk_branch2_ops,
1667 static struct clk_branch gcc_pcie_0_clkref_clk = {
1668 .halt_reg = 0x8c00c,
1669 .halt_check = BRANCH_HALT,
1671 .enable_reg = 0x8c00c,
1672 .enable_mask = BIT(0),
1673 .hw.init = &(struct clk_init_data){
1674 .name = "gcc_pcie_0_clkref_clk",
1675 .ops = &clk_branch2_ops,
1680 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1681 .halt_reg = 0x6b014,
1682 .halt_check = BRANCH_HALT_VOTED,
1684 .enable_reg = 0x5200c,
1685 .enable_mask = BIT(1),
1686 .hw.init = &(struct clk_init_data){
1687 .name = "gcc_pcie_0_mstr_axi_clk",
1688 .ops = &clk_branch2_ops,
1693 static struct clk_branch gcc_pcie_0_pipe_clk = {
1694 .halt_check = BRANCH_HALT_SKIP,
1696 .enable_reg = 0x5200c,
1697 .enable_mask = BIT(4),
1698 .hw.init = &(struct clk_init_data){
1699 .name = "gcc_pcie_0_pipe_clk",
1700 .ops = &clk_branch2_ops,
1705 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1706 .halt_reg = 0x6b010,
1707 .halt_check = BRANCH_HALT_VOTED,
1708 .hwcg_reg = 0x6b010,
1711 .enable_reg = 0x5200c,
1712 .enable_mask = BIT(0),
1713 .hw.init = &(struct clk_init_data){
1714 .name = "gcc_pcie_0_slv_axi_clk",
1715 .ops = &clk_branch2_ops,
1720 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1721 .halt_reg = 0x6b00c,
1722 .halt_check = BRANCH_HALT_VOTED,
1724 .enable_reg = 0x5200c,
1725 .enable_mask = BIT(5),
1726 .hw.init = &(struct clk_init_data){
1727 .name = "gcc_pcie_0_slv_q2a_axi_clk",
1728 .ops = &clk_branch2_ops,
1733 static struct clk_branch gcc_pcie_1_aux_clk = {
1734 .halt_reg = 0x8d01c,
1735 .halt_check = BRANCH_HALT_VOTED,
1737 .enable_reg = 0x52004,
1738 .enable_mask = BIT(29),
1739 .hw.init = &(struct clk_init_data){
1740 .name = "gcc_pcie_1_aux_clk",
1741 .parent_names = (const char *[]){
1742 "gcc_pcie_1_aux_clk_src",
1745 .flags = CLK_SET_RATE_PARENT,
1746 .ops = &clk_branch2_ops,
1751 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1752 .halt_reg = 0x8d018,
1753 .halt_check = BRANCH_HALT_VOTED,
1754 .hwcg_reg = 0x8d018,
1757 .enable_reg = 0x52004,
1758 .enable_mask = BIT(28),
1759 .hw.init = &(struct clk_init_data){
1760 .name = "gcc_pcie_1_cfg_ahb_clk",
1761 .ops = &clk_branch2_ops,
1766 static struct clk_branch gcc_pcie_1_clkref_clk = {
1767 .halt_reg = 0x8c02c,
1768 .halt_check = BRANCH_HALT,
1770 .enable_reg = 0x8c02c,
1771 .enable_mask = BIT(0),
1772 .hw.init = &(struct clk_init_data){
1773 .name = "gcc_pcie_1_clkref_clk",
1774 .ops = &clk_branch2_ops,
1779 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1780 .halt_reg = 0x8d014,
1781 .halt_check = BRANCH_HALT_VOTED,
1783 .enable_reg = 0x52004,
1784 .enable_mask = BIT(27),
1785 .hw.init = &(struct clk_init_data){
1786 .name = "gcc_pcie_1_mstr_axi_clk",
1787 .ops = &clk_branch2_ops,
1792 static struct clk_branch gcc_pcie_1_pipe_clk = {
1793 .halt_check = BRANCH_HALT_SKIP,
1795 .enable_reg = 0x52004,
1796 .enable_mask = BIT(30),
1797 .hw.init = &(struct clk_init_data){
1798 .name = "gcc_pcie_1_pipe_clk",
1799 .ops = &clk_branch2_ops,
1804 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1805 .halt_reg = 0x8d010,
1806 .halt_check = BRANCH_HALT_VOTED,
1807 .hwcg_reg = 0x8d010,
1810 .enable_reg = 0x52004,
1811 .enable_mask = BIT(26),
1812 .hw.init = &(struct clk_init_data){
1813 .name = "gcc_pcie_1_slv_axi_clk",
1814 .ops = &clk_branch2_ops,
1819 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1820 .halt_reg = 0x8d00c,
1821 .halt_check = BRANCH_HALT_VOTED,
1823 .enable_reg = 0x52004,
1824 .enable_mask = BIT(25),
1825 .hw.init = &(struct clk_init_data){
1826 .name = "gcc_pcie_1_slv_q2a_axi_clk",
1827 .ops = &clk_branch2_ops,
1832 static struct clk_branch gcc_pcie_phy_aux_clk = {
1833 .halt_reg = 0x6f004,
1834 .halt_check = BRANCH_HALT,
1836 .enable_reg = 0x6f004,
1837 .enable_mask = BIT(0),
1838 .hw.init = &(struct clk_init_data){
1839 .name = "gcc_pcie_phy_aux_clk",
1840 .parent_names = (const char *[]){
1841 "gcc_pcie_0_aux_clk_src",
1844 .flags = CLK_SET_RATE_PARENT,
1845 .ops = &clk_branch2_ops,
1850 static struct clk_branch gcc_pcie_phy_refgen_clk = {
1851 .halt_reg = 0x6f02c,
1852 .halt_check = BRANCH_HALT,
1854 .enable_reg = 0x6f02c,
1855 .enable_mask = BIT(0),
1856 .hw.init = &(struct clk_init_data){
1857 .name = "gcc_pcie_phy_refgen_clk",
1858 .parent_names = (const char *[]){
1859 "gcc_pcie_phy_refgen_clk_src",
1862 .flags = CLK_SET_RATE_PARENT,
1863 .ops = &clk_branch2_ops,
1868 static struct clk_branch gcc_pdm2_clk = {
1869 .halt_reg = 0x3300c,
1870 .halt_check = BRANCH_HALT,
1872 .enable_reg = 0x3300c,
1873 .enable_mask = BIT(0),
1874 .hw.init = &(struct clk_init_data){
1875 .name = "gcc_pdm2_clk",
1876 .parent_names = (const char *[]){
1880 .flags = CLK_SET_RATE_PARENT,
1881 .ops = &clk_branch2_ops,
1886 static struct clk_branch gcc_pdm_ahb_clk = {
1887 .halt_reg = 0x33004,
1888 .halt_check = BRANCH_HALT,
1889 .hwcg_reg = 0x33004,
1892 .enable_reg = 0x33004,
1893 .enable_mask = BIT(0),
1894 .hw.init = &(struct clk_init_data){
1895 .name = "gcc_pdm_ahb_clk",
1896 .ops = &clk_branch2_ops,
1901 static struct clk_branch gcc_pdm_xo4_clk = {
1902 .halt_reg = 0x33008,
1903 .halt_check = BRANCH_HALT,
1905 .enable_reg = 0x33008,
1906 .enable_mask = BIT(0),
1907 .hw.init = &(struct clk_init_data){
1908 .name = "gcc_pdm_xo4_clk",
1909 .ops = &clk_branch2_ops,
1914 static struct clk_branch gcc_prng_ahb_clk = {
1915 .halt_reg = 0x34004,
1916 .halt_check = BRANCH_HALT_VOTED,
1917 .hwcg_reg = 0x34004,
1920 .enable_reg = 0x52004,
1921 .enable_mask = BIT(13),
1922 .hw.init = &(struct clk_init_data){
1923 .name = "gcc_prng_ahb_clk",
1924 .ops = &clk_branch2_ops,
1929 static struct clk_branch gcc_qmip_camera_ahb_clk = {
1931 .halt_check = BRANCH_HALT,
1935 .enable_reg = 0xb014,
1936 .enable_mask = BIT(0),
1937 .hw.init = &(struct clk_init_data){
1938 .name = "gcc_qmip_camera_ahb_clk",
1939 .ops = &clk_branch2_ops,
1944 static struct clk_branch gcc_qmip_disp_ahb_clk = {
1946 .halt_check = BRANCH_HALT,
1950 .enable_reg = 0xb018,
1951 .enable_mask = BIT(0),
1952 .hw.init = &(struct clk_init_data){
1953 .name = "gcc_qmip_disp_ahb_clk",
1954 .ops = &clk_branch2_ops,
1959 static struct clk_branch gcc_qmip_video_ahb_clk = {
1961 .halt_check = BRANCH_HALT,
1965 .enable_reg = 0xb010,
1966 .enable_mask = BIT(0),
1967 .hw.init = &(struct clk_init_data){
1968 .name = "gcc_qmip_video_ahb_clk",
1969 .ops = &clk_branch2_ops,
1974 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
1975 .halt_reg = 0x4b000,
1976 .halt_check = BRANCH_HALT,
1978 .enable_reg = 0x4b000,
1979 .enable_mask = BIT(0),
1980 .hw.init = &(struct clk_init_data){
1981 .name = "gcc_qspi_cnoc_periph_ahb_clk",
1982 .ops = &clk_branch2_ops,
1987 static struct clk_branch gcc_qspi_core_clk = {
1988 .halt_reg = 0x4b004,
1989 .halt_check = BRANCH_HALT,
1991 .enable_reg = 0x4b004,
1992 .enable_mask = BIT(0),
1993 .hw.init = &(struct clk_init_data){
1994 .name = "gcc_qspi_core_clk",
1995 .parent_names = (const char *[]){
1996 "gcc_qspi_core_clk_src",
1999 .flags = CLK_SET_RATE_PARENT,
2000 .ops = &clk_branch2_ops,
2005 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2006 .halt_reg = 0x17030,
2007 .halt_check = BRANCH_HALT_VOTED,
2009 .enable_reg = 0x5200c,
2010 .enable_mask = BIT(10),
2011 .hw.init = &(struct clk_init_data){
2012 .name = "gcc_qupv3_wrap0_s0_clk",
2013 .parent_names = (const char *[]){
2014 "gcc_qupv3_wrap0_s0_clk_src",
2017 .flags = CLK_SET_RATE_PARENT,
2018 .ops = &clk_branch2_ops,
2023 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2024 .halt_reg = 0x17160,
2025 .halt_check = BRANCH_HALT_VOTED,
2027 .enable_reg = 0x5200c,
2028 .enable_mask = BIT(11),
2029 .hw.init = &(struct clk_init_data){
2030 .name = "gcc_qupv3_wrap0_s1_clk",
2031 .parent_names = (const char *[]){
2032 "gcc_qupv3_wrap0_s1_clk_src",
2035 .flags = CLK_SET_RATE_PARENT,
2036 .ops = &clk_branch2_ops,
2041 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2042 .halt_reg = 0x17290,
2043 .halt_check = BRANCH_HALT_VOTED,
2045 .enable_reg = 0x5200c,
2046 .enable_mask = BIT(12),
2047 .hw.init = &(struct clk_init_data){
2048 .name = "gcc_qupv3_wrap0_s2_clk",
2049 .parent_names = (const char *[]){
2050 "gcc_qupv3_wrap0_s2_clk_src",
2053 .flags = CLK_SET_RATE_PARENT,
2054 .ops = &clk_branch2_ops,
2059 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2060 .halt_reg = 0x173c0,
2061 .halt_check = BRANCH_HALT_VOTED,
2063 .enable_reg = 0x5200c,
2064 .enable_mask = BIT(13),
2065 .hw.init = &(struct clk_init_data){
2066 .name = "gcc_qupv3_wrap0_s3_clk",
2067 .parent_names = (const char *[]){
2068 "gcc_qupv3_wrap0_s3_clk_src",
2071 .flags = CLK_SET_RATE_PARENT,
2072 .ops = &clk_branch2_ops,
2077 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2078 .halt_reg = 0x174f0,
2079 .halt_check = BRANCH_HALT_VOTED,
2081 .enable_reg = 0x5200c,
2082 .enable_mask = BIT(14),
2083 .hw.init = &(struct clk_init_data){
2084 .name = "gcc_qupv3_wrap0_s4_clk",
2085 .parent_names = (const char *[]){
2086 "gcc_qupv3_wrap0_s4_clk_src",
2089 .flags = CLK_SET_RATE_PARENT,
2090 .ops = &clk_branch2_ops,
2095 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2096 .halt_reg = 0x17620,
2097 .halt_check = BRANCH_HALT_VOTED,
2099 .enable_reg = 0x5200c,
2100 .enable_mask = BIT(15),
2101 .hw.init = &(struct clk_init_data){
2102 .name = "gcc_qupv3_wrap0_s5_clk",
2103 .parent_names = (const char *[]){
2104 "gcc_qupv3_wrap0_s5_clk_src",
2107 .flags = CLK_SET_RATE_PARENT,
2108 .ops = &clk_branch2_ops,
2113 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2114 .halt_reg = 0x17750,
2115 .halt_check = BRANCH_HALT_VOTED,
2117 .enable_reg = 0x5200c,
2118 .enable_mask = BIT(16),
2119 .hw.init = &(struct clk_init_data){
2120 .name = "gcc_qupv3_wrap0_s6_clk",
2121 .parent_names = (const char *[]){
2122 "gcc_qupv3_wrap0_s6_clk_src",
2125 .flags = CLK_SET_RATE_PARENT,
2126 .ops = &clk_branch2_ops,
2131 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2132 .halt_reg = 0x17880,
2133 .halt_check = BRANCH_HALT_VOTED,
2135 .enable_reg = 0x5200c,
2136 .enable_mask = BIT(17),
2137 .hw.init = &(struct clk_init_data){
2138 .name = "gcc_qupv3_wrap0_s7_clk",
2139 .parent_names = (const char *[]){
2140 "gcc_qupv3_wrap0_s7_clk_src",
2143 .flags = CLK_SET_RATE_PARENT,
2144 .ops = &clk_branch2_ops,
2149 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2150 .halt_reg = 0x18014,
2151 .halt_check = BRANCH_HALT_VOTED,
2153 .enable_reg = 0x5200c,
2154 .enable_mask = BIT(22),
2155 .hw.init = &(struct clk_init_data){
2156 .name = "gcc_qupv3_wrap1_s0_clk",
2157 .parent_names = (const char *[]){
2158 "gcc_qupv3_wrap1_s0_clk_src",
2161 .flags = CLK_SET_RATE_PARENT,
2162 .ops = &clk_branch2_ops,
2167 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2168 .halt_reg = 0x18144,
2169 .halt_check = BRANCH_HALT_VOTED,
2171 .enable_reg = 0x5200c,
2172 .enable_mask = BIT(23),
2173 .hw.init = &(struct clk_init_data){
2174 .name = "gcc_qupv3_wrap1_s1_clk",
2175 .parent_names = (const char *[]){
2176 "gcc_qupv3_wrap1_s1_clk_src",
2179 .flags = CLK_SET_RATE_PARENT,
2180 .ops = &clk_branch2_ops,
2185 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2186 .halt_reg = 0x18274,
2187 .halt_check = BRANCH_HALT_VOTED,
2189 .enable_reg = 0x5200c,
2190 .enable_mask = BIT(24),
2191 .hw.init = &(struct clk_init_data){
2192 .name = "gcc_qupv3_wrap1_s2_clk",
2193 .parent_names = (const char *[]){
2194 "gcc_qupv3_wrap1_s2_clk_src",
2197 .flags = CLK_SET_RATE_PARENT,
2198 .ops = &clk_branch2_ops,
2203 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2204 .halt_reg = 0x183a4,
2205 .halt_check = BRANCH_HALT_VOTED,
2207 .enable_reg = 0x5200c,
2208 .enable_mask = BIT(25),
2209 .hw.init = &(struct clk_init_data){
2210 .name = "gcc_qupv3_wrap1_s3_clk",
2211 .parent_names = (const char *[]){
2212 "gcc_qupv3_wrap1_s3_clk_src",
2215 .flags = CLK_SET_RATE_PARENT,
2216 .ops = &clk_branch2_ops,
2221 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2222 .halt_reg = 0x184d4,
2223 .halt_check = BRANCH_HALT_VOTED,
2225 .enable_reg = 0x5200c,
2226 .enable_mask = BIT(26),
2227 .hw.init = &(struct clk_init_data){
2228 .name = "gcc_qupv3_wrap1_s4_clk",
2229 .parent_names = (const char *[]){
2230 "gcc_qupv3_wrap1_s4_clk_src",
2233 .flags = CLK_SET_RATE_PARENT,
2234 .ops = &clk_branch2_ops,
2239 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2240 .halt_reg = 0x18604,
2241 .halt_check = BRANCH_HALT_VOTED,
2243 .enable_reg = 0x5200c,
2244 .enable_mask = BIT(27),
2245 .hw.init = &(struct clk_init_data){
2246 .name = "gcc_qupv3_wrap1_s5_clk",
2247 .parent_names = (const char *[]){
2248 "gcc_qupv3_wrap1_s5_clk_src",
2251 .flags = CLK_SET_RATE_PARENT,
2252 .ops = &clk_branch2_ops,
2257 static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
2258 .halt_reg = 0x18734,
2259 .halt_check = BRANCH_HALT_VOTED,
2261 .enable_reg = 0x5200c,
2262 .enable_mask = BIT(28),
2263 .hw.init = &(struct clk_init_data){
2264 .name = "gcc_qupv3_wrap1_s6_clk",
2265 .parent_names = (const char *[]){
2266 "gcc_qupv3_wrap1_s6_clk_src",
2269 .flags = CLK_SET_RATE_PARENT,
2270 .ops = &clk_branch2_ops,
2275 static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
2276 .halt_reg = 0x18864,
2277 .halt_check = BRANCH_HALT_VOTED,
2279 .enable_reg = 0x5200c,
2280 .enable_mask = BIT(29),
2281 .hw.init = &(struct clk_init_data){
2282 .name = "gcc_qupv3_wrap1_s7_clk",
2283 .parent_names = (const char *[]){
2284 "gcc_qupv3_wrap1_s7_clk_src",
2287 .flags = CLK_SET_RATE_PARENT,
2288 .ops = &clk_branch2_ops,
2293 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2294 .halt_reg = 0x17004,
2295 .halt_check = BRANCH_HALT_VOTED,
2297 .enable_reg = 0x5200c,
2298 .enable_mask = BIT(6),
2299 .hw.init = &(struct clk_init_data){
2300 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2301 .ops = &clk_branch2_ops,
2306 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2307 .halt_reg = 0x17008,
2308 .halt_check = BRANCH_HALT_VOTED,
2309 .hwcg_reg = 0x17008,
2312 .enable_reg = 0x5200c,
2313 .enable_mask = BIT(7),
2314 .hw.init = &(struct clk_init_data){
2315 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2316 .ops = &clk_branch2_ops,
2321 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2322 .halt_reg = 0x1800c,
2323 .halt_check = BRANCH_HALT_VOTED,
2325 .enable_reg = 0x5200c,
2326 .enable_mask = BIT(20),
2327 .hw.init = &(struct clk_init_data){
2328 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2329 .ops = &clk_branch2_ops,
2334 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2335 .halt_reg = 0x18010,
2336 .halt_check = BRANCH_HALT_VOTED,
2337 .hwcg_reg = 0x18010,
2340 .enable_reg = 0x5200c,
2341 .enable_mask = BIT(21),
2342 .hw.init = &(struct clk_init_data){
2343 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2344 .ops = &clk_branch2_ops,
2349 static struct clk_branch gcc_sdcc2_ahb_clk = {
2350 .halt_reg = 0x14008,
2351 .halt_check = BRANCH_HALT,
2353 .enable_reg = 0x14008,
2354 .enable_mask = BIT(0),
2355 .hw.init = &(struct clk_init_data){
2356 .name = "gcc_sdcc2_ahb_clk",
2357 .ops = &clk_branch2_ops,
2362 static struct clk_branch gcc_sdcc2_apps_clk = {
2363 .halt_reg = 0x14004,
2364 .halt_check = BRANCH_HALT,
2366 .enable_reg = 0x14004,
2367 .enable_mask = BIT(0),
2368 .hw.init = &(struct clk_init_data){
2369 .name = "gcc_sdcc2_apps_clk",
2370 .parent_names = (const char *[]){
2371 "gcc_sdcc2_apps_clk_src",
2374 .flags = CLK_SET_RATE_PARENT,
2375 .ops = &clk_branch2_ops,
2380 static struct clk_branch gcc_sdcc4_ahb_clk = {
2381 .halt_reg = 0x16008,
2382 .halt_check = BRANCH_HALT,
2384 .enable_reg = 0x16008,
2385 .enable_mask = BIT(0),
2386 .hw.init = &(struct clk_init_data){
2387 .name = "gcc_sdcc4_ahb_clk",
2388 .ops = &clk_branch2_ops,
2393 static struct clk_branch gcc_sdcc4_apps_clk = {
2394 .halt_reg = 0x16004,
2395 .halt_check = BRANCH_HALT,
2397 .enable_reg = 0x16004,
2398 .enable_mask = BIT(0),
2399 .hw.init = &(struct clk_init_data){
2400 .name = "gcc_sdcc4_apps_clk",
2401 .parent_names = (const char *[]){
2402 "gcc_sdcc4_apps_clk_src",
2405 .flags = CLK_SET_RATE_PARENT,
2406 .ops = &clk_branch2_ops,
2411 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2413 .halt_check = BRANCH_HALT_VOTED,
2415 .enable_reg = 0x52004,
2416 .enable_mask = BIT(0),
2417 .hw.init = &(struct clk_init_data){
2418 .name = "gcc_sys_noc_cpuss_ahb_clk",
2419 .parent_names = (const char *[]){
2420 "gcc_cpuss_ahb_clk_src",
2423 .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2424 .ops = &clk_branch2_ops,
2429 static struct clk_branch gcc_tsif_ahb_clk = {
2430 .halt_reg = 0x36004,
2431 .halt_check = BRANCH_HALT,
2433 .enable_reg = 0x36004,
2434 .enable_mask = BIT(0),
2435 .hw.init = &(struct clk_init_data){
2436 .name = "gcc_tsif_ahb_clk",
2437 .ops = &clk_branch2_ops,
2442 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2443 .halt_reg = 0x3600c,
2444 .halt_check = BRANCH_HALT,
2446 .enable_reg = 0x3600c,
2447 .enable_mask = BIT(0),
2448 .hw.init = &(struct clk_init_data){
2449 .name = "gcc_tsif_inactivity_timers_clk",
2450 .ops = &clk_branch2_ops,
2455 static struct clk_branch gcc_tsif_ref_clk = {
2456 .halt_reg = 0x36008,
2457 .halt_check = BRANCH_HALT,
2459 .enable_reg = 0x36008,
2460 .enable_mask = BIT(0),
2461 .hw.init = &(struct clk_init_data){
2462 .name = "gcc_tsif_ref_clk",
2463 .parent_names = (const char *[]){
2464 "gcc_tsif_ref_clk_src",
2467 .flags = CLK_SET_RATE_PARENT,
2468 .ops = &clk_branch2_ops,
2473 static struct clk_branch gcc_ufs_card_ahb_clk = {
2474 .halt_reg = 0x75010,
2475 .halt_check = BRANCH_HALT,
2476 .hwcg_reg = 0x75010,
2479 .enable_reg = 0x75010,
2480 .enable_mask = BIT(0),
2481 .hw.init = &(struct clk_init_data){
2482 .name = "gcc_ufs_card_ahb_clk",
2483 .ops = &clk_branch2_ops,
2488 static struct clk_branch gcc_ufs_card_axi_clk = {
2489 .halt_reg = 0x7500c,
2490 .halt_check = BRANCH_HALT,
2491 .hwcg_reg = 0x7500c,
2494 .enable_reg = 0x7500c,
2495 .enable_mask = BIT(0),
2496 .hw.init = &(struct clk_init_data){
2497 .name = "gcc_ufs_card_axi_clk",
2498 .parent_names = (const char *[]){
2499 "gcc_ufs_card_axi_clk_src",
2502 .flags = CLK_SET_RATE_PARENT,
2503 .ops = &clk_branch2_ops,
2508 static struct clk_branch gcc_ufs_card_clkref_clk = {
2509 .halt_reg = 0x8c004,
2510 .halt_check = BRANCH_HALT,
2512 .enable_reg = 0x8c004,
2513 .enable_mask = BIT(0),
2514 .hw.init = &(struct clk_init_data){
2515 .name = "gcc_ufs_card_clkref_clk",
2516 .ops = &clk_branch2_ops,
2521 static struct clk_branch gcc_ufs_card_ice_core_clk = {
2522 .halt_reg = 0x75058,
2523 .halt_check = BRANCH_HALT,
2524 .hwcg_reg = 0x75058,
2527 .enable_reg = 0x75058,
2528 .enable_mask = BIT(0),
2529 .hw.init = &(struct clk_init_data){
2530 .name = "gcc_ufs_card_ice_core_clk",
2531 .parent_names = (const char *[]){
2532 "gcc_ufs_card_ice_core_clk_src",
2535 .flags = CLK_SET_RATE_PARENT,
2536 .ops = &clk_branch2_ops,
2541 static struct clk_branch gcc_ufs_card_phy_aux_clk = {
2542 .halt_reg = 0x7508c,
2543 .halt_check = BRANCH_HALT,
2544 .hwcg_reg = 0x7508c,
2547 .enable_reg = 0x7508c,
2548 .enable_mask = BIT(0),
2549 .hw.init = &(struct clk_init_data){
2550 .name = "gcc_ufs_card_phy_aux_clk",
2551 .parent_names = (const char *[]){
2552 "gcc_ufs_card_phy_aux_clk_src",
2555 .flags = CLK_SET_RATE_PARENT,
2556 .ops = &clk_branch2_ops,
2561 static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
2562 .halt_check = BRANCH_HALT_SKIP,
2564 .enable_reg = 0x75018,
2565 .enable_mask = BIT(0),
2566 .hw.init = &(struct clk_init_data){
2567 .name = "gcc_ufs_card_rx_symbol_0_clk",
2568 .ops = &clk_branch2_ops,
2573 static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
2574 .halt_check = BRANCH_HALT_SKIP,
2576 .enable_reg = 0x750a8,
2577 .enable_mask = BIT(0),
2578 .hw.init = &(struct clk_init_data){
2579 .name = "gcc_ufs_card_rx_symbol_1_clk",
2580 .ops = &clk_branch2_ops,
2585 static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
2586 .halt_check = BRANCH_HALT_SKIP,
2588 .enable_reg = 0x75014,
2589 .enable_mask = BIT(0),
2590 .hw.init = &(struct clk_init_data){
2591 .name = "gcc_ufs_card_tx_symbol_0_clk",
2592 .ops = &clk_branch2_ops,
2597 static struct clk_branch gcc_ufs_card_unipro_core_clk = {
2598 .halt_reg = 0x75054,
2599 .halt_check = BRANCH_HALT,
2600 .hwcg_reg = 0x75054,
2603 .enable_reg = 0x75054,
2604 .enable_mask = BIT(0),
2605 .hw.init = &(struct clk_init_data){
2606 .name = "gcc_ufs_card_unipro_core_clk",
2607 .parent_names = (const char *[]){
2608 "gcc_ufs_card_unipro_core_clk_src",
2611 .flags = CLK_SET_RATE_PARENT,
2612 .ops = &clk_branch2_ops,
2617 static struct clk_branch gcc_ufs_mem_clkref_clk = {
2618 .halt_reg = 0x8c000,
2619 .halt_check = BRANCH_HALT,
2621 .enable_reg = 0x8c000,
2622 .enable_mask = BIT(0),
2623 .hw.init = &(struct clk_init_data){
2624 .name = "gcc_ufs_mem_clkref_clk",
2625 .ops = &clk_branch2_ops,
2630 static struct clk_branch gcc_ufs_phy_ahb_clk = {
2631 .halt_reg = 0x77010,
2632 .halt_check = BRANCH_HALT,
2633 .hwcg_reg = 0x77010,
2636 .enable_reg = 0x77010,
2637 .enable_mask = BIT(0),
2638 .hw.init = &(struct clk_init_data){
2639 .name = "gcc_ufs_phy_ahb_clk",
2640 .ops = &clk_branch2_ops,
2645 static struct clk_branch gcc_ufs_phy_axi_clk = {
2646 .halt_reg = 0x7700c,
2647 .halt_check = BRANCH_HALT,
2648 .hwcg_reg = 0x7700c,
2651 .enable_reg = 0x7700c,
2652 .enable_mask = BIT(0),
2653 .hw.init = &(struct clk_init_data){
2654 .name = "gcc_ufs_phy_axi_clk",
2655 .parent_names = (const char *[]){
2656 "gcc_ufs_phy_axi_clk_src",
2659 .flags = CLK_SET_RATE_PARENT,
2660 .ops = &clk_branch2_ops,
2665 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2666 .halt_reg = 0x77058,
2667 .halt_check = BRANCH_HALT,
2668 .hwcg_reg = 0x77058,
2671 .enable_reg = 0x77058,
2672 .enable_mask = BIT(0),
2673 .hw.init = &(struct clk_init_data){
2674 .name = "gcc_ufs_phy_ice_core_clk",
2675 .parent_names = (const char *[]){
2676 "gcc_ufs_phy_ice_core_clk_src",
2679 .flags = CLK_SET_RATE_PARENT,
2680 .ops = &clk_branch2_ops,
2685 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2686 .halt_reg = 0x7708c,
2687 .halt_check = BRANCH_HALT,
2688 .hwcg_reg = 0x7708c,
2691 .enable_reg = 0x7708c,
2692 .enable_mask = BIT(0),
2693 .hw.init = &(struct clk_init_data){
2694 .name = "gcc_ufs_phy_phy_aux_clk",
2695 .parent_names = (const char *[]){
2696 "gcc_ufs_phy_phy_aux_clk_src",
2699 .flags = CLK_SET_RATE_PARENT,
2700 .ops = &clk_branch2_ops,
2705 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2706 .halt_check = BRANCH_HALT_SKIP,
2708 .enable_reg = 0x77018,
2709 .enable_mask = BIT(0),
2710 .hw.init = &(struct clk_init_data){
2711 .name = "gcc_ufs_phy_rx_symbol_0_clk",
2712 .ops = &clk_branch2_ops,
2717 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2718 .halt_check = BRANCH_HALT_SKIP,
2720 .enable_reg = 0x770a8,
2721 .enable_mask = BIT(0),
2722 .hw.init = &(struct clk_init_data){
2723 .name = "gcc_ufs_phy_rx_symbol_1_clk",
2724 .ops = &clk_branch2_ops,
2729 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2730 .halt_check = BRANCH_HALT_SKIP,
2732 .enable_reg = 0x77014,
2733 .enable_mask = BIT(0),
2734 .hw.init = &(struct clk_init_data){
2735 .name = "gcc_ufs_phy_tx_symbol_0_clk",
2736 .ops = &clk_branch2_ops,
2741 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2742 .halt_reg = 0x77054,
2743 .halt_check = BRANCH_HALT,
2744 .hwcg_reg = 0x77054,
2747 .enable_reg = 0x77054,
2748 .enable_mask = BIT(0),
2749 .hw.init = &(struct clk_init_data){
2750 .name = "gcc_ufs_phy_unipro_core_clk",
2751 .parent_names = (const char *[]){
2752 "gcc_ufs_phy_unipro_core_clk_src",
2755 .flags = CLK_SET_RATE_PARENT,
2756 .ops = &clk_branch2_ops,
2761 static struct clk_branch gcc_usb30_prim_master_clk = {
2763 .halt_check = BRANCH_HALT,
2765 .enable_reg = 0xf00c,
2766 .enable_mask = BIT(0),
2767 .hw.init = &(struct clk_init_data){
2768 .name = "gcc_usb30_prim_master_clk",
2769 .parent_names = (const char *[]){
2770 "gcc_usb30_prim_master_clk_src",
2773 .flags = CLK_SET_RATE_PARENT,
2774 .ops = &clk_branch2_ops,
2779 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2781 .halt_check = BRANCH_HALT,
2783 .enable_reg = 0xf014,
2784 .enable_mask = BIT(0),
2785 .hw.init = &(struct clk_init_data){
2786 .name = "gcc_usb30_prim_mock_utmi_clk",
2787 .parent_names = (const char *[]){
2788 "gcc_usb30_prim_mock_utmi_clk_src",
2791 .flags = CLK_SET_RATE_PARENT,
2792 .ops = &clk_branch2_ops,
2797 static struct clk_branch gcc_usb30_prim_sleep_clk = {
2799 .halt_check = BRANCH_HALT,
2801 .enable_reg = 0xf010,
2802 .enable_mask = BIT(0),
2803 .hw.init = &(struct clk_init_data){
2804 .name = "gcc_usb30_prim_sleep_clk",
2805 .ops = &clk_branch2_ops,
2810 static struct clk_branch gcc_usb30_sec_master_clk = {
2811 .halt_reg = 0x1000c,
2812 .halt_check = BRANCH_HALT,
2814 .enable_reg = 0x1000c,
2815 .enable_mask = BIT(0),
2816 .hw.init = &(struct clk_init_data){
2817 .name = "gcc_usb30_sec_master_clk",
2818 .parent_names = (const char *[]){
2819 "gcc_usb30_sec_master_clk_src",
2822 .flags = CLK_SET_RATE_PARENT,
2823 .ops = &clk_branch2_ops,
2828 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
2829 .halt_reg = 0x10014,
2830 .halt_check = BRANCH_HALT,
2832 .enable_reg = 0x10014,
2833 .enable_mask = BIT(0),
2834 .hw.init = &(struct clk_init_data){
2835 .name = "gcc_usb30_sec_mock_utmi_clk",
2836 .parent_names = (const char *[]){
2837 "gcc_usb30_sec_mock_utmi_clk_src",
2840 .flags = CLK_SET_RATE_PARENT,
2841 .ops = &clk_branch2_ops,
2846 static struct clk_branch gcc_usb30_sec_sleep_clk = {
2847 .halt_reg = 0x10010,
2848 .halt_check = BRANCH_HALT,
2850 .enable_reg = 0x10010,
2851 .enable_mask = BIT(0),
2852 .hw.init = &(struct clk_init_data){
2853 .name = "gcc_usb30_sec_sleep_clk",
2854 .ops = &clk_branch2_ops,
2859 static struct clk_branch gcc_usb3_prim_clkref_clk = {
2860 .halt_reg = 0x8c008,
2861 .halt_check = BRANCH_HALT,
2863 .enable_reg = 0x8c008,
2864 .enable_mask = BIT(0),
2865 .hw.init = &(struct clk_init_data){
2866 .name = "gcc_usb3_prim_clkref_clk",
2867 .ops = &clk_branch2_ops,
2872 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2874 .halt_check = BRANCH_HALT,
2876 .enable_reg = 0xf04c,
2877 .enable_mask = BIT(0),
2878 .hw.init = &(struct clk_init_data){
2879 .name = "gcc_usb3_prim_phy_aux_clk",
2880 .parent_names = (const char *[]){
2881 "gcc_usb3_prim_phy_aux_clk_src",
2884 .flags = CLK_SET_RATE_PARENT,
2885 .ops = &clk_branch2_ops,
2890 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2892 .halt_check = BRANCH_HALT,
2894 .enable_reg = 0xf050,
2895 .enable_mask = BIT(0),
2896 .hw.init = &(struct clk_init_data){
2897 .name = "gcc_usb3_prim_phy_com_aux_clk",
2898 .parent_names = (const char *[]){
2899 "gcc_usb3_prim_phy_aux_clk_src",
2902 .flags = CLK_SET_RATE_PARENT,
2903 .ops = &clk_branch2_ops,
2908 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2909 .halt_check = BRANCH_HALT_SKIP,
2911 .enable_reg = 0xf054,
2912 .enable_mask = BIT(0),
2913 .hw.init = &(struct clk_init_data){
2914 .name = "gcc_usb3_prim_phy_pipe_clk",
2915 .ops = &clk_branch2_ops,
2920 static struct clk_branch gcc_usb3_sec_clkref_clk = {
2921 .halt_reg = 0x8c028,
2922 .halt_check = BRANCH_HALT,
2924 .enable_reg = 0x8c028,
2925 .enable_mask = BIT(0),
2926 .hw.init = &(struct clk_init_data){
2927 .name = "gcc_usb3_sec_clkref_clk",
2928 .ops = &clk_branch2_ops,
2933 static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
2934 .halt_reg = 0x1004c,
2935 .halt_check = BRANCH_HALT,
2937 .enable_reg = 0x1004c,
2938 .enable_mask = BIT(0),
2939 .hw.init = &(struct clk_init_data){
2940 .name = "gcc_usb3_sec_phy_aux_clk",
2941 .parent_names = (const char *[]){
2942 "gcc_usb3_sec_phy_aux_clk_src",
2945 .flags = CLK_SET_RATE_PARENT,
2946 .ops = &clk_branch2_ops,
2951 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
2952 .halt_reg = 0x10050,
2953 .halt_check = BRANCH_HALT,
2955 .enable_reg = 0x10050,
2956 .enable_mask = BIT(0),
2957 .hw.init = &(struct clk_init_data){
2958 .name = "gcc_usb3_sec_phy_com_aux_clk",
2959 .parent_names = (const char *[]){
2960 "gcc_usb3_sec_phy_aux_clk_src",
2963 .flags = CLK_SET_RATE_PARENT,
2964 .ops = &clk_branch2_ops,
2969 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
2970 .halt_check = BRANCH_HALT_SKIP,
2972 .enable_reg = 0x10054,
2973 .enable_mask = BIT(0),
2974 .hw.init = &(struct clk_init_data){
2975 .name = "gcc_usb3_sec_phy_pipe_clk",
2976 .ops = &clk_branch2_ops,
2981 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2982 .halt_reg = 0x6a004,
2983 .halt_check = BRANCH_HALT,
2984 .hwcg_reg = 0x6a004,
2987 .enable_reg = 0x6a004,
2988 .enable_mask = BIT(0),
2989 .hw.init = &(struct clk_init_data){
2990 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2991 .ops = &clk_branch2_ops,
2996 static struct clk_branch gcc_vdda_vs_clk = {
2997 .halt_reg = 0x7a00c,
2998 .halt_check = BRANCH_HALT,
3000 .enable_reg = 0x7a00c,
3001 .enable_mask = BIT(0),
3002 .hw.init = &(struct clk_init_data){
3003 .name = "gcc_vdda_vs_clk",
3004 .parent_names = (const char *[]){
3005 "gcc_vsensor_clk_src",
3008 .flags = CLK_SET_RATE_PARENT,
3009 .ops = &clk_branch2_ops,
3014 static struct clk_branch gcc_vddcx_vs_clk = {
3015 .halt_reg = 0x7a004,
3016 .halt_check = BRANCH_HALT,
3018 .enable_reg = 0x7a004,
3019 .enable_mask = BIT(0),
3020 .hw.init = &(struct clk_init_data){
3021 .name = "gcc_vddcx_vs_clk",
3022 .parent_names = (const char *[]){
3023 "gcc_vsensor_clk_src",
3026 .flags = CLK_SET_RATE_PARENT,
3027 .ops = &clk_branch2_ops,
3032 static struct clk_branch gcc_vddmx_vs_clk = {
3033 .halt_reg = 0x7a008,
3034 .halt_check = BRANCH_HALT,
3036 .enable_reg = 0x7a008,
3037 .enable_mask = BIT(0),
3038 .hw.init = &(struct clk_init_data){
3039 .name = "gcc_vddmx_vs_clk",
3040 .parent_names = (const char *[]){
3041 "gcc_vsensor_clk_src",
3044 .flags = CLK_SET_RATE_PARENT,
3045 .ops = &clk_branch2_ops,
3050 static struct clk_branch gcc_video_ahb_clk = {
3052 .halt_check = BRANCH_HALT,
3056 .enable_reg = 0xb004,
3057 .enable_mask = BIT(0),
3058 .hw.init = &(struct clk_init_data){
3059 .name = "gcc_video_ahb_clk",
3060 .flags = CLK_IS_CRITICAL,
3061 .ops = &clk_branch2_ops,
3066 static struct clk_branch gcc_video_axi_clk = {
3068 .halt_check = BRANCH_VOTED,
3070 .enable_reg = 0xb01c,
3071 .enable_mask = BIT(0),
3072 .hw.init = &(struct clk_init_data){
3073 .name = "gcc_video_axi_clk",
3074 .ops = &clk_branch2_ops,
3079 static struct clk_branch gcc_video_xo_clk = {
3081 .halt_check = BRANCH_HALT,
3083 .enable_reg = 0xb028,
3084 .enable_mask = BIT(0),
3085 .hw.init = &(struct clk_init_data){
3086 .name = "gcc_video_xo_clk",
3087 .flags = CLK_IS_CRITICAL,
3088 .ops = &clk_branch2_ops,
3093 static struct clk_branch gcc_vs_ctrl_ahb_clk = {
3094 .halt_reg = 0x7a014,
3095 .halt_check = BRANCH_HALT,
3096 .hwcg_reg = 0x7a014,
3099 .enable_reg = 0x7a014,
3100 .enable_mask = BIT(0),
3101 .hw.init = &(struct clk_init_data){
3102 .name = "gcc_vs_ctrl_ahb_clk",
3103 .ops = &clk_branch2_ops,
3108 static struct clk_branch gcc_vs_ctrl_clk = {
3109 .halt_reg = 0x7a010,
3110 .halt_check = BRANCH_HALT,
3112 .enable_reg = 0x7a010,
3113 .enable_mask = BIT(0),
3114 .hw.init = &(struct clk_init_data){
3115 .name = "gcc_vs_ctrl_clk",
3116 .parent_names = (const char *[]){
3117 "gcc_vs_ctrl_clk_src",
3120 .flags = CLK_SET_RATE_PARENT,
3121 .ops = &clk_branch2_ops,
3126 static struct clk_branch gcc_cpuss_dvm_bus_clk = {
3127 .halt_reg = 0x48190,
3128 .halt_check = BRANCH_HALT,
3130 .enable_reg = 0x48190,
3131 .enable_mask = BIT(0),
3132 .hw.init = &(struct clk_init_data){
3133 .name = "gcc_cpuss_dvm_bus_clk",
3134 .flags = CLK_IS_CRITICAL,
3135 .ops = &clk_branch2_ops,
3140 static struct clk_branch gcc_cpuss_gnoc_clk = {
3141 .halt_reg = 0x48004,
3142 .halt_check = BRANCH_HALT_VOTED,
3143 .hwcg_reg = 0x48004,
3146 .enable_reg = 0x52004,
3147 .enable_mask = BIT(22),
3148 .hw.init = &(struct clk_init_data){
3149 .name = "gcc_cpuss_gnoc_clk",
3150 .flags = CLK_IS_CRITICAL,
3151 .ops = &clk_branch2_ops,
3156 /* TODO: Remove after DTS updated to protect these */
3157 #ifdef CONFIG_SDM_LPASSCC_845
3158 static struct clk_branch gcc_lpass_q6_axi_clk = {
3159 .halt_reg = 0x47000,
3160 .halt_check = BRANCH_HALT,
3162 .enable_reg = 0x47000,
3163 .enable_mask = BIT(0),
3164 .hw.init = &(struct clk_init_data){
3165 .name = "gcc_lpass_q6_axi_clk",
3166 .flags = CLK_IS_CRITICAL,
3167 .ops = &clk_branch2_ops,
3172 static struct clk_branch gcc_lpass_sway_clk = {
3173 .halt_reg = 0x47008,
3174 .halt_check = BRANCH_HALT,
3176 .enable_reg = 0x47008,
3177 .enable_mask = BIT(0),
3178 .hw.init = &(struct clk_init_data){
3179 .name = "gcc_lpass_sway_clk",
3180 .flags = CLK_IS_CRITICAL,
3181 .ops = &clk_branch2_ops,
3187 static struct gdsc pcie_0_gdsc = {
3190 .name = "pcie_0_gdsc",
3192 .pwrsts = PWRSTS_OFF_ON,
3193 .flags = POLL_CFG_GDSCR,
3196 static struct gdsc pcie_1_gdsc = {
3199 .name = "pcie_1_gdsc",
3201 .pwrsts = PWRSTS_OFF_ON,
3202 .flags = POLL_CFG_GDSCR,
3205 static struct gdsc ufs_card_gdsc = {
3208 .name = "ufs_card_gdsc",
3210 .pwrsts = PWRSTS_OFF_ON,
3211 .flags = POLL_CFG_GDSCR,
3214 static struct gdsc ufs_phy_gdsc = {
3217 .name = "ufs_phy_gdsc",
3219 .pwrsts = PWRSTS_OFF_ON,
3220 .flags = POLL_CFG_GDSCR,
3223 static struct gdsc usb30_prim_gdsc = {
3226 .name = "usb30_prim_gdsc",
3228 .pwrsts = PWRSTS_OFF_ON,
3229 .flags = POLL_CFG_GDSCR,
3232 static struct gdsc usb30_sec_gdsc = {
3235 .name = "usb30_sec_gdsc",
3237 .pwrsts = PWRSTS_OFF_ON,
3238 .flags = POLL_CFG_GDSCR,
3241 static struct gdsc hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc = {
3244 .name = "hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc",
3246 .pwrsts = PWRSTS_OFF_ON,
3249 static struct gdsc hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc = {
3252 .name = "hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc",
3254 .pwrsts = PWRSTS_OFF_ON,
3257 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu1_gdsc = {
3260 .name = "hlos1_vote_aggre_noc_mmu_tbu1_gdsc",
3262 .pwrsts = PWRSTS_OFF_ON,
3265 static struct gdsc hlos1_vote_aggre_noc_mmu_tbu2_gdsc = {
3268 .name = "hlos1_vote_aggre_noc_mmu_tbu2_gdsc",
3270 .pwrsts = PWRSTS_OFF_ON,
3273 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
3276 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
3278 .pwrsts = PWRSTS_OFF_ON,
3281 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
3284 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
3286 .pwrsts = PWRSTS_OFF_ON,
3289 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
3292 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
3294 .pwrsts = PWRSTS_OFF_ON,
3297 static struct clk_regmap *gcc_sdm845_clocks[] = {
3298 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3299 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
3300 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3301 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3302 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3303 [GCC_APC_VS_CLK] = &gcc_apc_vs_clk.clkr,
3304 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3305 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3306 [GCC_CAMERA_AXI_CLK] = &gcc_camera_axi_clk.clkr,
3307 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3308 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
3309 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
3310 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
3311 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3312 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3313 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
3314 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3315 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
3316 [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr,
3317 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3318 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3319 [GCC_DISP_AXI_CLK] = &gcc_disp_axi_clk.clkr,
3320 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
3321 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
3322 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3323 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3324 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3325 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3326 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3327 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3328 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3329 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3330 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3331 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3332 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
3333 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3334 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3335 [GCC_GPU_VS_CLK] = &gcc_gpu_vs_clk.clkr,
3336 [GCC_MSS_AXIS2_CLK] = &gcc_mss_axis2_clk.clkr,
3337 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3338 [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
3339 [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
3340 [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
3341 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
3342 [GCC_MSS_VS_CLK] = &gcc_mss_vs_clk.clkr,
3343 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3344 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3345 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3346 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
3347 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3348 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3349 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3350 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3351 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3352 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3353 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3354 [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
3355 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3356 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3357 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3358 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3359 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3360 [GCC_PCIE_PHY_REFGEN_CLK] = &gcc_pcie_phy_refgen_clk.clkr,
3361 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
3362 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3363 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3364 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3365 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3366 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3367 [GCC_QMIP_CAMERA_AHB_CLK] = &gcc_qmip_camera_ahb_clk.clkr,
3368 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3369 [GCC_QMIP_VIDEO_AHB_CLK] = &gcc_qmip_video_ahb_clk.clkr,
3370 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3371 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3372 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3373 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3374 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3375 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3376 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3377 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3378 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3379 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3380 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3381 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3382 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3383 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3384 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3385 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3386 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3387 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3388 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3389 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3390 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3391 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3392 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3393 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3394 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3395 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3396 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3397 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3398 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3399 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3400 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
3401 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
3402 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3403 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3404 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3405 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3406 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3407 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3408 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3409 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3410 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3411 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3412 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3413 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3414 [GCC_TSIF_INACTIVITY_TIMERS_CLK] =
3415 &gcc_tsif_inactivity_timers_clk.clkr,
3416 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3417 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
3418 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
3419 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
3420 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
3421 [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
3422 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
3423 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
3424 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
3425 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
3426 [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
3427 [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
3428 [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
3429 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
3430 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
3431 &gcc_ufs_card_unipro_core_clk_src.clkr,
3432 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
3433 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3434 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3435 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3436 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3437 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3438 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3439 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3440 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3441 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3442 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3443 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3444 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3445 &gcc_ufs_phy_unipro_core_clk_src.clkr,
3446 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3447 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3448 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3449 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3450 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3451 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3452 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3453 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3454 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3455 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
3456 &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3457 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3458 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
3459 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3460 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3461 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3462 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3463 [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
3464 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3465 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3466 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3467 [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
3468 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3469 [GCC_VDDA_VS_CLK] = &gcc_vdda_vs_clk.clkr,
3470 [GCC_VDDCX_VS_CLK] = &gcc_vddcx_vs_clk.clkr,
3471 [GCC_VDDMX_VS_CLK] = &gcc_vddmx_vs_clk.clkr,
3472 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
3473 [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
3474 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3475 [GCC_VS_CTRL_AHB_CLK] = &gcc_vs_ctrl_ahb_clk.clkr,
3476 [GCC_VS_CTRL_CLK] = &gcc_vs_ctrl_clk.clkr,
3477 [GCC_VS_CTRL_CLK_SRC] = &gcc_vs_ctrl_clk_src.clkr,
3478 [GCC_VSENSOR_CLK_SRC] = &gcc_vsensor_clk_src.clkr,
3479 [GPLL0] = &gpll0.clkr,
3480 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
3481 [GPLL4] = &gpll4.clkr,
3482 [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
3483 [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3484 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3485 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3486 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3487 #ifdef CONFIG_SDM_LPASSCC_845
3488 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
3489 [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
3493 static const struct qcom_reset_map gcc_sdm845_resets[] = {
3494 [GCC_MMSS_BCR] = { 0xb000 },
3495 [GCC_PCIE_0_BCR] = { 0x6b000 },
3496 [GCC_PCIE_1_BCR] = { 0x8d000 },
3497 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3498 [GCC_PDM_BCR] = { 0x33000 },
3499 [GCC_PRNG_BCR] = { 0x34000 },
3500 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3501 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3502 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3503 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3504 [GCC_SDCC2_BCR] = { 0x14000 },
3505 [GCC_SDCC4_BCR] = { 0x16000 },
3506 [GCC_TSIF_BCR] = { 0x36000 },
3507 [GCC_UFS_CARD_BCR] = { 0x75000 },
3508 [GCC_UFS_PHY_BCR] = { 0x77000 },
3509 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3510 [GCC_USB30_SEC_BCR] = { 0x10000 },
3511 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3512 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3513 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3514 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3515 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3516 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3517 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3518 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3519 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3522 static struct gdsc *gcc_sdm845_gdscs[] = {
3523 [PCIE_0_GDSC] = &pcie_0_gdsc,
3524 [PCIE_1_GDSC] = &pcie_1_gdsc,
3525 [UFS_CARD_GDSC] = &ufs_card_gdsc,
3526 [UFS_PHY_GDSC] = &ufs_phy_gdsc,
3527 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3528 [USB30_SEC_GDSC] = &usb30_sec_gdsc,
3529 [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] =
3530 &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc,
3531 [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] =
3532 &hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc,
3533 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] =
3534 &hlos1_vote_aggre_noc_mmu_tbu1_gdsc,
3535 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] =
3536 &hlos1_vote_aggre_noc_mmu_tbu2_gdsc,
3537 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
3538 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
3539 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] =
3540 &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
3541 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
3544 static const struct regmap_config gcc_sdm845_regmap_config = {
3548 .max_register = 0x182090,
3552 static const struct qcom_cc_desc gcc_sdm845_desc = {
3553 .config = &gcc_sdm845_regmap_config,
3554 .clks = gcc_sdm845_clocks,
3555 .num_clks = ARRAY_SIZE(gcc_sdm845_clocks),
3556 .resets = gcc_sdm845_resets,
3557 .num_resets = ARRAY_SIZE(gcc_sdm845_resets),
3558 .gdscs = gcc_sdm845_gdscs,
3559 .num_gdscs = ARRAY_SIZE(gcc_sdm845_gdscs),
3562 static const struct of_device_id gcc_sdm845_match_table[] = {
3563 { .compatible = "qcom,gcc-sdm845" },
3566 MODULE_DEVICE_TABLE(of, gcc_sdm845_match_table);
3568 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3569 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk),
3570 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk),
3571 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk),
3572 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk),
3573 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk),
3574 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk),
3575 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk),
3576 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk),
3577 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk),
3578 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk),
3579 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk),
3580 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk),
3581 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk),
3582 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk),
3583 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk),
3584 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk),
3587 static int gcc_sdm845_probe(struct platform_device *pdev)
3589 struct regmap *regmap;
3592 regmap = qcom_cc_map(pdev, &gcc_sdm845_desc);
3594 return PTR_ERR(regmap);
3596 /* Disable the GPLL0 active input to MMSS and GPU via MISC registers */
3597 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
3598 regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
3600 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
3601 ARRAY_SIZE(gcc_dfs_clocks));
3605 return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);
3608 static struct platform_driver gcc_sdm845_driver = {
3609 .probe = gcc_sdm845_probe,
3611 .name = "gcc-sdm845",
3612 .of_match_table = gcc_sdm845_match_table,
3616 static int __init gcc_sdm845_init(void)
3618 return platform_driver_register(&gcc_sdm845_driver);
3620 subsys_initcall(gcc_sdm845_init);
3622 static void __exit gcc_sdm845_exit(void)
3624 platform_driver_unregister(&gcc_sdm845_driver);
3626 module_exit(gcc_sdm845_exit);
3628 MODULE_DESCRIPTION("QTI GCC SDM845 Driver");
3629 MODULE_LICENSE("GPL v2");
3630 MODULE_ALIAS("platform:gcc-sdm845");