1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2018, Craig Tatlor.
7 #include <linux/kernel.h>
8 #include <linux/bitops.h>
10 #include <linux/platform_device.h>
11 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/clk-provider.h>
15 #include <linux/regmap.h>
16 #include <linux/reset-controller.h>
18 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
21 #include "clk-regmap.h"
22 #include "clk-alpha-pll.h"
24 #include "clk-branch.h"
28 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
40 static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div[] = {
43 { P_GPLL0_EARLY_DIV, 6 },
46 static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div[] = {
52 static const struct parent_map gcc_parent_map_xo_gpll0[] = {
57 static const char * const gcc_parent_names_xo_gpll0[] = {
62 static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = {
66 { P_GPLL0_EARLY_DIV, 6 },
69 static const char * const gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div[] = {
76 static const struct parent_map gcc_parent_map_xo_sleep_clk[] = {
81 static const char * const gcc_parent_names_xo_sleep_clk[] = {
86 static const struct parent_map gcc_parent_map_xo_gpll4[] = {
91 static const char * const gcc_parent_names_xo_gpll4[] = {
96 static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
99 { P_GPLL0_EARLY_DIV, 3 },
102 { P_GPLL1_EARLY_DIV, 6 },
105 static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
114 static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = {
118 { P_GPLL0_EARLY_DIV, 6 },
121 static const char * const gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div[] = {
128 static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = {
131 { P_GPLL0_EARLY_DIV, 2 },
135 static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4[] = {
142 static struct clk_fixed_factor xo = {
145 .hw.init = &(struct clk_init_data){
147 .parent_names = (const char *[]){ "xo_board" },
149 .ops = &clk_fixed_factor_ops,
153 static struct clk_alpha_pll gpll0_early = {
155 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
157 .enable_reg = 0x52000,
158 .enable_mask = BIT(0),
159 .hw.init = &(struct clk_init_data){
160 .name = "gpll0_early",
161 .parent_names = (const char *[]){ "xo" },
163 .ops = &clk_alpha_pll_ops,
168 static struct clk_fixed_factor gpll0_early_div = {
171 .hw.init = &(struct clk_init_data){
172 .name = "gpll0_early_div",
173 .parent_names = (const char *[]){ "gpll0_early" },
175 .ops = &clk_fixed_factor_ops,
179 static struct clk_alpha_pll_postdiv gpll0 = {
181 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
182 .clkr.hw.init = &(struct clk_init_data){
184 .parent_names = (const char *[]){ "gpll0_early" },
186 .ops = &clk_alpha_pll_postdiv_ops,
190 static struct clk_alpha_pll gpll1_early = {
192 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
194 .enable_reg = 0x52000,
195 .enable_mask = BIT(1),
196 .hw.init = &(struct clk_init_data){
197 .name = "gpll1_early",
198 .parent_names = (const char *[]){ "xo" },
200 .ops = &clk_alpha_pll_ops,
205 static struct clk_fixed_factor gpll1_early_div = {
208 .hw.init = &(struct clk_init_data){
209 .name = "gpll1_early_div",
210 .parent_names = (const char *[]){ "gpll1_early" },
212 .ops = &clk_fixed_factor_ops,
216 static struct clk_alpha_pll_postdiv gpll1 = {
218 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
219 .clkr.hw.init = &(struct clk_init_data){
221 .parent_names = (const char *[]){ "gpll1_early" },
223 .ops = &clk_alpha_pll_postdiv_ops,
227 static struct clk_alpha_pll gpll4_early = {
229 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
231 .enable_reg = 0x52000,
232 .enable_mask = BIT(4),
233 .hw.init = &(struct clk_init_data){
234 .name = "gpll4_early",
235 .parent_names = (const char *[]){ "xo" },
237 .ops = &clk_alpha_pll_ops,
242 static struct clk_alpha_pll_postdiv gpll4 = {
244 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
245 .clkr.hw.init = &(struct clk_init_data)
248 .parent_names = (const char *[]) { "gpll4_early" },
250 .ops = &clk_alpha_pll_postdiv_ops,
254 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
255 F(19200000, P_XO, 1, 0, 0),
256 F(50000000, P_GPLL0, 12, 0, 0),
260 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
264 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
265 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
266 .clkr.hw.init = &(struct clk_init_data){
267 .name = "blsp1_qup1_i2c_apps_clk_src",
268 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
270 .ops = &clk_rcg2_ops,
274 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
275 F(960000, P_XO, 10, 1, 2),
276 F(4800000, P_XO, 4, 0, 0),
277 F(9600000, P_XO, 2, 0, 0),
278 F(15000000, P_GPLL0, 10, 1, 4),
279 F(19200000, P_XO, 1, 0, 0),
280 F(25000000, P_GPLL0, 12, 1, 2),
281 F(50000000, P_GPLL0, 12, 0, 0),
285 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
289 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
290 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
291 .clkr.hw.init = &(struct clk_init_data){
292 .name = "blsp1_qup1_spi_apps_clk_src",
293 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
295 .ops = &clk_rcg2_ops,
299 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
303 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
304 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
305 .clkr.hw.init = &(struct clk_init_data){
306 .name = "blsp1_qup2_i2c_apps_clk_src",
307 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
309 .ops = &clk_rcg2_ops,
313 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
317 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
318 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
319 .clkr.hw.init = &(struct clk_init_data){
320 .name = "blsp1_qup2_spi_apps_clk_src",
321 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
323 .ops = &clk_rcg2_ops,
327 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
331 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
332 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
333 .clkr.hw.init = &(struct clk_init_data){
334 .name = "blsp1_qup3_i2c_apps_clk_src",
335 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
337 .ops = &clk_rcg2_ops,
341 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
345 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
346 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
347 .clkr.hw.init = &(struct clk_init_data){
348 .name = "blsp1_qup3_spi_apps_clk_src",
349 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
351 .ops = &clk_rcg2_ops,
355 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
359 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
360 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
361 .clkr.hw.init = &(struct clk_init_data){
362 .name = "blsp1_qup4_i2c_apps_clk_src",
363 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
365 .ops = &clk_rcg2_ops,
369 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
373 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
374 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
375 .clkr.hw.init = &(struct clk_init_data){
376 .name = "blsp1_qup4_spi_apps_clk_src",
377 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
379 .ops = &clk_rcg2_ops,
383 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
384 F(3686400, P_GPLL0, 1, 96, 15625),
385 F(7372800, P_GPLL0, 1, 192, 15625),
386 F(14745600, P_GPLL0, 1, 384, 15625),
387 F(16000000, P_GPLL0, 5, 2, 15),
388 F(19200000, P_XO, 1, 0, 0),
389 F(24000000, P_GPLL0, 5, 1, 5),
390 F(32000000, P_GPLL0, 1, 4, 75),
391 F(40000000, P_GPLL0, 15, 0, 0),
392 F(46400000, P_GPLL0, 1, 29, 375),
393 F(48000000, P_GPLL0, 12.5, 0, 0),
394 F(51200000, P_GPLL0, 1, 32, 375),
395 F(56000000, P_GPLL0, 1, 7, 75),
396 F(58982400, P_GPLL0, 1, 1536, 15625),
397 F(60000000, P_GPLL0, 10, 0, 0),
398 F(63157895, P_GPLL0, 9.5, 0, 0),
402 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
406 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
407 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
408 .clkr.hw.init = &(struct clk_init_data){
409 .name = "blsp1_uart1_apps_clk_src",
410 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
412 .ops = &clk_rcg2_ops,
416 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
420 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
421 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
422 .clkr.hw.init = &(struct clk_init_data){
423 .name = "blsp1_uart2_apps_clk_src",
424 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
426 .ops = &clk_rcg2_ops,
430 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
434 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
435 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
436 .clkr.hw.init = &(struct clk_init_data){
437 .name = "blsp2_qup1_i2c_apps_clk_src",
438 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
440 .ops = &clk_rcg2_ops,
444 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
448 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
449 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
450 .clkr.hw.init = &(struct clk_init_data){
451 .name = "blsp2_qup1_spi_apps_clk_src",
452 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
454 .ops = &clk_rcg2_ops,
458 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
462 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
463 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
464 .clkr.hw.init = &(struct clk_init_data){
465 .name = "blsp2_qup2_i2c_apps_clk_src",
466 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
468 .ops = &clk_rcg2_ops,
472 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
476 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
477 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
478 .clkr.hw.init = &(struct clk_init_data){
479 .name = "blsp2_qup2_spi_apps_clk_src",
480 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
482 .ops = &clk_rcg2_ops,
486 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
490 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
491 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
492 .clkr.hw.init = &(struct clk_init_data){
493 .name = "blsp2_qup3_i2c_apps_clk_src",
494 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
496 .ops = &clk_rcg2_ops,
500 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
504 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
505 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
506 .clkr.hw.init = &(struct clk_init_data){
507 .name = "blsp2_qup3_spi_apps_clk_src",
508 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
510 .ops = &clk_rcg2_ops,
514 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
518 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
519 .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
520 .clkr.hw.init = &(struct clk_init_data){
521 .name = "blsp2_qup4_i2c_apps_clk_src",
522 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
524 .ops = &clk_rcg2_ops,
528 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
532 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
533 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
534 .clkr.hw.init = &(struct clk_init_data){
535 .name = "blsp2_qup4_spi_apps_clk_src",
536 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
538 .ops = &clk_rcg2_ops,
542 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
546 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
547 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
548 .clkr.hw.init = &(struct clk_init_data){
549 .name = "blsp2_uart1_apps_clk_src",
550 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
552 .ops = &clk_rcg2_ops,
556 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
560 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
561 .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
562 .clkr.hw.init = &(struct clk_init_data){
563 .name = "blsp2_uart2_apps_clk_src",
564 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
566 .ops = &clk_rcg2_ops,
570 static const struct freq_tbl ftbl_gp1_clk_src[] = {
571 F(19200000, P_XO, 1, 0, 0),
572 F(100000000, P_GPLL0, 6, 0, 0),
573 F(200000000, P_GPLL0, 3, 0, 0),
577 static struct clk_rcg2 gp1_clk_src = {
581 .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
582 .freq_tbl = ftbl_gp1_clk_src,
583 .clkr.hw.init = &(struct clk_init_data){
584 .name = "gp1_clk_src",
585 .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
587 .ops = &clk_rcg2_ops,
591 static struct clk_rcg2 gp2_clk_src = {
595 .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
596 .freq_tbl = ftbl_gp1_clk_src,
597 .clkr.hw.init = &(struct clk_init_data){
598 .name = "gp2_clk_src",
599 .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
601 .ops = &clk_rcg2_ops,
605 static struct clk_rcg2 gp3_clk_src = {
609 .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
610 .freq_tbl = ftbl_gp1_clk_src,
611 .clkr.hw.init = &(struct clk_init_data){
612 .name = "gp3_clk_src",
613 .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
615 .ops = &clk_rcg2_ops,
619 static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {
620 F(300000000, P_GPLL0, 2, 0, 0),
621 F(600000000, P_GPLL0, 1, 0, 0),
625 static struct clk_rcg2 hmss_gpll0_clk_src = {
629 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
630 .freq_tbl = ftbl_hmss_gpll0_clk_src,
631 .clkr.hw.init = &(struct clk_init_data){
632 .name = "hmss_gpll0_clk_src",
633 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
635 .ops = &clk_rcg2_ops,
639 static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] = {
640 F(384000000, P_GPLL4, 4, 0, 0),
641 F(768000000, P_GPLL4, 2, 0, 0),
642 F(1536000000, P_GPLL4, 1, 0, 0),
646 static struct clk_rcg2 hmss_gpll4_clk_src = {
650 .parent_map = gcc_parent_map_xo_gpll4,
651 .freq_tbl = ftbl_hmss_gpll4_clk_src,
652 .clkr.hw.init = &(struct clk_init_data){
653 .name = "hmss_gpll4_clk_src",
654 .parent_names = gcc_parent_names_xo_gpll4,
656 .ops = &clk_rcg2_ops,
660 static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
661 F(19200000, P_XO, 1, 0, 0),
665 static struct clk_rcg2 hmss_rbcpr_clk_src = {
669 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
670 .freq_tbl = ftbl_hmss_rbcpr_clk_src,
671 .clkr.hw.init = &(struct clk_init_data){
672 .name = "hmss_rbcpr_clk_src",
673 .parent_names = gcc_parent_names_xo_gpll0,
675 .ops = &clk_rcg2_ops,
679 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
680 F(60000000, P_GPLL0, 10, 0, 0),
684 static struct clk_rcg2 pdm2_clk_src = {
688 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
689 .freq_tbl = ftbl_pdm2_clk_src,
690 .clkr.hw.init = &(struct clk_init_data){
691 .name = "pdm2_clk_src",
692 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
694 .ops = &clk_rcg2_ops,
698 static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
699 F(19200000, P_XO, 1, 0, 0),
700 F(80200000, P_GPLL1_EARLY_DIV, 5, 0, 0),
701 F(160400000, P_GPLL1, 5, 0, 0),
702 F(267333333, P_GPLL1, 3, 0, 0),
706 static struct clk_rcg2 qspi_ser_clk_src = {
710 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
711 .freq_tbl = ftbl_qspi_ser_clk_src,
712 .clkr.hw.init = &(struct clk_init_data){
713 .name = "qspi_ser_clk_src",
714 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
716 .ops = &clk_rcg2_ops,
720 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
721 F(144000, P_XO, 16, 3, 25),
722 F(400000, P_XO, 12, 1, 4),
723 F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
724 F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
725 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
726 F(100000000, P_GPLL0, 6, 0, 0),
727 F(192000000, P_GPLL4, 8, 0, 0),
728 F(384000000, P_GPLL4, 4, 0, 0),
732 static struct clk_rcg2 sdcc1_apps_clk_src = {
736 .parent_map = gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div,
737 .freq_tbl = ftbl_sdcc1_apps_clk_src,
738 .clkr.hw.init = &(struct clk_init_data){
739 .name = "sdcc1_apps_clk_src",
740 .parent_names = gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div,
742 .ops = &clk_rcg2_ops,
746 static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
747 F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
748 F(150000000, P_GPLL0, 4, 0, 0),
749 F(200000000, P_GPLL0, 3, 0, 0),
750 F(300000000, P_GPLL0, 2, 0, 0),
754 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
758 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
759 .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
760 .clkr.hw.init = &(struct clk_init_data){
761 .name = "sdcc1_ice_core_clk_src",
762 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
764 .ops = &clk_rcg2_ops,
768 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
769 F(144000, P_XO, 16, 3, 25),
770 F(400000, P_XO, 12, 1, 4),
771 F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
772 F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
773 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
774 F(100000000, P_GPLL0, 6, 0, 0),
775 F(192000000, P_GPLL4, 8, 0, 0),
776 F(200000000, P_GPLL0, 3, 0, 0),
780 static struct clk_rcg2 sdcc2_apps_clk_src = {
784 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4,
785 .freq_tbl = ftbl_sdcc2_apps_clk_src,
786 .clkr.hw.init = &(struct clk_init_data){
787 .name = "sdcc2_apps_clk_src",
788 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4,
790 .ops = &clk_rcg2_ops,
794 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
795 F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
796 F(100000000, P_GPLL0, 6, 0, 0),
797 F(150000000, P_GPLL0, 4, 0, 0),
798 F(200000000, P_GPLL0, 3, 0, 0),
799 F(240000000, P_GPLL0, 2.5, 0, 0),
803 static struct clk_rcg2 ufs_axi_clk_src = {
807 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
808 .freq_tbl = ftbl_ufs_axi_clk_src,
809 .clkr.hw.init = &(struct clk_init_data){
810 .name = "ufs_axi_clk_src",
811 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
813 .ops = &clk_rcg2_ops,
817 static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
818 F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
819 F(150000000, P_GPLL0, 4, 0, 0),
820 F(300000000, P_GPLL0, 2, 0, 0),
824 static struct clk_rcg2 ufs_ice_core_clk_src = {
828 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
829 .freq_tbl = ftbl_ufs_ice_core_clk_src,
830 .clkr.hw.init = &(struct clk_init_data){
831 .name = "ufs_ice_core_clk_src",
832 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
834 .ops = &clk_rcg2_ops,
838 static struct clk_rcg2 ufs_phy_aux_clk_src = {
842 .parent_map = gcc_parent_map_xo_sleep_clk,
843 .freq_tbl = ftbl_hmss_rbcpr_clk_src,
844 .clkr.hw.init = &(struct clk_init_data){
845 .name = "ufs_phy_aux_clk_src",
846 .parent_names = gcc_parent_names_xo_sleep_clk,
848 .ops = &clk_rcg2_ops,
852 static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = {
853 F(37500000, P_GPLL0_EARLY_DIV, 8, 0, 0),
854 F(75000000, P_GPLL0, 8, 0, 0),
855 F(150000000, P_GPLL0, 4, 0, 0),
859 static struct clk_rcg2 ufs_unipro_core_clk_src = {
863 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
864 .freq_tbl = ftbl_ufs_unipro_core_clk_src,
865 .clkr.hw.init = &(struct clk_init_data){
866 .name = "ufs_unipro_core_clk_src",
867 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
869 .ops = &clk_rcg2_ops,
873 static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
874 F(19200000, P_XO, 1, 0, 0),
875 F(60000000, P_GPLL0, 10, 0, 0),
876 F(120000000, P_GPLL0, 5, 0, 0),
880 static struct clk_rcg2 usb20_master_clk_src = {
884 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
885 .freq_tbl = ftbl_usb20_master_clk_src,
886 .clkr.hw.init = &(struct clk_init_data){
887 .name = "usb20_master_clk_src",
888 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
890 .ops = &clk_rcg2_ops,
894 static const struct freq_tbl ftbl_usb20_mock_utmi_clk_src[] = {
895 F(19200000, P_XO, 1, 0, 0),
896 F(60000000, P_GPLL0, 10, 0, 0),
900 static struct clk_rcg2 usb20_mock_utmi_clk_src = {
904 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
905 .freq_tbl = ftbl_usb20_mock_utmi_clk_src,
906 .clkr.hw.init = &(struct clk_init_data){
907 .name = "usb20_mock_utmi_clk_src",
908 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
910 .ops = &clk_rcg2_ops,
914 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
915 F(19200000, P_XO, 1, 0, 0),
916 F(66666667, P_GPLL0_EARLY_DIV, 4.5, 0, 0),
917 F(120000000, P_GPLL0, 5, 0, 0),
918 F(133333333, P_GPLL0, 4.5, 0, 0),
919 F(150000000, P_GPLL0, 4, 0, 0),
920 F(200000000, P_GPLL0, 3, 0, 0),
921 F(240000000, P_GPLL0, 2.5, 0, 0),
925 static struct clk_rcg2 usb30_master_clk_src = {
929 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
930 .freq_tbl = ftbl_usb30_master_clk_src,
931 .clkr.hw.init = &(struct clk_init_data){
932 .name = "usb30_master_clk_src",
933 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
935 .ops = &clk_rcg2_ops,
939 static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
940 F(19200000, P_XO, 1, 0, 0),
941 F(40000000, P_GPLL0_EARLY_DIV, 7.5, 0, 0),
942 F(60000000, P_GPLL0, 10, 0, 0),
946 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
950 .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
951 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
952 .clkr.hw.init = &(struct clk_init_data){
953 .name = "usb30_mock_utmi_clk_src",
954 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
956 .ops = &clk_rcg2_ops,
960 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
961 F(1200000, P_XO, 16, 0, 0),
962 F(19200000, P_XO, 1, 0, 0),
966 static struct clk_rcg2 usb3_phy_aux_clk_src = {
970 .parent_map = gcc_parent_map_xo_sleep_clk,
971 .freq_tbl = ftbl_usb3_phy_aux_clk_src,
972 .clkr.hw.init = &(struct clk_init_data){
973 .name = "usb3_phy_aux_clk_src",
974 .parent_names = gcc_parent_names_xo_sleep_clk,
976 .ops = &clk_rcg2_ops,
980 static struct clk_branch gcc_aggre2_ufs_axi_clk = {
982 .halt_check = BRANCH_HALT,
984 .enable_reg = 0x75034,
985 .enable_mask = BIT(0),
986 .hw.init = &(struct clk_init_data){
987 .name = "gcc_aggre2_ufs_axi_clk",
988 .parent_names = (const char *[]){
992 .ops = &clk_branch2_ops,
997 static struct clk_branch gcc_aggre2_usb3_axi_clk = {
999 .halt_check = BRANCH_HALT,
1001 .enable_reg = 0xf03c,
1002 .enable_mask = BIT(0),
1003 .hw.init = &(struct clk_init_data){
1004 .name = "gcc_aggre2_usb3_axi_clk",
1005 .parent_names = (const char *[]){
1006 "usb30_master_clk_src",
1009 .ops = &clk_branch2_ops,
1014 static struct clk_branch gcc_bimc_gfx_clk = {
1015 .halt_reg = 0x7106c,
1016 .halt_check = BRANCH_VOTED,
1018 .enable_reg = 0x7106c,
1019 .enable_mask = BIT(0),
1020 .hw.init = &(struct clk_init_data){
1021 .name = "gcc_bimc_gfx_clk",
1022 .ops = &clk_branch2_ops,
1027 static struct clk_branch gcc_bimc_hmss_axi_clk = {
1028 .halt_reg = 0x48004,
1029 .halt_check = BRANCH_HALT_VOTED,
1031 .enable_reg = 0x52004,
1032 .enable_mask = BIT(22),
1033 .hw.init = &(struct clk_init_data){
1034 .name = "gcc_bimc_hmss_axi_clk",
1035 .ops = &clk_branch2_ops,
1040 static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
1041 .halt_reg = 0x4401c,
1042 .halt_check = BRANCH_HALT,
1044 .enable_reg = 0x4401c,
1045 .enable_mask = BIT(0),
1046 .hw.init = &(struct clk_init_data){
1047 .name = "gcc_bimc_mss_q6_axi_clk",
1048 .ops = &clk_branch2_ops,
1053 static struct clk_branch gcc_blsp1_ahb_clk = {
1054 .halt_reg = 0x17004,
1055 .halt_check = BRANCH_HALT_VOTED,
1057 .enable_reg = 0x52004,
1058 .enable_mask = BIT(17),
1059 .hw.init = &(struct clk_init_data){
1060 .name = "gcc_blsp1_ahb_clk",
1061 .ops = &clk_branch2_ops,
1066 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1067 .halt_reg = 0x19008,
1068 .halt_check = BRANCH_HALT,
1070 .enable_reg = 0x19008,
1071 .enable_mask = BIT(0),
1072 .hw.init = &(struct clk_init_data){
1073 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1074 .parent_names = (const char *[]){
1075 "blsp1_qup1_i2c_apps_clk_src",
1078 .flags = CLK_SET_RATE_PARENT,
1079 .ops = &clk_branch2_ops,
1084 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1085 .halt_reg = 0x19004,
1086 .halt_check = BRANCH_HALT,
1088 .enable_reg = 0x19004,
1089 .enable_mask = BIT(0),
1090 .hw.init = &(struct clk_init_data){
1091 .name = "gcc_blsp1_qup1_spi_apps_clk",
1092 .parent_names = (const char *[]){
1093 "blsp1_qup1_spi_apps_clk_src",
1096 .flags = CLK_SET_RATE_PARENT,
1097 .ops = &clk_branch2_ops,
1102 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1103 .halt_reg = 0x1b008,
1104 .halt_check = BRANCH_HALT,
1106 .enable_reg = 0x1b008,
1107 .enable_mask = BIT(0),
1108 .hw.init = &(struct clk_init_data){
1109 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1110 .parent_names = (const char *[]){
1111 "blsp1_qup2_i2c_apps_clk_src",
1114 .flags = CLK_SET_RATE_PARENT,
1115 .ops = &clk_branch2_ops,
1120 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1121 .halt_reg = 0x1b004,
1122 .halt_check = BRANCH_HALT,
1124 .enable_reg = 0x1b004,
1125 .enable_mask = BIT(0),
1126 .hw.init = &(struct clk_init_data){
1127 .name = "gcc_blsp1_qup2_spi_apps_clk",
1128 .parent_names = (const char *[]){
1129 "blsp1_qup2_spi_apps_clk_src",
1132 .flags = CLK_SET_RATE_PARENT,
1133 .ops = &clk_branch2_ops,
1138 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1139 .halt_reg = 0x1d008,
1140 .halt_check = BRANCH_HALT,
1142 .enable_reg = 0x1d008,
1143 .enable_mask = BIT(0),
1144 .hw.init = &(struct clk_init_data){
1145 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1146 .parent_names = (const char *[]){
1147 "blsp1_qup3_i2c_apps_clk_src",
1150 .flags = CLK_SET_RATE_PARENT,
1151 .ops = &clk_branch2_ops,
1156 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1157 .halt_reg = 0x1d004,
1158 .halt_check = BRANCH_HALT,
1160 .enable_reg = 0x1d004,
1161 .enable_mask = BIT(0),
1162 .hw.init = &(struct clk_init_data){
1163 .name = "gcc_blsp1_qup3_spi_apps_clk",
1164 .parent_names = (const char *[]){
1165 "blsp1_qup3_spi_apps_clk_src",
1168 .flags = CLK_SET_RATE_PARENT,
1169 .ops = &clk_branch2_ops,
1174 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1175 .halt_reg = 0x1f008,
1176 .halt_check = BRANCH_HALT,
1178 .enable_reg = 0x1f008,
1179 .enable_mask = BIT(0),
1180 .hw.init = &(struct clk_init_data){
1181 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1182 .parent_names = (const char *[]){
1183 "blsp1_qup4_i2c_apps_clk_src",
1186 .flags = CLK_SET_RATE_PARENT,
1187 .ops = &clk_branch2_ops,
1192 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1193 .halt_reg = 0x1f004,
1194 .halt_check = BRANCH_HALT,
1196 .enable_reg = 0x1f004,
1197 .enable_mask = BIT(0),
1198 .hw.init = &(struct clk_init_data){
1199 .name = "gcc_blsp1_qup4_spi_apps_clk",
1200 .parent_names = (const char *[]){
1201 "blsp1_qup4_spi_apps_clk_src",
1204 .flags = CLK_SET_RATE_PARENT,
1205 .ops = &clk_branch2_ops,
1210 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1211 .halt_reg = 0x1a004,
1212 .halt_check = BRANCH_HALT,
1214 .enable_reg = 0x1a004,
1215 .enable_mask = BIT(0),
1216 .hw.init = &(struct clk_init_data){
1217 .name = "gcc_blsp1_uart1_apps_clk",
1218 .parent_names = (const char *[]){
1219 "blsp1_uart1_apps_clk_src",
1222 .flags = CLK_SET_RATE_PARENT,
1223 .ops = &clk_branch2_ops,
1228 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1229 .halt_reg = 0x1c004,
1230 .halt_check = BRANCH_HALT,
1232 .enable_reg = 0x1c004,
1233 .enable_mask = BIT(0),
1234 .hw.init = &(struct clk_init_data){
1235 .name = "gcc_blsp1_uart2_apps_clk",
1236 .parent_names = (const char *[]){
1237 "blsp1_uart2_apps_clk_src",
1240 .flags = CLK_SET_RATE_PARENT,
1241 .ops = &clk_branch2_ops,
1246 static struct clk_branch gcc_blsp2_ahb_clk = {
1247 .halt_reg = 0x25004,
1248 .halt_check = BRANCH_HALT_VOTED,
1250 .enable_reg = 0x52004,
1251 .enable_mask = BIT(15),
1252 .hw.init = &(struct clk_init_data){
1253 .name = "gcc_blsp2_ahb_clk",
1254 .ops = &clk_branch2_ops,
1259 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1260 .halt_reg = 0x26008,
1261 .halt_check = BRANCH_HALT,
1263 .enable_reg = 0x26008,
1264 .enable_mask = BIT(0),
1265 .hw.init = &(struct clk_init_data){
1266 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1267 .parent_names = (const char *[]){
1268 "blsp2_qup1_i2c_apps_clk_src",
1271 .flags = CLK_SET_RATE_PARENT,
1272 .ops = &clk_branch2_ops,
1277 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1278 .halt_reg = 0x26004,
1279 .halt_check = BRANCH_HALT,
1281 .enable_reg = 0x26004,
1282 .enable_mask = BIT(0),
1283 .hw.init = &(struct clk_init_data){
1284 .name = "gcc_blsp2_qup1_spi_apps_clk",
1285 .parent_names = (const char *[]){
1286 "blsp2_qup1_spi_apps_clk_src",
1289 .flags = CLK_SET_RATE_PARENT,
1290 .ops = &clk_branch2_ops,
1295 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1296 .halt_reg = 0x28008,
1297 .halt_check = BRANCH_HALT,
1299 .enable_reg = 0x28008,
1300 .enable_mask = BIT(0),
1301 .hw.init = &(struct clk_init_data){
1302 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1303 .parent_names = (const char *[]){
1304 "blsp2_qup2_i2c_apps_clk_src",
1307 .flags = CLK_SET_RATE_PARENT,
1308 .ops = &clk_branch2_ops,
1313 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1314 .halt_reg = 0x28004,
1315 .halt_check = BRANCH_HALT,
1317 .enable_reg = 0x28004,
1318 .enable_mask = BIT(0),
1319 .hw.init = &(struct clk_init_data){
1320 .name = "gcc_blsp2_qup2_spi_apps_clk",
1321 .parent_names = (const char *[]){
1322 "blsp2_qup2_spi_apps_clk_src",
1325 .flags = CLK_SET_RATE_PARENT,
1326 .ops = &clk_branch2_ops,
1331 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1332 .halt_reg = 0x2a008,
1333 .halt_check = BRANCH_HALT,
1335 .enable_reg = 0x2a008,
1336 .enable_mask = BIT(0),
1337 .hw.init = &(struct clk_init_data){
1338 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1339 .parent_names = (const char *[]){
1340 "blsp2_qup3_i2c_apps_clk_src",
1343 .flags = CLK_SET_RATE_PARENT,
1344 .ops = &clk_branch2_ops,
1349 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1350 .halt_reg = 0x2a004,
1351 .halt_check = BRANCH_HALT,
1353 .enable_reg = 0x2a004,
1354 .enable_mask = BIT(0),
1355 .hw.init = &(struct clk_init_data){
1356 .name = "gcc_blsp2_qup3_spi_apps_clk",
1357 .parent_names = (const char *[]){
1358 "blsp2_qup3_spi_apps_clk_src",
1361 .flags = CLK_SET_RATE_PARENT,
1362 .ops = &clk_branch2_ops,
1367 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1368 .halt_reg = 0x2c008,
1369 .halt_check = BRANCH_HALT,
1371 .enable_reg = 0x2c008,
1372 .enable_mask = BIT(0),
1373 .hw.init = &(struct clk_init_data){
1374 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1375 .parent_names = (const char *[]){
1376 "blsp2_qup4_i2c_apps_clk_src",
1379 .flags = CLK_SET_RATE_PARENT,
1380 .ops = &clk_branch2_ops,
1385 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1386 .halt_reg = 0x2c004,
1387 .halt_check = BRANCH_HALT,
1389 .enable_reg = 0x2c004,
1390 .enable_mask = BIT(0),
1391 .hw.init = &(struct clk_init_data){
1392 .name = "gcc_blsp2_qup4_spi_apps_clk",
1393 .parent_names = (const char *[]){
1394 "blsp2_qup4_spi_apps_clk_src",
1397 .flags = CLK_SET_RATE_PARENT,
1398 .ops = &clk_branch2_ops,
1403 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1404 .halt_reg = 0x27004,
1405 .halt_check = BRANCH_HALT,
1407 .enable_reg = 0x27004,
1408 .enable_mask = BIT(0),
1409 .hw.init = &(struct clk_init_data){
1410 .name = "gcc_blsp2_uart1_apps_clk",
1411 .parent_names = (const char *[]){
1412 "blsp2_uart1_apps_clk_src",
1415 .flags = CLK_SET_RATE_PARENT,
1416 .ops = &clk_branch2_ops,
1421 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1422 .halt_reg = 0x29004,
1423 .halt_check = BRANCH_HALT,
1425 .enable_reg = 0x29004,
1426 .enable_mask = BIT(0),
1427 .hw.init = &(struct clk_init_data){
1428 .name = "gcc_blsp2_uart2_apps_clk",
1429 .parent_names = (const char *[]){
1430 "blsp2_uart2_apps_clk_src",
1433 .flags = CLK_SET_RATE_PARENT,
1434 .ops = &clk_branch2_ops,
1439 static struct clk_branch gcc_boot_rom_ahb_clk = {
1440 .halt_reg = 0x38004,
1441 .halt_check = BRANCH_HALT_VOTED,
1443 .enable_reg = 0x52004,
1444 .enable_mask = BIT(10),
1445 .hw.init = &(struct clk_init_data){
1446 .name = "gcc_boot_rom_ahb_clk",
1447 .ops = &clk_branch2_ops,
1452 static struct clk_branch gcc_cfg_noc_usb2_axi_clk = {
1454 .halt_check = BRANCH_HALT,
1456 .enable_reg = 0x5058,
1457 .enable_mask = BIT(0),
1458 .hw.init = &(struct clk_init_data){
1459 .name = "gcc_cfg_noc_usb2_axi_clk",
1460 .parent_names = (const char *[]){
1461 "usb20_master_clk_src",
1464 .ops = &clk_branch2_ops,
1469 static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
1471 .halt_check = BRANCH_HALT,
1473 .enable_reg = 0x5018,
1474 .enable_mask = BIT(0),
1475 .hw.init = &(struct clk_init_data){
1476 .name = "gcc_cfg_noc_usb3_axi_clk",
1477 .parent_names = (const char *[]){
1478 "usb30_master_clk_src",
1481 .ops = &clk_branch2_ops,
1486 static struct clk_branch gcc_dcc_ahb_clk = {
1487 .halt_reg = 0x84004,
1489 .enable_reg = 0x84004,
1490 .enable_mask = BIT(0),
1491 .hw.init = &(struct clk_init_data){
1492 .name = "gcc_dcc_ahb_clk",
1493 .ops = &clk_branch2_ops,
1498 static struct clk_branch gcc_gp1_clk = {
1499 .halt_reg = 0x64000,
1500 .halt_check = BRANCH_HALT,
1502 .enable_reg = 0x64000,
1503 .enable_mask = BIT(0),
1504 .hw.init = &(struct clk_init_data){
1505 .name = "gcc_gp1_clk",
1506 .parent_names = (const char *[]){
1510 .flags = CLK_SET_RATE_PARENT,
1511 .ops = &clk_branch2_ops,
1516 static struct clk_branch gcc_gp2_clk = {
1517 .halt_reg = 0x65000,
1518 .halt_check = BRANCH_HALT,
1520 .enable_reg = 0x65000,
1521 .enable_mask = BIT(0),
1522 .hw.init = &(struct clk_init_data){
1523 .name = "gcc_gp2_clk",
1524 .parent_names = (const char *[]){
1528 .flags = CLK_SET_RATE_PARENT,
1529 .ops = &clk_branch2_ops,
1534 static struct clk_branch gcc_gp3_clk = {
1535 .halt_reg = 0x66000,
1536 .halt_check = BRANCH_HALT,
1538 .enable_reg = 0x66000,
1539 .enable_mask = BIT(0),
1540 .hw.init = &(struct clk_init_data){
1541 .name = "gcc_gp3_clk",
1542 .parent_names = (const char *[]){
1546 .flags = CLK_SET_RATE_PARENT,
1547 .ops = &clk_branch2_ops,
1552 static struct clk_branch gcc_gpu_bimc_gfx_clk = {
1553 .halt_reg = 0x71010,
1554 .halt_check = BRANCH_VOTED,
1556 .enable_reg = 0x71010,
1557 .enable_mask = BIT(0),
1558 .hw.init = &(struct clk_init_data){
1559 .name = "gcc_gpu_bimc_gfx_clk",
1560 .ops = &clk_branch2_ops,
1565 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1566 .halt_reg = 0x71004,
1567 .halt_check = BRANCH_VOTED,
1569 .enable_reg = 0x71004,
1570 .enable_mask = BIT(0),
1571 .hw.init = &(struct clk_init_data){
1572 .name = "gcc_gpu_cfg_ahb_clk",
1573 .ops = &clk_branch2_ops,
1578 static struct clk_branch gcc_gpu_gpll0_clk = {
1579 .halt_reg = 0x5200c,
1580 .halt_check = BRANCH_HALT_DELAY,
1582 .enable_reg = 0x5200c,
1583 .enable_mask = BIT(4),
1584 .hw.init = &(struct clk_init_data){
1585 .name = "gcc_gpu_gpll0_clk",
1586 .parent_names = (const char *[]){
1590 .ops = &clk_branch2_ops,
1595 static struct clk_branch gcc_gpu_gpll0_div_clk = {
1596 .halt_reg = 0x5200c,
1597 .halt_check = BRANCH_HALT_DELAY,
1599 .enable_reg = 0x5200c,
1600 .enable_mask = BIT(3),
1601 .hw.init = &(struct clk_init_data){
1602 .name = "gcc_gpu_gpll0_div_clk",
1603 .parent_names = (const char *[]){
1607 .ops = &clk_branch2_ops,
1612 static struct clk_branch gcc_hmss_dvm_bus_clk = {
1613 .halt_reg = 0x4808c,
1614 .halt_check = BRANCH_HALT,
1616 .enable_reg = 0x4808c,
1617 .enable_mask = BIT(0),
1618 .hw.init = &(struct clk_init_data){
1619 .name = "gcc_hmss_dvm_bus_clk",
1620 .ops = &clk_branch2_ops,
1621 .flags = CLK_IGNORE_UNUSED,
1626 static struct clk_branch gcc_hmss_rbcpr_clk = {
1627 .halt_reg = 0x48008,
1628 .halt_check = BRANCH_HALT,
1630 .enable_reg = 0x48008,
1631 .enable_mask = BIT(0),
1632 .hw.init = &(struct clk_init_data){
1633 .name = "gcc_hmss_rbcpr_clk",
1634 .parent_names = (const char *[]){
1635 "hmss_rbcpr_clk_src",
1638 .flags = CLK_SET_RATE_PARENT,
1639 .ops = &clk_branch2_ops,
1644 static struct clk_branch gcc_mmss_gpll0_clk = {
1645 .halt_reg = 0x5200c,
1646 .halt_check = BRANCH_HALT_DELAY,
1648 .enable_reg = 0x5200c,
1649 .enable_mask = BIT(1),
1650 .hw.init = &(struct clk_init_data){
1651 .name = "gcc_mmss_gpll0_clk",
1652 .parent_names = (const char *[]){
1656 .ops = &clk_branch2_ops,
1661 static struct clk_branch gcc_mmss_gpll0_div_clk = {
1662 .halt_reg = 0x5200c,
1663 .halt_check = BRANCH_HALT_DELAY,
1665 .enable_reg = 0x5200c,
1666 .enable_mask = BIT(0),
1667 .hw.init = &(struct clk_init_data){
1668 .name = "gcc_mmss_gpll0_div_clk",
1669 .parent_names = (const char *[]){
1673 .ops = &clk_branch2_ops,
1678 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
1680 .halt_check = BRANCH_HALT,
1682 .enable_reg = 0x9004,
1683 .enable_mask = BIT(0),
1684 .hw.init = &(struct clk_init_data){
1685 .name = "gcc_mmss_noc_cfg_ahb_clk",
1686 .ops = &clk_branch2_ops,
1691 static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
1693 .halt_check = BRANCH_HALT,
1695 .enable_reg = 0x9000,
1696 .enable_mask = BIT(0),
1697 .hw.init = &(struct clk_init_data){
1698 .name = "gcc_mmss_sys_noc_axi_clk",
1699 .ops = &clk_branch2_ops,
1704 static struct clk_branch gcc_mss_cfg_ahb_clk = {
1705 .halt_reg = 0x8a000,
1707 .enable_reg = 0x8a000,
1708 .enable_mask = BIT(0),
1709 .hw.init = &(struct clk_init_data){
1710 .name = "gcc_mss_cfg_ahb_clk",
1711 .ops = &clk_branch2_ops,
1716 static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
1717 .halt_reg = 0x8a004,
1719 .enable_reg = 0x8a004,
1720 .enable_mask = BIT(0),
1721 .hw.init = &(struct clk_init_data){
1722 .name = "gcc_mss_mnoc_bimc_axi_clk",
1723 .ops = &clk_branch2_ops,
1728 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
1729 .halt_reg = 0x8a040,
1731 .enable_reg = 0x8a040,
1732 .enable_mask = BIT(0),
1733 .hw.init = &(struct clk_init_data){
1734 .name = "gcc_mss_q6_bimc_axi_clk",
1735 .ops = &clk_branch2_ops,
1740 static struct clk_branch gcc_mss_snoc_axi_clk = {
1741 .halt_reg = 0x8a03c,
1743 .enable_reg = 0x8a03c,
1744 .enable_mask = BIT(0),
1745 .hw.init = &(struct clk_init_data){
1746 .name = "gcc_mss_snoc_axi_clk",
1747 .ops = &clk_branch2_ops,
1752 static struct clk_branch gcc_pdm2_clk = {
1753 .halt_reg = 0x3300c,
1754 .halt_check = BRANCH_HALT,
1756 .enable_reg = 0x3300c,
1757 .enable_mask = BIT(0),
1758 .hw.init = &(struct clk_init_data){
1759 .name = "gcc_pdm2_clk",
1760 .parent_names = (const char *[]){
1764 .flags = CLK_SET_RATE_PARENT,
1765 .ops = &clk_branch2_ops,
1770 static struct clk_branch gcc_pdm_ahb_clk = {
1771 .halt_reg = 0x33004,
1772 .halt_check = BRANCH_HALT,
1774 .enable_reg = 0x33004,
1775 .enable_mask = BIT(0),
1776 .hw.init = &(struct clk_init_data){
1777 .name = "gcc_pdm_ahb_clk",
1778 .ops = &clk_branch2_ops,
1783 static struct clk_branch gcc_prng_ahb_clk = {
1784 .halt_reg = 0x34004,
1785 .halt_check = BRANCH_HALT_VOTED,
1787 .enable_reg = 0x52004,
1788 .enable_mask = BIT(13),
1789 .hw.init = &(struct clk_init_data){
1790 .name = "gcc_prng_ahb_clk",
1791 .ops = &clk_branch2_ops,
1796 static struct clk_branch gcc_qspi_ahb_clk = {
1797 .halt_reg = 0x4d004,
1798 .halt_check = BRANCH_HALT,
1800 .enable_reg = 0x4d004,
1801 .enable_mask = BIT(0),
1802 .hw.init = &(struct clk_init_data){
1803 .name = "gcc_qspi_ahb_clk",
1804 .ops = &clk_branch2_ops,
1809 static struct clk_branch gcc_qspi_ser_clk = {
1810 .halt_reg = 0x4d008,
1811 .halt_check = BRANCH_HALT,
1813 .enable_reg = 0x4d008,
1814 .enable_mask = BIT(0),
1815 .hw.init = &(struct clk_init_data){
1816 .name = "gcc_qspi_ser_clk",
1817 .parent_names = (const char *[]){
1821 .flags = CLK_SET_RATE_PARENT,
1822 .ops = &clk_branch2_ops,
1827 static struct clk_branch gcc_rx0_usb2_clkref_clk = {
1828 .halt_reg = 0x88018,
1829 .halt_check = BRANCH_HALT_VOTED,
1831 .enable_reg = 0x88018,
1832 .enable_mask = BIT(0),
1833 .hw.init = &(struct clk_init_data){
1834 .name = "gcc_rx0_usb2_clkref_clk",
1835 .ops = &clk_branch2_ops,
1840 static struct clk_branch gcc_rx1_usb2_clkref_clk = {
1841 .halt_reg = 0x88014,
1842 .halt_check = BRANCH_HALT_VOTED,
1844 .enable_reg = 0x88014,
1845 .enable_mask = BIT(0),
1846 .hw.init = &(struct clk_init_data){
1847 .name = "gcc_rx1_usb2_clkref_clk",
1848 .ops = &clk_branch2_ops,
1853 static struct clk_branch gcc_sdcc1_ahb_clk = {
1854 .halt_reg = 0x16008,
1855 .halt_check = BRANCH_HALT,
1857 .enable_reg = 0x16008,
1858 .enable_mask = BIT(0),
1859 .hw.init = &(struct clk_init_data){
1860 .name = "gcc_sdcc1_ahb_clk",
1861 .ops = &clk_branch2_ops,
1866 static struct clk_branch gcc_sdcc1_apps_clk = {
1867 .halt_reg = 0x16004,
1868 .halt_check = BRANCH_HALT,
1870 .enable_reg = 0x16004,
1871 .enable_mask = BIT(0),
1872 .hw.init = &(struct clk_init_data){
1873 .name = "gcc_sdcc1_apps_clk",
1874 .parent_names = (const char *[]){
1875 "sdcc1_apps_clk_src",
1878 .flags = CLK_SET_RATE_PARENT,
1879 .ops = &clk_branch2_ops,
1884 static struct clk_branch gcc_sdcc1_ice_core_clk = {
1885 .halt_reg = 0x1600c,
1886 .halt_check = BRANCH_HALT,
1888 .enable_reg = 0x1600c,
1889 .enable_mask = BIT(0),
1890 .hw.init = &(struct clk_init_data){
1891 .name = "gcc_sdcc1_ice_core_clk",
1892 .parent_names = (const char *[]){
1893 "sdcc1_ice_core_clk_src",
1896 .flags = CLK_SET_RATE_PARENT,
1897 .ops = &clk_branch2_ops,
1902 static struct clk_branch gcc_sdcc2_ahb_clk = {
1903 .halt_reg = 0x14008,
1904 .halt_check = BRANCH_HALT,
1906 .enable_reg = 0x14008,
1907 .enable_mask = BIT(0),
1908 .hw.init = &(struct clk_init_data){
1909 .name = "gcc_sdcc2_ahb_clk",
1910 .ops = &clk_branch2_ops,
1915 static struct clk_branch gcc_sdcc2_apps_clk = {
1916 .halt_reg = 0x14004,
1917 .halt_check = BRANCH_HALT,
1919 .enable_reg = 0x14004,
1920 .enable_mask = BIT(0),
1921 .hw.init = &(struct clk_init_data){
1922 .name = "gcc_sdcc2_apps_clk",
1923 .parent_names = (const char *[]){
1924 "sdcc2_apps_clk_src",
1927 .flags = CLK_SET_RATE_PARENT,
1928 .ops = &clk_branch2_ops,
1933 static struct clk_branch gcc_ufs_ahb_clk = {
1934 .halt_reg = 0x7500c,
1935 .halt_check = BRANCH_HALT,
1937 .enable_reg = 0x7500c,
1938 .enable_mask = BIT(0),
1939 .hw.init = &(struct clk_init_data){
1940 .name = "gcc_ufs_ahb_clk",
1941 .ops = &clk_branch2_ops,
1946 static struct clk_branch gcc_ufs_axi_clk = {
1947 .halt_reg = 0x75008,
1948 .halt_check = BRANCH_HALT,
1950 .enable_reg = 0x75008,
1951 .enable_mask = BIT(0),
1952 .hw.init = &(struct clk_init_data){
1953 .name = "gcc_ufs_axi_clk",
1954 .parent_names = (const char *[]){
1958 .flags = CLK_SET_RATE_PARENT,
1959 .ops = &clk_branch2_ops,
1964 static struct clk_branch gcc_ufs_clkref_clk = {
1965 .halt_reg = 0x88008,
1966 .halt_check = BRANCH_HALT,
1968 .enable_reg = 0x88008,
1969 .enable_mask = BIT(0),
1970 .hw.init = &(struct clk_init_data){
1971 .name = "gcc_ufs_clkref_clk",
1972 .ops = &clk_branch2_ops,
1977 static struct clk_branch gcc_ufs_ice_core_clk = {
1978 .halt_reg = 0x7600c,
1979 .halt_check = BRANCH_HALT,
1981 .enable_reg = 0x7600c,
1982 .enable_mask = BIT(0),
1983 .hw.init = &(struct clk_init_data){
1984 .name = "gcc_ufs_ice_core_clk",
1985 .parent_names = (const char *[]){
1986 "ufs_ice_core_clk_src",
1989 .flags = CLK_SET_RATE_PARENT,
1990 .ops = &clk_branch2_ops,
1995 static struct clk_branch gcc_ufs_phy_aux_clk = {
1996 .halt_reg = 0x76040,
1997 .halt_check = BRANCH_HALT,
1999 .enable_reg = 0x76040,
2000 .enable_mask = BIT(0),
2001 .hw.init = &(struct clk_init_data){
2002 .name = "gcc_ufs_phy_aux_clk",
2003 .parent_names = (const char *[]){
2004 "ufs_phy_aux_clk_src",
2007 .flags = CLK_SET_RATE_PARENT,
2008 .ops = &clk_branch2_ops,
2013 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2014 .halt_reg = 0x75014,
2015 .halt_check = BRANCH_HALT_SKIP,
2017 .enable_reg = 0x75014,
2018 .enable_mask = BIT(0),
2019 .hw.init = &(struct clk_init_data){
2020 .name = "gcc_ufs_rx_symbol_0_clk",
2021 .ops = &clk_branch2_ops,
2026 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2027 .halt_reg = 0x7605c,
2028 .halt_check = BRANCH_HALT_SKIP,
2030 .enable_reg = 0x7605c,
2031 .enable_mask = BIT(0),
2032 .hw.init = &(struct clk_init_data){
2033 .name = "gcc_ufs_rx_symbol_1_clk",
2034 .ops = &clk_branch2_ops,
2039 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2040 .halt_reg = 0x75010,
2041 .halt_check = BRANCH_HALT_SKIP,
2043 .enable_reg = 0x75010,
2044 .enable_mask = BIT(0),
2045 .hw.init = &(struct clk_init_data){
2046 .name = "gcc_ufs_tx_symbol_0_clk",
2047 .ops = &clk_branch2_ops,
2052 static struct clk_branch gcc_ufs_unipro_core_clk = {
2053 .halt_reg = 0x76008,
2054 .halt_check = BRANCH_HALT,
2056 .enable_reg = 0x76008,
2057 .enable_mask = BIT(0),
2058 .hw.init = &(struct clk_init_data){
2059 .name = "gcc_ufs_unipro_core_clk",
2060 .parent_names = (const char *[]){
2061 "ufs_unipro_core_clk_src",
2063 .flags = CLK_SET_RATE_PARENT,
2065 .ops = &clk_branch2_ops,
2070 static struct clk_branch gcc_usb20_master_clk = {
2071 .halt_reg = 0x2f004,
2072 .halt_check = BRANCH_HALT,
2074 .enable_reg = 0x2f004,
2075 .enable_mask = BIT(0),
2076 .hw.init = &(struct clk_init_data){
2077 .name = "gcc_usb20_master_clk",
2078 .parent_names = (const char *[]){
2079 "usb20_master_clk_src"
2081 .flags = CLK_SET_RATE_PARENT,
2083 .ops = &clk_branch2_ops,
2088 static struct clk_branch gcc_usb20_mock_utmi_clk = {
2089 .halt_reg = 0x2f00c,
2090 .halt_check = BRANCH_HALT,
2092 .enable_reg = 0x2f00c,
2093 .enable_mask = BIT(0),
2094 .hw.init = &(struct clk_init_data){
2095 .name = "gcc_usb20_mock_utmi_clk",
2096 .parent_names = (const char *[]){
2097 "usb20_mock_utmi_clk_src",
2100 .flags = CLK_SET_RATE_PARENT,
2101 .ops = &clk_branch2_ops,
2106 static struct clk_branch gcc_usb20_sleep_clk = {
2107 .halt_reg = 0x2f008,
2108 .halt_check = BRANCH_HALT,
2110 .enable_reg = 0x2f008,
2111 .enable_mask = BIT(0),
2112 .hw.init = &(struct clk_init_data){
2113 .name = "gcc_usb20_sleep_clk",
2114 .ops = &clk_branch2_ops,
2119 static struct clk_branch gcc_usb30_master_clk = {
2121 .halt_check = BRANCH_HALT,
2123 .enable_reg = 0xf008,
2124 .enable_mask = BIT(0),
2125 .hw.init = &(struct clk_init_data){
2126 .name = "gcc_usb30_master_clk",
2127 .parent_names = (const char *[]){
2128 "usb30_master_clk_src",
2131 .flags = CLK_SET_RATE_PARENT,
2132 .ops = &clk_branch2_ops,
2137 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2139 .halt_check = BRANCH_HALT,
2141 .enable_reg = 0xf010,
2142 .enable_mask = BIT(0),
2143 .hw.init = &(struct clk_init_data){
2144 .name = "gcc_usb30_mock_utmi_clk",
2145 .parent_names = (const char *[]){
2146 "usb30_mock_utmi_clk_src",
2149 .flags = CLK_SET_RATE_PARENT,
2150 .ops = &clk_branch2_ops,
2155 static struct clk_branch gcc_usb30_sleep_clk = {
2157 .halt_check = BRANCH_HALT,
2159 .enable_reg = 0xf00c,
2160 .enable_mask = BIT(0),
2161 .hw.init = &(struct clk_init_data){
2162 .name = "gcc_usb30_sleep_clk",
2163 .ops = &clk_branch2_ops,
2168 static struct clk_branch gcc_usb3_clkref_clk = {
2169 .halt_reg = 0x8800c,
2170 .halt_check = BRANCH_HALT,
2172 .enable_reg = 0x8800c,
2173 .enable_mask = BIT(0),
2174 .hw.init = &(struct clk_init_data){
2175 .name = "gcc_usb3_clkref_clk",
2176 .ops = &clk_branch2_ops,
2181 static struct clk_branch gcc_usb3_phy_aux_clk = {
2182 .halt_reg = 0x50000,
2183 .halt_check = BRANCH_HALT,
2185 .enable_reg = 0x50000,
2186 .enable_mask = BIT(0),
2187 .hw.init = &(struct clk_init_data){
2188 .name = "gcc_usb3_phy_aux_clk",
2189 .parent_names = (const char *[]){
2190 "usb3_phy_aux_clk_src",
2193 .flags = CLK_SET_RATE_PARENT,
2194 .ops = &clk_branch2_ops,
2199 static struct clk_branch gcc_usb3_phy_pipe_clk = {
2200 .halt_reg = 0x50004,
2201 .halt_check = BRANCH_HALT_DELAY,
2203 .enable_reg = 0x50004,
2204 .enable_mask = BIT(0),
2205 .hw.init = &(struct clk_init_data){
2206 .name = "gcc_usb3_phy_pipe_clk",
2207 .ops = &clk_branch2_ops,
2212 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2213 .halt_reg = 0x6a004,
2214 .halt_check = BRANCH_HALT,
2216 .enable_reg = 0x6a004,
2217 .enable_mask = BIT(0),
2218 .hw.init = &(struct clk_init_data){
2219 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2220 .ops = &clk_branch2_ops,
2225 static struct gdsc ufs_gdsc = {
2231 .pwrsts = PWRSTS_OFF_ON,
2235 static struct gdsc usb_30_gdsc = {
2239 .name = "usb_30_gdsc",
2241 .pwrsts = PWRSTS_OFF_ON,
2245 static struct gdsc pcie_0_gdsc = {
2249 .name = "pcie_0_gdsc",
2251 .pwrsts = PWRSTS_OFF_ON,
2255 static struct clk_hw *gcc_sdm660_hws[] = {
2257 &gpll0_early_div.hw,
2258 &gpll1_early_div.hw,
2261 static struct clk_regmap *gcc_sdm660_clocks[] = {
2262 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2263 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2264 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2265 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2266 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2267 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2268 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2269 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2270 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2271 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2272 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2273 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2274 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2275 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2276 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2277 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2278 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2279 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2280 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2281 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2282 [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
2283 [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
2284 [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
2285 [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
2286 [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
2287 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2288 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2289 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2290 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2291 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2292 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2293 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2294 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2295 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2296 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2297 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2298 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2299 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2300 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2301 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2302 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2303 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2304 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2305 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2306 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2307 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2308 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2309 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2310 [GCC_CFG_NOC_USB2_AXI_CLK] = &gcc_cfg_noc_usb2_axi_clk.clkr,
2311 [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
2312 [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
2313 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2314 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2315 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2316 [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
2317 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
2318 [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
2319 [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
2320 [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,
2321 [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
2322 [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
2323 [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
2324 [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
2325 [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
2326 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2327 [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
2328 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
2329 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
2330 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2331 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2332 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2333 [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
2334 [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
2335 [GCC_RX0_USB2_CLKREF_CLK] = &gcc_rx0_usb2_clkref_clk.clkr,
2336 [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
2337 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2338 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2339 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2340 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2341 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2342 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
2343 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2344 [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
2345 [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
2346 [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
2347 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
2348 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
2349 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
2350 [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
2351 [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
2352 [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
2353 [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
2354 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2355 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2356 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2357 [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
2358 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2359 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2360 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2361 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2362 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2363 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2364 [GPLL0] = &gpll0.clkr,
2365 [GPLL0_EARLY] = &gpll0_early.clkr,
2366 [GPLL1] = &gpll1.clkr,
2367 [GPLL1_EARLY] = &gpll1_early.clkr,
2368 [GPLL4] = &gpll4.clkr,
2369 [GPLL4_EARLY] = &gpll4_early.clkr,
2370 [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
2371 [HMSS_GPLL4_CLK_SRC] = &hmss_gpll4_clk_src.clkr,
2372 [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
2373 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2374 [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
2375 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2376 [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
2377 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2378 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2379 [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
2380 [UFS_PHY_AUX_CLK_SRC] = &ufs_phy_aux_clk_src.clkr,
2381 [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr,
2382 [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
2383 [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
2384 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2385 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2386 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2389 static struct gdsc *gcc_sdm660_gdscs[] = {
2390 [UFS_GDSC] = &ufs_gdsc,
2391 [USB_30_GDSC] = &usb_30_gdsc,
2392 [PCIE_0_GDSC] = &pcie_0_gdsc,
2395 static const struct qcom_reset_map gcc_sdm660_resets[] = {
2396 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
2397 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
2398 [GCC_UFS_BCR] = { 0x75000 },
2399 [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
2400 [GCC_USB3_PHY_BCR] = { 0x50020 },
2401 [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
2402 [GCC_USB_20_BCR] = { 0x2f000 },
2403 [GCC_USB_30_BCR] = { 0xf000 },
2404 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
2407 static const struct regmap_config gcc_sdm660_regmap_config = {
2411 .max_register = 0x94000,
2415 static const struct qcom_cc_desc gcc_sdm660_desc = {
2416 .config = &gcc_sdm660_regmap_config,
2417 .clks = gcc_sdm660_clocks,
2418 .num_clks = ARRAY_SIZE(gcc_sdm660_clocks),
2419 .resets = gcc_sdm660_resets,
2420 .num_resets = ARRAY_SIZE(gcc_sdm660_resets),
2421 .gdscs = gcc_sdm660_gdscs,
2422 .num_gdscs = ARRAY_SIZE(gcc_sdm660_gdscs),
2425 static const struct of_device_id gcc_sdm660_match_table[] = {
2426 { .compatible = "qcom,gcc-sdm630" },
2427 { .compatible = "qcom,gcc-sdm660" },
2430 MODULE_DEVICE_TABLE(of, gcc_sdm660_match_table);
2432 static int gcc_sdm660_probe(struct platform_device *pdev)
2435 struct regmap *regmap;
2437 regmap = qcom_cc_map(pdev, &gcc_sdm660_desc);
2439 return PTR_ERR(regmap);
2442 * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
2443 * turned off by hardware during certain apps low power modes.
2445 ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
2449 /* Register the hws */
2450 for (i = 0; i < ARRAY_SIZE(gcc_sdm660_hws); i++) {
2451 ret = devm_clk_hw_register(&pdev->dev, gcc_sdm660_hws[i]);
2456 return qcom_cc_really_probe(pdev, &gcc_sdm660_desc, regmap);
2459 static struct platform_driver gcc_sdm660_driver = {
2460 .probe = gcc_sdm660_probe,
2462 .name = "gcc-sdm660",
2463 .of_match_table = gcc_sdm660_match_table,
2467 static int __init gcc_sdm660_init(void)
2469 return platform_driver_register(&gcc_sdm660_driver);
2471 core_initcall_sync(gcc_sdm660_init);
2473 static void __exit gcc_sdm660_exit(void)
2475 platform_driver_unregister(&gcc_sdm660_driver);
2477 module_exit(gcc_sdm660_exit);
2479 MODULE_LICENSE("GPL v2");
2480 MODULE_DESCRIPTION("QCOM GCC sdm660 Driver");