drivers/clk/qcom/gcc-sc7280.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk-provider.h>
   7 #include <linux/kernel.h>
   8 #include <linux/module.h>
   9 #include <linux/of_device.h>
  10 #include <linux/of.h>
  11 #include <linux/regmap.h>
  12
  13 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
  14
  15 #include "clk-alpha-pll.h"
  16 #include "clk-branch.h"
  17 #include "clk-rcg.h"
  18 #include "clk-regmap-divider.h"
  19 #include "clk-regmap-mux.h"
  20 #include "common.h"
  21 #include "gdsc.h"
  22 #include "reset.h"
  23
  24 enum {
  25         P_BI_TCXO,
  26         P_GCC_GPLL0_OUT_EVEN,
  27         P_GCC_GPLL0_OUT_MAIN,
  28         P_GCC_GPLL0_OUT_ODD,
  29         P_GCC_GPLL10_OUT_MAIN,
  30         P_GCC_GPLL4_OUT_MAIN,
  31         P_GCC_GPLL9_OUT_MAIN,
  32         P_PCIE_0_PIPE_CLK,
  33         P_PCIE_1_PIPE_CLK,
  34         P_SLEEP_CLK,
  35         P_UFS_PHY_RX_SYMBOL_0_CLK,
  36         P_UFS_PHY_RX_SYMBOL_1_CLK,
  37         P_UFS_PHY_TX_SYMBOL_0_CLK,
  38         P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
  39         P_GCC_MSS_GPLL0_MAIN_DIV_CLK,
  40 };
  41
  42 static struct clk_alpha_pll gcc_gpll0 = {
  43         .offset = 0x0,
  44         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  45         .clkr = {
  46                 .enable_reg = 0x52010,
  47                 .enable_mask = BIT(0),
  48                 .hw.init = &(struct clk_init_data){
  49                         .name = "gcc_gpll0",
  50                         .parent_data = &(const struct clk_parent_data){
  51                                 .fw_name = "bi_tcxo",
  52                         },
  53                         .num_parents = 1,
  54                         .ops = &clk_alpha_pll_fixed_lucid_ops,
  55                 },
  56         },
  57 };
  58
  59 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
  60         { 0x1, 2 },
  61         { }
  62 };
  63
  64 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
  65         .offset = 0x0,
  66         .post_div_shift = 8,
  67         .post_div_table = post_div_table_gcc_gpll0_out_even,
  68         .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
  69         .width = 4,
  70         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  71         .clkr.hw.init = &(struct clk_init_data){
  72                 .name = "gcc_gpll0_out_even",
  73                 .parent_hws = (const struct clk_hw*[]){
  74                         &gcc_gpll0.clkr.hw,
  75                 },
  76                 .num_parents = 1,
  77                 .ops = &clk_alpha_pll_postdiv_lucid_ops,
  78         },
  79 };
  80
  81 static const struct clk_div_table post_div_table_gcc_gpll0_out_odd[] = {
  82         { 0x3, 3 },
  83         { }
  84 };
  85
  86 static struct clk_alpha_pll_postdiv gcc_gpll0_out_odd = {
  87         .offset = 0x0,
  88         .post_div_shift = 12,
  89         .post_div_table = post_div_table_gcc_gpll0_out_odd,
  90         .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_odd),
  91         .width = 4,
  92         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  93         .clkr.hw.init = &(struct clk_init_data){
  94                 .name = "gcc_gpll0_out_odd",
  95                 .parent_hws = (const struct clk_hw*[]){
  96                         &gcc_gpll0.clkr.hw,
  97                 },
  98                 .num_parents = 1,
  99                 .ops = &clk_alpha_pll_postdiv_lucid_ops,
 100         },
 101 };
 102
 103 static struct clk_alpha_pll gcc_gpll1 = {
 104         .offset = 0x1000,
 105         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 106         .clkr = {
 107                 .enable_reg = 0x52010,
 108                 .enable_mask = BIT(1),
 109                 .hw.init = &(struct clk_init_data){
 110                         .name = "gcc_gpll1",
 111                         .parent_data = &(const struct clk_parent_data){
 112                                 .fw_name = "bi_tcxo",
 113                         },
 114                         .num_parents = 1,
 115                         .ops = &clk_alpha_pll_fixed_lucid_ops,
 116                 },
 117         },
 118 };
 119
 120 static struct clk_alpha_pll gcc_gpll10 = {
 121         .offset = 0x1e000,
 122         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 123         .clkr = {
 124                 .enable_reg = 0x52010,
 125                 .enable_mask = BIT(9),
 126                 .hw.init = &(struct clk_init_data){
 127                         .name = "gcc_gpll10",
 128                         .parent_data = &(const struct clk_parent_data){
 129                                 .fw_name = "bi_tcxo",
 130                         },
 131                         .num_parents = 1,
 132                         .ops = &clk_alpha_pll_fixed_lucid_ops,
 133                 },
 134         },
 135 };
 136
 137 static struct clk_alpha_pll gcc_gpll4 = {
 138         .offset = 0x76000,
 139         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 140         .clkr = {
 141                 .enable_reg = 0x52010,
 142                 .enable_mask = BIT(4),
 143                 .hw.init = &(struct clk_init_data){
 144                         .name = "gcc_gpll4",
 145                         .parent_data = &(const struct clk_parent_data){
 146                                 .fw_name = "bi_tcxo",
 147                         },
 148                         .num_parents = 1,
 149                         .ops = &clk_alpha_pll_fixed_lucid_ops,
 150                 },
 151         },
 152 };
 153
 154 static struct clk_alpha_pll gcc_gpll9 = {
 155         .offset = 0x1c000,
 156         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 157         .clkr = {
 158                 .enable_reg = 0x52010,
 159                 .enable_mask = BIT(8),
 160                 .hw.init = &(struct clk_init_data){
 161                         .name = "gcc_gpll9",
 162                         .parent_data = &(const struct clk_parent_data){
 163                                 .fw_name = "bi_tcxo",
 164                         },
 165                         .num_parents = 1,
 166                         .ops = &clk_alpha_pll_fixed_lucid_ops,
 167                 },
 168         },
 169 };
 170
 171 static struct clk_branch gcc_mss_gpll0_main_div_clk_src = {
 172         .halt_check = BRANCH_HALT_DELAY,
 173         .clkr = {
 174                 .enable_reg = 0x52000,
 175                 .enable_mask = BIT(17),
 176                 .hw.init = &(struct clk_init_data){
 177                         .name = "gcc_mss_gpll0_main_div_clk_src",
 178                         .parent_hws = (const struct clk_hw*[]){
 179                                 &gcc_gpll0_out_even.clkr.hw,
 180                         },
 181                         .num_parents = 1,
 182                         .flags = CLK_SET_RATE_PARENT,
 183                         .ops = &clk_branch2_ops,
 184                 },
 185         },
 186 };
 187
 188 static const struct parent_map gcc_parent_map_0[] = {
 189         { P_BI_TCXO, 0 },
 190         { P_GCC_GPLL0_OUT_MAIN, 1 },
 191         { P_GCC_GPLL0_OUT_EVEN, 6 },
 192 };
 193
 194 static const struct clk_parent_data gcc_parent_data_0[] = {
 195         { .fw_name = "bi_tcxo" },
 196         { .hw = &gcc_gpll0.clkr.hw },
 197         { .hw = &gcc_gpll0_out_even.clkr.hw },
 198 };
 199
 200 static const struct parent_map gcc_parent_map_1[] = {
 201         { P_BI_TCXO, 0 },
 202         { P_GCC_GPLL0_OUT_MAIN, 1 },
 203         { P_GCC_GPLL0_OUT_ODD, 3 },
 204         { P_GCC_GPLL0_OUT_EVEN, 6 },
 205 };
 206
 207 static const struct clk_parent_data gcc_parent_data_1[] = {
 208         { .fw_name = "bi_tcxo" },
 209         { .hw = &gcc_gpll0.clkr.hw },
 210         { .hw = &gcc_gpll0_out_odd.clkr.hw },
 211         { .hw = &gcc_gpll0_out_even.clkr.hw },
 212 };
 213
 214 static const struct parent_map gcc_parent_map_2[] = {
 215         { P_BI_TCXO, 0 },
 216         { P_SLEEP_CLK, 5 },
 217 };
 218
 219 static const struct clk_parent_data gcc_parent_data_2[] = {
 220         { .fw_name = "bi_tcxo" },
 221         { .fw_name = "sleep_clk" },
 222 };
 223
 224 static const struct parent_map gcc_parent_map_3[] = {
 225         { P_BI_TCXO, 0 },
 226 };
 227
 228 static const struct clk_parent_data gcc_parent_data_3[] = {
 229         { .fw_name = "bi_tcxo" },
 230 };
 231
 232 static const struct parent_map gcc_parent_map_4[] = {
 233         { P_BI_TCXO, 0 },
 234         { P_GCC_GPLL0_OUT_MAIN, 1 },
 235         { P_GCC_GPLL0_OUT_ODD, 3 },
 236         { P_SLEEP_CLK, 5 },
 237         { P_GCC_GPLL0_OUT_EVEN, 6 },
 238 };
 239
 240 static const struct clk_parent_data gcc_parent_data_4[] = {
 241         { .fw_name = "bi_tcxo" },
 242         { .hw = &gcc_gpll0.clkr.hw },
 243         { .hw = &gcc_gpll0_out_odd.clkr.hw },
 244         { .fw_name = "sleep_clk" },
 245         { .hw = &gcc_gpll0_out_even.clkr.hw },
 246 };
 247
 248 static const struct parent_map gcc_parent_map_5[] = {
 249         { P_BI_TCXO, 0 },
 250         { P_GCC_GPLL0_OUT_EVEN, 6 },
 251 };
 252
 253 static const struct clk_parent_data gcc_parent_data_5[] = {
 254         { .fw_name = "bi_tcxo" },
 255         { .hw = &gcc_gpll0_out_even.clkr.hw },
 256 };
 257
 258 static const struct parent_map gcc_parent_map_6[] = {
 259         { P_PCIE_0_PIPE_CLK, 0 },
 260         { P_BI_TCXO, 2 },
 261 };
 262
 263 static const struct clk_parent_data gcc_parent_data_6[] = {
 264         { .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" },
 265         { .fw_name = "bi_tcxo" },
 266 };
 267
 268 static const struct parent_map gcc_parent_map_7[] = {
 269         { P_PCIE_1_PIPE_CLK, 0 },
 270         { P_BI_TCXO, 2 },
 271 };
 272
 273 static const struct clk_parent_data gcc_parent_data_7[] = {
 274         { .fw_name = "pcie_1_pipe_clk", .name = "pcie_1_pipe_clk" },
 275         { .fw_name = "bi_tcxo" },
 276 };
 277
 278 static const struct parent_map gcc_parent_map_8[] = {
 279         { P_BI_TCXO, 0 },
 280         { P_GCC_GPLL0_OUT_MAIN, 1 },
 281         { P_GCC_GPLL0_OUT_ODD, 3 },
 282         { P_GCC_GPLL10_OUT_MAIN, 5 },
 283         { P_GCC_GPLL0_OUT_EVEN, 6 },
 284 };
 285
 286 static const struct clk_parent_data gcc_parent_data_8[] = {
 287         { .fw_name = "bi_tcxo" },
 288         { .hw = &gcc_gpll0.clkr.hw },
 289         { .hw = &gcc_gpll0_out_odd.clkr.hw },
 290         { .hw = &gcc_gpll10.clkr.hw },
 291         { .hw = &gcc_gpll0_out_even.clkr.hw },
 292 };
 293
 294 static const struct parent_map gcc_parent_map_9[] = {
 295         { P_BI_TCXO, 0 },
 296         { P_GCC_GPLL0_OUT_MAIN, 1 },
 297         { P_GCC_GPLL9_OUT_MAIN, 2 },
 298         { P_GCC_GPLL0_OUT_ODD, 3 },
 299         { P_GCC_GPLL4_OUT_MAIN, 5 },
 300         { P_GCC_GPLL0_OUT_EVEN, 6 },
 301 };
 302
 303 static const struct clk_parent_data gcc_parent_data_9[] = {
 304         { .fw_name = "bi_tcxo" },
 305         { .hw = &gcc_gpll0.clkr.hw },
 306         { .hw = &gcc_gpll9.clkr.hw },
 307         { .hw = &gcc_gpll0_out_odd.clkr.hw },
 308         { .hw = &gcc_gpll4.clkr.hw },
 309         { .hw = &gcc_gpll0_out_even.clkr.hw },
 310 };
 311
 312 static const struct parent_map gcc_parent_map_10[] = {
 313         { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
 314         { P_BI_TCXO, 2 },
 315 };
 316
 317 static const struct clk_parent_data gcc_parent_data_10[] = {
 318         { .fw_name = "ufs_phy_rx_symbol_0_clk" },
 319         { .fw_name = "bi_tcxo" },
 320 };
 321
 322 static const struct parent_map gcc_parent_map_11[] = {
 323         { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
 324         { P_BI_TCXO, 2 },
 325 };
 326
 327 static const struct clk_parent_data gcc_parent_data_11[] = {
 328         { .fw_name = "ufs_phy_rx_symbol_1_clk" },
 329         { .fw_name = "bi_tcxo" },
 330 };
 331
 332 static const struct parent_map gcc_parent_map_12[] = {
 333         { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
 334         { P_BI_TCXO, 2 },
 335 };
 336
 337 static const struct clk_parent_data gcc_parent_data_12[] = {
 338         { .fw_name = "ufs_phy_tx_symbol_0_clk" },
 339         { .fw_name = "bi_tcxo" },
 340 };
 341
 342 static const struct parent_map gcc_parent_map_13[] = {
 343         { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
 344         { P_BI_TCXO, 2 },
 345 };
 346
 347 static const struct clk_parent_data gcc_parent_data_13[] = {
 348         { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
 349         { .fw_name = "bi_tcxo" },
 350 };
 351
 352 static const struct parent_map gcc_parent_map_14[] = {
 353         { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
 354         { P_BI_TCXO, 2 },
 355 };
 356
 357 static const struct clk_parent_data gcc_parent_data_14[] = {
 358         { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
 359         { .fw_name = "bi_tcxo" },
 360 };
 361
 362 static const struct parent_map gcc_parent_map_15[] = {
 363         { P_BI_TCXO, 0 },
 364         { P_GCC_MSS_GPLL0_MAIN_DIV_CLK, 1 },
 365 };
 366
 367 static const struct clk_parent_data gcc_parent_data_15[] = {
 368         { .fw_name = "bi_tcxo" },
 369         { .hw = &gcc_mss_gpll0_main_div_clk_src.clkr.hw },
 370 };
 371
 372 static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
 373         .reg = 0x6b054,
 374         .shift = 0,
 375         .width = 2,
 376         .parent_map = gcc_parent_map_6,
 377         .clkr = {
 378                 .hw.init = &(struct clk_init_data){
 379                         .name = "gcc_pcie_0_pipe_clk_src",
 380                         .parent_data = gcc_parent_data_6,
 381                         .num_parents = ARRAY_SIZE(gcc_parent_data_6),
 382                         .ops = &clk_regmap_mux_closest_ops,
 383                 },
 384         },
 385 };
 386
 387 static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
 388         .reg = 0x8d054,
 389         .shift = 0,
 390         .width = 2,
 391         .parent_map = gcc_parent_map_7,
 392         .clkr = {
 393                 .hw.init = &(struct clk_init_data){
 394                         .name = "gcc_pcie_1_pipe_clk_src",
 395                         .parent_data = gcc_parent_data_7,
 396                         .num_parents = ARRAY_SIZE(gcc_parent_data_7),
 397                         .ops = &clk_regmap_mux_closest_ops,
 398                 },
 399         },
 400 };
 401
 402 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
 403         .reg = 0x77058,
 404         .shift = 0,
 405         .width = 2,
 406         .parent_map = gcc_parent_map_10,
 407         .clkr = {
 408                 .hw.init = &(struct clk_init_data){
 409                         .name = "gcc_ufs_phy_rx_symbol_0_clk_src",
 410                         .parent_data = gcc_parent_data_10,
 411                         .num_parents = ARRAY_SIZE(gcc_parent_data_10),
 412                         .ops = &clk_regmap_mux_closest_ops,
 413                 },
 414         },
 415 };
 416
 417 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
 418         .reg = 0x770c8,
 419         .shift = 0,
 420         .width = 2,
 421         .parent_map = gcc_parent_map_11,
 422         .clkr = {
 423                 .hw.init = &(struct clk_init_data){
 424                         .name = "gcc_ufs_phy_rx_symbol_1_clk_src",
 425                         .parent_data = gcc_parent_data_11,
 426                         .num_parents = ARRAY_SIZE(gcc_parent_data_11),
 427                         .ops = &clk_regmap_mux_closest_ops,
 428                 },
 429         },
 430 };
 431
 432 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
 433         .reg = 0x77048,
 434         .shift = 0,
 435         .width = 2,
 436         .parent_map = gcc_parent_map_12,
 437         .clkr = {
 438                 .hw.init = &(struct clk_init_data){
 439                         .name = "gcc_ufs_phy_tx_symbol_0_clk_src",
 440                         .parent_data = gcc_parent_data_12,
 441                         .num_parents = ARRAY_SIZE(gcc_parent_data_12),
 442                         .ops = &clk_regmap_mux_closest_ops,
 443                 },
 444         },
 445 };
 446
 447 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
 448         .reg = 0xf060,
 449         .shift = 0,
 450         .width = 2,
 451         .parent_map = gcc_parent_map_13,
 452         .clkr = {
 453                 .hw.init = &(struct clk_init_data){
 454                         .name = "gcc_usb3_prim_phy_pipe_clk_src",
 455                         .parent_data = gcc_parent_data_13,
 456                         .num_parents = ARRAY_SIZE(gcc_parent_data_13),
 457                         .ops = &clk_regmap_mux_closest_ops,
 458                 },
 459         },
 460 };
 461
 462 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
 463         .reg = 0x9e060,
 464         .shift = 0,
 465         .width = 2,
 466         .parent_map = gcc_parent_map_14,
 467         .clkr = {
 468                 .hw.init = &(struct clk_init_data){
 469                         .name = "gcc_usb3_sec_phy_pipe_clk_src",
 470                         .parent_data = gcc_parent_data_14,
 471                         .num_parents = ARRAY_SIZE(gcc_parent_data_14),
 472                         .ops = &clk_regmap_mux_closest_ops,
 473                 },
 474         },
 475 };
 476
 477 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 478         F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
 479         F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 480         F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0),
 481         { }
 482 };
 483
 484 static struct clk_rcg2 gcc_gp1_clk_src = {
 485         .cmd_rcgr = 0x64004,
 486         .mnd_width = 16,
 487         .hid_width = 5,
 488         .parent_map = gcc_parent_map_4,
 489         .freq_tbl = ftbl_gcc_gp1_clk_src,
 490         .clkr.hw.init = &(struct clk_init_data){
 491                 .name = "gcc_gp1_clk_src",
 492                 .parent_data = gcc_parent_data_4,
 493                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 494                 .ops = &clk_rcg2_ops,
 495         },
 496 };
 497
 498 static struct clk_rcg2 gcc_gp2_clk_src = {
 499         .cmd_rcgr = 0x65004,
 500         .mnd_width = 16,
 501         .hid_width = 5,
 502         .parent_map = gcc_parent_map_4,
 503         .freq_tbl = ftbl_gcc_gp1_clk_src,
 504         .clkr.hw.init = &(struct clk_init_data){
 505                 .name = "gcc_gp2_clk_src",
 506                 .parent_data = gcc_parent_data_4,
 507                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 508                 .ops = &clk_rcg2_ops,
 509         },
 510 };
 511
 512 static struct clk_rcg2 gcc_gp3_clk_src = {
 513         .cmd_rcgr = 0x66004,
 514         .mnd_width = 16,
 515         .hid_width = 5,
 516         .parent_map = gcc_parent_map_4,
 517         .freq_tbl = ftbl_gcc_gp1_clk_src,
 518         .clkr.hw.init = &(struct clk_init_data){
 519                 .name = "gcc_gp3_clk_src",
 520                 .parent_data = gcc_parent_data_4,
 521                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 522                 .ops = &clk_rcg2_ops,
 523         },
 524 };
 525
 526 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
 527         F(9600000, P_BI_TCXO, 2, 0, 0),
 528         F(19200000, P_BI_TCXO, 1, 0, 0),
 529         { }
 530 };
 531
 532 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
 533         .cmd_rcgr = 0x6b058,
 534         .mnd_width = 16,
 535         .hid_width = 5,
 536         .parent_map = gcc_parent_map_2,
 537         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 538         .clkr.hw.init = &(struct clk_init_data){
 539                 .name = "gcc_pcie_0_aux_clk_src",
 540                 .parent_data = gcc_parent_data_2,
 541                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 542                 .ops = &clk_rcg2_ops,
 543         },
 544 };
 545
 546 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
 547         F(19200000, P_BI_TCXO, 1, 0, 0),
 548         F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 549         { }
 550 };
 551
 552 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
 553         .cmd_rcgr = 0x6b03c,
 554         .mnd_width = 0,
 555         .hid_width = 5,
 556         .parent_map = gcc_parent_map_0,
 557         .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 558         .clkr.hw.init = &(struct clk_init_data){
 559                 .name = "gcc_pcie_0_phy_rchng_clk_src",
 560                 .parent_data = gcc_parent_data_0,
 561                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 562                 .ops = &clk_rcg2_ops,
 563         },
 564 };
 565
 566 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
 567         .cmd_rcgr = 0x8d058,
 568         .mnd_width = 16,
 569         .hid_width = 5,
 570         .parent_map = gcc_parent_map_2,
 571         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 572         .clkr.hw.init = &(struct clk_init_data){
 573                 .name = "gcc_pcie_1_aux_clk_src",
 574                 .parent_data = gcc_parent_data_2,
 575                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 576                 .ops = &clk_rcg2_ops,
 577         },
 578 };
 579
 580 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
 581         .cmd_rcgr = 0x8d03c,
 582         .mnd_width = 0,
 583         .hid_width = 5,
 584         .parent_map = gcc_parent_map_0,
 585         .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 586         .clkr.hw.init = &(struct clk_init_data){
 587                 .name = "gcc_pcie_1_phy_rchng_clk_src",
 588                 .parent_data = gcc_parent_data_0,
 589                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 590                 .flags = CLK_SET_RATE_PARENT,
 591                 .ops = &clk_rcg2_ops,
 592         },
 593 };
 594
 595 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
 596         F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0),
 597         { }
 598 };
 599
 600 static struct clk_rcg2 gcc_pdm2_clk_src = {
 601         .cmd_rcgr = 0x33010,
 602         .mnd_width = 0,
 603         .hid_width = 5,
 604         .parent_map = gcc_parent_map_0,
 605         .freq_tbl = ftbl_gcc_pdm2_clk_src,
 606         .clkr.hw.init = &(struct clk_init_data){
 607                 .name = "gcc_pdm2_clk_src",
 608                 .parent_data = gcc_parent_data_0,
 609                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 610                 .flags = CLK_SET_RATE_PARENT,
 611                 .ops = &clk_rcg2_ops,
 612         },
 613 };
 614
 615 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
 616         F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 617         F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
 618         F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
 619         F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
 620         { }
 621 };
 622
 623 static struct clk_rcg2 gcc_qspi_core_clk_src = {
 624         .cmd_rcgr = 0x4b00c,
 625         .mnd_width = 0,
 626         .hid_width = 5,
 627         .parent_map = gcc_parent_map_0,
 628         .freq_tbl = ftbl_gcc_qspi_core_clk_src,
 629         .clkr.hw.init = &(struct clk_init_data){
 630                 .name = "gcc_qspi_core_clk_src",
 631                 .parent_data = gcc_parent_data_0,
 632                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 633                 .ops = &clk_rcg2_floor_ops,
 634         },
 635 };
 636
 637 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
 638         F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 639         F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 640         F(19200000, P_BI_TCXO, 1, 0, 0),
 641         F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 642         F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 643         F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 644         F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 645         F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
 646         F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 647         F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 648         F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 649         F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
 650         F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
 651         F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
 652         F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0),
 653         { }
 654 };
 655
 656 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
 657         .name = "gcc_qupv3_wrap0_s0_clk_src",
 658         .parent_data = gcc_parent_data_0,
 659         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 660         .ops = &clk_rcg2_ops,
 661 };
 662
 663 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
 664         .cmd_rcgr = 0x17010,
 665         .mnd_width = 16,
 666         .hid_width = 5,
 667         .parent_map = gcc_parent_map_0,
 668         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 669         .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
 670 };
 671
 672 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
 673         .name = "gcc_qupv3_wrap0_s1_clk_src",
 674         .parent_data = gcc_parent_data_0,
 675         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 676         .ops = &clk_rcg2_ops,
 677 };
 678
 679 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
 680         .cmd_rcgr = 0x17140,
 681         .mnd_width = 16,
 682         .hid_width = 5,
 683         .parent_map = gcc_parent_map_0,
 684         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 685         .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
 686 };
 687
 688 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
 689         F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 690         F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 691         F(19200000, P_BI_TCXO, 1, 0, 0),
 692         F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 693         F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 694         F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 695         F(52174000, P_GCC_GPLL0_OUT_MAIN, 1, 2, 23),
 696         F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 697         F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
 698         F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 699         F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 700         F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 701         { }
 702 };
 703
 704 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
 705         .name = "gcc_qupv3_wrap0_s2_clk_src",
 706         .parent_data = gcc_parent_data_0,
 707         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 708         .ops = &clk_rcg2_ops,
 709 };
 710
 711 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
 712         .cmd_rcgr = 0x17270,
 713         .mnd_width = 16,
 714         .hid_width = 5,
 715         .parent_map = gcc_parent_map_0,
 716         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 717         .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
 718 };
 719
 720 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
 721         .name = "gcc_qupv3_wrap0_s3_clk_src",
 722         .parent_data = gcc_parent_data_0,
 723         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 724         .ops = &clk_rcg2_ops,
 725 };
 726
 727 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
 728         .cmd_rcgr = 0x173a0,
 729         .mnd_width = 16,
 730         .hid_width = 5,
 731         .parent_map = gcc_parent_map_0,
 732         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 733         .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
 734 };
 735
 736 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
 737         .name = "gcc_qupv3_wrap0_s4_clk_src",
 738         .parent_data = gcc_parent_data_0,
 739         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 740         .ops = &clk_rcg2_ops,
 741 };
 742
 743 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
 744         .cmd_rcgr = 0x174d0,
 745         .mnd_width = 16,
 746         .hid_width = 5,
 747         .parent_map = gcc_parent_map_0,
 748         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 749         .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
 750 };
 751
 752 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
 753         .name = "gcc_qupv3_wrap0_s5_clk_src",
 754         .parent_data = gcc_parent_data_0,
 755         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 756         .ops = &clk_rcg2_ops,
 757 };
 758
 759 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
 760         .cmd_rcgr = 0x17600,
 761         .mnd_width = 16,
 762         .hid_width = 5,
 763         .parent_map = gcc_parent_map_0,
 764         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 765         .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
 766 };
 767
 768 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
 769         .name = "gcc_qupv3_wrap0_s6_clk_src",
 770         .parent_data = gcc_parent_data_0,
 771         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 772         .ops = &clk_rcg2_ops,
 773 };
 774
 775 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
 776         .cmd_rcgr = 0x17730,
 777         .mnd_width = 16,
 778         .hid_width = 5,
 779         .parent_map = gcc_parent_map_0,
 780         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 781         .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
 782 };
 783
 784 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
 785         .name = "gcc_qupv3_wrap0_s7_clk_src",
 786         .parent_data = gcc_parent_data_0,
 787         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 788         .ops = &clk_rcg2_ops,
 789 };
 790
 791 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
 792         .cmd_rcgr = 0x17860,
 793         .mnd_width = 16,
 794         .hid_width = 5,
 795         .parent_map = gcc_parent_map_0,
 796         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 797         .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
 798 };
 799
 800 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
 801         .name = "gcc_qupv3_wrap1_s0_clk_src",
 802         .parent_data = gcc_parent_data_0,
 803         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 804         .ops = &clk_rcg2_ops,
 805 };
 806
 807 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
 808         .cmd_rcgr = 0x18010,
 809         .mnd_width = 16,
 810         .hid_width = 5,
 811         .parent_map = gcc_parent_map_0,
 812         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 813         .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
 814 };
 815
 816 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
 817         .name = "gcc_qupv3_wrap1_s1_clk_src",
 818         .parent_data = gcc_parent_data_0,
 819         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 820         .ops = &clk_rcg2_ops,
 821 };
 822
 823 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
 824         .cmd_rcgr = 0x18140,
 825         .mnd_width = 16,
 826         .hid_width = 5,
 827         .parent_map = gcc_parent_map_0,
 828         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 829         .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
 830 };
 831
 832 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
 833         .name = "gcc_qupv3_wrap1_s2_clk_src",
 834         .parent_data = gcc_parent_data_0,
 835         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 836         .ops = &clk_rcg2_ops,
 837 };
 838
 839 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
 840         .cmd_rcgr = 0x18270,
 841         .mnd_width = 16,
 842         .hid_width = 5,
 843         .parent_map = gcc_parent_map_0,
 844         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 845         .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
 846 };
 847
 848 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
 849         .name = "gcc_qupv3_wrap1_s3_clk_src",
 850         .parent_data = gcc_parent_data_0,
 851         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 852         .ops = &clk_rcg2_ops,
 853 };
 854
 855 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
 856         .cmd_rcgr = 0x183a0,
 857         .mnd_width = 16,
 858         .hid_width = 5,
 859         .parent_map = gcc_parent_map_0,
 860         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 861         .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
 862 };
 863
 864 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
 865         .name = "gcc_qupv3_wrap1_s4_clk_src",
 866         .parent_data = gcc_parent_data_0,
 867         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 868         .ops = &clk_rcg2_ops,
 869 };
 870
 871 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
 872         .cmd_rcgr = 0x184d0,
 873         .mnd_width = 16,
 874         .hid_width = 5,
 875         .parent_map = gcc_parent_map_0,
 876         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 877         .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
 878 };
 879
 880 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
 881         .name = "gcc_qupv3_wrap1_s5_clk_src",
 882         .parent_data = gcc_parent_data_0,
 883         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 884         .ops = &clk_rcg2_ops,
 885 };
 886
 887 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
 888         .cmd_rcgr = 0x18600,
 889         .mnd_width = 16,
 890         .hid_width = 5,
 891         .parent_map = gcc_parent_map_0,
 892         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 893         .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
 894 };
 895
 896 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
 897         .name = "gcc_qupv3_wrap1_s6_clk_src",
 898         .parent_data = gcc_parent_data_0,
 899         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 900         .ops = &clk_rcg2_ops,
 901 };
 902
 903 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
 904         .cmd_rcgr = 0x18730,
 905         .mnd_width = 16,
 906         .hid_width = 5,
 907         .parent_map = gcc_parent_map_0,
 908         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 909         .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
 910 };
 911
 912 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
 913         .name = "gcc_qupv3_wrap1_s7_clk_src",
 914         .parent_data = gcc_parent_data_0,
 915         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 916         .ops = &clk_rcg2_ops,
 917 };
 918
 919 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
 920         .cmd_rcgr = 0x18860,
 921         .mnd_width = 16,
 922         .hid_width = 5,
 923         .parent_map = gcc_parent_map_0,
 924         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 925         .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
 926 };
 927
 928 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
 929         F(144000, P_BI_TCXO, 16, 3, 25),
 930         F(400000, P_BI_TCXO, 12, 1, 4),
 931         F(19200000, P_BI_TCXO, 1, 0, 0),
 932         F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3),
 933         F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
 934         F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
 935         F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 936         F(192000000, P_GCC_GPLL10_OUT_MAIN, 2, 0, 0),
 937         F(384000000, P_GCC_GPLL10_OUT_MAIN, 1, 0, 0),
 938         { }
 939 };
 940
 941 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
 942         .cmd_rcgr = 0x7500c,
 943         .mnd_width = 8,
 944         .hid_width = 5,
 945         .parent_map = gcc_parent_map_8,
 946         .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
 947         .clkr.hw.init = &(struct clk_init_data){
 948                 .name = "gcc_sdcc1_apps_clk_src",
 949                 .parent_data = gcc_parent_data_8,
 950                 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
 951                 .ops = &clk_rcg2_floor_ops,
 952         },
 953 };
 954
 955 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
 956         F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 957         F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
 958         F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
 959         { }
 960 };
 961
 962 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
 963         .cmd_rcgr = 0x7502c,
 964         .mnd_width = 0,
 965         .hid_width = 5,
 966         .parent_map = gcc_parent_map_1,
 967         .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
 968         .clkr.hw.init = &(struct clk_init_data){
 969                 .name = "gcc_sdcc1_ice_core_clk_src",
 970                 .parent_data = gcc_parent_data_1,
 971                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 972                 .ops = &clk_rcg2_floor_ops,
 973         },
 974 };
 975
 976 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
 977         F(400000, P_BI_TCXO, 12, 1, 4),
 978         F(19200000, P_BI_TCXO, 1, 0, 0),
 979         F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
 980         F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
 981         F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 982         F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
 983         { }
 984 };
 985
 986 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
 987         .cmd_rcgr = 0x1400c,
 988         .mnd_width = 8,
 989         .hid_width = 5,
 990         .parent_map = gcc_parent_map_9,
 991         .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
 992         .clkr.hw.init = &(struct clk_init_data){
 993                 .name = "gcc_sdcc2_apps_clk_src",
 994                 .parent_data = gcc_parent_data_9,
 995                 .num_parents = ARRAY_SIZE(gcc_parent_data_9),
 996                 .flags = CLK_OPS_PARENT_ENABLE,
 997                 .ops = &clk_rcg2_floor_ops,
 998         },
 999 };
1000
1001 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
1002         F(400000, P_BI_TCXO, 12, 1, 4),
1003         F(19200000, P_BI_TCXO, 1, 0, 0),
1004         F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1005         F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1006         F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1007         { }
1008 };
1009
1010 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
1011         .cmd_rcgr = 0x1600c,
1012         .mnd_width = 8,
1013         .hid_width = 5,
1014         .parent_map = gcc_parent_map_1,
1015         .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
1016         .clkr.hw.init = &(struct clk_init_data){
1017                 .name = "gcc_sdcc4_apps_clk_src",
1018                 .parent_data = gcc_parent_data_1,
1019                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1020                 .ops = &clk_rcg2_floor_ops,
1021         },
1022 };
1023
1024 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
1025         F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1026         F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1027         F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1028         F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
1029         { }
1030 };
1031
1032 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1033         .cmd_rcgr = 0x77024,
1034         .mnd_width = 8,
1035         .hid_width = 5,
1036         .parent_map = gcc_parent_map_0,
1037         .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
1038         .clkr.hw.init = &(struct clk_init_data){
1039                 .name = "gcc_ufs_phy_axi_clk_src",
1040                 .parent_data = gcc_parent_data_0,
1041                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1042                 .ops = &clk_rcg2_ops,
1043         },
1044 };
1045
1046 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
1047         F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1048         F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1049         F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
1050         { }
1051 };
1052
1053 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1054         .cmd_rcgr = 0x7706c,
1055         .mnd_width = 0,
1056         .hid_width = 5,
1057         .parent_map = gcc_parent_map_0,
1058         .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1059         .clkr.hw.init = &(struct clk_init_data){
1060                 .name = "gcc_ufs_phy_ice_core_clk_src",
1061                 .parent_data = gcc_parent_data_0,
1062                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1063                 .ops = &clk_rcg2_ops,
1064         },
1065 };
1066
1067 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1068         .cmd_rcgr = 0x770a0,
1069         .mnd_width = 0,
1070         .hid_width = 5,
1071         .parent_map = gcc_parent_map_3,
1072         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1073         .clkr.hw.init = &(struct clk_init_data){
1074                 .name = "gcc_ufs_phy_phy_aux_clk_src",
1075                 .parent_data = gcc_parent_data_3,
1076                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1077                 .ops = &clk_rcg2_ops,
1078         },
1079 };
1080
1081 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1082         .cmd_rcgr = 0x77084,
1083         .mnd_width = 0,
1084         .hid_width = 5,
1085         .parent_map = gcc_parent_map_0,
1086         .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1087         .clkr.hw.init = &(struct clk_init_data){
1088                 .name = "gcc_ufs_phy_unipro_core_clk_src",
1089                 .parent_data = gcc_parent_data_0,
1090                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1091                 .ops = &clk_rcg2_ops,
1092         },
1093 };
1094
1095 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1096         F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1097         F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1098         F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0),
1099         F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1100         { }
1101 };
1102
1103 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1104         .cmd_rcgr = 0xf020,
1105         .mnd_width = 8,
1106         .hid_width = 5,
1107         .parent_map = gcc_parent_map_1,
1108         .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1109         .clkr.hw.init = &(struct clk_init_data){
1110                 .name = "gcc_usb30_prim_master_clk_src",
1111                 .parent_data = gcc_parent_data_1,
1112                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1113                 .ops = &clk_rcg2_ops,
1114         },
1115 };
1116
1117 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
1118         F(19200000, P_BI_TCXO, 1, 0, 0),
1119         { }
1120 };
1121
1122 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1123         .cmd_rcgr = 0xf038,
1124         .mnd_width = 0,
1125         .hid_width = 5,
1126         .parent_map = gcc_parent_map_3,
1127         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1128         .clkr.hw.init = &(struct clk_init_data){
1129                 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1130                 .parent_data = gcc_parent_data_3,
1131                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1132                 .ops = &clk_rcg2_ops,
1133         },
1134 };
1135
1136 static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk_src[] = {
1137         F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0),
1138         F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0),
1139         { }
1140 };
1141
1142 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1143         .cmd_rcgr = 0x9e020,
1144         .mnd_width = 8,
1145         .hid_width = 5,
1146         .parent_map = gcc_parent_map_5,
1147         .freq_tbl = ftbl_gcc_usb30_sec_master_clk_src,
1148         .clkr.hw.init = &(struct clk_init_data){
1149                 .name = "gcc_usb30_sec_master_clk_src",
1150                 .parent_data = gcc_parent_data_5,
1151                 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
1152                 .ops = &clk_rcg2_ops,
1153         },
1154 };
1155
1156 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1157         .cmd_rcgr = 0x9e038,
1158         .mnd_width = 0,
1159         .hid_width = 5,
1160         .parent_map = gcc_parent_map_3,
1161         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1162         .clkr.hw.init = &(struct clk_init_data){
1163                 .name = "gcc_usb30_sec_mock_utmi_clk_src",
1164                 .parent_data = gcc_parent_data_3,
1165                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1166                 .ops = &clk_rcg2_ops,
1167         },
1168 };
1169
1170 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1171         .cmd_rcgr = 0xf064,
1172         .mnd_width = 0,
1173         .hid_width = 5,
1174         .parent_map = gcc_parent_map_2,
1175         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1176         .clkr.hw.init = &(struct clk_init_data){
1177                 .name = "gcc_usb3_prim_phy_aux_clk_src",
1178                 .parent_data = gcc_parent_data_2,
1179                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1180                 .ops = &clk_rcg2_ops,
1181         },
1182 };
1183
1184 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1185         .cmd_rcgr = 0x9e064,
1186         .mnd_width = 0,
1187         .hid_width = 5,
1188         .parent_map = gcc_parent_map_2,
1189         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1190         .clkr.hw.init = &(struct clk_init_data){
1191                 .name = "gcc_usb3_sec_phy_aux_clk_src",
1192                 .parent_data = gcc_parent_data_2,
1193                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1194                 .ops = &clk_rcg2_ops,
1195         },
1196 };
1197
1198 static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = {
1199         F(4800000, P_BI_TCXO, 4, 0, 0),
1200         F(19200000, P_BI_TCXO, 1, 0, 0),
1201         { }
1202 };
1203
1204 static struct clk_rcg2 gcc_sec_ctrl_clk_src = {
1205         .cmd_rcgr = 0x3d02c,
1206         .mnd_width = 0,
1207         .hid_width = 5,
1208         .parent_map = gcc_parent_map_3,
1209         .freq_tbl = ftbl_gcc_sec_ctrl_clk_src,
1210         .clkr.hw.init = &(struct clk_init_data){
1211                 .name = "gcc_sec_ctrl_clk_src",
1212                 .parent_data = gcc_parent_data_3,
1213                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1214                 .ops = &clk_rcg2_ops,
1215         },
1216 };
1217
1218 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1219         .reg = 0xf050,
1220         .shift = 0,
1221         .width = 4,
1222         .clkr.hw.init = &(struct clk_init_data) {
1223                 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1224                 .parent_hws = (const struct clk_hw*[]){
1225                         &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1226                 },
1227                 .num_parents = 1,
1228                 .flags = CLK_SET_RATE_PARENT,
1229                 .ops = &clk_regmap_div_ro_ops,
1230         },
1231 };
1232
1233 static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
1234         .reg = 0x9e050,
1235         .shift = 0,
1236         .width = 4,
1237         .clkr.hw.init = &(struct clk_init_data) {
1238                 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
1239                 .parent_hws = (const struct clk_hw*[]){
1240                         &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
1241                 },
1242                 .num_parents = 1,
1243                 .flags = CLK_SET_RATE_PARENT,
1244                 .ops = &clk_regmap_div_ro_ops,
1245         },
1246 };
1247
1248 static struct clk_branch gcc_pcie_clkref_en = {
1249         .halt_reg = 0x8c004,
1250         .halt_check = BRANCH_HALT,
1251         .clkr = {
1252                 .enable_reg = 0x8c004,
1253                 .enable_mask = BIT(0),
1254                 .hw.init = &(struct clk_init_data){
1255                         .name = "gcc_pcie_clkref_en",
1256                         .ops = &clk_branch2_ops,
1257                 },
1258         },
1259 };
1260
1261 static struct clk_branch gcc_edp_clkref_en = {
1262         .halt_reg = 0x8c008,
1263         .halt_check = BRANCH_HALT,
1264         .clkr = {
1265                 .enable_reg = 0x8c008,
1266                 .enable_mask = BIT(0),
1267                 .hw.init = &(struct clk_init_data){
1268                         .name = "gcc_edp_clkref_en",
1269                         .ops = &clk_branch2_ops,
1270                 },
1271         },
1272 };
1273
1274 static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = {
1275         .halt_reg = 0x6b080,
1276         .halt_check = BRANCH_HALT_SKIP,
1277         .hwcg_reg = 0x6b080,
1278         .hwcg_bit = 1,
1279         .clkr = {
1280                 .enable_reg = 0x52000,
1281                 .enable_mask = BIT(12),
1282                 .hw.init = &(struct clk_init_data){
1283                         .name = "gcc_aggre_noc_pcie_0_axi_clk",
1284                         .ops = &clk_branch2_ops,
1285                 },
1286         },
1287 };
1288
1289 static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = {
1290         .halt_reg = 0x8d084,
1291         .halt_check = BRANCH_HALT_SKIP,
1292         .hwcg_reg = 0x8d084,
1293         .hwcg_bit = 1,
1294         .clkr = {
1295                 .enable_reg = 0x52000,
1296                 .enable_mask = BIT(11),
1297                 .hw.init = &(struct clk_init_data){
1298                         .name = "gcc_aggre_noc_pcie_1_axi_clk",
1299                         .ops = &clk_branch2_ops,
1300                 },
1301         },
1302 };
1303
1304 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1305         .halt_reg = 0x90010,
1306         .halt_check = BRANCH_HALT_VOTED,
1307         .hwcg_reg = 0x90010,
1308         .hwcg_bit = 1,
1309         .clkr = {
1310                 .enable_reg = 0x52000,
1311                 .enable_mask = BIT(18),
1312                 .hw.init = &(struct clk_init_data){
1313                         .name = "gcc_aggre_noc_pcie_tbu_clk",
1314                         .ops = &clk_branch2_ops,
1315                 },
1316         },
1317 };
1318
1319 static struct clk_branch gcc_aggre_noc_pcie_center_sf_axi_clk = {
1320         .halt_reg = 0x8d088,
1321         .halt_check = BRANCH_HALT_VOTED,
1322         .hwcg_reg = 0x8d088,
1323         .hwcg_bit = 1,
1324         .clkr = {
1325                 .enable_reg = 0x52008,
1326                 .enable_mask = BIT(28),
1327                 .hw.init = &(struct clk_init_data){
1328                         .name = "gcc_aggre_noc_pcie_center_sf_axi_clk",
1329                         .ops = &clk_branch2_ops,
1330                 },
1331         },
1332 };
1333
1334 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1335         .halt_reg = 0x770cc,
1336         .halt_check = BRANCH_HALT_VOTED,
1337         .hwcg_reg = 0x770cc,
1338         .hwcg_bit = 1,
1339         .clkr = {
1340                 .enable_reg = 0x770cc,
1341                 .enable_mask = BIT(0),
1342                 .hw.init = &(struct clk_init_data){
1343                         .name = "gcc_aggre_ufs_phy_axi_clk",
1344                         .parent_hws = (const struct clk_hw*[]){
1345                                 &gcc_ufs_phy_axi_clk_src.clkr.hw,
1346                         },
1347                         .num_parents = 1,
1348                         .flags = CLK_SET_RATE_PARENT,
1349                         .ops = &clk_branch2_ops,
1350                 },
1351         },
1352 };
1353
1354 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1355         .halt_reg = 0xf080,
1356         .halt_check = BRANCH_HALT_VOTED,
1357         .hwcg_reg = 0xf080,
1358         .hwcg_bit = 1,
1359         .clkr = {
1360                 .enable_reg = 0xf080,
1361                 .enable_mask = BIT(0),
1362                 .hw.init = &(struct clk_init_data){
1363                         .name = "gcc_aggre_usb3_prim_axi_clk",
1364                         .parent_hws = (const struct clk_hw*[]){
1365                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
1366                         },
1367                         .num_parents = 1,
1368                         .flags = CLK_SET_RATE_PARENT,
1369                         .ops = &clk_branch2_ops,
1370                 },
1371         },
1372 };
1373
1374 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1375         .halt_reg = 0x9e080,
1376         .halt_check = BRANCH_HALT_VOTED,
1377         .hwcg_reg = 0x9e080,
1378         .hwcg_bit = 1,
1379         .clkr = {
1380                 .enable_reg = 0x9e080,
1381                 .enable_mask = BIT(0),
1382                 .hw.init = &(struct clk_init_data){
1383                         .name = "gcc_aggre_usb3_sec_axi_clk",
1384                         .parent_hws = (const struct clk_hw*[]){
1385                                 &gcc_usb30_sec_master_clk_src.clkr.hw,
1386                         },
1387                         .num_parents = 1,
1388                         .flags = CLK_SET_RATE_PARENT,
1389                         .ops = &clk_branch2_ops,
1390                 },
1391         },
1392 };
1393
1394 static struct clk_branch gcc_camera_hf_axi_clk = {
1395         .halt_reg = 0x26010,
1396         .halt_check = BRANCH_HALT_SKIP,
1397         .hwcg_reg = 0x26010,
1398         .hwcg_bit = 1,
1399         .clkr = {
1400                 .enable_reg = 0x26010,
1401                 .enable_mask = BIT(0),
1402                 .hw.init = &(struct clk_init_data){
1403                         .name = "gcc_camera_hf_axi_clk",
1404                         .ops = &clk_branch2_ops,
1405                 },
1406         },
1407 };
1408
1409 static struct clk_branch gcc_camera_sf_axi_clk = {
1410         .halt_reg = 0x2601c,
1411         .halt_check = BRANCH_HALT_SKIP,
1412         .hwcg_reg = 0x2601c,
1413         .hwcg_bit = 1,
1414         .clkr = {
1415                 .enable_reg = 0x2601c,
1416                 .enable_mask = BIT(0),
1417                 .hw.init = &(struct clk_init_data){
1418                         .name = "gcc_camera_sf_axi_clk",
1419                         .ops = &clk_branch2_ops,
1420                 },
1421         },
1422 };
1423
1424 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1425         .halt_reg = 0xf07c,
1426         .halt_check = BRANCH_HALT_VOTED,
1427         .hwcg_reg = 0xf07c,
1428         .hwcg_bit = 1,
1429         .clkr = {
1430                 .enable_reg = 0xf07c,
1431                 .enable_mask = BIT(0),
1432                 .hw.init = &(struct clk_init_data){
1433                         .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1434                         .parent_hws = (const struct clk_hw*[]){
1435                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
1436                         },
1437                         .num_parents = 1,
1438                         .flags = CLK_SET_RATE_PARENT,
1439                         .ops = &clk_branch2_ops,
1440                 },
1441         },
1442 };
1443
1444 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1445         .halt_reg = 0x9e07c,
1446         .halt_check = BRANCH_HALT_VOTED,
1447         .hwcg_reg = 0x9e07c,
1448         .hwcg_bit = 1,
1449         .clkr = {
1450                 .enable_reg = 0x9e07c,
1451                 .enable_mask = BIT(0),
1452                 .hw.init = &(struct clk_init_data){
1453                         .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1454                         .parent_hws = (const struct clk_hw*[]){
1455                                 &gcc_usb30_sec_master_clk_src.clkr.hw,
1456                         },
1457                         .num_parents = 1,
1458                         .flags = CLK_SET_RATE_PARENT,
1459                         .ops = &clk_branch2_ops,
1460                 },
1461         },
1462 };
1463
1464 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1465         .halt_reg = 0x71154,
1466         .halt_check = BRANCH_HALT_SKIP,
1467         .hwcg_reg = 0x71154,
1468         .hwcg_bit = 1,
1469         .clkr = {
1470                 .enable_reg = 0x71154,
1471                 .enable_mask = BIT(0),
1472                 .hw.init = &(struct clk_init_data){
1473                         .name = "gcc_ddrss_gpu_axi_clk",
1474                         .ops = &clk_branch2_aon_ops,
1475                 },
1476         },
1477 };
1478
1479 static struct clk_branch gcc_ddrss_pcie_sf_clk = {
1480         .halt_reg = 0x8d080,
1481         .halt_check = BRANCH_HALT_SKIP,
1482         .hwcg_reg = 0x8d080,
1483         .hwcg_bit = 1,
1484         .clkr = {
1485                 .enable_reg = 0x52000,
1486                 .enable_mask = BIT(19),
1487                 .hw.init = &(struct clk_init_data){
1488                         .name = "gcc_ddrss_pcie_sf_clk",
1489                         .ops = &clk_branch2_ops,
1490                 },
1491         },
1492 };
1493
1494 static struct clk_branch gcc_disp_gpll0_clk_src = {
1495         .halt_check = BRANCH_HALT_DELAY,
1496         .clkr = {
1497                 .enable_reg = 0x52000,
1498                 .enable_mask = BIT(7),
1499                 .hw.init = &(struct clk_init_data){
1500                         .name = "gcc_disp_gpll0_clk_src",
1501                         .parent_hws = (const struct clk_hw*[]){
1502                                 &gcc_gpll0.clkr.hw,
1503                         },
1504                         .num_parents = 1,
1505                         .flags = CLK_SET_RATE_PARENT,
1506                         .ops = &clk_branch2_ops,
1507                 },
1508         },
1509 };
1510
1511 static struct clk_branch gcc_disp_hf_axi_clk = {
1512         .halt_reg = 0x2700c,
1513         .halt_check = BRANCH_HALT_SKIP,
1514         .hwcg_reg = 0x2700c,
1515         .hwcg_bit = 1,
1516         .clkr = {
1517                 .enable_reg = 0x2700c,
1518                 .enable_mask = BIT(0),
1519                 .hw.init = &(struct clk_init_data){
1520                         .name = "gcc_disp_hf_axi_clk",
1521                         .ops = &clk_branch2_ops,
1522                 },
1523         },
1524 };
1525
1526 static struct clk_branch gcc_disp_sf_axi_clk = {
1527         .halt_reg = 0x27014,
1528         .halt_check = BRANCH_HALT_SKIP,
1529         .hwcg_reg = 0x27014,
1530         .hwcg_bit = 1,
1531         .clkr = {
1532                 .enable_reg = 0x27014,
1533                 .enable_mask = BIT(0),
1534                 .hw.init = &(struct clk_init_data){
1535                         .name = "gcc_disp_sf_axi_clk",
1536                         .ops = &clk_branch2_ops,
1537                 },
1538         },
1539 };
1540
1541 static struct clk_branch gcc_gp1_clk = {
1542         .halt_reg = 0x64000,
1543         .halt_check = BRANCH_HALT,
1544         .clkr = {
1545                 .enable_reg = 0x64000,
1546                 .enable_mask = BIT(0),
1547                 .hw.init = &(struct clk_init_data){
1548                         .name = "gcc_gp1_clk",
1549                         .parent_hws = (const struct clk_hw*[]){
1550                                 &gcc_gp1_clk_src.clkr.hw,
1551                         },
1552                         .num_parents = 1,
1553                         .flags = CLK_SET_RATE_PARENT,
1554                         .ops = &clk_branch2_ops,
1555                 },
1556         },
1557 };
1558
1559 static struct clk_branch gcc_gp2_clk = {
1560         .halt_reg = 0x65000,
1561         .halt_check = BRANCH_HALT,
1562         .clkr = {
1563                 .enable_reg = 0x65000,
1564                 .enable_mask = BIT(0),
1565                 .hw.init = &(struct clk_init_data){
1566                         .name = "gcc_gp2_clk",
1567                         .parent_hws = (const struct clk_hw*[]){
1568                                 &gcc_gp2_clk_src.clkr.hw,
1569                         },
1570                         .num_parents = 1,
1571                         .flags = CLK_SET_RATE_PARENT,
1572                         .ops = &clk_branch2_ops,
1573                 },
1574         },
1575 };
1576
1577 static struct clk_branch gcc_gp3_clk = {
1578         .halt_reg = 0x66000,
1579         .halt_check = BRANCH_HALT,
1580         .clkr = {
1581                 .enable_reg = 0x66000,
1582                 .enable_mask = BIT(0),
1583                 .hw.init = &(struct clk_init_data){
1584                         .name = "gcc_gp3_clk",
1585                         .parent_hws = (const struct clk_hw*[]){
1586                                 &gcc_gp3_clk_src.clkr.hw,
1587                         },
1588                         .num_parents = 1,
1589                         .flags = CLK_SET_RATE_PARENT,
1590                         .ops = &clk_branch2_ops,
1591                 },
1592         },
1593 };
1594
1595 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1596         .halt_check = BRANCH_HALT_DELAY,
1597         .clkr = {
1598                 .enable_reg = 0x52000,
1599                 .enable_mask = BIT(15),
1600                 .hw.init = &(struct clk_init_data){
1601                         .name = "gcc_gpu_gpll0_clk_src",
1602                         .parent_hws = (const struct clk_hw*[]){
1603                                 &gcc_gpll0.clkr.hw,
1604                         },
1605                         .num_parents = 1,
1606                         .flags = CLK_SET_RATE_PARENT,
1607                         .ops = &clk_branch2_ops,
1608                 },
1609         },
1610 };
1611
1612 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1613         .halt_check = BRANCH_HALT_DELAY,
1614         .clkr = {
1615                 .enable_reg = 0x52000,
1616                 .enable_mask = BIT(16),
1617                 .hw.init = &(struct clk_init_data){
1618                         .name = "gcc_gpu_gpll0_div_clk_src",
1619                         .parent_hws = (const struct clk_hw*[]){
1620                                 &gcc_gpll0_out_even.clkr.hw,
1621                         },
1622                         .num_parents = 1,
1623                         .flags = CLK_SET_RATE_PARENT,
1624                         .ops = &clk_branch2_ops,
1625                 },
1626         },
1627 };
1628
1629 static struct clk_branch gcc_gpu_iref_en = {
1630         .halt_reg = 0x8c014,
1631         .halt_check = BRANCH_HALT,
1632         .clkr = {
1633                 .enable_reg = 0x8c014,
1634                 .enable_mask = BIT(0),
1635                 .hw.init = &(struct clk_init_data){
1636                         .name = "gcc_gpu_iref_en",
1637                         .ops = &clk_branch2_ops,
1638                 },
1639         },
1640 };
1641
1642 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1643         .halt_reg = 0x7100c,
1644         .halt_check = BRANCH_HALT_VOTED,
1645         .hwcg_reg = 0x7100c,
1646         .hwcg_bit = 1,
1647         .clkr = {
1648                 .enable_reg = 0x7100c,
1649                 .enable_mask = BIT(0),
1650                 .hw.init = &(struct clk_init_data){
1651                         .name = "gcc_gpu_memnoc_gfx_clk",
1652                         .ops = &clk_branch2_aon_ops,
1653                 },
1654         },
1655 };
1656
1657 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1658         .halt_reg = 0x71018,
1659         .halt_check = BRANCH_HALT,
1660         .clkr = {
1661                 .enable_reg = 0x71018,
1662                 .enable_mask = BIT(0),
1663                 .hw.init = &(struct clk_init_data){
1664                         .name = "gcc_gpu_snoc_dvm_gfx_clk",
1665                         .ops = &clk_branch2_aon_ops,
1666                 },
1667         },
1668 };
1669
1670 static struct clk_branch gcc_pcie0_phy_rchng_clk = {
1671         .halt_reg = 0x6b038,
1672         .halt_check = BRANCH_HALT_VOTED,
1673         .clkr = {
1674                 .enable_reg = 0x52000,
1675                 .enable_mask = BIT(22),
1676                 .hw.init = &(struct clk_init_data){
1677                         .name = "gcc_pcie0_phy_rchng_clk",
1678                         .parent_hws = (const struct clk_hw*[]){
1679                                 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
1680                         },
1681                         .num_parents = 1,
1682                         .flags = CLK_SET_RATE_PARENT,
1683                         .ops = &clk_branch2_ops,
1684                 },
1685         },
1686 };
1687
1688 static struct clk_branch gcc_pcie1_phy_rchng_clk = {
1689         .halt_reg = 0x8d038,
1690         .halt_check = BRANCH_HALT_VOTED,
1691         .clkr = {
1692                 .enable_reg = 0x52000,
1693                 .enable_mask = BIT(23),
1694                 .hw.init = &(struct clk_init_data){
1695                         .name = "gcc_pcie1_phy_rchng_clk",
1696                         .parent_hws = (const struct clk_hw*[]){
1697                                 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
1698                         },
1699                         .num_parents = 1,
1700                         .flags = CLK_SET_RATE_PARENT,
1701                         .ops = &clk_branch2_ops,
1702                 },
1703         },
1704 };
1705
1706 static struct clk_branch gcc_pcie_0_aux_clk = {
1707         .halt_reg = 0x6b028,
1708         .halt_check = BRANCH_HALT_VOTED,
1709         .clkr = {
1710                 .enable_reg = 0x52008,
1711                 .enable_mask = BIT(3),
1712                 .hw.init = &(struct clk_init_data){
1713                         .name = "gcc_pcie_0_aux_clk",
1714                         .parent_hws = (const struct clk_hw*[]){
1715                                 &gcc_pcie_0_aux_clk_src.clkr.hw,
1716                         },
1717                         .num_parents = 1,
1718                         .flags = CLK_SET_RATE_PARENT,
1719                         .ops = &clk_branch2_ops,
1720                 },
1721         },
1722 };
1723
1724 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1725         .halt_reg = 0x6b024,
1726         .halt_check = BRANCH_HALT_VOTED,
1727         .hwcg_reg = 0x6b024,
1728         .hwcg_bit = 1,
1729         .clkr = {
1730                 .enable_reg = 0x52008,
1731                 .enable_mask = BIT(2),
1732                 .hw.init = &(struct clk_init_data){
1733                         .name = "gcc_pcie_0_cfg_ahb_clk",
1734                         .ops = &clk_branch2_ops,
1735                 },
1736         },
1737 };
1738
1739 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1740         .halt_reg = 0x6b01c,
1741         .halt_check = BRANCH_HALT_SKIP,
1742         .clkr = {
1743                 .enable_reg = 0x52008,
1744                 .enable_mask = BIT(1),
1745                 .hw.init = &(struct clk_init_data){
1746                         .name = "gcc_pcie_0_mstr_axi_clk",
1747                         .ops = &clk_branch2_ops,
1748                 },
1749         },
1750 };
1751
1752 static struct clk_branch gcc_pcie_0_pipe_clk = {
1753         .halt_reg = 0x6b030,
1754         .halt_check = BRANCH_HALT_SKIP,
1755         .clkr = {
1756                 .enable_reg = 0x52008,
1757                 .enable_mask = BIT(4),
1758                 .hw.init = &(struct clk_init_data){
1759                         .name = "gcc_pcie_0_pipe_clk",
1760                         .parent_hws = (const struct clk_hw*[]){
1761                                 &gcc_pcie_0_pipe_clk_src.clkr.hw,
1762                         },
1763                         .num_parents = 1,
1764                         .flags = CLK_SET_RATE_PARENT,
1765                         .ops = &clk_branch2_ops,
1766                 },
1767         },
1768 };
1769
1770 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1771         .halt_reg = 0x6b014,
1772         .halt_check = BRANCH_HALT_VOTED,
1773         .clkr = {
1774                 .enable_reg = 0x52008,
1775                 .enable_mask = BIT(0),
1776                 .hw.init = &(struct clk_init_data){
1777                         .name = "gcc_pcie_0_slv_axi_clk",
1778                         .ops = &clk_branch2_ops,
1779                 },
1780         },
1781 };
1782
1783 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1784         .halt_reg = 0x6b010,
1785         .halt_check = BRANCH_HALT_VOTED,
1786         .clkr = {
1787                 .enable_reg = 0x52008,
1788                 .enable_mask = BIT(5),
1789                 .hw.init = &(struct clk_init_data){
1790                         .name = "gcc_pcie_0_slv_q2a_axi_clk",
1791                         .ops = &clk_branch2_ops,
1792                 },
1793         },
1794 };
1795
1796 static struct clk_branch gcc_pcie_1_aux_clk = {
1797         .halt_reg = 0x8d028,
1798         .halt_check = BRANCH_HALT_VOTED,
1799         .clkr = {
1800                 .enable_reg = 0x52000,
1801                 .enable_mask = BIT(29),
1802                 .hw.init = &(struct clk_init_data){
1803                         .name = "gcc_pcie_1_aux_clk",
1804                         .parent_hws = (const struct clk_hw*[]){
1805                                 &gcc_pcie_1_aux_clk_src.clkr.hw,
1806                         },
1807                         .num_parents = 1,
1808                         .flags = CLK_SET_RATE_PARENT,
1809                         .ops = &clk_branch2_ops,
1810                 },
1811         },
1812 };
1813
1814 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1815         .halt_reg = 0x8d024,
1816         .halt_check = BRANCH_HALT_VOTED,
1817         .hwcg_reg = 0x8d024,
1818         .hwcg_bit = 1,
1819         .clkr = {
1820                 .enable_reg = 0x52000,
1821                 .enable_mask = BIT(28),
1822                 .hw.init = &(struct clk_init_data){
1823                         .name = "gcc_pcie_1_cfg_ahb_clk",
1824                         .ops = &clk_branch2_ops,
1825                 },
1826         },
1827 };
1828
1829 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1830         .halt_reg = 0x8d01c,
1831         .halt_check = BRANCH_HALT_SKIP,
1832         .clkr = {
1833                 .enable_reg = 0x52000,
1834                 .enable_mask = BIT(27),
1835                 .hw.init = &(struct clk_init_data){
1836                         .name = "gcc_pcie_1_mstr_axi_clk",
1837                         .ops = &clk_branch2_ops,
1838                 },
1839         },
1840 };
1841
1842 static struct clk_branch gcc_pcie_1_pipe_clk = {
1843         .halt_reg = 0x8d030,
1844         .halt_check = BRANCH_HALT_SKIP,
1845         .clkr = {
1846                 .enable_reg = 0x52000,
1847                 .enable_mask = BIT(30),
1848                 .hw.init = &(struct clk_init_data){
1849                         .name = "gcc_pcie_1_pipe_clk",
1850                         .parent_hws = (const struct clk_hw*[]){
1851                                 &gcc_pcie_1_pipe_clk_src.clkr.hw,
1852                         },
1853                         .num_parents = 1,
1854                         .flags = CLK_SET_RATE_PARENT,
1855                         .ops = &clk_branch2_ops,
1856                 },
1857         },
1858 };
1859
1860 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1861         .halt_reg = 0x8d014,
1862         .halt_check = BRANCH_HALT_VOTED,
1863         .clkr = {
1864                 .enable_reg = 0x52000,
1865                 .enable_mask = BIT(26),
1866                 .hw.init = &(struct clk_init_data){
1867                         .name = "gcc_pcie_1_slv_axi_clk",
1868                         .ops = &clk_branch2_ops,
1869                 },
1870         },
1871 };
1872
1873 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1874         .halt_reg = 0x8d010,
1875         .halt_check = BRANCH_HALT_VOTED,
1876         .clkr = {
1877                 .enable_reg = 0x52000,
1878                 .enable_mask = BIT(25),
1879                 .hw.init = &(struct clk_init_data){
1880                         .name = "gcc_pcie_1_slv_q2a_axi_clk",
1881                         .ops = &clk_branch2_ops,
1882                 },
1883         },
1884 };
1885
1886 static struct clk_branch gcc_pcie_throttle_core_clk = {
1887         .halt_reg = 0x90018,
1888         .halt_check = BRANCH_HALT_SKIP,
1889         .hwcg_reg = 0x90018,
1890         .hwcg_bit = 1,
1891         .clkr = {
1892                 .enable_reg = 0x52000,
1893                 .enable_mask = BIT(20),
1894                 .hw.init = &(struct clk_init_data){
1895                         .name = "gcc_pcie_throttle_core_clk",
1896                         .ops = &clk_branch2_ops,
1897                 },
1898         },
1899 };
1900
1901 static struct clk_branch gcc_pdm2_clk = {
1902         .halt_reg = 0x3300c,
1903         .halt_check = BRANCH_HALT,
1904         .clkr = {
1905                 .enable_reg = 0x3300c,
1906                 .enable_mask = BIT(0),
1907                 .hw.init = &(struct clk_init_data){
1908                         .name = "gcc_pdm2_clk",
1909                         .parent_hws = (const struct clk_hw*[]){
1910                                 &gcc_pdm2_clk_src.clkr.hw,
1911                         },
1912                         .num_parents = 1,
1913                         .flags = CLK_SET_RATE_PARENT,
1914                         .ops = &clk_branch2_ops,
1915                 },
1916         },
1917 };
1918
1919 static struct clk_branch gcc_pdm_ahb_clk = {
1920         .halt_reg = 0x33004,
1921         .halt_check = BRANCH_HALT_VOTED,
1922         .hwcg_reg = 0x33004,
1923         .hwcg_bit = 1,
1924         .clkr = {
1925                 .enable_reg = 0x33004,
1926                 .enable_mask = BIT(0),
1927                 .hw.init = &(struct clk_init_data){
1928                         .name = "gcc_pdm_ahb_clk",
1929                         .ops = &clk_branch2_ops,
1930                 },
1931         },
1932 };
1933
1934 static struct clk_branch gcc_pdm_xo4_clk = {
1935         .halt_reg = 0x33008,
1936         .halt_check = BRANCH_HALT,
1937         .clkr = {
1938                 .enable_reg = 0x33008,
1939                 .enable_mask = BIT(0),
1940                 .hw.init = &(struct clk_init_data){
1941                         .name = "gcc_pdm_xo4_clk",
1942                         .ops = &clk_branch2_ops,
1943                 },
1944         },
1945 };
1946
1947 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
1948         .halt_reg = 0x26008,
1949         .halt_check = BRANCH_HALT_VOTED,
1950         .hwcg_reg = 0x26008,
1951         .hwcg_bit = 1,
1952         .clkr = {
1953                 .enable_reg = 0x26008,
1954                 .enable_mask = BIT(0),
1955                 .hw.init = &(struct clk_init_data){
1956                         .name = "gcc_qmip_camera_nrt_ahb_clk",
1957                         .ops = &clk_branch2_ops,
1958                 },
1959         },
1960 };
1961
1962 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
1963         .halt_reg = 0x2600c,
1964         .halt_check = BRANCH_HALT_VOTED,
1965         .hwcg_reg = 0x2600c,
1966         .hwcg_bit = 1,
1967         .clkr = {
1968                 .enable_reg = 0x2600c,
1969                 .enable_mask = BIT(0),
1970                 .hw.init = &(struct clk_init_data){
1971                         .name = "gcc_qmip_camera_rt_ahb_clk",
1972                         .ops = &clk_branch2_ops,
1973                 },
1974         },
1975 };
1976
1977 static struct clk_branch gcc_qmip_disp_ahb_clk = {
1978         .halt_reg = 0x27008,
1979         .halt_check = BRANCH_HALT_VOTED,
1980         .clkr = {
1981                 .enable_reg = 0x27008,
1982                 .enable_mask = BIT(0),
1983                 .hw.init = &(struct clk_init_data){
1984                         .name = "gcc_qmip_disp_ahb_clk",
1985                         .ops = &clk_branch2_ops,
1986                 },
1987         },
1988 };
1989
1990 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
1991         .halt_reg = 0x28008,
1992         .halt_check = BRANCH_HALT_VOTED,
1993         .hwcg_reg = 0x28008,
1994         .hwcg_bit = 1,
1995         .clkr = {
1996                 .enable_reg = 0x28008,
1997                 .enable_mask = BIT(0),
1998                 .hw.init = &(struct clk_init_data){
1999                         .name = "gcc_qmip_video_vcodec_ahb_clk",
2000                         .ops = &clk_branch2_ops,
2001                 },
2002         },
2003 };
2004
2005 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
2006         .halt_reg = 0x4b004,
2007         .halt_check = BRANCH_HALT,
2008         .hwcg_reg = 0x4b004,
2009         .hwcg_bit = 1,
2010         .clkr = {
2011                 .enable_reg = 0x4b004,
2012                 .enable_mask = BIT(0),
2013                 .hw.init = &(struct clk_init_data){
2014                         .name = "gcc_qspi_cnoc_periph_ahb_clk",
2015                         .ops = &clk_branch2_ops,
2016                 },
2017         },
2018 };
2019
2020 static struct clk_branch gcc_qspi_core_clk = {
2021         .halt_reg = 0x4b008,
2022         .halt_check = BRANCH_HALT,
2023         .clkr = {
2024                 .enable_reg = 0x4b008,
2025                 .enable_mask = BIT(0),
2026                 .hw.init = &(struct clk_init_data){
2027                         .name = "gcc_qspi_core_clk",
2028                         .parent_hws = (const struct clk_hw*[]){
2029                                 &gcc_qspi_core_clk_src.clkr.hw,
2030                         },
2031                         .num_parents = 1,
2032                         .flags = CLK_SET_RATE_PARENT,
2033                         .ops = &clk_branch2_ops,
2034                 },
2035         },
2036 };
2037
2038 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2039         .halt_reg = 0x23008,
2040         .halt_check = BRANCH_HALT_VOTED,
2041         .clkr = {
2042                 .enable_reg = 0x52008,
2043                 .enable_mask = BIT(9),
2044                 .hw.init = &(struct clk_init_data){
2045                         .name = "gcc_qupv3_wrap0_core_2x_clk",
2046                         .ops = &clk_branch2_ops,
2047                 },
2048         },
2049 };
2050
2051 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2052         .halt_reg = 0x23000,
2053         .halt_check = BRANCH_HALT_VOTED,
2054         .clkr = {
2055                 .enable_reg = 0x52008,
2056                 .enable_mask = BIT(8),
2057                 .hw.init = &(struct clk_init_data){
2058                         .name = "gcc_qupv3_wrap0_core_clk",
2059                         .ops = &clk_branch2_ops,
2060                 },
2061         },
2062 };
2063
2064 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2065         .halt_reg = 0x1700c,
2066         .halt_check = BRANCH_HALT_VOTED,
2067         .clkr = {
2068                 .enable_reg = 0x52008,
2069                 .enable_mask = BIT(10),
2070                 .hw.init = &(struct clk_init_data){
2071                         .name = "gcc_qupv3_wrap0_s0_clk",
2072                         .parent_hws = (const struct clk_hw*[]){
2073                                 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2074                         },
2075                         .num_parents = 1,
2076                         .flags = CLK_SET_RATE_PARENT,
2077                         .ops = &clk_branch2_ops,
2078                 },
2079         },
2080 };
2081
2082 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2083         .halt_reg = 0x1713c,
2084         .halt_check = BRANCH_HALT_VOTED,
2085         .clkr = {
2086                 .enable_reg = 0x52008,
2087                 .enable_mask = BIT(11),
2088                 .hw.init = &(struct clk_init_data){
2089                         .name = "gcc_qupv3_wrap0_s1_clk",
2090                         .parent_hws = (const struct clk_hw*[]){
2091                                 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2092                         },
2093                         .num_parents = 1,
2094                         .flags = CLK_SET_RATE_PARENT,
2095                         .ops = &clk_branch2_ops,
2096                 },
2097         },
2098 };
2099
2100 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2101         .halt_reg = 0x1726c,
2102         .halt_check = BRANCH_HALT_VOTED,
2103         .clkr = {
2104                 .enable_reg = 0x52008,
2105                 .enable_mask = BIT(12),
2106                 .hw.init = &(struct clk_init_data){
2107                         .name = "gcc_qupv3_wrap0_s2_clk",
2108                         .parent_hws = (const struct clk_hw*[]){
2109                                 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2110                         },
2111                         .num_parents = 1,
2112                         .flags = CLK_SET_RATE_PARENT,
2113                         .ops = &clk_branch2_ops,
2114                 },
2115         },
2116 };
2117
2118 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2119         .halt_reg = 0x1739c,
2120         .halt_check = BRANCH_HALT_VOTED,
2121         .clkr = {
2122                 .enable_reg = 0x52008,
2123                 .enable_mask = BIT(13),
2124                 .hw.init = &(struct clk_init_data){
2125                         .name = "gcc_qupv3_wrap0_s3_clk",
2126                         .parent_hws = (const struct clk_hw*[]){
2127                                 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2128                         },
2129                         .num_parents = 1,
2130                         .flags = CLK_SET_RATE_PARENT,
2131                         .ops = &clk_branch2_ops,
2132                 },
2133         },
2134 };
2135
2136 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2137         .halt_reg = 0x174cc,
2138         .halt_check = BRANCH_HALT_VOTED,
2139         .clkr = {
2140                 .enable_reg = 0x52008,
2141                 .enable_mask = BIT(14),
2142                 .hw.init = &(struct clk_init_data){
2143                         .name = "gcc_qupv3_wrap0_s4_clk",
2144                         .parent_hws = (const struct clk_hw*[]){
2145                                 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2146                         },
2147                         .num_parents = 1,
2148                         .flags = CLK_SET_RATE_PARENT,
2149                         .ops = &clk_branch2_ops,
2150                 },
2151         },
2152 };
2153
2154 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2155         .halt_reg = 0x175fc,
2156         .halt_check = BRANCH_HALT_VOTED,
2157         .clkr = {
2158                 .enable_reg = 0x52008,
2159                 .enable_mask = BIT(15),
2160                 .hw.init = &(struct clk_init_data){
2161                         .name = "gcc_qupv3_wrap0_s5_clk",
2162                         .parent_hws = (const struct clk_hw*[]){
2163                                 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2164                         },
2165                         .num_parents = 1,
2166                         .flags = CLK_SET_RATE_PARENT,
2167                         .ops = &clk_branch2_ops,
2168                 },
2169         },
2170 };
2171
2172 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2173         .halt_reg = 0x1772c,
2174         .halt_check = BRANCH_HALT_VOTED,
2175         .clkr = {
2176                 .enable_reg = 0x52008,
2177                 .enable_mask = BIT(16),
2178                 .hw.init = &(struct clk_init_data){
2179                         .name = "gcc_qupv3_wrap0_s6_clk",
2180                         .parent_hws = (const struct clk_hw*[]){
2181                                 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
2182                         },
2183                         .num_parents = 1,
2184                         .flags = CLK_SET_RATE_PARENT,
2185                         .ops = &clk_branch2_ops,
2186                 },
2187         },
2188 };
2189
2190 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2191         .halt_reg = 0x1785c,
2192         .halt_check = BRANCH_HALT_VOTED,
2193         .clkr = {
2194                 .enable_reg = 0x52008,
2195                 .enable_mask = BIT(17),
2196                 .hw.init = &(struct clk_init_data){
2197                         .name = "gcc_qupv3_wrap0_s7_clk",
2198                         .parent_hws = (const struct clk_hw*[]){
2199                                 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
2200                         },
2201                         .num_parents = 1,
2202                         .flags = CLK_SET_RATE_PARENT,
2203                         .ops = &clk_branch2_ops,
2204                 },
2205         },
2206 };
2207
2208 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
2209         .halt_reg = 0x23140,
2210         .halt_check = BRANCH_HALT_VOTED,
2211         .clkr = {
2212                 .enable_reg = 0x52008,
2213                 .enable_mask = BIT(18),
2214                 .hw.init = &(struct clk_init_data){
2215                         .name = "gcc_qupv3_wrap1_core_2x_clk",
2216                         .ops = &clk_branch2_ops,
2217                 },
2218         },
2219 };
2220
2221 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
2222         .halt_reg = 0x23138,
2223         .halt_check = BRANCH_HALT_VOTED,
2224         .clkr = {
2225                 .enable_reg = 0x52008,
2226                 .enable_mask = BIT(19),
2227                 .hw.init = &(struct clk_init_data){
2228                         .name = "gcc_qupv3_wrap1_core_clk",
2229                         .ops = &clk_branch2_ops,
2230                 },
2231         },
2232 };
2233
2234 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2235         .halt_reg = 0x1800c,
2236         .halt_check = BRANCH_HALT_VOTED,
2237         .clkr = {
2238                 .enable_reg = 0x52008,
2239                 .enable_mask = BIT(22),
2240                 .hw.init = &(struct clk_init_data){
2241                         .name = "gcc_qupv3_wrap1_s0_clk",
2242                         .parent_hws = (const struct clk_hw*[]){
2243                                 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2244                         },
2245                         .num_parents = 1,
2246                         .flags = CLK_SET_RATE_PARENT,
2247                         .ops = &clk_branch2_ops,
2248                 },
2249         },
2250 };
2251
2252 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2253         .halt_reg = 0x1813c,
2254         .halt_check = BRANCH_HALT_VOTED,
2255         .clkr = {
2256                 .enable_reg = 0x52008,
2257                 .enable_mask = BIT(23),
2258                 .hw.init = &(struct clk_init_data){
2259                         .name = "gcc_qupv3_wrap1_s1_clk",
2260                         .parent_hws = (const struct clk_hw*[]){
2261                                 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2262                         },
2263                         .num_parents = 1,
2264                         .flags = CLK_SET_RATE_PARENT,
2265                         .ops = &clk_branch2_ops,
2266                 },
2267         },
2268 };
2269
2270 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2271         .halt_reg = 0x1826c,
2272         .halt_check = BRANCH_HALT_VOTED,
2273         .clkr = {
2274                 .enable_reg = 0x52008,
2275                 .enable_mask = BIT(24),
2276                 .hw.init = &(struct clk_init_data){
2277                         .name = "gcc_qupv3_wrap1_s2_clk",
2278                         .parent_hws = (const struct clk_hw*[]){
2279                                 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2280                         },
2281                         .num_parents = 1,
2282                         .flags = CLK_SET_RATE_PARENT,
2283                         .ops = &clk_branch2_ops,
2284                 },
2285         },
2286 };
2287
2288 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2289         .halt_reg = 0x1839c,
2290         .halt_check = BRANCH_HALT_VOTED,
2291         .clkr = {
2292                 .enable_reg = 0x52008,
2293                 .enable_mask = BIT(25),
2294                 .hw.init = &(struct clk_init_data){
2295                         .name = "gcc_qupv3_wrap1_s3_clk",
2296                         .parent_hws = (const struct clk_hw*[]){
2297                                 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2298                         },
2299                         .num_parents = 1,
2300                         .flags = CLK_SET_RATE_PARENT,
2301                         .ops = &clk_branch2_ops,
2302                 },
2303         },
2304 };
2305
2306 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2307         .halt_reg = 0x184cc,
2308         .halt_check = BRANCH_HALT_VOTED,
2309         .clkr = {
2310                 .enable_reg = 0x52008,
2311                 .enable_mask = BIT(26),
2312                 .hw.init = &(struct clk_init_data){
2313                         .name = "gcc_qupv3_wrap1_s4_clk",
2314                         .parent_hws = (const struct clk_hw*[]){
2315                                 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2316                         },
2317                         .num_parents = 1,
2318                         .flags = CLK_SET_RATE_PARENT,
2319                         .ops = &clk_branch2_ops,
2320                 },
2321         },
2322 };
2323
2324 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2325         .halt_reg = 0x185fc,
2326         .halt_check = BRANCH_HALT_VOTED,
2327         .clkr = {
2328                 .enable_reg = 0x52008,
2329                 .enable_mask = BIT(27),
2330                 .hw.init = &(struct clk_init_data){
2331                         .name = "gcc_qupv3_wrap1_s5_clk",
2332                         .parent_hws = (const struct clk_hw*[]){
2333                                 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2334                         },
2335                         .num_parents = 1,
2336                         .flags = CLK_SET_RATE_PARENT,
2337                         .ops = &clk_branch2_ops,
2338                 },
2339         },
2340 };
2341
2342 static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
2343         .halt_reg = 0x1872c,
2344         .halt_check = BRANCH_HALT_VOTED,
2345         .clkr = {
2346                 .enable_reg = 0x52000,
2347                 .enable_mask = BIT(13),
2348                 .hw.init = &(struct clk_init_data){
2349                         .name = "gcc_qupv3_wrap1_s6_clk",
2350                         .parent_hws = (const struct clk_hw*[]){
2351                                 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
2352                         },
2353                         .num_parents = 1,
2354                         .flags = CLK_SET_RATE_PARENT,
2355                         .ops = &clk_branch2_ops,
2356                 },
2357         },
2358 };
2359
2360 static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
2361         .halt_reg = 0x1885c,
2362         .halt_check = BRANCH_HALT_VOTED,
2363         .clkr = {
2364                 .enable_reg = 0x52000,
2365                 .enable_mask = BIT(14),
2366                 .hw.init = &(struct clk_init_data){
2367                         .name = "gcc_qupv3_wrap1_s7_clk",
2368                         .parent_hws = (const struct clk_hw*[]){
2369                                 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
2370                         },
2371                         .num_parents = 1,
2372                         .flags = CLK_SET_RATE_PARENT,
2373                         .ops = &clk_branch2_ops,
2374                 },
2375         },
2376 };
2377
2378 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2379         .halt_reg = 0x17004,
2380         .halt_check = BRANCH_HALT_VOTED,
2381         .hwcg_reg = 0x17004,
2382         .hwcg_bit = 1,
2383         .clkr = {
2384                 .enable_reg = 0x52008,
2385                 .enable_mask = BIT(6),
2386                 .hw.init = &(struct clk_init_data){
2387                         .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2388                         .ops = &clk_branch2_ops,
2389                 },
2390         },
2391 };
2392
2393 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2394         .halt_reg = 0x17008,
2395         .halt_check = BRANCH_HALT_VOTED,
2396         .hwcg_reg = 0x17008,
2397         .hwcg_bit = 1,
2398         .clkr = {
2399                 .enable_reg = 0x52008,
2400                 .enable_mask = BIT(7),
2401                 .hw.init = &(struct clk_init_data){
2402                         .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2403                         .ops = &clk_branch2_ops,
2404                 },
2405         },
2406 };
2407
2408 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2409         .halt_reg = 0x18004,
2410         .halt_check = BRANCH_HALT_VOTED,
2411         .hwcg_reg = 0x18004,
2412         .hwcg_bit = 1,
2413         .clkr = {
2414                 .enable_reg = 0x52008,
2415                 .enable_mask = BIT(20),
2416                 .hw.init = &(struct clk_init_data){
2417                         .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2418                         .ops = &clk_branch2_ops,
2419                 },
2420         },
2421 };
2422
2423 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2424         .halt_reg = 0x18008,
2425         .halt_check = BRANCH_HALT_VOTED,
2426         .hwcg_reg = 0x18008,
2427         .hwcg_bit = 1,
2428         .clkr = {
2429                 .enable_reg = 0x52008,
2430                 .enable_mask = BIT(21),
2431                 .hw.init = &(struct clk_init_data){
2432                         .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2433                         .ops = &clk_branch2_ops,
2434                 },
2435         },
2436 };
2437
2438 static struct clk_branch gcc_sdcc1_ahb_clk = {
2439         .halt_reg = 0x75004,
2440         .halt_check = BRANCH_HALT,
2441         .clkr = {
2442                 .enable_reg = 0x75004,
2443                 .enable_mask = BIT(0),
2444                 .hw.init = &(struct clk_init_data){
2445                         .name = "gcc_sdcc1_ahb_clk",
2446                         .ops = &clk_branch2_ops,
2447                 },
2448         },
2449 };
2450
2451 static struct clk_branch gcc_sdcc1_apps_clk = {
2452         .halt_reg = 0x75008,
2453         .halt_check = BRANCH_HALT,
2454         .clkr = {
2455                 .enable_reg = 0x75008,
2456                 .enable_mask = BIT(0),
2457                 .hw.init = &(struct clk_init_data){
2458                         .name = "gcc_sdcc1_apps_clk",
2459                         .parent_hws = (const struct clk_hw*[]){
2460                                 &gcc_sdcc1_apps_clk_src.clkr.hw,
2461                         },
2462                         .num_parents = 1,
2463                         .flags = CLK_SET_RATE_PARENT,
2464                         .ops = &clk_branch2_ops,
2465                 },
2466         },
2467 };
2468
2469 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2470         .halt_reg = 0x75024,
2471         .halt_check = BRANCH_HALT_VOTED,
2472         .hwcg_reg = 0x75024,
2473         .hwcg_bit = 1,
2474         .clkr = {
2475                 .enable_reg = 0x75024,
2476                 .enable_mask = BIT(0),
2477                 .hw.init = &(struct clk_init_data){
2478                         .name = "gcc_sdcc1_ice_core_clk",
2479                         .parent_hws = (const struct clk_hw*[]){
2480                                 &gcc_sdcc1_ice_core_clk_src.clkr.hw,
2481                         },
2482                         .num_parents = 1,
2483                         .flags = CLK_SET_RATE_PARENT,
2484                         .ops = &clk_branch2_ops,
2485                 },
2486         },
2487 };
2488
2489 static struct clk_branch gcc_sdcc2_ahb_clk = {
2490         .halt_reg = 0x14008,
2491         .halt_check = BRANCH_HALT,
2492         .clkr = {
2493                 .enable_reg = 0x14008,
2494                 .enable_mask = BIT(0),
2495                 .hw.init = &(struct clk_init_data){
2496                         .name = "gcc_sdcc2_ahb_clk",
2497                         .ops = &clk_branch2_ops,
2498                 },
2499         },
2500 };
2501
2502 static struct clk_branch gcc_sdcc2_apps_clk = {
2503         .halt_reg = 0x14004,
2504         .halt_check = BRANCH_HALT,
2505         .clkr = {
2506                 .enable_reg = 0x14004,
2507                 .enable_mask = BIT(0),
2508                 .hw.init = &(struct clk_init_data){
2509                         .name = "gcc_sdcc2_apps_clk",
2510                         .parent_hws = (const struct clk_hw*[]){
2511                                 &gcc_sdcc2_apps_clk_src.clkr.hw,
2512                         },
2513                         .num_parents = 1,
2514                         .flags = CLK_SET_RATE_PARENT,
2515                         .ops = &clk_branch2_ops,
2516                 },
2517         },
2518 };
2519
2520 static struct clk_branch gcc_sdcc4_ahb_clk = {
2521         .halt_reg = 0x16008,
2522         .halt_check = BRANCH_HALT,
2523         .clkr = {
2524                 .enable_reg = 0x16008,
2525                 .enable_mask = BIT(0),
2526                 .hw.init = &(struct clk_init_data){
2527                         .name = "gcc_sdcc4_ahb_clk",
2528                         .ops = &clk_branch2_ops,
2529                 },
2530         },
2531 };
2532
2533 static struct clk_branch gcc_sdcc4_apps_clk = {
2534         .halt_reg = 0x16004,
2535         .halt_check = BRANCH_HALT,
2536         .clkr = {
2537                 .enable_reg = 0x16004,
2538                 .enable_mask = BIT(0),
2539                 .hw.init = &(struct clk_init_data){
2540                         .name = "gcc_sdcc4_apps_clk",
2541                         .parent_hws = (const struct clk_hw*[]){
2542                                 &gcc_sdcc4_apps_clk_src.clkr.hw,
2543                         },
2544                         .num_parents = 1,
2545                         .flags = CLK_SET_RATE_PARENT,
2546                         .ops = &clk_branch2_ops,
2547                 },
2548         },
2549 };
2550
2551 static struct clk_branch gcc_throttle_pcie_ahb_clk = {
2552         .halt_reg = 0x9001c,
2553         .halt_check = BRANCH_HALT,
2554         .clkr = {
2555                 .enable_reg = 0x9001c,
2556                 .enable_mask = BIT(0),
2557                 .hw.init = &(struct clk_init_data){
2558                         .name = "gcc_throttle_pcie_ahb_clk",
2559                         .ops = &clk_branch2_ops,
2560                 },
2561         },
2562 };
2563
2564 static struct clk_branch gcc_titan_nrt_throttle_core_clk = {
2565         .halt_reg = 0x26024,
2566         .halt_check = BRANCH_HALT_SKIP,
2567         .hwcg_reg = 0x26024,
2568         .hwcg_bit = 1,
2569         .clkr = {
2570                 .enable_reg = 0x26024,
2571                 .enable_mask = BIT(0),
2572                 .hw.init = &(struct clk_init_data){
2573                         .name = "gcc_titan_nrt_throttle_core_clk",
2574                         .ops = &clk_branch2_ops,
2575                 },
2576         },
2577 };
2578
2579 static struct clk_branch gcc_titan_rt_throttle_core_clk = {
2580         .halt_reg = 0x26018,
2581         .halt_check = BRANCH_HALT_SKIP,
2582         .hwcg_reg = 0x26018,
2583         .hwcg_bit = 1,
2584         .clkr = {
2585                 .enable_reg = 0x26018,
2586                 .enable_mask = BIT(0),
2587                 .hw.init = &(struct clk_init_data){
2588                         .name = "gcc_titan_rt_throttle_core_clk",
2589                         .ops = &clk_branch2_ops,
2590                 },
2591         },
2592 };
2593
2594 static struct clk_branch gcc_ufs_1_clkref_en = {
2595         .halt_reg = 0x8c000,
2596         .halt_check = BRANCH_HALT,
2597         .clkr = {
2598                 .enable_reg = 0x8c000,
2599                 .enable_mask = BIT(0),
2600                 .hw.init = &(struct clk_init_data){
2601                         .name = "gcc_ufs_1_clkref_en",
2602                         .ops = &clk_branch2_ops,
2603                 },
2604         },
2605 };
2606
2607 static struct clk_branch gcc_ufs_phy_ahb_clk = {
2608         .halt_reg = 0x77018,
2609         .halt_check = BRANCH_HALT_VOTED,
2610         .hwcg_reg = 0x77018,
2611         .hwcg_bit = 1,
2612         .clkr = {
2613                 .enable_reg = 0x77018,
2614                 .enable_mask = BIT(0),
2615                 .hw.init = &(struct clk_init_data){
2616                         .name = "gcc_ufs_phy_ahb_clk",
2617                         .ops = &clk_branch2_ops,
2618                 },
2619         },
2620 };
2621
2622 static struct clk_branch gcc_ufs_phy_axi_clk = {
2623         .halt_reg = 0x77010,
2624         .halt_check = BRANCH_HALT_VOTED,
2625         .hwcg_reg = 0x77010,
2626         .hwcg_bit = 1,
2627         .clkr = {
2628                 .enable_reg = 0x77010,
2629                 .enable_mask = BIT(0),
2630                 .hw.init = &(struct clk_init_data){
2631                         .name = "gcc_ufs_phy_axi_clk",
2632                         .parent_hws = (const struct clk_hw*[]){
2633                                 &gcc_ufs_phy_axi_clk_src.clkr.hw,
2634                         },
2635                         .num_parents = 1,
2636                         .flags = CLK_SET_RATE_PARENT,
2637                         .ops = &clk_branch2_ops,
2638                 },
2639         },
2640 };
2641
2642 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2643         .halt_reg = 0x77064,
2644         .halt_check = BRANCH_HALT_VOTED,
2645         .hwcg_reg = 0x77064,
2646         .hwcg_bit = 1,
2647         .clkr = {
2648                 .enable_reg = 0x77064,
2649                 .enable_mask = BIT(0),
2650                 .hw.init = &(struct clk_init_data){
2651                         .name = "gcc_ufs_phy_ice_core_clk",
2652                         .parent_hws = (const struct clk_hw*[]){
2653                                 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2654                         },
2655                         .num_parents = 1,
2656                         .flags = CLK_SET_RATE_PARENT,
2657                         .ops = &clk_branch2_ops,
2658                 },
2659         },
2660 };
2661
2662 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2663         .halt_reg = 0x7709c,
2664         .halt_check = BRANCH_HALT_VOTED,
2665         .hwcg_reg = 0x7709c,
2666         .hwcg_bit = 1,
2667         .clkr = {
2668                 .enable_reg = 0x7709c,
2669                 .enable_mask = BIT(0),
2670                 .hw.init = &(struct clk_init_data){
2671                         .name = "gcc_ufs_phy_phy_aux_clk",
2672                         .parent_hws = (const struct clk_hw*[]){
2673                                 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2674                         },
2675                         .num_parents = 1,
2676                         .flags = CLK_SET_RATE_PARENT,
2677                         .ops = &clk_branch2_ops,
2678                 },
2679         },
2680 };
2681
2682 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2683         .halt_reg = 0x77020,
2684         .halt_check = BRANCH_HALT_DELAY,
2685         .clkr = {
2686                 .enable_reg = 0x77020,
2687                 .enable_mask = BIT(0),
2688                 .hw.init = &(struct clk_init_data){
2689                         .name = "gcc_ufs_phy_rx_symbol_0_clk",
2690                         .parent_hws = (const struct clk_hw*[]){
2691                                 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
2692                         },
2693                         .num_parents = 1,
2694                         .flags = CLK_SET_RATE_PARENT,
2695                         .ops = &clk_branch2_ops,
2696                 },
2697         },
2698 };
2699
2700 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2701         .halt_reg = 0x770b8,
2702         .halt_check = BRANCH_HALT_DELAY,
2703         .clkr = {
2704                 .enable_reg = 0x770b8,
2705                 .enable_mask = BIT(0),
2706                 .hw.init = &(struct clk_init_data){
2707                         .name = "gcc_ufs_phy_rx_symbol_1_clk",
2708                         .parent_hws = (const struct clk_hw*[]){
2709                                 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
2710                         },
2711                         .num_parents = 1,
2712                         .flags = CLK_SET_RATE_PARENT,
2713                         .ops = &clk_branch2_ops,
2714                 },
2715         },
2716 };
2717
2718 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2719         .halt_reg = 0x7701c,
2720         .halt_check = BRANCH_HALT_DELAY,
2721         .clkr = {
2722                 .enable_reg = 0x7701c,
2723                 .enable_mask = BIT(0),
2724                 .hw.init = &(struct clk_init_data){
2725                         .name = "gcc_ufs_phy_tx_symbol_0_clk",
2726                         .parent_hws = (const struct clk_hw*[]){
2727                                 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
2728                         },
2729                         .num_parents = 1,
2730                         .flags = CLK_SET_RATE_PARENT,
2731                         .ops = &clk_branch2_ops,
2732                 },
2733         },
2734 };
2735
2736 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2737         .halt_reg = 0x7705c,
2738         .halt_check = BRANCH_HALT_VOTED,
2739         .hwcg_reg = 0x7705c,
2740         .hwcg_bit = 1,
2741         .clkr = {
2742                 .enable_reg = 0x7705c,
2743                 .enable_mask = BIT(0),
2744                 .hw.init = &(struct clk_init_data){
2745                         .name = "gcc_ufs_phy_unipro_core_clk",
2746                         .parent_hws = (const struct clk_hw*[]){
2747                                 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2748                         },
2749                         .num_parents = 1,
2750                         .flags = CLK_SET_RATE_PARENT,
2751                         .ops = &clk_branch2_ops,
2752                 },
2753         },
2754 };
2755
2756 static struct clk_branch gcc_usb30_prim_master_clk = {
2757         .halt_reg = 0xf010,
2758         .halt_check = BRANCH_HALT,
2759         .clkr = {
2760                 .enable_reg = 0xf010,
2761                 .enable_mask = BIT(0),
2762                 .hw.init = &(struct clk_init_data){
2763                         .name = "gcc_usb30_prim_master_clk",
2764                         .parent_hws = (const struct clk_hw*[]){
2765                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
2766                         },
2767                         .num_parents = 1,
2768                         .flags = CLK_SET_RATE_PARENT,
2769                         .ops = &clk_branch2_ops,
2770                 },
2771         },
2772 };
2773
2774 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2775         .halt_reg = 0xf01c,
2776         .halt_check = BRANCH_HALT,
2777         .clkr = {
2778                 .enable_reg = 0xf01c,
2779                 .enable_mask = BIT(0),
2780                 .hw.init = &(struct clk_init_data){
2781                         .name = "gcc_usb30_prim_mock_utmi_clk",
2782                         .parent_data = &(const struct clk_parent_data){
2783                                 .hw =
2784                                         &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
2785                         },
2786                         .num_parents = 1,
2787                         .flags = CLK_SET_RATE_PARENT,
2788                         .ops = &clk_branch2_ops,
2789                 },
2790         },
2791 };
2792
2793 static struct clk_branch gcc_usb30_prim_sleep_clk = {
2794         .halt_reg = 0xf018,
2795         .halt_check = BRANCH_HALT,
2796         .clkr = {
2797                 .enable_reg = 0xf018,
2798                 .enable_mask = BIT(0),
2799                 .hw.init = &(struct clk_init_data){
2800                         .name = "gcc_usb30_prim_sleep_clk",
2801                         .ops = &clk_branch2_ops,
2802                 },
2803         },
2804 };
2805
2806 static struct clk_branch gcc_usb30_sec_master_clk = {
2807         .halt_reg = 0x9e010,
2808         .halt_check = BRANCH_HALT,
2809         .clkr = {
2810                 .enable_reg = 0x9e010,
2811                 .enable_mask = BIT(0),
2812                 .hw.init = &(struct clk_init_data){
2813                         .name = "gcc_usb30_sec_master_clk",
2814                         .parent_hws = (const struct clk_hw*[]){
2815                                 &gcc_usb30_sec_master_clk_src.clkr.hw,
2816                         },
2817                         .num_parents = 1,
2818                         .flags = CLK_SET_RATE_PARENT,
2819                         .ops = &clk_branch2_ops,
2820                 },
2821         },
2822 };
2823
2824 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
2825         .halt_reg = 0x9e01c,
2826         .halt_check = BRANCH_HALT,
2827         .clkr = {
2828                 .enable_reg = 0x9e01c,
2829                 .enable_mask = BIT(0),
2830                 .hw.init = &(struct clk_init_data){
2831                         .name = "gcc_usb30_sec_mock_utmi_clk",
2832                         .parent_data = &(const struct clk_parent_data){
2833                                 .hw =
2834                                         &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
2835                         },
2836                         .num_parents = 1,
2837                         .flags = CLK_SET_RATE_PARENT,
2838                         .ops = &clk_branch2_ops,
2839                 },
2840         },
2841 };
2842
2843 static struct clk_branch gcc_usb30_sec_sleep_clk = {
2844         .halt_reg = 0x9e018,
2845         .halt_check = BRANCH_HALT,
2846         .clkr = {
2847                 .enable_reg = 0x9e018,
2848                 .enable_mask = BIT(0),
2849                 .hw.init = &(struct clk_init_data){
2850                         .name = "gcc_usb30_sec_sleep_clk",
2851                         .ops = &clk_branch2_ops,
2852                 },
2853         },
2854 };
2855
2856 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2857         .halt_reg = 0xf054,
2858         .halt_check = BRANCH_HALT,
2859         .clkr = {
2860                 .enable_reg = 0xf054,
2861                 .enable_mask = BIT(0),
2862                 .hw.init = &(struct clk_init_data){
2863                         .name = "gcc_usb3_prim_phy_aux_clk",
2864                         .parent_hws = (const struct clk_hw*[]){
2865                                 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2866                         },
2867                         .num_parents = 1,
2868                         .flags = CLK_SET_RATE_PARENT,
2869                         .ops = &clk_branch2_ops,
2870                 },
2871         },
2872 };
2873
2874 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2875         .halt_reg = 0xf058,
2876         .halt_check = BRANCH_HALT,
2877         .clkr = {
2878                 .enable_reg = 0xf058,
2879                 .enable_mask = BIT(0),
2880                 .hw.init = &(struct clk_init_data){
2881                         .name = "gcc_usb3_prim_phy_com_aux_clk",
2882                         .parent_hws = (const struct clk_hw*[]){
2883                                 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2884                         },
2885                         .num_parents = 1,
2886                         .flags = CLK_SET_RATE_PARENT,
2887                         .ops = &clk_branch2_ops,
2888                 },
2889         },
2890 };
2891
2892 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2893         .halt_reg = 0xf05c,
2894         .halt_check = BRANCH_HALT_DELAY,
2895         .hwcg_reg = 0xf05c,
2896         .hwcg_bit = 1,
2897         .clkr = {
2898                 .enable_reg = 0xf05c,
2899                 .enable_mask = BIT(0),
2900                 .hw.init = &(struct clk_init_data){
2901                         .name = "gcc_usb3_prim_phy_pipe_clk",
2902                         .parent_hws = (const struct clk_hw*[]){
2903                                 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
2904                         },
2905                         .num_parents = 1,
2906                         .flags = CLK_SET_RATE_PARENT,
2907                         .ops = &clk_branch2_ops,
2908                 },
2909         },
2910 };
2911
2912 static struct clk_branch gcc_cfg_noc_lpass_clk = {
2913         .halt_reg = 0x47020,
2914         .halt_check = BRANCH_HALT,
2915         .clkr = {
2916                 .enable_reg = 0x47020,
2917                 .enable_mask = BIT(0),
2918                 .hw.init = &(struct clk_init_data){
2919                         .name = "gcc_cfg_noc_lpass_clk",
2920                         .ops = &clk_branch2_aon_ops,
2921                 },
2922         },
2923 };
2924 static struct clk_branch gcc_mss_cfg_ahb_clk = {
2925         .halt_reg = 0x8a000,
2926         .halt_check = BRANCH_HALT,
2927         .clkr = {
2928                 .enable_reg = 0x8a000,
2929                 .enable_mask = BIT(0),
2930                 .hw.init = &(struct clk_init_data){
2931                         .name = "gcc_mss_cfg_ahb_clk",
2932                         .ops = &clk_branch2_ops,
2933                 },
2934         },
2935 };
2936
2937 static struct clk_branch gcc_mss_offline_axi_clk = {
2938         .halt_reg = 0x8a004,
2939         .halt_check = BRANCH_HALT_DELAY,
2940         .clkr = {
2941                 .enable_reg = 0x8a004,
2942                 .enable_mask = BIT(0),
2943                 .hw.init = &(struct clk_init_data){
2944                         .name = "gcc_mss_offline_axi_clk",
2945                         .ops = &clk_branch2_ops,
2946                 },
2947         },
2948 };
2949
2950 static struct clk_branch gcc_mss_snoc_axi_clk = {
2951         .halt_reg = 0x8a154,
2952         .halt_check = BRANCH_HALT_DELAY,
2953         .clkr = {
2954                 .enable_reg = 0x8a154,
2955                 .enable_mask = BIT(0),
2956                 .hw.init = &(struct clk_init_data){
2957                         .name = "gcc_mss_snoc_axi_clk",
2958                         .ops = &clk_branch2_ops,
2959                 },
2960         },
2961 };
2962
2963 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
2964         .halt_reg = 0x8a158,
2965         .halt_check = BRANCH_HALT,
2966         .clkr = {
2967                 .enable_reg = 0x8a158,
2968                 .enable_mask = BIT(0),
2969                 .hw.init = &(struct clk_init_data){
2970                         .name = "gcc_mss_q6_memnoc_axi_clk",
2971                         .ops = &clk_branch2_ops,
2972                 },
2973         },
2974 };
2975
2976 static struct clk_regmap_mux gcc_mss_q6ss_boot_clk_src = {
2977         .reg = 0x8a2a4,
2978         .shift = 0,
2979         .width = 1,
2980         .parent_map = gcc_parent_map_15,
2981         .clkr = {
2982                 .hw.init = &(struct clk_init_data){
2983                         .name = "gcc_mss_q6ss_boot_clk_src",
2984                         .parent_data = gcc_parent_data_15,
2985                         .num_parents = ARRAY_SIZE(gcc_parent_data_15),
2986                         .ops = &clk_regmap_mux_closest_ops,
2987                 },
2988         },
2989 };
2990
2991 static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
2992         .halt_reg = 0x9e054,
2993         .halt_check = BRANCH_HALT,
2994         .clkr = {
2995                 .enable_reg = 0x9e054,
2996                 .enable_mask = BIT(0),
2997                 .hw.init = &(struct clk_init_data){
2998                         .name = "gcc_usb3_sec_phy_aux_clk",
2999                         .parent_hws = (const struct clk_hw*[]){
3000                                 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3001                         },
3002                         .num_parents = 1,
3003                         .flags = CLK_SET_RATE_PARENT,
3004                         .ops = &clk_branch2_ops,
3005                 },
3006         },
3007 };
3008
3009 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
3010         .halt_reg = 0x9e058,
3011         .halt_check = BRANCH_HALT,
3012         .clkr = {
3013                 .enable_reg = 0x9e058,
3014                 .enable_mask = BIT(0),
3015                 .hw.init = &(struct clk_init_data){
3016                         .name = "gcc_usb3_sec_phy_com_aux_clk",
3017                         .parent_hws = (const struct clk_hw*[]){
3018                                 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3019                         },
3020                         .num_parents = 1,
3021                         .flags = CLK_SET_RATE_PARENT,
3022                         .ops = &clk_branch2_ops,
3023                 },
3024         },
3025 };
3026
3027 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
3028         .halt_reg = 0x9e05c,
3029         .halt_check = BRANCH_HALT_SKIP,
3030         .hwcg_reg = 0x9e05c,
3031         .hwcg_bit = 1,
3032         .clkr = {
3033                 .enable_reg = 0x9e05c,
3034                 .enable_mask = BIT(0),
3035                 .hw.init = &(struct clk_init_data){
3036                         .name = "gcc_usb3_sec_phy_pipe_clk",
3037                         .parent_hws = (const struct clk_hw*[]){
3038                                 &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
3039                         },
3040                         .num_parents = 1,
3041                         .flags = CLK_SET_RATE_PARENT,
3042                         .ops = &clk_branch2_ops,
3043                 },
3044         },
3045 };
3046
3047 static struct clk_branch gcc_video_axi0_clk = {
3048         .halt_reg = 0x2800c,
3049         .halt_check = BRANCH_HALT_SKIP,
3050         .hwcg_reg = 0x2800c,
3051         .hwcg_bit = 1,
3052         .clkr = {
3053                 .enable_reg = 0x2800c,
3054                 .enable_mask = BIT(0),
3055                 .hw.init = &(struct clk_init_data){
3056                         .name = "gcc_video_axi0_clk",
3057                         .ops = &clk_branch2_ops,
3058                 },
3059         },
3060 };
3061
3062 static struct clk_branch gcc_video_mvp_throttle_core_clk = {
3063         .halt_reg = 0x28010,
3064         .halt_check = BRANCH_HALT_SKIP,
3065         .hwcg_reg = 0x28010,
3066         .hwcg_bit = 1,
3067         .clkr = {
3068                 .enable_reg = 0x28010,
3069                 .enable_mask = BIT(0),
3070                 .hw.init = &(struct clk_init_data){
3071                         .name = "gcc_video_mvp_throttle_core_clk",
3072                         .ops = &clk_branch2_ops,
3073                 },
3074         },
3075 };
3076
3077 static struct clk_branch gcc_wpss_ahb_clk = {
3078         .halt_reg = 0x9d154,
3079         .halt_check = BRANCH_HALT,
3080         .clkr = {
3081                 .enable_reg = 0x9d154,
3082                 .enable_mask = BIT(0),
3083                 .hw.init = &(struct clk_init_data){
3084                         .name = "gcc_wpss_ahb_clk",
3085                         .ops = &clk_branch2_ops,
3086                 },
3087         },
3088 };
3089
3090 static struct clk_branch gcc_wpss_ahb_bdg_mst_clk = {
3091         .halt_reg = 0x9d158,
3092         .halt_check = BRANCH_HALT,
3093         .clkr = {
3094                 .enable_reg = 0x9d158,
3095                 .enable_mask = BIT(0),
3096                 .hw.init = &(struct clk_init_data){
3097                         .name = "gcc_wpss_ahb_bdg_mst_clk",
3098                         .ops = &clk_branch2_ops,
3099                 },
3100         },
3101 };
3102
3103 static struct clk_branch gcc_wpss_rscp_clk = {
3104         .halt_reg = 0x9d16c,
3105         .halt_check = BRANCH_HALT,
3106         .clkr = {
3107                 .enable_reg = 0x9d16c,
3108                 .enable_mask = BIT(0),
3109                 .hw.init = &(struct clk_init_data){
3110                         .name = "gcc_wpss_rscp_clk",
3111                         .ops = &clk_branch2_ops,
3112                 },
3113         },
3114 };
3115
3116 static struct gdsc gcc_pcie_0_gdsc = {
3117         .gdscr = 0x6b004,
3118         .pd = {
3119                 .name = "gcc_pcie_0_gdsc",
3120         },
3121         .pwrsts = PWRSTS_OFF_ON,
3122         .flags = VOTABLE,
3123 };
3124
3125 static struct gdsc gcc_pcie_1_gdsc = {
3126         .gdscr = 0x8d004,
3127         .pd = {
3128                 .name = "gcc_pcie_1_gdsc",
3129         },
3130         .pwrsts = PWRSTS_OFF_ON,
3131         .flags = VOTABLE,
3132 };
3133
3134 static struct gdsc gcc_ufs_phy_gdsc = {
3135         .gdscr = 0x77004,
3136         .pd = {
3137                 .name = "gcc_ufs_phy_gdsc",
3138         },
3139         .pwrsts = PWRSTS_OFF_ON,
3140         .flags = VOTABLE,
3141 };
3142
3143 static struct gdsc gcc_usb30_prim_gdsc = {
3144         .gdscr = 0xf004,
3145         .pd = {
3146                 .name = "gcc_usb30_prim_gdsc",
3147         },
3148         .pwrsts = PWRSTS_OFF_ON,
3149         .flags = VOTABLE,
3150 };
3151
3152 static struct gdsc gcc_usb30_sec_gdsc = {
3153         .gdscr = 0x9e004,
3154         .pd = {
3155                 .name = "gcc_usb30_sec_gdsc",
3156         },
3157         .pwrsts = PWRSTS_OFF_ON,
3158         .flags = VOTABLE,
3159 };
3160
3161 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
3162         .gdscr = 0x7d050,
3163         .pd = {
3164                 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
3165         },
3166         .pwrsts = PWRSTS_OFF_ON,
3167         .flags = VOTABLE,
3168 };
3169
3170 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
3171         .gdscr = 0x7d058,
3172         .pd = {
3173                 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
3174         },
3175         .pwrsts = PWRSTS_OFF_ON,
3176         .flags = VOTABLE,
3177 };
3178
3179 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = {
3180         .gdscr = 0x7d054,
3181         .pd = {
3182                 .name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc",
3183         },
3184         .pwrsts = PWRSTS_OFF_ON,
3185         .flags = VOTABLE,
3186 };
3187
3188 static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {
3189         .gdscr = 0x7d05c,
3190         .pd = {
3191                 .name = "hlos1_vote_turing_mmu_tbu0_gdsc",
3192         },
3193         .pwrsts = PWRSTS_OFF_ON,
3194         .flags = VOTABLE,
3195 };
3196
3197 static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {
3198         .gdscr = 0x7d060,
3199         .pd = {
3200                 .name = "hlos1_vote_turing_mmu_tbu1_gdsc",
3201         },
3202         .pwrsts = PWRSTS_OFF_ON,
3203         .flags = VOTABLE,
3204 };
3205
3206 static struct clk_regmap *gcc_sc7280_clocks[] = {
3207         [GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr,
3208         [GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr,
3209         [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3210         [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3211         [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3212         [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3213         [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3214         [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3215         [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3216         [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3217         [GCC_DDRSS_PCIE_SF_CLK] = &gcc_ddrss_pcie_sf_clk.clkr,
3218         [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
3219         [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3220         [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
3221         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3222         [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3223         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3224         [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3225         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3226         [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3227         [GCC_GPLL0] = &gcc_gpll0.clkr,
3228         [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
3229         [GCC_GPLL0_OUT_ODD] = &gcc_gpll0_out_odd.clkr,
3230         [GCC_GPLL1] = &gcc_gpll1.clkr,
3231         [GCC_GPLL10] = &gcc_gpll10.clkr,
3232         [GCC_GPLL4] = &gcc_gpll4.clkr,
3233         [GCC_GPLL9] = &gcc_gpll9.clkr,
3234         [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3235         [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3236         [GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr,
3237         [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3238         [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3239         [GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr,
3240         [GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr,
3241         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3242         [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3243         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3244         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3245         [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
3246         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3247         [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
3248         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3249         [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3250         [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3251         [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3252         [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3253         [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3254         [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
3255         [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3256         [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
3257         [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3258         [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3259         [GCC_PCIE_THROTTLE_CORE_CLK] = &gcc_pcie_throttle_core_clk.clkr,
3260         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3261         [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3262         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3263         [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3264         [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3265         [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3266         [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3267         [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3268         [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3269         [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3270         [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3271         [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3272         [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3273         [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3274         [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3275         [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3276         [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3277         [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3278         [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3279         [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3280         [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3281         [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3282         [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3283         [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3284         [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3285         [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3286         [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3287         [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3288         [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3289         [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
3290         [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
3291         [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3292         [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3293         [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3294         [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3295         [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3296         [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3297         [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3298         [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3299         [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3300         [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3301         [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3302         [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3303         [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3304         [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3305         [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
3306         [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
3307         [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3308         [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3309         [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3310         [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3311         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3312         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3313         [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
3314         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3315         [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
3316         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3317         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3318         [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3319         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3320         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3321         [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3322         [GCC_THROTTLE_PCIE_AHB_CLK] = &gcc_throttle_pcie_ahb_clk.clkr,
3323         [GCC_TITAN_NRT_THROTTLE_CORE_CLK] =
3324                 &gcc_titan_nrt_throttle_core_clk.clkr,
3325         [GCC_TITAN_RT_THROTTLE_CORE_CLK] = &gcc_titan_rt_throttle_core_clk.clkr,
3326         [GCC_UFS_1_CLKREF_EN] = &gcc_ufs_1_clkref_en.clkr,
3327         [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3328         [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3329         [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3330         [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3331         [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3332         [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3333         [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3334         [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3335         [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] =
3336                 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
3337         [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3338         [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] =
3339                 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
3340         [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3341         [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] =
3342                 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
3343         [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3344         [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3345                 &gcc_ufs_phy_unipro_core_clk_src.clkr,
3346         [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3347         [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3348         [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3349         [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3350                 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3351         [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] =
3352                 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3353         [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3354         [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3355         [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3356         [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3357         [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
3358                         &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3359         [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] =
3360                         &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
3361         [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3362         [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3363         [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3364         [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3365         [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3366         [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
3367         [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3368         [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3369         [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3370         [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
3371         [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
3372         [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3373         [GCC_VIDEO_MVP_THROTTLE_CORE_CLK] =
3374                         &gcc_video_mvp_throttle_core_clk.clkr,
3375         [GCC_CFG_NOC_LPASS_CLK] = &gcc_cfg_noc_lpass_clk.clkr,
3376         [GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC] = &gcc_mss_gpll0_main_div_clk_src.clkr,
3377         [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3378         [GCC_MSS_OFFLINE_AXI_CLK] = &gcc_mss_offline_axi_clk.clkr,
3379         [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
3380         [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
3381         [GCC_MSS_Q6SS_BOOT_CLK_SRC] = &gcc_mss_q6ss_boot_clk_src.clkr,
3382         [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3383         [GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK] =
3384                                 &gcc_aggre_noc_pcie_center_sf_axi_clk.clkr,
3385         [GCC_PCIE_CLKREF_EN] = &gcc_pcie_clkref_en.clkr,
3386         [GCC_EDP_CLKREF_EN] = &gcc_edp_clkref_en.clkr,
3387         [GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr,
3388         [GCC_WPSS_AHB_CLK] = &gcc_wpss_ahb_clk.clkr,
3389         [GCC_WPSS_AHB_BDG_MST_CLK] = &gcc_wpss_ahb_bdg_mst_clk.clkr,
3390         [GCC_WPSS_RSCP_CLK] = &gcc_wpss_rscp_clk.clkr,
3391 };
3392
3393 static struct gdsc *gcc_sc7280_gdscs[] = {
3394         [GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc,
3395         [GCC_PCIE_1_GDSC] = &gcc_pcie_1_gdsc,
3396         [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc,
3397         [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
3398         [GCC_USB30_SEC_GDSC] = &gcc_usb30_sec_gdsc,
3399         [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
3400         [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
3401         [HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc,
3402         [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,
3403         [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
3404 };
3405
3406 static const struct qcom_reset_map gcc_sc7280_resets[] = {
3407         [GCC_PCIE_0_BCR] = { 0x6b000 },
3408         [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3409         [GCC_PCIE_1_BCR] = { 0x8d000 },
3410         [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3411         [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3412         [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3413         [GCC_SDCC1_BCR] = { 0x75000 },
3414         [GCC_SDCC2_BCR] = { 0x14000 },
3415         [GCC_SDCC4_BCR] = { 0x16000 },
3416         [GCC_UFS_PHY_BCR] = { 0x77000 },
3417         [GCC_USB30_PRIM_BCR] = { 0xf000 },
3418         [GCC_USB30_SEC_BCR] = { 0x9e000 },
3419         [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3420         [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3421         [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3422         [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3423 };
3424
3425 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3426         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3427         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3428         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3429         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3430         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3431         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3432         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3433         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
3434         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3435         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3436         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3437         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3438         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3439         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3440         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
3441         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
3442 };
3443
3444 static const struct regmap_config gcc_sc7280_regmap_config = {
3445         .reg_bits = 32,
3446         .reg_stride = 4,
3447         .val_bits = 32,
3448         .max_register = 0x9f128,
3449         .fast_io = true,
3450 };
3451
3452 static const struct qcom_cc_desc gcc_sc7280_desc = {
3453         .config = &gcc_sc7280_regmap_config,
3454         .clks = gcc_sc7280_clocks,
3455         .num_clks = ARRAY_SIZE(gcc_sc7280_clocks),
3456         .resets = gcc_sc7280_resets,
3457         .num_resets = ARRAY_SIZE(gcc_sc7280_resets),
3458         .gdscs = gcc_sc7280_gdscs,
3459         .num_gdscs = ARRAY_SIZE(gcc_sc7280_gdscs),
3460 };
3461
3462 static const struct of_device_id gcc_sc7280_match_table[] = {
3463         { .compatible = "qcom,gcc-sc7280" },
3464         { }
3465 };
3466 MODULE_DEVICE_TABLE(of, gcc_sc7280_match_table);
3467
3468 static int gcc_sc7280_probe(struct platform_device *pdev)
3469 {
3470         struct regmap *regmap;
3471         int ret;
3472
3473         regmap = qcom_cc_map(pdev, &gcc_sc7280_desc);
3474         if (IS_ERR(regmap))
3475                 return PTR_ERR(regmap);
3476
3477         /*
3478          * Keep the clocks always-ON
3479          * GCC_CAMERA_AHB_CLK/XO_CLK, GCC_DISP_AHB_CLK/XO_CLK
3480          * GCC_VIDEO_AHB_CLK/XO_CLK, GCC_GPU_CFG_AHB_CLK
3481          */
3482         regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0));
3483         regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0));
3484         regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0));
3485         regmap_update_bits(regmap, 0x2701C, BIT(0), BIT(0));
3486         regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0));
3487         regmap_update_bits(regmap, 0x28014, BIT(0), BIT(0));
3488         regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
3489
3490         ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
3491                         ARRAY_SIZE(gcc_dfs_clocks));
3492         if (ret)
3493                 return ret;
3494
3495         return qcom_cc_really_probe(pdev, &gcc_sc7280_desc, regmap);
3496 }
3497
3498 static struct platform_driver gcc_sc7280_driver = {
3499         .probe = gcc_sc7280_probe,
3500         .driver = {
3501                 .name = "gcc-sc7280",
3502                 .of_match_table = gcc_sc7280_match_table,
3503         },
3504 };
3505
3506 static int __init gcc_sc7280_init(void)
3507 {
3508         return platform_driver_register(&gcc_sc7280_driver);
3509 }
3510 subsys_initcall(gcc_sc7280_init);
3511
3512 static void __exit gcc_sc7280_exit(void)
3513 {
3514         platform_driver_unregister(&gcc_sc7280_driver);
3515 }
3516 module_exit(gcc_sc7280_exit);
3517
3518 MODULE_DESCRIPTION("QTI GCC SC7280 Driver");
3519 MODULE_LICENSE("GPL v2");