drivers/clk/qcom/gcc-sc7280.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk-provider.h>
   7 #include <linux/kernel.h>
   8 #include <linux/module.h>
   9 #include <linux/of_device.h>
  10 #include <linux/of.h>
  11 #include <linux/regmap.h>
  12
  13 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
  14
  15 #include "clk-alpha-pll.h"
  16 #include "clk-branch.h"
  17 #include "clk-rcg.h"
  18 #include "clk-regmap-divider.h"
  19 #include "clk-regmap-mux.h"
  20 #include "common.h"
  21 #include "gdsc.h"
  22 #include "reset.h"
  23
  24 enum {
  25         P_BI_TCXO,
  26         P_GCC_GPLL0_OUT_EVEN,
  27         P_GCC_GPLL0_OUT_MAIN,
  28         P_GCC_GPLL0_OUT_ODD,
  29         P_GCC_GPLL10_OUT_MAIN,
  30         P_GCC_GPLL4_OUT_MAIN,
  31         P_GCC_GPLL9_OUT_MAIN,
  32         P_PCIE_0_PIPE_CLK,
  33         P_PCIE_1_PIPE_CLK,
  34         P_SLEEP_CLK,
  35         P_UFS_PHY_RX_SYMBOL_0_CLK,
  36         P_UFS_PHY_RX_SYMBOL_1_CLK,
  37         P_UFS_PHY_TX_SYMBOL_0_CLK,
  38         P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
  39         P_GCC_MSS_GPLL0_MAIN_DIV_CLK,
  40 };
  41
  42 static struct clk_alpha_pll gcc_gpll0 = {
  43         .offset = 0x0,
  44         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  45         .clkr = {
  46                 .enable_reg = 0x52010,
  47                 .enable_mask = BIT(0),
  48                 .hw.init = &(struct clk_init_data){
  49                         .name = "gcc_gpll0",
  50                         .parent_data = &(const struct clk_parent_data){
  51                                 .fw_name = "bi_tcxo",
  52                         },
  53                         .num_parents = 1,
  54                         .ops = &clk_alpha_pll_fixed_lucid_ops,
  55                 },
  56         },
  57 };
  58
  59 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
  60         { 0x1, 2 },
  61         { }
  62 };
  63
  64 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
  65         .offset = 0x0,
  66         .post_div_shift = 8,
  67         .post_div_table = post_div_table_gcc_gpll0_out_even,
  68         .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
  69         .width = 4,
  70         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  71         .clkr.hw.init = &(struct clk_init_data){
  72                 .name = "gcc_gpll0_out_even",
  73                 .parent_data = &(const struct clk_parent_data){
  74                         .hw = &gcc_gpll0.clkr.hw,
  75                 },
  76                 .num_parents = 1,
  77                 .ops = &clk_alpha_pll_postdiv_lucid_ops,
  78         },
  79 };
  80
  81 static const struct clk_div_table post_div_table_gcc_gpll0_out_odd[] = {
  82         { 0x3, 3 },
  83         { }
  84 };
  85
  86 static struct clk_alpha_pll_postdiv gcc_gpll0_out_odd = {
  87         .offset = 0x0,
  88         .post_div_shift = 12,
  89         .post_div_table = post_div_table_gcc_gpll0_out_odd,
  90         .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_odd),
  91         .width = 4,
  92         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  93         .clkr.hw.init = &(struct clk_init_data){
  94                 .name = "gcc_gpll0_out_odd",
  95                 .parent_data = &(const struct clk_parent_data){
  96                         .hw = &gcc_gpll0.clkr.hw,
  97                 },
  98                 .num_parents = 1,
  99                 .ops = &clk_alpha_pll_postdiv_lucid_ops,
 100         },
 101 };
 102
 103 static struct clk_alpha_pll gcc_gpll1 = {
 104         .offset = 0x1000,
 105         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 106         .clkr = {
 107                 .enable_reg = 0x52010,
 108                 .enable_mask = BIT(1),
 109                 .hw.init = &(struct clk_init_data){
 110                         .name = "gcc_gpll1",
 111                         .parent_data = &(const struct clk_parent_data){
 112                                 .fw_name = "bi_tcxo",
 113                         },
 114                         .num_parents = 1,
 115                         .ops = &clk_alpha_pll_fixed_lucid_ops,
 116                 },
 117         },
 118 };
 119
 120 static struct clk_alpha_pll gcc_gpll10 = {
 121         .offset = 0x1e000,
 122         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 123         .clkr = {
 124                 .enable_reg = 0x52010,
 125                 .enable_mask = BIT(9),
 126                 .hw.init = &(struct clk_init_data){
 127                         .name = "gcc_gpll10",
 128                         .parent_data = &(const struct clk_parent_data){
 129                                 .fw_name = "bi_tcxo",
 130                         },
 131                         .num_parents = 1,
 132                         .ops = &clk_alpha_pll_fixed_lucid_ops,
 133                 },
 134         },
 135 };
 136
 137 static struct clk_alpha_pll gcc_gpll4 = {
 138         .offset = 0x76000,
 139         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 140         .clkr = {
 141                 .enable_reg = 0x52010,
 142                 .enable_mask = BIT(4),
 143                 .hw.init = &(struct clk_init_data){
 144                         .name = "gcc_gpll4",
 145                         .parent_data = &(const struct clk_parent_data){
 146                                 .fw_name = "bi_tcxo",
 147                         },
 148                         .num_parents = 1,
 149                         .ops = &clk_alpha_pll_fixed_lucid_ops,
 150                 },
 151         },
 152 };
 153
 154 static struct clk_alpha_pll gcc_gpll9 = {
 155         .offset = 0x1c000,
 156         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
 157         .clkr = {
 158                 .enable_reg = 0x52010,
 159                 .enable_mask = BIT(8),
 160                 .hw.init = &(struct clk_init_data){
 161                         .name = "gcc_gpll9",
 162                         .parent_data = &(const struct clk_parent_data){
 163                                 .fw_name = "bi_tcxo",
 164                         },
 165                         .num_parents = 1,
 166                         .ops = &clk_alpha_pll_fixed_lucid_ops,
 167                 },
 168         },
 169 };
 170
 171 static struct clk_branch gcc_mss_gpll0_main_div_clk_src = {
 172         .halt_check = BRANCH_HALT_DELAY,
 173         .clkr = {
 174                 .enable_reg = 0x52000,
 175                 .enable_mask = BIT(17),
 176                 .hw.init = &(struct clk_init_data){
 177                         .name = "gcc_mss_gpll0_main_div_clk_src",
 178                         .parent_data = &(const struct clk_parent_data){
 179                                 .hw = &gcc_gpll0_out_even.clkr.hw,
 180                         },
 181                         .num_parents = 1,
 182                         .flags = CLK_SET_RATE_PARENT,
 183                         .ops = &clk_branch2_ops,
 184                 },
 185         },
 186 };
 187
 188 static const struct parent_map gcc_parent_map_0[] = {
 189         { P_BI_TCXO, 0 },
 190         { P_GCC_GPLL0_OUT_MAIN, 1 },
 191         { P_GCC_GPLL0_OUT_EVEN, 6 },
 192 };
 193
 194 static const struct clk_parent_data gcc_parent_data_0[] = {
 195         { .fw_name = "bi_tcxo" },
 196         { .hw = &gcc_gpll0.clkr.hw },
 197         { .hw = &gcc_gpll0_out_even.clkr.hw },
 198 };
 199
 200 static const struct clk_parent_data gcc_parent_data_0_ao[] = {
 201         { .fw_name = "bi_tcxo_ao" },
 202         { .hw = &gcc_gpll0.clkr.hw },
 203         { .hw = &gcc_gpll0_out_even.clkr.hw },
 204 };
 205
 206 static const struct parent_map gcc_parent_map_1[] = {
 207         { P_BI_TCXO, 0 },
 208         { P_GCC_GPLL0_OUT_MAIN, 1 },
 209         { P_GCC_GPLL0_OUT_ODD, 3 },
 210         { P_GCC_GPLL0_OUT_EVEN, 6 },
 211 };
 212
 213 static const struct clk_parent_data gcc_parent_data_1[] = {
 214         { .fw_name = "bi_tcxo" },
 215         { .hw = &gcc_gpll0.clkr.hw },
 216         { .hw = &gcc_gpll0_out_odd.clkr.hw },
 217         { .hw = &gcc_gpll0_out_even.clkr.hw },
 218 };
 219
 220 static const struct parent_map gcc_parent_map_2[] = {
 221         { P_BI_TCXO, 0 },
 222         { P_SLEEP_CLK, 5 },
 223 };
 224
 225 static const struct clk_parent_data gcc_parent_data_2[] = {
 226         { .fw_name = "bi_tcxo" },
 227         { .fw_name = "sleep_clk" },
 228 };
 229
 230 static const struct parent_map gcc_parent_map_3[] = {
 231         { P_BI_TCXO, 0 },
 232 };
 233
 234 static const struct clk_parent_data gcc_parent_data_3[] = {
 235         { .fw_name = "bi_tcxo" },
 236 };
 237
 238 static const struct parent_map gcc_parent_map_4[] = {
 239         { P_BI_TCXO, 0 },
 240         { P_GCC_GPLL0_OUT_MAIN, 1 },
 241         { P_GCC_GPLL0_OUT_ODD, 3 },
 242         { P_SLEEP_CLK, 5 },
 243         { P_GCC_GPLL0_OUT_EVEN, 6 },
 244 };
 245
 246 static const struct clk_parent_data gcc_parent_data_4[] = {
 247         { .fw_name = "bi_tcxo" },
 248         { .hw = &gcc_gpll0.clkr.hw },
 249         { .hw = &gcc_gpll0_out_odd.clkr.hw },
 250         { .fw_name = "sleep_clk" },
 251         { .hw = &gcc_gpll0_out_even.clkr.hw },
 252 };
 253
 254 static const struct parent_map gcc_parent_map_5[] = {
 255         { P_BI_TCXO, 0 },
 256         { P_GCC_GPLL0_OUT_EVEN, 6 },
 257 };
 258
 259 static const struct clk_parent_data gcc_parent_data_5[] = {
 260         { .fw_name = "bi_tcxo" },
 261         { .hw = &gcc_gpll0_out_even.clkr.hw },
 262 };
 263
 264 static const struct parent_map gcc_parent_map_6[] = {
 265         { P_PCIE_0_PIPE_CLK, 0 },
 266         { P_BI_TCXO, 2 },
 267 };
 268
 269 static const struct clk_parent_data gcc_parent_data_6[] = {
 270         { .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" },
 271         { .fw_name = "bi_tcxo" },
 272 };
 273
 274 static const struct parent_map gcc_parent_map_7[] = {
 275         { P_PCIE_1_PIPE_CLK, 0 },
 276         { P_BI_TCXO, 2 },
 277 };
 278
 279 static const struct clk_parent_data gcc_parent_data_7[] = {
 280         { .fw_name = "pcie_1_pipe_clk", .name = "pcie_1_pipe_clk" },
 281         { .fw_name = "bi_tcxo" },
 282 };
 283
 284 static const struct parent_map gcc_parent_map_8[] = {
 285         { P_BI_TCXO, 0 },
 286         { P_GCC_GPLL0_OUT_MAIN, 1 },
 287         { P_GCC_GPLL0_OUT_ODD, 3 },
 288         { P_GCC_GPLL10_OUT_MAIN, 5 },
 289         { P_GCC_GPLL0_OUT_EVEN, 6 },
 290 };
 291
 292 static const struct clk_parent_data gcc_parent_data_8[] = {
 293         { .fw_name = "bi_tcxo" },
 294         { .hw = &gcc_gpll0.clkr.hw },
 295         { .hw = &gcc_gpll0_out_odd.clkr.hw },
 296         { .hw = &gcc_gpll10.clkr.hw },
 297         { .hw = &gcc_gpll0_out_even.clkr.hw },
 298 };
 299
 300 static const struct parent_map gcc_parent_map_9[] = {
 301         { P_BI_TCXO, 0 },
 302         { P_GCC_GPLL0_OUT_MAIN, 1 },
 303         { P_GCC_GPLL9_OUT_MAIN, 2 },
 304         { P_GCC_GPLL0_OUT_ODD, 3 },
 305         { P_GCC_GPLL4_OUT_MAIN, 5 },
 306         { P_GCC_GPLL0_OUT_EVEN, 6 },
 307 };
 308
 309 static const struct clk_parent_data gcc_parent_data_9[] = {
 310         { .fw_name = "bi_tcxo" },
 311         { .hw = &gcc_gpll0.clkr.hw },
 312         { .hw = &gcc_gpll9.clkr.hw },
 313         { .hw = &gcc_gpll0_out_odd.clkr.hw },
 314         { .hw = &gcc_gpll4.clkr.hw },
 315         { .hw = &gcc_gpll0_out_even.clkr.hw },
 316 };
 317
 318 static const struct parent_map gcc_parent_map_10[] = {
 319         { P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
 320         { P_BI_TCXO, 2 },
 321 };
 322
 323 static const struct clk_parent_data gcc_parent_data_10[] = {
 324         { .fw_name = "ufs_phy_rx_symbol_0_clk" },
 325         { .fw_name = "bi_tcxo" },
 326 };
 327
 328 static const struct parent_map gcc_parent_map_11[] = {
 329         { P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
 330         { P_BI_TCXO, 2 },
 331 };
 332
 333 static const struct clk_parent_data gcc_parent_data_11[] = {
 334         { .fw_name = "ufs_phy_rx_symbol_1_clk" },
 335         { .fw_name = "bi_tcxo" },
 336 };
 337
 338 static const struct parent_map gcc_parent_map_12[] = {
 339         { P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
 340         { P_BI_TCXO, 2 },
 341 };
 342
 343 static const struct clk_parent_data gcc_parent_data_12[] = {
 344         { .fw_name = "ufs_phy_tx_symbol_0_clk" },
 345         { .fw_name = "bi_tcxo" },
 346 };
 347
 348 static const struct parent_map gcc_parent_map_13[] = {
 349         { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
 350         { P_BI_TCXO, 2 },
 351 };
 352
 353 static const struct clk_parent_data gcc_parent_data_13[] = {
 354         { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
 355         { .fw_name = "bi_tcxo" },
 356 };
 357
 358 static const struct parent_map gcc_parent_map_14[] = {
 359         { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
 360         { P_BI_TCXO, 2 },
 361 };
 362
 363 static const struct clk_parent_data gcc_parent_data_14[] = {
 364         { .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
 365         { .fw_name = "bi_tcxo" },
 366 };
 367
 368 static const struct parent_map gcc_parent_map_15[] = {
 369         { P_BI_TCXO, 0 },
 370         { P_GCC_MSS_GPLL0_MAIN_DIV_CLK, 1 },
 371 };
 372
 373 static const struct clk_parent_data gcc_parent_data_15[] = {
 374         { .fw_name = "bi_tcxo" },
 375         { .hw = &gcc_mss_gpll0_main_div_clk_src.clkr.hw },
 376 };
 377
 378 static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
 379         .reg = 0x6b054,
 380         .shift = 0,
 381         .width = 2,
 382         .parent_map = gcc_parent_map_6,
 383         .clkr = {
 384                 .hw.init = &(struct clk_init_data){
 385                         .name = "gcc_pcie_0_pipe_clk_src",
 386                         .parent_data = gcc_parent_data_6,
 387                         .num_parents = ARRAY_SIZE(gcc_parent_data_6),
 388                         .ops = &clk_regmap_mux_closest_ops,
 389                 },
 390         },
 391 };
 392
 393 static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
 394         .reg = 0x8d054,
 395         .shift = 0,
 396         .width = 2,
 397         .parent_map = gcc_parent_map_7,
 398         .clkr = {
 399                 .hw.init = &(struct clk_init_data){
 400                         .name = "gcc_pcie_1_pipe_clk_src",
 401                         .parent_data = gcc_parent_data_7,
 402                         .num_parents = ARRAY_SIZE(gcc_parent_data_7),
 403                         .ops = &clk_regmap_mux_closest_ops,
 404                 },
 405         },
 406 };
 407
 408 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
 409         .reg = 0x77058,
 410         .shift = 0,
 411         .width = 2,
 412         .parent_map = gcc_parent_map_10,
 413         .clkr = {
 414                 .hw.init = &(struct clk_init_data){
 415                         .name = "gcc_ufs_phy_rx_symbol_0_clk_src",
 416                         .parent_data = gcc_parent_data_10,
 417                         .num_parents = ARRAY_SIZE(gcc_parent_data_10),
 418                         .ops = &clk_regmap_mux_closest_ops,
 419                 },
 420         },
 421 };
 422
 423 static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
 424         .reg = 0x770c8,
 425         .shift = 0,
 426         .width = 2,
 427         .parent_map = gcc_parent_map_11,
 428         .clkr = {
 429                 .hw.init = &(struct clk_init_data){
 430                         .name = "gcc_ufs_phy_rx_symbol_1_clk_src",
 431                         .parent_data = gcc_parent_data_11,
 432                         .num_parents = ARRAY_SIZE(gcc_parent_data_11),
 433                         .ops = &clk_regmap_mux_closest_ops,
 434                 },
 435         },
 436 };
 437
 438 static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
 439         .reg = 0x77048,
 440         .shift = 0,
 441         .width = 2,
 442         .parent_map = gcc_parent_map_12,
 443         .clkr = {
 444                 .hw.init = &(struct clk_init_data){
 445                         .name = "gcc_ufs_phy_tx_symbol_0_clk_src",
 446                         .parent_data = gcc_parent_data_12,
 447                         .num_parents = ARRAY_SIZE(gcc_parent_data_12),
 448                         .ops = &clk_regmap_mux_closest_ops,
 449                 },
 450         },
 451 };
 452
 453 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
 454         .reg = 0xf060,
 455         .shift = 0,
 456         .width = 2,
 457         .parent_map = gcc_parent_map_13,
 458         .clkr = {
 459                 .hw.init = &(struct clk_init_data){
 460                         .name = "gcc_usb3_prim_phy_pipe_clk_src",
 461                         .parent_data = gcc_parent_data_13,
 462                         .num_parents = ARRAY_SIZE(gcc_parent_data_13),
 463                         .ops = &clk_regmap_mux_closest_ops,
 464                 },
 465         },
 466 };
 467
 468 static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
 469         .reg = 0x9e060,
 470         .shift = 0,
 471         .width = 2,
 472         .parent_map = gcc_parent_map_14,
 473         .clkr = {
 474                 .hw.init = &(struct clk_init_data){
 475                         .name = "gcc_usb3_sec_phy_pipe_clk_src",
 476                         .parent_data = gcc_parent_data_14,
 477                         .num_parents = ARRAY_SIZE(gcc_parent_data_14),
 478                         .ops = &clk_regmap_mux_closest_ops,
 479                 },
 480         },
 481 };
 482 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
 483         F(19200000, P_BI_TCXO, 1, 0, 0),
 484         { }
 485 };
 486
 487 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
 488         .cmd_rcgr = 0x4800c,
 489         .mnd_width = 0,
 490         .hid_width = 5,
 491         .parent_map = gcc_parent_map_0,
 492         .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
 493         .clkr.hw.init = &(struct clk_init_data){
 494                 .name = "gcc_cpuss_ahb_clk_src",
 495                 .parent_data = gcc_parent_data_0_ao,
 496                 .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
 497                 .ops = &clk_rcg2_ops,
 498         },
 499 };
 500
 501 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 502         F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
 503         F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 504         F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0),
 505         { }
 506 };
 507
 508 static struct clk_rcg2 gcc_gp1_clk_src = {
 509         .cmd_rcgr = 0x64004,
 510         .mnd_width = 16,
 511         .hid_width = 5,
 512         .parent_map = gcc_parent_map_4,
 513         .freq_tbl = ftbl_gcc_gp1_clk_src,
 514         .clkr.hw.init = &(struct clk_init_data){
 515                 .name = "gcc_gp1_clk_src",
 516                 .parent_data = gcc_parent_data_4,
 517                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 518                 .ops = &clk_rcg2_ops,
 519         },
 520 };
 521
 522 static struct clk_rcg2 gcc_gp2_clk_src = {
 523         .cmd_rcgr = 0x65004,
 524         .mnd_width = 16,
 525         .hid_width = 5,
 526         .parent_map = gcc_parent_map_4,
 527         .freq_tbl = ftbl_gcc_gp1_clk_src,
 528         .clkr.hw.init = &(struct clk_init_data){
 529                 .name = "gcc_gp2_clk_src",
 530                 .parent_data = gcc_parent_data_4,
 531                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 532                 .ops = &clk_rcg2_ops,
 533         },
 534 };
 535
 536 static struct clk_rcg2 gcc_gp3_clk_src = {
 537         .cmd_rcgr = 0x66004,
 538         .mnd_width = 16,
 539         .hid_width = 5,
 540         .parent_map = gcc_parent_map_4,
 541         .freq_tbl = ftbl_gcc_gp1_clk_src,
 542         .clkr.hw.init = &(struct clk_init_data){
 543                 .name = "gcc_gp3_clk_src",
 544                 .parent_data = gcc_parent_data_4,
 545                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 546                 .ops = &clk_rcg2_ops,
 547         },
 548 };
 549
 550 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
 551         F(9600000, P_BI_TCXO, 2, 0, 0),
 552         F(19200000, P_BI_TCXO, 1, 0, 0),
 553         { }
 554 };
 555
 556 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
 557         .cmd_rcgr = 0x6b058,
 558         .mnd_width = 16,
 559         .hid_width = 5,
 560         .parent_map = gcc_parent_map_2,
 561         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 562         .clkr.hw.init = &(struct clk_init_data){
 563                 .name = "gcc_pcie_0_aux_clk_src",
 564                 .parent_data = gcc_parent_data_2,
 565                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 566                 .ops = &clk_rcg2_ops,
 567         },
 568 };
 569
 570 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
 571         F(19200000, P_BI_TCXO, 1, 0, 0),
 572         F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 573         { }
 574 };
 575
 576 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
 577         .cmd_rcgr = 0x6b03c,
 578         .mnd_width = 0,
 579         .hid_width = 5,
 580         .parent_map = gcc_parent_map_0,
 581         .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 582         .clkr.hw.init = &(struct clk_init_data){
 583                 .name = "gcc_pcie_0_phy_rchng_clk_src",
 584                 .parent_data = gcc_parent_data_0,
 585                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 586                 .ops = &clk_rcg2_ops,
 587         },
 588 };
 589
 590 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
 591         .cmd_rcgr = 0x8d058,
 592         .mnd_width = 16,
 593         .hid_width = 5,
 594         .parent_map = gcc_parent_map_2,
 595         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
 596         .clkr.hw.init = &(struct clk_init_data){
 597                 .name = "gcc_pcie_1_aux_clk_src",
 598                 .parent_data = gcc_parent_data_2,
 599                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 600                 .ops = &clk_rcg2_ops,
 601         },
 602 };
 603
 604 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
 605         .cmd_rcgr = 0x8d03c,
 606         .mnd_width = 0,
 607         .hid_width = 5,
 608         .parent_map = gcc_parent_map_0,
 609         .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
 610         .clkr.hw.init = &(struct clk_init_data){
 611                 .name = "gcc_pcie_1_phy_rchng_clk_src",
 612                 .parent_data = gcc_parent_data_0,
 613                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 614                 .flags = CLK_SET_RATE_PARENT,
 615                 .ops = &clk_rcg2_ops,
 616         },
 617 };
 618
 619 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
 620         F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0),
 621         { }
 622 };
 623
 624 static struct clk_rcg2 gcc_pdm2_clk_src = {
 625         .cmd_rcgr = 0x33010,
 626         .mnd_width = 0,
 627         .hid_width = 5,
 628         .parent_map = gcc_parent_map_0,
 629         .freq_tbl = ftbl_gcc_pdm2_clk_src,
 630         .clkr.hw.init = &(struct clk_init_data){
 631                 .name = "gcc_pdm2_clk_src",
 632                 .parent_data = gcc_parent_data_0,
 633                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 634                 .flags = CLK_SET_RATE_PARENT,
 635                 .ops = &clk_rcg2_ops,
 636         },
 637 };
 638
 639 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
 640         F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 641         F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
 642         F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
 643         F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
 644         { }
 645 };
 646
 647 static struct clk_rcg2 gcc_qspi_core_clk_src = {
 648         .cmd_rcgr = 0x4b00c,
 649         .mnd_width = 0,
 650         .hid_width = 5,
 651         .parent_map = gcc_parent_map_0,
 652         .freq_tbl = ftbl_gcc_qspi_core_clk_src,
 653         .clkr.hw.init = &(struct clk_init_data){
 654                 .name = "gcc_qspi_core_clk_src",
 655                 .parent_data = gcc_parent_data_0,
 656                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 657                 .ops = &clk_rcg2_floor_ops,
 658         },
 659 };
 660
 661 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
 662         F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 663         F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 664         F(19200000, P_BI_TCXO, 1, 0, 0),
 665         F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 666         F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 667         F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 668         F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 669         F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
 670         F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 671         F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 672         F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 673         F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
 674         F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
 675         F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
 676         F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0),
 677         { }
 678 };
 679
 680 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
 681         .name = "gcc_qupv3_wrap0_s0_clk_src",
 682         .parent_data = gcc_parent_data_0,
 683         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 684         .ops = &clk_rcg2_ops,
 685 };
 686
 687 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
 688         .cmd_rcgr = 0x17010,
 689         .mnd_width = 16,
 690         .hid_width = 5,
 691         .parent_map = gcc_parent_map_0,
 692         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 693         .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
 694 };
 695
 696 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
 697         .name = "gcc_qupv3_wrap0_s1_clk_src",
 698         .parent_data = gcc_parent_data_0,
 699         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 700         .ops = &clk_rcg2_ops,
 701 };
 702
 703 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
 704         .cmd_rcgr = 0x17140,
 705         .mnd_width = 16,
 706         .hid_width = 5,
 707         .parent_map = gcc_parent_map_0,
 708         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 709         .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
 710 };
 711
 712 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
 713         F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
 714         F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
 715         F(19200000, P_BI_TCXO, 1, 0, 0),
 716         F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
 717         F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
 718         F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
 719         F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
 720         F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
 721         F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
 722         F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
 723         F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
 724         { }
 725 };
 726
 727 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
 728         .name = "gcc_qupv3_wrap0_s2_clk_src",
 729         .parent_data = gcc_parent_data_0,
 730         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 731         .ops = &clk_rcg2_ops,
 732 };
 733
 734 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
 735         .cmd_rcgr = 0x17270,
 736         .mnd_width = 16,
 737         .hid_width = 5,
 738         .parent_map = gcc_parent_map_0,
 739         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 740         .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
 741 };
 742
 743 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
 744         .name = "gcc_qupv3_wrap0_s3_clk_src",
 745         .parent_data = gcc_parent_data_0,
 746         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 747         .ops = &clk_rcg2_ops,
 748 };
 749
 750 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
 751         .cmd_rcgr = 0x173a0,
 752         .mnd_width = 16,
 753         .hid_width = 5,
 754         .parent_map = gcc_parent_map_0,
 755         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 756         .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
 757 };
 758
 759 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
 760         .name = "gcc_qupv3_wrap0_s4_clk_src",
 761         .parent_data = gcc_parent_data_0,
 762         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 763         .ops = &clk_rcg2_ops,
 764 };
 765
 766 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
 767         .cmd_rcgr = 0x174d0,
 768         .mnd_width = 16,
 769         .hid_width = 5,
 770         .parent_map = gcc_parent_map_0,
 771         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 772         .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
 773 };
 774
 775 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
 776         .name = "gcc_qupv3_wrap0_s5_clk_src",
 777         .parent_data = gcc_parent_data_0,
 778         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 779         .ops = &clk_rcg2_ops,
 780 };
 781
 782 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
 783         .cmd_rcgr = 0x17600,
 784         .mnd_width = 16,
 785         .hid_width = 5,
 786         .parent_map = gcc_parent_map_0,
 787         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 788         .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
 789 };
 790
 791 static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
 792         .name = "gcc_qupv3_wrap0_s6_clk_src",
 793         .parent_data = gcc_parent_data_0,
 794         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 795         .ops = &clk_rcg2_ops,
 796 };
 797
 798 static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
 799         .cmd_rcgr = 0x17730,
 800         .mnd_width = 16,
 801         .hid_width = 5,
 802         .parent_map = gcc_parent_map_0,
 803         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 804         .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
 805 };
 806
 807 static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
 808         .name = "gcc_qupv3_wrap0_s7_clk_src",
 809         .parent_data = gcc_parent_data_0,
 810         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 811         .ops = &clk_rcg2_ops,
 812 };
 813
 814 static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
 815         .cmd_rcgr = 0x17860,
 816         .mnd_width = 16,
 817         .hid_width = 5,
 818         .parent_map = gcc_parent_map_0,
 819         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 820         .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
 821 };
 822
 823 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
 824         .name = "gcc_qupv3_wrap1_s0_clk_src",
 825         .parent_data = gcc_parent_data_0,
 826         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 827         .ops = &clk_rcg2_ops,
 828 };
 829
 830 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
 831         .cmd_rcgr = 0x18010,
 832         .mnd_width = 16,
 833         .hid_width = 5,
 834         .parent_map = gcc_parent_map_0,
 835         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 836         .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
 837 };
 838
 839 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
 840         .name = "gcc_qupv3_wrap1_s1_clk_src",
 841         .parent_data = gcc_parent_data_0,
 842         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 843         .ops = &clk_rcg2_ops,
 844 };
 845
 846 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
 847         .cmd_rcgr = 0x18140,
 848         .mnd_width = 16,
 849         .hid_width = 5,
 850         .parent_map = gcc_parent_map_0,
 851         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 852         .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
 853 };
 854
 855 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
 856         .name = "gcc_qupv3_wrap1_s2_clk_src",
 857         .parent_data = gcc_parent_data_0,
 858         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 859         .ops = &clk_rcg2_ops,
 860 };
 861
 862 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
 863         .cmd_rcgr = 0x18270,
 864         .mnd_width = 16,
 865         .hid_width = 5,
 866         .parent_map = gcc_parent_map_0,
 867         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 868         .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
 869 };
 870
 871 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
 872         .name = "gcc_qupv3_wrap1_s3_clk_src",
 873         .parent_data = gcc_parent_data_0,
 874         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 875         .ops = &clk_rcg2_ops,
 876 };
 877
 878 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
 879         .cmd_rcgr = 0x183a0,
 880         .mnd_width = 16,
 881         .hid_width = 5,
 882         .parent_map = gcc_parent_map_0,
 883         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 884         .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
 885 };
 886
 887 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
 888         .name = "gcc_qupv3_wrap1_s4_clk_src",
 889         .parent_data = gcc_parent_data_0,
 890         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 891         .ops = &clk_rcg2_ops,
 892 };
 893
 894 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
 895         .cmd_rcgr = 0x184d0,
 896         .mnd_width = 16,
 897         .hid_width = 5,
 898         .parent_map = gcc_parent_map_0,
 899         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 900         .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
 901 };
 902
 903 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
 904         .name = "gcc_qupv3_wrap1_s5_clk_src",
 905         .parent_data = gcc_parent_data_0,
 906         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 907         .ops = &clk_rcg2_ops,
 908 };
 909
 910 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
 911         .cmd_rcgr = 0x18600,
 912         .mnd_width = 16,
 913         .hid_width = 5,
 914         .parent_map = gcc_parent_map_0,
 915         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 916         .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
 917 };
 918
 919 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
 920         .name = "gcc_qupv3_wrap1_s6_clk_src",
 921         .parent_data = gcc_parent_data_0,
 922         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 923         .ops = &clk_rcg2_ops,
 924 };
 925
 926 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
 927         .cmd_rcgr = 0x18730,
 928         .mnd_width = 16,
 929         .hid_width = 5,
 930         .parent_map = gcc_parent_map_0,
 931         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 932         .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
 933 };
 934
 935 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
 936         .name = "gcc_qupv3_wrap1_s7_clk_src",
 937         .parent_data = gcc_parent_data_0,
 938         .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 939         .ops = &clk_rcg2_ops,
 940 };
 941
 942 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
 943         .cmd_rcgr = 0x18860,
 944         .mnd_width = 16,
 945         .hid_width = 5,
 946         .parent_map = gcc_parent_map_0,
 947         .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
 948         .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
 949 };
 950
 951 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
 952         F(144000, P_BI_TCXO, 16, 3, 25),
 953         F(400000, P_BI_TCXO, 12, 1, 4),
 954         F(19200000, P_BI_TCXO, 1, 0, 0),
 955         F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3),
 956         F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
 957         F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
 958         F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 959         F(192000000, P_GCC_GPLL10_OUT_MAIN, 2, 0, 0),
 960         F(384000000, P_GCC_GPLL10_OUT_MAIN, 1, 0, 0),
 961         { }
 962 };
 963
 964 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
 965         .cmd_rcgr = 0x7500c,
 966         .mnd_width = 8,
 967         .hid_width = 5,
 968         .parent_map = gcc_parent_map_8,
 969         .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
 970         .clkr.hw.init = &(struct clk_init_data){
 971                 .name = "gcc_sdcc1_apps_clk_src",
 972                 .parent_data = gcc_parent_data_8,
 973                 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
 974                 .ops = &clk_rcg2_floor_ops,
 975         },
 976 };
 977
 978 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
 979         F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
 980         F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
 981         F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
 982         { }
 983 };
 984
 985 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
 986         .cmd_rcgr = 0x7502c,
 987         .mnd_width = 0,
 988         .hid_width = 5,
 989         .parent_map = gcc_parent_map_1,
 990         .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
 991         .clkr.hw.init = &(struct clk_init_data){
 992                 .name = "gcc_sdcc1_ice_core_clk_src",
 993                 .parent_data = gcc_parent_data_1,
 994                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 995                 .ops = &clk_rcg2_floor_ops,
 996         },
 997 };
 998
 999 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
1000         F(400000, P_BI_TCXO, 12, 1, 4),
1001         F(19200000, P_BI_TCXO, 1, 0, 0),
1002         F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1003         F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1004         F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1005         F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1006         { }
1007 };
1008
1009 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
1010         .cmd_rcgr = 0x1400c,
1011         .mnd_width = 8,
1012         .hid_width = 5,
1013         .parent_map = gcc_parent_map_9,
1014         .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
1015         .clkr.hw.init = &(struct clk_init_data){
1016                 .name = "gcc_sdcc2_apps_clk_src",
1017                 .parent_data = gcc_parent_data_9,
1018                 .num_parents = ARRAY_SIZE(gcc_parent_data_9),
1019                 .flags = CLK_OPS_PARENT_ENABLE,
1020                 .ops = &clk_rcg2_floor_ops,
1021         },
1022 };
1023
1024 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
1025         F(400000, P_BI_TCXO, 12, 1, 4),
1026         F(19200000, P_BI_TCXO, 1, 0, 0),
1027         F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1028         F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1029         F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1030         { }
1031 };
1032
1033 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
1034         .cmd_rcgr = 0x1600c,
1035         .mnd_width = 8,
1036         .hid_width = 5,
1037         .parent_map = gcc_parent_map_1,
1038         .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
1039         .clkr.hw.init = &(struct clk_init_data){
1040                 .name = "gcc_sdcc4_apps_clk_src",
1041                 .parent_data = gcc_parent_data_1,
1042                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1043                 .ops = &clk_rcg2_floor_ops,
1044         },
1045 };
1046
1047 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
1048         F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1049         F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1050         F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1051         F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
1052         { }
1053 };
1054
1055 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1056         .cmd_rcgr = 0x77024,
1057         .mnd_width = 8,
1058         .hid_width = 5,
1059         .parent_map = gcc_parent_map_0,
1060         .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
1061         .clkr.hw.init = &(struct clk_init_data){
1062                 .name = "gcc_ufs_phy_axi_clk_src",
1063                 .parent_data = gcc_parent_data_0,
1064                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1065                 .ops = &clk_rcg2_ops,
1066         },
1067 };
1068
1069 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
1070         F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1071         F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
1072         F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
1073         { }
1074 };
1075
1076 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1077         .cmd_rcgr = 0x7706c,
1078         .mnd_width = 0,
1079         .hid_width = 5,
1080         .parent_map = gcc_parent_map_0,
1081         .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1082         .clkr.hw.init = &(struct clk_init_data){
1083                 .name = "gcc_ufs_phy_ice_core_clk_src",
1084                 .parent_data = gcc_parent_data_0,
1085                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1086                 .ops = &clk_rcg2_ops,
1087         },
1088 };
1089
1090 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1091         .cmd_rcgr = 0x770a0,
1092         .mnd_width = 0,
1093         .hid_width = 5,
1094         .parent_map = gcc_parent_map_3,
1095         .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1096         .clkr.hw.init = &(struct clk_init_data){
1097                 .name = "gcc_ufs_phy_phy_aux_clk_src",
1098                 .parent_data = gcc_parent_data_3,
1099                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1100                 .ops = &clk_rcg2_ops,
1101         },
1102 };
1103
1104 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1105         .cmd_rcgr = 0x77084,
1106         .mnd_width = 0,
1107         .hid_width = 5,
1108         .parent_map = gcc_parent_map_0,
1109         .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1110         .clkr.hw.init = &(struct clk_init_data){
1111                 .name = "gcc_ufs_phy_unipro_core_clk_src",
1112                 .parent_data = gcc_parent_data_0,
1113                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1114                 .ops = &clk_rcg2_ops,
1115         },
1116 };
1117
1118 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1119         F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1120         F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1121         F(200000000, P_GCC_GPLL0_OUT_ODD, 1, 0, 0),
1122         F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1123         { }
1124 };
1125
1126 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1127         .cmd_rcgr = 0xf020,
1128         .mnd_width = 8,
1129         .hid_width = 5,
1130         .parent_map = gcc_parent_map_1,
1131         .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1132         .clkr.hw.init = &(struct clk_init_data){
1133                 .name = "gcc_usb30_prim_master_clk_src",
1134                 .parent_data = gcc_parent_data_1,
1135                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1136                 .ops = &clk_rcg2_ops,
1137         },
1138 };
1139
1140 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
1141         F(19200000, P_BI_TCXO, 1, 0, 0),
1142         { }
1143 };
1144
1145 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1146         .cmd_rcgr = 0xf038,
1147         .mnd_width = 0,
1148         .hid_width = 5,
1149         .parent_map = gcc_parent_map_3,
1150         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1151         .clkr.hw.init = &(struct clk_init_data){
1152                 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1153                 .parent_data = gcc_parent_data_3,
1154                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1155                 .ops = &clk_rcg2_ops,
1156         },
1157 };
1158
1159 static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk_src[] = {
1160         F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0),
1161         F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0),
1162         { }
1163 };
1164
1165 static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1166         .cmd_rcgr = 0x9e020,
1167         .mnd_width = 8,
1168         .hid_width = 5,
1169         .parent_map = gcc_parent_map_5,
1170         .freq_tbl = ftbl_gcc_usb30_sec_master_clk_src,
1171         .clkr.hw.init = &(struct clk_init_data){
1172                 .name = "gcc_usb30_sec_master_clk_src",
1173                 .parent_data = gcc_parent_data_5,
1174                 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
1175                 .ops = &clk_rcg2_ops,
1176         },
1177 };
1178
1179 static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1180         .cmd_rcgr = 0x9e038,
1181         .mnd_width = 0,
1182         .hid_width = 5,
1183         .parent_map = gcc_parent_map_3,
1184         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1185         .clkr.hw.init = &(struct clk_init_data){
1186                 .name = "gcc_usb30_sec_mock_utmi_clk_src",
1187                 .parent_data = gcc_parent_data_3,
1188                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1189                 .ops = &clk_rcg2_ops,
1190         },
1191 };
1192
1193 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1194         .cmd_rcgr = 0xf064,
1195         .mnd_width = 0,
1196         .hid_width = 5,
1197         .parent_map = gcc_parent_map_2,
1198         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1199         .clkr.hw.init = &(struct clk_init_data){
1200                 .name = "gcc_usb3_prim_phy_aux_clk_src",
1201                 .parent_data = gcc_parent_data_2,
1202                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1203                 .ops = &clk_rcg2_ops,
1204         },
1205 };
1206
1207 static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1208         .cmd_rcgr = 0x9e064,
1209         .mnd_width = 0,
1210         .hid_width = 5,
1211         .parent_map = gcc_parent_map_2,
1212         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1213         .clkr.hw.init = &(struct clk_init_data){
1214                 .name = "gcc_usb3_sec_phy_aux_clk_src",
1215                 .parent_data = gcc_parent_data_2,
1216                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
1217                 .ops = &clk_rcg2_ops,
1218         },
1219 };
1220
1221 static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = {
1222         F(4800000, P_BI_TCXO, 4, 0, 0),
1223         F(19200000, P_BI_TCXO, 1, 0, 0),
1224         { }
1225 };
1226
1227 static struct clk_rcg2 gcc_sec_ctrl_clk_src = {
1228         .cmd_rcgr = 0x3d02c,
1229         .mnd_width = 0,
1230         .hid_width = 5,
1231         .parent_map = gcc_parent_map_3,
1232         .freq_tbl = ftbl_gcc_sec_ctrl_clk_src,
1233         .clkr.hw.init = &(struct clk_init_data){
1234                 .name = "gcc_sec_ctrl_clk_src",
1235                 .parent_data = gcc_parent_data_3,
1236                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
1237                 .ops = &clk_rcg2_ops,
1238         },
1239 };
1240
1241 static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = {
1242         .reg = 0x48024,
1243         .shift = 0,
1244         .width = 4,
1245         .clkr.hw.init = &(struct clk_init_data) {
1246                 .name = "gcc_cpuss_ahb_postdiv_clk_src",
1247                 .parent_data = &(const struct clk_parent_data){
1248                         .hw = &gcc_cpuss_ahb_clk_src.clkr.hw,
1249                 },
1250                 .num_parents = 1,
1251                 .flags = CLK_SET_RATE_PARENT,
1252                 .ops = &clk_regmap_div_ro_ops,
1253         },
1254 };
1255
1256 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1257         .reg = 0xf050,
1258         .shift = 0,
1259         .width = 4,
1260         .clkr.hw.init = &(struct clk_init_data) {
1261                 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1262                 .parent_data = &(const struct clk_parent_data){
1263                         .hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1264                 },
1265                 .num_parents = 1,
1266                 .flags = CLK_SET_RATE_PARENT,
1267                 .ops = &clk_regmap_div_ro_ops,
1268         },
1269 };
1270
1271 static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
1272         .reg = 0x9e050,
1273         .shift = 0,
1274         .width = 4,
1275         .clkr.hw.init = &(struct clk_init_data) {
1276                 .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
1277                 .parent_data = &(const struct clk_parent_data){
1278                         .hw = &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
1279                 },
1280                 .num_parents = 1,
1281                 .flags = CLK_SET_RATE_PARENT,
1282                 .ops = &clk_regmap_div_ro_ops,
1283         },
1284 };
1285
1286 static struct clk_branch gcc_pcie_clkref_en = {
1287         .halt_reg = 0x8c004,
1288         .halt_check = BRANCH_HALT,
1289         .clkr = {
1290                 .enable_reg = 0x8c004,
1291                 .enable_mask = BIT(0),
1292                 .hw.init = &(struct clk_init_data){
1293                         .name = "gcc_pcie_clkref_en",
1294                         .ops = &clk_branch2_ops,
1295                 },
1296         },
1297 };
1298
1299 static struct clk_branch gcc_edp_clkref_en = {
1300         .halt_reg = 0x8c008,
1301         .halt_check = BRANCH_HALT,
1302         .clkr = {
1303                 .enable_reg = 0x8c008,
1304                 .enable_mask = BIT(0),
1305                 .hw.init = &(struct clk_init_data){
1306                         .name = "gcc_edp_clkref_en",
1307                         .ops = &clk_branch2_ops,
1308                 },
1309         },
1310 };
1311
1312 static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = {
1313         .halt_reg = 0x6b080,
1314         .halt_check = BRANCH_HALT_SKIP,
1315         .hwcg_reg = 0x6b080,
1316         .hwcg_bit = 1,
1317         .clkr = {
1318                 .enable_reg = 0x52000,
1319                 .enable_mask = BIT(12),
1320                 .hw.init = &(struct clk_init_data){
1321                         .name = "gcc_aggre_noc_pcie_0_axi_clk",
1322                         .ops = &clk_branch2_ops,
1323                 },
1324         },
1325 };
1326
1327 static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = {
1328         .halt_reg = 0x8d084,
1329         .halt_check = BRANCH_HALT_SKIP,
1330         .hwcg_reg = 0x8d084,
1331         .hwcg_bit = 1,
1332         .clkr = {
1333                 .enable_reg = 0x52000,
1334                 .enable_mask = BIT(11),
1335                 .hw.init = &(struct clk_init_data){
1336                         .name = "gcc_aggre_noc_pcie_1_axi_clk",
1337                         .ops = &clk_branch2_ops,
1338                 },
1339         },
1340 };
1341
1342 static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1343         .halt_reg = 0x90010,
1344         .halt_check = BRANCH_HALT_VOTED,
1345         .hwcg_reg = 0x90010,
1346         .hwcg_bit = 1,
1347         .clkr = {
1348                 .enable_reg = 0x52000,
1349                 .enable_mask = BIT(18),
1350                 .hw.init = &(struct clk_init_data){
1351                         .name = "gcc_aggre_noc_pcie_tbu_clk",
1352                         .ops = &clk_branch2_ops,
1353                 },
1354         },
1355 };
1356
1357 static struct clk_branch gcc_aggre_noc_pcie_center_sf_axi_clk = {
1358         .halt_reg = 0x8d088,
1359         .halt_check = BRANCH_HALT_VOTED,
1360         .hwcg_reg = 0x8d088,
1361         .hwcg_bit = 1,
1362         .clkr = {
1363                 .enable_reg = 0x52008,
1364                 .enable_mask = BIT(28),
1365                 .hw.init = &(struct clk_init_data){
1366                         .name = "gcc_aggre_noc_pcie_center_sf_axi_clk",
1367                         .ops = &clk_branch2_ops,
1368                 },
1369         },
1370 };
1371
1372 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1373         .halt_reg = 0x770cc,
1374         .halt_check = BRANCH_HALT_VOTED,
1375         .hwcg_reg = 0x770cc,
1376         .hwcg_bit = 1,
1377         .clkr = {
1378                 .enable_reg = 0x770cc,
1379                 .enable_mask = BIT(0),
1380                 .hw.init = &(struct clk_init_data){
1381                         .name = "gcc_aggre_ufs_phy_axi_clk",
1382                         .parent_data = &(const struct clk_parent_data){
1383                                 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
1384                         },
1385                         .num_parents = 1,
1386                         .flags = CLK_SET_RATE_PARENT,
1387                         .ops = &clk_branch2_ops,
1388                 },
1389         },
1390 };
1391
1392 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1393         .halt_reg = 0xf080,
1394         .halt_check = BRANCH_HALT_VOTED,
1395         .hwcg_reg = 0xf080,
1396         .hwcg_bit = 1,
1397         .clkr = {
1398                 .enable_reg = 0xf080,
1399                 .enable_mask = BIT(0),
1400                 .hw.init = &(struct clk_init_data){
1401                         .name = "gcc_aggre_usb3_prim_axi_clk",
1402                         .parent_data = &(const struct clk_parent_data){
1403                                 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
1404                         },
1405                         .num_parents = 1,
1406                         .flags = CLK_SET_RATE_PARENT,
1407                         .ops = &clk_branch2_ops,
1408                 },
1409         },
1410 };
1411
1412 static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1413         .halt_reg = 0x9e080,
1414         .halt_check = BRANCH_HALT_VOTED,
1415         .hwcg_reg = 0x9e080,
1416         .hwcg_bit = 1,
1417         .clkr = {
1418                 .enable_reg = 0x9e080,
1419                 .enable_mask = BIT(0),
1420                 .hw.init = &(struct clk_init_data){
1421                         .name = "gcc_aggre_usb3_sec_axi_clk",
1422                         .parent_data = &(const struct clk_parent_data){
1423                                 .hw = &gcc_usb30_sec_master_clk_src.clkr.hw,
1424                         },
1425                         .num_parents = 1,
1426                         .flags = CLK_SET_RATE_PARENT,
1427                         .ops = &clk_branch2_ops,
1428                 },
1429         },
1430 };
1431
1432 static struct clk_branch gcc_camera_hf_axi_clk = {
1433         .halt_reg = 0x26010,
1434         .halt_check = BRANCH_HALT_SKIP,
1435         .hwcg_reg = 0x26010,
1436         .hwcg_bit = 1,
1437         .clkr = {
1438                 .enable_reg = 0x26010,
1439                 .enable_mask = BIT(0),
1440                 .hw.init = &(struct clk_init_data){
1441                         .name = "gcc_camera_hf_axi_clk",
1442                         .ops = &clk_branch2_ops,
1443                 },
1444         },
1445 };
1446
1447 static struct clk_branch gcc_camera_sf_axi_clk = {
1448         .halt_reg = 0x2601c,
1449         .halt_check = BRANCH_HALT_SKIP,
1450         .hwcg_reg = 0x2601c,
1451         .hwcg_bit = 1,
1452         .clkr = {
1453                 .enable_reg = 0x2601c,
1454                 .enable_mask = BIT(0),
1455                 .hw.init = &(struct clk_init_data){
1456                         .name = "gcc_camera_sf_axi_clk",
1457                         .ops = &clk_branch2_ops,
1458                 },
1459         },
1460 };
1461
1462 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1463         .halt_reg = 0xf07c,
1464         .halt_check = BRANCH_HALT_VOTED,
1465         .hwcg_reg = 0xf07c,
1466         .hwcg_bit = 1,
1467         .clkr = {
1468                 .enable_reg = 0xf07c,
1469                 .enable_mask = BIT(0),
1470                 .hw.init = &(struct clk_init_data){
1471                         .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1472                         .parent_data = &(const struct clk_parent_data){
1473                                 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
1474                         },
1475                         .num_parents = 1,
1476                         .flags = CLK_SET_RATE_PARENT,
1477                         .ops = &clk_branch2_ops,
1478                 },
1479         },
1480 };
1481
1482 static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1483         .halt_reg = 0x9e07c,
1484         .halt_check = BRANCH_HALT_VOTED,
1485         .hwcg_reg = 0x9e07c,
1486         .hwcg_bit = 1,
1487         .clkr = {
1488                 .enable_reg = 0x9e07c,
1489                 .enable_mask = BIT(0),
1490                 .hw.init = &(struct clk_init_data){
1491                         .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1492                         .parent_data = &(const struct clk_parent_data){
1493                                 .hw = &gcc_usb30_sec_master_clk_src.clkr.hw,
1494                         },
1495                         .num_parents = 1,
1496                         .flags = CLK_SET_RATE_PARENT,
1497                         .ops = &clk_branch2_ops,
1498                 },
1499         },
1500 };
1501
1502 /* For CPUSS functionality the AHB clock needs to be left enabled */
1503 static struct clk_branch gcc_cpuss_ahb_clk = {
1504         .halt_reg = 0x48000,
1505         .halt_check = BRANCH_HALT_VOTED,
1506         .hwcg_reg = 0x48000,
1507         .hwcg_bit = 1,
1508         .clkr = {
1509                 .enable_reg = 0x52000,
1510                 .enable_mask = BIT(21),
1511                 .hw.init = &(struct clk_init_data){
1512                         .name = "gcc_cpuss_ahb_clk",
1513                         .parent_data = &(const struct clk_parent_data){
1514                                 .hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
1515                         },
1516                         .num_parents = 1,
1517                         .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1518                         .ops = &clk_branch2_ops,
1519                 },
1520         },
1521 };
1522
1523 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1524         .halt_reg = 0x71154,
1525         .halt_check = BRANCH_HALT_SKIP,
1526         .hwcg_reg = 0x71154,
1527         .hwcg_bit = 1,
1528         .clkr = {
1529                 .enable_reg = 0x71154,
1530                 .enable_mask = BIT(0),
1531                 .hw.init = &(struct clk_init_data){
1532                         .name = "gcc_ddrss_gpu_axi_clk",
1533                         .ops = &clk_branch2_aon_ops,
1534                 },
1535         },
1536 };
1537
1538 static struct clk_branch gcc_ddrss_pcie_sf_clk = {
1539         .halt_reg = 0x8d080,
1540         .halt_check = BRANCH_HALT_SKIP,
1541         .hwcg_reg = 0x8d080,
1542         .hwcg_bit = 1,
1543         .clkr = {
1544                 .enable_reg = 0x52000,
1545                 .enable_mask = BIT(19),
1546                 .hw.init = &(struct clk_init_data){
1547                         .name = "gcc_ddrss_pcie_sf_clk",
1548                         .ops = &clk_branch2_ops,
1549                 },
1550         },
1551 };
1552
1553 static struct clk_branch gcc_disp_gpll0_clk_src = {
1554         .halt_check = BRANCH_HALT_DELAY,
1555         .clkr = {
1556                 .enable_reg = 0x52000,
1557                 .enable_mask = BIT(7),
1558                 .hw.init = &(struct clk_init_data){
1559                         .name = "gcc_disp_gpll0_clk_src",
1560                         .parent_data = &(const struct clk_parent_data){
1561                                 .hw = &gcc_gpll0.clkr.hw,
1562                         },
1563                         .num_parents = 1,
1564                         .flags = CLK_SET_RATE_PARENT,
1565                         .ops = &clk_branch2_ops,
1566                 },
1567         },
1568 };
1569
1570 static struct clk_branch gcc_disp_hf_axi_clk = {
1571         .halt_reg = 0x2700c,
1572         .halt_check = BRANCH_HALT_SKIP,
1573         .hwcg_reg = 0x2700c,
1574         .hwcg_bit = 1,
1575         .clkr = {
1576                 .enable_reg = 0x2700c,
1577                 .enable_mask = BIT(0),
1578                 .hw.init = &(struct clk_init_data){
1579                         .name = "gcc_disp_hf_axi_clk",
1580                         .ops = &clk_branch2_ops,
1581                 },
1582         },
1583 };
1584
1585 static struct clk_branch gcc_disp_sf_axi_clk = {
1586         .halt_reg = 0x27014,
1587         .halt_check = BRANCH_HALT_SKIP,
1588         .hwcg_reg = 0x27014,
1589         .hwcg_bit = 1,
1590         .clkr = {
1591                 .enable_reg = 0x27014,
1592                 .enable_mask = BIT(0),
1593                 .hw.init = &(struct clk_init_data){
1594                         .name = "gcc_disp_sf_axi_clk",
1595                         .ops = &clk_branch2_ops,
1596                 },
1597         },
1598 };
1599
1600 static struct clk_branch gcc_gp1_clk = {
1601         .halt_reg = 0x64000,
1602         .halt_check = BRANCH_HALT,
1603         .clkr = {
1604                 .enable_reg = 0x64000,
1605                 .enable_mask = BIT(0),
1606                 .hw.init = &(struct clk_init_data){
1607                         .name = "gcc_gp1_clk",
1608                         .parent_data = &(const struct clk_parent_data){
1609                                 .hw = &gcc_gp1_clk_src.clkr.hw,
1610                         },
1611                         .num_parents = 1,
1612                         .flags = CLK_SET_RATE_PARENT,
1613                         .ops = &clk_branch2_ops,
1614                 },
1615         },
1616 };
1617
1618 static struct clk_branch gcc_gp2_clk = {
1619         .halt_reg = 0x65000,
1620         .halt_check = BRANCH_HALT,
1621         .clkr = {
1622                 .enable_reg = 0x65000,
1623                 .enable_mask = BIT(0),
1624                 .hw.init = &(struct clk_init_data){
1625                         .name = "gcc_gp2_clk",
1626                         .parent_data = &(const struct clk_parent_data){
1627                                 .hw = &gcc_gp2_clk_src.clkr.hw,
1628                         },
1629                         .num_parents = 1,
1630                         .flags = CLK_SET_RATE_PARENT,
1631                         .ops = &clk_branch2_ops,
1632                 },
1633         },
1634 };
1635
1636 static struct clk_branch gcc_gp3_clk = {
1637         .halt_reg = 0x66000,
1638         .halt_check = BRANCH_HALT,
1639         .clkr = {
1640                 .enable_reg = 0x66000,
1641                 .enable_mask = BIT(0),
1642                 .hw.init = &(struct clk_init_data){
1643                         .name = "gcc_gp3_clk",
1644                         .parent_data = &(const struct clk_parent_data){
1645                                 .hw = &gcc_gp3_clk_src.clkr.hw,
1646                         },
1647                         .num_parents = 1,
1648                         .flags = CLK_SET_RATE_PARENT,
1649                         .ops = &clk_branch2_ops,
1650                 },
1651         },
1652 };
1653
1654 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1655         .halt_check = BRANCH_HALT_DELAY,
1656         .clkr = {
1657                 .enable_reg = 0x52000,
1658                 .enable_mask = BIT(15),
1659                 .hw.init = &(struct clk_init_data){
1660                         .name = "gcc_gpu_gpll0_clk_src",
1661                         .parent_data = &(const struct clk_parent_data){
1662                                 .hw = &gcc_gpll0.clkr.hw,
1663                         },
1664                         .num_parents = 1,
1665                         .flags = CLK_SET_RATE_PARENT,
1666                         .ops = &clk_branch2_ops,
1667                 },
1668         },
1669 };
1670
1671 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1672         .halt_check = BRANCH_HALT_DELAY,
1673         .clkr = {
1674                 .enable_reg = 0x52000,
1675                 .enable_mask = BIT(16),
1676                 .hw.init = &(struct clk_init_data){
1677                         .name = "gcc_gpu_gpll0_div_clk_src",
1678                         .parent_data = &(const struct clk_parent_data){
1679                                 .hw = &gcc_gpll0_out_even.clkr.hw,
1680                         },
1681                         .num_parents = 1,
1682                         .flags = CLK_SET_RATE_PARENT,
1683                         .ops = &clk_branch2_ops,
1684                 },
1685         },
1686 };
1687
1688 static struct clk_branch gcc_gpu_iref_en = {
1689         .halt_reg = 0x8c014,
1690         .halt_check = BRANCH_HALT,
1691         .clkr = {
1692                 .enable_reg = 0x8c014,
1693                 .enable_mask = BIT(0),
1694                 .hw.init = &(struct clk_init_data){
1695                         .name = "gcc_gpu_iref_en",
1696                         .ops = &clk_branch2_ops,
1697                 },
1698         },
1699 };
1700
1701 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1702         .halt_reg = 0x7100c,
1703         .halt_check = BRANCH_HALT_VOTED,
1704         .hwcg_reg = 0x7100c,
1705         .hwcg_bit = 1,
1706         .clkr = {
1707                 .enable_reg = 0x7100c,
1708                 .enable_mask = BIT(0),
1709                 .hw.init = &(struct clk_init_data){
1710                         .name = "gcc_gpu_memnoc_gfx_clk",
1711                         .ops = &clk_branch2_aon_ops,
1712                 },
1713         },
1714 };
1715
1716 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1717         .halt_reg = 0x71018,
1718         .halt_check = BRANCH_HALT,
1719         .clkr = {
1720                 .enable_reg = 0x71018,
1721                 .enable_mask = BIT(0),
1722                 .hw.init = &(struct clk_init_data){
1723                         .name = "gcc_gpu_snoc_dvm_gfx_clk",
1724                         .ops = &clk_branch2_aon_ops,
1725                 },
1726         },
1727 };
1728
1729 static struct clk_branch gcc_pcie0_phy_rchng_clk = {
1730         .halt_reg = 0x6b038,
1731         .halt_check = BRANCH_HALT_VOTED,
1732         .clkr = {
1733                 .enable_reg = 0x52000,
1734                 .enable_mask = BIT(22),
1735                 .hw.init = &(struct clk_init_data){
1736                         .name = "gcc_pcie0_phy_rchng_clk",
1737                         .parent_data = &(const struct clk_parent_data){
1738                                 .hw = &gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
1739                         },
1740                         .num_parents = 1,
1741                         .flags = CLK_SET_RATE_PARENT,
1742                         .ops = &clk_branch2_ops,
1743                 },
1744         },
1745 };
1746
1747 static struct clk_branch gcc_pcie1_phy_rchng_clk = {
1748         .halt_reg = 0x8d038,
1749         .halt_check = BRANCH_HALT_VOTED,
1750         .clkr = {
1751                 .enable_reg = 0x52000,
1752                 .enable_mask = BIT(23),
1753                 .hw.init = &(struct clk_init_data){
1754                         .name = "gcc_pcie1_phy_rchng_clk",
1755                         .parent_data = &(const struct clk_parent_data){
1756                                 .hw = &gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
1757                         },
1758                         .num_parents = 1,
1759                         .flags = CLK_SET_RATE_PARENT,
1760                         .ops = &clk_branch2_ops,
1761                 },
1762         },
1763 };
1764
1765 static struct clk_branch gcc_pcie_0_aux_clk = {
1766         .halt_reg = 0x6b028,
1767         .halt_check = BRANCH_HALT_VOTED,
1768         .clkr = {
1769                 .enable_reg = 0x52008,
1770                 .enable_mask = BIT(3),
1771                 .hw.init = &(struct clk_init_data){
1772                         .name = "gcc_pcie_0_aux_clk",
1773                         .parent_data = &(const struct clk_parent_data){
1774                                 .hw = &gcc_pcie_0_aux_clk_src.clkr.hw,
1775                         },
1776                         .num_parents = 1,
1777                         .flags = CLK_SET_RATE_PARENT,
1778                         .ops = &clk_branch2_ops,
1779                 },
1780         },
1781 };
1782
1783 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1784         .halt_reg = 0x6b024,
1785         .halt_check = BRANCH_HALT_VOTED,
1786         .hwcg_reg = 0x6b024,
1787         .hwcg_bit = 1,
1788         .clkr = {
1789                 .enable_reg = 0x52008,
1790                 .enable_mask = BIT(2),
1791                 .hw.init = &(struct clk_init_data){
1792                         .name = "gcc_pcie_0_cfg_ahb_clk",
1793                         .ops = &clk_branch2_ops,
1794                 },
1795         },
1796 };
1797
1798 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1799         .halt_reg = 0x6b01c,
1800         .halt_check = BRANCH_HALT_SKIP,
1801         .clkr = {
1802                 .enable_reg = 0x52008,
1803                 .enable_mask = BIT(1),
1804                 .hw.init = &(struct clk_init_data){
1805                         .name = "gcc_pcie_0_mstr_axi_clk",
1806                         .ops = &clk_branch2_ops,
1807                 },
1808         },
1809 };
1810
1811 static struct clk_branch gcc_pcie_0_pipe_clk = {
1812         .halt_reg = 0x6b030,
1813         .halt_check = BRANCH_HALT_SKIP,
1814         .clkr = {
1815                 .enable_reg = 0x52008,
1816                 .enable_mask = BIT(4),
1817                 .hw.init = &(struct clk_init_data){
1818                         .name = "gcc_pcie_0_pipe_clk",
1819                         .parent_data = &(const struct clk_parent_data){
1820                                 .hw = &gcc_pcie_0_pipe_clk_src.clkr.hw,
1821                         },
1822                         .num_parents = 1,
1823                         .flags = CLK_SET_RATE_PARENT,
1824                         .ops = &clk_branch2_ops,
1825                 },
1826         },
1827 };
1828
1829 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1830         .halt_reg = 0x6b014,
1831         .halt_check = BRANCH_HALT_VOTED,
1832         .clkr = {
1833                 .enable_reg = 0x52008,
1834                 .enable_mask = BIT(0),
1835                 .hw.init = &(struct clk_init_data){
1836                         .name = "gcc_pcie_0_slv_axi_clk",
1837                         .ops = &clk_branch2_ops,
1838                 },
1839         },
1840 };
1841
1842 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1843         .halt_reg = 0x6b010,
1844         .halt_check = BRANCH_HALT_VOTED,
1845         .clkr = {
1846                 .enable_reg = 0x52008,
1847                 .enable_mask = BIT(5),
1848                 .hw.init = &(struct clk_init_data){
1849                         .name = "gcc_pcie_0_slv_q2a_axi_clk",
1850                         .ops = &clk_branch2_ops,
1851                 },
1852         },
1853 };
1854
1855 static struct clk_branch gcc_pcie_1_aux_clk = {
1856         .halt_reg = 0x8d028,
1857         .halt_check = BRANCH_HALT_VOTED,
1858         .clkr = {
1859                 .enable_reg = 0x52000,
1860                 .enable_mask = BIT(29),
1861                 .hw.init = &(struct clk_init_data){
1862                         .name = "gcc_pcie_1_aux_clk",
1863                         .parent_data = &(const struct clk_parent_data){
1864                                 .hw = &gcc_pcie_1_aux_clk_src.clkr.hw,
1865                         },
1866                         .num_parents = 1,
1867                         .flags = CLK_SET_RATE_PARENT,
1868                         .ops = &clk_branch2_ops,
1869                 },
1870         },
1871 };
1872
1873 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1874         .halt_reg = 0x8d024,
1875         .halt_check = BRANCH_HALT_VOTED,
1876         .hwcg_reg = 0x8d024,
1877         .hwcg_bit = 1,
1878         .clkr = {
1879                 .enable_reg = 0x52000,
1880                 .enable_mask = BIT(28),
1881                 .hw.init = &(struct clk_init_data){
1882                         .name = "gcc_pcie_1_cfg_ahb_clk",
1883                         .ops = &clk_branch2_ops,
1884                 },
1885         },
1886 };
1887
1888 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1889         .halt_reg = 0x8d01c,
1890         .halt_check = BRANCH_HALT_SKIP,
1891         .clkr = {
1892                 .enable_reg = 0x52000,
1893                 .enable_mask = BIT(27),
1894                 .hw.init = &(struct clk_init_data){
1895                         .name = "gcc_pcie_1_mstr_axi_clk",
1896                         .ops = &clk_branch2_ops,
1897                 },
1898         },
1899 };
1900
1901 static struct clk_branch gcc_pcie_1_pipe_clk = {
1902         .halt_reg = 0x8d030,
1903         .halt_check = BRANCH_HALT_SKIP,
1904         .clkr = {
1905                 .enable_reg = 0x52000,
1906                 .enable_mask = BIT(30),
1907                 .hw.init = &(struct clk_init_data){
1908                         .name = "gcc_pcie_1_pipe_clk",
1909                         .parent_data = &(const struct clk_parent_data){
1910                                 .hw = &gcc_pcie_1_pipe_clk_src.clkr.hw,
1911                         },
1912                         .num_parents = 1,
1913                         .flags = CLK_SET_RATE_PARENT,
1914                         .ops = &clk_branch2_ops,
1915                 },
1916         },
1917 };
1918
1919 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1920         .halt_reg = 0x8d014,
1921         .halt_check = BRANCH_HALT_VOTED,
1922         .clkr = {
1923                 .enable_reg = 0x52000,
1924                 .enable_mask = BIT(26),
1925                 .hw.init = &(struct clk_init_data){
1926                         .name = "gcc_pcie_1_slv_axi_clk",
1927                         .ops = &clk_branch2_ops,
1928                 },
1929         },
1930 };
1931
1932 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1933         .halt_reg = 0x8d010,
1934         .halt_check = BRANCH_HALT_VOTED,
1935         .clkr = {
1936                 .enable_reg = 0x52000,
1937                 .enable_mask = BIT(25),
1938                 .hw.init = &(struct clk_init_data){
1939                         .name = "gcc_pcie_1_slv_q2a_axi_clk",
1940                         .ops = &clk_branch2_ops,
1941                 },
1942         },
1943 };
1944
1945 static struct clk_branch gcc_pcie_throttle_core_clk = {
1946         .halt_reg = 0x90018,
1947         .halt_check = BRANCH_HALT_SKIP,
1948         .hwcg_reg = 0x90018,
1949         .hwcg_bit = 1,
1950         .clkr = {
1951                 .enable_reg = 0x52000,
1952                 .enable_mask = BIT(20),
1953                 .hw.init = &(struct clk_init_data){
1954                         .name = "gcc_pcie_throttle_core_clk",
1955                         .ops = &clk_branch2_ops,
1956                 },
1957         },
1958 };
1959
1960 static struct clk_branch gcc_pdm2_clk = {
1961         .halt_reg = 0x3300c,
1962         .halt_check = BRANCH_HALT,
1963         .clkr = {
1964                 .enable_reg = 0x3300c,
1965                 .enable_mask = BIT(0),
1966                 .hw.init = &(struct clk_init_data){
1967                         .name = "gcc_pdm2_clk",
1968                         .parent_data = &(const struct clk_parent_data){
1969                                 .hw = &gcc_pdm2_clk_src.clkr.hw,
1970                         },
1971                         .num_parents = 1,
1972                         .flags = CLK_SET_RATE_PARENT,
1973                         .ops = &clk_branch2_ops,
1974                 },
1975         },
1976 };
1977
1978 static struct clk_branch gcc_pdm_ahb_clk = {
1979         .halt_reg = 0x33004,
1980         .halt_check = BRANCH_HALT_VOTED,
1981         .hwcg_reg = 0x33004,
1982         .hwcg_bit = 1,
1983         .clkr = {
1984                 .enable_reg = 0x33004,
1985                 .enable_mask = BIT(0),
1986                 .hw.init = &(struct clk_init_data){
1987                         .name = "gcc_pdm_ahb_clk",
1988                         .ops = &clk_branch2_ops,
1989                 },
1990         },
1991 };
1992
1993 static struct clk_branch gcc_pdm_xo4_clk = {
1994         .halt_reg = 0x33008,
1995         .halt_check = BRANCH_HALT,
1996         .clkr = {
1997                 .enable_reg = 0x33008,
1998                 .enable_mask = BIT(0),
1999                 .hw.init = &(struct clk_init_data){
2000                         .name = "gcc_pdm_xo4_clk",
2001                         .ops = &clk_branch2_ops,
2002                 },
2003         },
2004 };
2005
2006 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2007         .halt_reg = 0x26008,
2008         .halt_check = BRANCH_HALT_VOTED,
2009         .hwcg_reg = 0x26008,
2010         .hwcg_bit = 1,
2011         .clkr = {
2012                 .enable_reg = 0x26008,
2013                 .enable_mask = BIT(0),
2014                 .hw.init = &(struct clk_init_data){
2015                         .name = "gcc_qmip_camera_nrt_ahb_clk",
2016                         .ops = &clk_branch2_ops,
2017                 },
2018         },
2019 };
2020
2021 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2022         .halt_reg = 0x2600c,
2023         .halt_check = BRANCH_HALT_VOTED,
2024         .hwcg_reg = 0x2600c,
2025         .hwcg_bit = 1,
2026         .clkr = {
2027                 .enable_reg = 0x2600c,
2028                 .enable_mask = BIT(0),
2029                 .hw.init = &(struct clk_init_data){
2030                         .name = "gcc_qmip_camera_rt_ahb_clk",
2031                         .ops = &clk_branch2_ops,
2032                 },
2033         },
2034 };
2035
2036 static struct clk_branch gcc_qmip_disp_ahb_clk = {
2037         .halt_reg = 0x27008,
2038         .halt_check = BRANCH_HALT_VOTED,
2039         .clkr = {
2040                 .enable_reg = 0x27008,
2041                 .enable_mask = BIT(0),
2042                 .hw.init = &(struct clk_init_data){
2043                         .name = "gcc_qmip_disp_ahb_clk",
2044                         .ops = &clk_branch2_ops,
2045                 },
2046         },
2047 };
2048
2049 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2050         .halt_reg = 0x28008,
2051         .halt_check = BRANCH_HALT_VOTED,
2052         .hwcg_reg = 0x28008,
2053         .hwcg_bit = 1,
2054         .clkr = {
2055                 .enable_reg = 0x28008,
2056                 .enable_mask = BIT(0),
2057                 .hw.init = &(struct clk_init_data){
2058                         .name = "gcc_qmip_video_vcodec_ahb_clk",
2059                         .ops = &clk_branch2_ops,
2060                 },
2061         },
2062 };
2063
2064 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
2065         .halt_reg = 0x4b004,
2066         .halt_check = BRANCH_HALT,
2067         .hwcg_reg = 0x4b004,
2068         .hwcg_bit = 1,
2069         .clkr = {
2070                 .enable_reg = 0x4b004,
2071                 .enable_mask = BIT(0),
2072                 .hw.init = &(struct clk_init_data){
2073                         .name = "gcc_qspi_cnoc_periph_ahb_clk",
2074                         .ops = &clk_branch2_ops,
2075                 },
2076         },
2077 };
2078
2079 static struct clk_branch gcc_qspi_core_clk = {
2080         .halt_reg = 0x4b008,
2081         .halt_check = BRANCH_HALT,
2082         .clkr = {
2083                 .enable_reg = 0x4b008,
2084                 .enable_mask = BIT(0),
2085                 .hw.init = &(struct clk_init_data){
2086                         .name = "gcc_qspi_core_clk",
2087                         .parent_data = &(const struct clk_parent_data){
2088                                 .hw = &gcc_qspi_core_clk_src.clkr.hw,
2089                         },
2090                         .num_parents = 1,
2091                         .flags = CLK_SET_RATE_PARENT,
2092                         .ops = &clk_branch2_ops,
2093                 },
2094         },
2095 };
2096
2097 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2098         .halt_reg = 0x23008,
2099         .halt_check = BRANCH_HALT_VOTED,
2100         .clkr = {
2101                 .enable_reg = 0x52008,
2102                 .enable_mask = BIT(9),
2103                 .hw.init = &(struct clk_init_data){
2104                         .name = "gcc_qupv3_wrap0_core_2x_clk",
2105                         .ops = &clk_branch2_ops,
2106                 },
2107         },
2108 };
2109
2110 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2111         .halt_reg = 0x23000,
2112         .halt_check = BRANCH_HALT_VOTED,
2113         .clkr = {
2114                 .enable_reg = 0x52008,
2115                 .enable_mask = BIT(8),
2116                 .hw.init = &(struct clk_init_data){
2117                         .name = "gcc_qupv3_wrap0_core_clk",
2118                         .ops = &clk_branch2_ops,
2119                 },
2120         },
2121 };
2122
2123 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2124         .halt_reg = 0x1700c,
2125         .halt_check = BRANCH_HALT_VOTED,
2126         .clkr = {
2127                 .enable_reg = 0x52008,
2128                 .enable_mask = BIT(10),
2129                 .hw.init = &(struct clk_init_data){
2130                         .name = "gcc_qupv3_wrap0_s0_clk",
2131                         .parent_data = &(const struct clk_parent_data){
2132                                 .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2133                         },
2134                         .num_parents = 1,
2135                         .flags = CLK_SET_RATE_PARENT,
2136                         .ops = &clk_branch2_ops,
2137                 },
2138         },
2139 };
2140
2141 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2142         .halt_reg = 0x1713c,
2143         .halt_check = BRANCH_HALT_VOTED,
2144         .clkr = {
2145                 .enable_reg = 0x52008,
2146                 .enable_mask = BIT(11),
2147                 .hw.init = &(struct clk_init_data){
2148                         .name = "gcc_qupv3_wrap0_s1_clk",
2149                         .parent_data = &(const struct clk_parent_data){
2150                                 .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2151                         },
2152                         .num_parents = 1,
2153                         .flags = CLK_SET_RATE_PARENT,
2154                         .ops = &clk_branch2_ops,
2155                 },
2156         },
2157 };
2158
2159 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2160         .halt_reg = 0x1726c,
2161         .halt_check = BRANCH_HALT_VOTED,
2162         .clkr = {
2163                 .enable_reg = 0x52008,
2164                 .enable_mask = BIT(12),
2165                 .hw.init = &(struct clk_init_data){
2166                         .name = "gcc_qupv3_wrap0_s2_clk",
2167                         .parent_data = &(const struct clk_parent_data){
2168                                 .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2169                         },
2170                         .num_parents = 1,
2171                         .flags = CLK_SET_RATE_PARENT,
2172                         .ops = &clk_branch2_ops,
2173                 },
2174         },
2175 };
2176
2177 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2178         .halt_reg = 0x1739c,
2179         .halt_check = BRANCH_HALT_VOTED,
2180         .clkr = {
2181                 .enable_reg = 0x52008,
2182                 .enable_mask = BIT(13),
2183                 .hw.init = &(struct clk_init_data){
2184                         .name = "gcc_qupv3_wrap0_s3_clk",
2185                         .parent_data = &(const struct clk_parent_data){
2186                                 .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2187                         },
2188                         .num_parents = 1,
2189                         .flags = CLK_SET_RATE_PARENT,
2190                         .ops = &clk_branch2_ops,
2191                 },
2192         },
2193 };
2194
2195 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2196         .halt_reg = 0x174cc,
2197         .halt_check = BRANCH_HALT_VOTED,
2198         .clkr = {
2199                 .enable_reg = 0x52008,
2200                 .enable_mask = BIT(14),
2201                 .hw.init = &(struct clk_init_data){
2202                         .name = "gcc_qupv3_wrap0_s4_clk",
2203                         .parent_data = &(const struct clk_parent_data){
2204                                 .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2205                         },
2206                         .num_parents = 1,
2207                         .flags = CLK_SET_RATE_PARENT,
2208                         .ops = &clk_branch2_ops,
2209                 },
2210         },
2211 };
2212
2213 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2214         .halt_reg = 0x175fc,
2215         .halt_check = BRANCH_HALT_VOTED,
2216         .clkr = {
2217                 .enable_reg = 0x52008,
2218                 .enable_mask = BIT(15),
2219                 .hw.init = &(struct clk_init_data){
2220                         .name = "gcc_qupv3_wrap0_s5_clk",
2221                         .parent_data = &(const struct clk_parent_data){
2222                                 .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2223                         },
2224                         .num_parents = 1,
2225                         .flags = CLK_SET_RATE_PARENT,
2226                         .ops = &clk_branch2_ops,
2227                 },
2228         },
2229 };
2230
2231 static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2232         .halt_reg = 0x1772c,
2233         .halt_check = BRANCH_HALT_VOTED,
2234         .clkr = {
2235                 .enable_reg = 0x52008,
2236                 .enable_mask = BIT(16),
2237                 .hw.init = &(struct clk_init_data){
2238                         .name = "gcc_qupv3_wrap0_s6_clk",
2239                         .parent_data = &(const struct clk_parent_data){
2240                                 .hw = &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
2241                         },
2242                         .num_parents = 1,
2243                         .flags = CLK_SET_RATE_PARENT,
2244                         .ops = &clk_branch2_ops,
2245                 },
2246         },
2247 };
2248
2249 static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2250         .halt_reg = 0x1785c,
2251         .halt_check = BRANCH_HALT_VOTED,
2252         .clkr = {
2253                 .enable_reg = 0x52008,
2254                 .enable_mask = BIT(17),
2255                 .hw.init = &(struct clk_init_data){
2256                         .name = "gcc_qupv3_wrap0_s7_clk",
2257                         .parent_data = &(const struct clk_parent_data){
2258                                 .hw = &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
2259                         },
2260                         .num_parents = 1,
2261                         .flags = CLK_SET_RATE_PARENT,
2262                         .ops = &clk_branch2_ops,
2263                 },
2264         },
2265 };
2266
2267 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
2268         .halt_reg = 0x23140,
2269         .halt_check = BRANCH_HALT_VOTED,
2270         .clkr = {
2271                 .enable_reg = 0x52008,
2272                 .enable_mask = BIT(18),
2273                 .hw.init = &(struct clk_init_data){
2274                         .name = "gcc_qupv3_wrap1_core_2x_clk",
2275                         .ops = &clk_branch2_ops,
2276                 },
2277         },
2278 };
2279
2280 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
2281         .halt_reg = 0x23138,
2282         .halt_check = BRANCH_HALT_VOTED,
2283         .clkr = {
2284                 .enable_reg = 0x52008,
2285                 .enable_mask = BIT(19),
2286                 .hw.init = &(struct clk_init_data){
2287                         .name = "gcc_qupv3_wrap1_core_clk",
2288                         .ops = &clk_branch2_ops,
2289                 },
2290         },
2291 };
2292
2293 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2294         .halt_reg = 0x1800c,
2295         .halt_check = BRANCH_HALT_VOTED,
2296         .clkr = {
2297                 .enable_reg = 0x52008,
2298                 .enable_mask = BIT(22),
2299                 .hw.init = &(struct clk_init_data){
2300                         .name = "gcc_qupv3_wrap1_s0_clk",
2301                         .parent_data = &(const struct clk_parent_data){
2302                                 .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2303                         },
2304                         .num_parents = 1,
2305                         .flags = CLK_SET_RATE_PARENT,
2306                         .ops = &clk_branch2_ops,
2307                 },
2308         },
2309 };
2310
2311 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2312         .halt_reg = 0x1813c,
2313         .halt_check = BRANCH_HALT_VOTED,
2314         .clkr = {
2315                 .enable_reg = 0x52008,
2316                 .enable_mask = BIT(23),
2317                 .hw.init = &(struct clk_init_data){
2318                         .name = "gcc_qupv3_wrap1_s1_clk",
2319                         .parent_data = &(const struct clk_parent_data){
2320                                 .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2321                         },
2322                         .num_parents = 1,
2323                         .flags = CLK_SET_RATE_PARENT,
2324                         .ops = &clk_branch2_ops,
2325                 },
2326         },
2327 };
2328
2329 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2330         .halt_reg = 0x1826c,
2331         .halt_check = BRANCH_HALT_VOTED,
2332         .clkr = {
2333                 .enable_reg = 0x52008,
2334                 .enable_mask = BIT(24),
2335                 .hw.init = &(struct clk_init_data){
2336                         .name = "gcc_qupv3_wrap1_s2_clk",
2337                         .parent_data = &(const struct clk_parent_data){
2338                                 .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2339                         },
2340                         .num_parents = 1,
2341                         .flags = CLK_SET_RATE_PARENT,
2342                         .ops = &clk_branch2_ops,
2343                 },
2344         },
2345 };
2346
2347 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2348         .halt_reg = 0x1839c,
2349         .halt_check = BRANCH_HALT_VOTED,
2350         .clkr = {
2351                 .enable_reg = 0x52008,
2352                 .enable_mask = BIT(25),
2353                 .hw.init = &(struct clk_init_data){
2354                         .name = "gcc_qupv3_wrap1_s3_clk",
2355                         .parent_data = &(const struct clk_parent_data){
2356                                 .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2357                         },
2358                         .num_parents = 1,
2359                         .flags = CLK_SET_RATE_PARENT,
2360                         .ops = &clk_branch2_ops,
2361                 },
2362         },
2363 };
2364
2365 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2366         .halt_reg = 0x184cc,
2367         .halt_check = BRANCH_HALT_VOTED,
2368         .clkr = {
2369                 .enable_reg = 0x52008,
2370                 .enable_mask = BIT(26),
2371                 .hw.init = &(struct clk_init_data){
2372                         .name = "gcc_qupv3_wrap1_s4_clk",
2373                         .parent_data = &(const struct clk_parent_data){
2374                                 .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2375                         },
2376                         .num_parents = 1,
2377                         .flags = CLK_SET_RATE_PARENT,
2378                         .ops = &clk_branch2_ops,
2379                 },
2380         },
2381 };
2382
2383 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2384         .halt_reg = 0x185fc,
2385         .halt_check = BRANCH_HALT_VOTED,
2386         .clkr = {
2387                 .enable_reg = 0x52008,
2388                 .enable_mask = BIT(27),
2389                 .hw.init = &(struct clk_init_data){
2390                         .name = "gcc_qupv3_wrap1_s5_clk",
2391                         .parent_data = &(const struct clk_parent_data){
2392                                 .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2393                         },
2394                         .num_parents = 1,
2395                         .flags = CLK_SET_RATE_PARENT,
2396                         .ops = &clk_branch2_ops,
2397                 },
2398         },
2399 };
2400
2401 static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
2402         .halt_reg = 0x1872c,
2403         .halt_check = BRANCH_HALT_VOTED,
2404         .clkr = {
2405                 .enable_reg = 0x52000,
2406                 .enable_mask = BIT(13),
2407                 .hw.init = &(struct clk_init_data){
2408                         .name = "gcc_qupv3_wrap1_s6_clk",
2409                         .parent_data = &(const struct clk_parent_data){
2410                                 .hw = &gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
2411                         },
2412                         .num_parents = 1,
2413                         .flags = CLK_SET_RATE_PARENT,
2414                         .ops = &clk_branch2_ops,
2415                 },
2416         },
2417 };
2418
2419 static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
2420         .halt_reg = 0x1885c,
2421         .halt_check = BRANCH_HALT_VOTED,
2422         .clkr = {
2423                 .enable_reg = 0x52000,
2424                 .enable_mask = BIT(14),
2425                 .hw.init = &(struct clk_init_data){
2426                         .name = "gcc_qupv3_wrap1_s7_clk",
2427                         .parent_data = &(const struct clk_parent_data){
2428                                 .hw = &gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
2429                         },
2430                         .num_parents = 1,
2431                         .flags = CLK_SET_RATE_PARENT,
2432                         .ops = &clk_branch2_ops,
2433                 },
2434         },
2435 };
2436
2437 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2438         .halt_reg = 0x17004,
2439         .halt_check = BRANCH_HALT_VOTED,
2440         .hwcg_reg = 0x17004,
2441         .hwcg_bit = 1,
2442         .clkr = {
2443                 .enable_reg = 0x52008,
2444                 .enable_mask = BIT(6),
2445                 .hw.init = &(struct clk_init_data){
2446                         .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2447                         .ops = &clk_branch2_ops,
2448                 },
2449         },
2450 };
2451
2452 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2453         .halt_reg = 0x17008,
2454         .halt_check = BRANCH_HALT_VOTED,
2455         .hwcg_reg = 0x17008,
2456         .hwcg_bit = 1,
2457         .clkr = {
2458                 .enable_reg = 0x52008,
2459                 .enable_mask = BIT(7),
2460                 .hw.init = &(struct clk_init_data){
2461                         .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2462                         .ops = &clk_branch2_ops,
2463                 },
2464         },
2465 };
2466
2467 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2468         .halt_reg = 0x18004,
2469         .halt_check = BRANCH_HALT_VOTED,
2470         .hwcg_reg = 0x18004,
2471         .hwcg_bit = 1,
2472         .clkr = {
2473                 .enable_reg = 0x52008,
2474                 .enable_mask = BIT(20),
2475                 .hw.init = &(struct clk_init_data){
2476                         .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2477                         .ops = &clk_branch2_ops,
2478                 },
2479         },
2480 };
2481
2482 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2483         .halt_reg = 0x18008,
2484         .halt_check = BRANCH_HALT_VOTED,
2485         .hwcg_reg = 0x18008,
2486         .hwcg_bit = 1,
2487         .clkr = {
2488                 .enable_reg = 0x52008,
2489                 .enable_mask = BIT(21),
2490                 .hw.init = &(struct clk_init_data){
2491                         .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2492                         .ops = &clk_branch2_ops,
2493                 },
2494         },
2495 };
2496
2497 static struct clk_branch gcc_sdcc1_ahb_clk = {
2498         .halt_reg = 0x75004,
2499         .halt_check = BRANCH_HALT,
2500         .clkr = {
2501                 .enable_reg = 0x75004,
2502                 .enable_mask = BIT(0),
2503                 .hw.init = &(struct clk_init_data){
2504                         .name = "gcc_sdcc1_ahb_clk",
2505                         .ops = &clk_branch2_ops,
2506                 },
2507         },
2508 };
2509
2510 static struct clk_branch gcc_sdcc1_apps_clk = {
2511         .halt_reg = 0x75008,
2512         .halt_check = BRANCH_HALT,
2513         .clkr = {
2514                 .enable_reg = 0x75008,
2515                 .enable_mask = BIT(0),
2516                 .hw.init = &(struct clk_init_data){
2517                         .name = "gcc_sdcc1_apps_clk",
2518                         .parent_data = &(const struct clk_parent_data){
2519                                 .hw = &gcc_sdcc1_apps_clk_src.clkr.hw,
2520                         },
2521                         .num_parents = 1,
2522                         .flags = CLK_SET_RATE_PARENT,
2523                         .ops = &clk_branch2_ops,
2524                 },
2525         },
2526 };
2527
2528 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2529         .halt_reg = 0x75024,
2530         .halt_check = BRANCH_HALT_VOTED,
2531         .hwcg_reg = 0x75024,
2532         .hwcg_bit = 1,
2533         .clkr = {
2534                 .enable_reg = 0x75024,
2535                 .enable_mask = BIT(0),
2536                 .hw.init = &(struct clk_init_data){
2537                         .name = "gcc_sdcc1_ice_core_clk",
2538                         .parent_data = &(const struct clk_parent_data){
2539                                 .hw = &gcc_sdcc1_ice_core_clk_src.clkr.hw,
2540                         },
2541                         .num_parents = 1,
2542                         .flags = CLK_SET_RATE_PARENT,
2543                         .ops = &clk_branch2_ops,
2544                 },
2545         },
2546 };
2547
2548 static struct clk_branch gcc_sdcc2_ahb_clk = {
2549         .halt_reg = 0x14008,
2550         .halt_check = BRANCH_HALT,
2551         .clkr = {
2552                 .enable_reg = 0x14008,
2553                 .enable_mask = BIT(0),
2554                 .hw.init = &(struct clk_init_data){
2555                         .name = "gcc_sdcc2_ahb_clk",
2556                         .ops = &clk_branch2_ops,
2557                 },
2558         },
2559 };
2560
2561 static struct clk_branch gcc_sdcc2_apps_clk = {
2562         .halt_reg = 0x14004,
2563         .halt_check = BRANCH_HALT,
2564         .clkr = {
2565                 .enable_reg = 0x14004,
2566                 .enable_mask = BIT(0),
2567                 .hw.init = &(struct clk_init_data){
2568                         .name = "gcc_sdcc2_apps_clk",
2569                         .parent_data = &(const struct clk_parent_data){
2570                                 .hw = &gcc_sdcc2_apps_clk_src.clkr.hw,
2571                         },
2572                         .num_parents = 1,
2573                         .flags = CLK_SET_RATE_PARENT,
2574                         .ops = &clk_branch2_ops,
2575                 },
2576         },
2577 };
2578
2579 static struct clk_branch gcc_sdcc4_ahb_clk = {
2580         .halt_reg = 0x16008,
2581         .halt_check = BRANCH_HALT,
2582         .clkr = {
2583                 .enable_reg = 0x16008,
2584                 .enable_mask = BIT(0),
2585                 .hw.init = &(struct clk_init_data){
2586                         .name = "gcc_sdcc4_ahb_clk",
2587                         .ops = &clk_branch2_ops,
2588                 },
2589         },
2590 };
2591
2592 static struct clk_branch gcc_sdcc4_apps_clk = {
2593         .halt_reg = 0x16004,
2594         .halt_check = BRANCH_HALT,
2595         .clkr = {
2596                 .enable_reg = 0x16004,
2597                 .enable_mask = BIT(0),
2598                 .hw.init = &(struct clk_init_data){
2599                         .name = "gcc_sdcc4_apps_clk",
2600                         .parent_data = &(const struct clk_parent_data){
2601                                 .hw = &gcc_sdcc4_apps_clk_src.clkr.hw,
2602                         },
2603                         .num_parents = 1,
2604                         .flags = CLK_SET_RATE_PARENT,
2605                         .ops = &clk_branch2_ops,
2606                 },
2607         },
2608 };
2609
2610 /* For CPUSS functionality the AHB clock needs to be left enabled */
2611 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2612         .halt_reg = 0x48178,
2613         .halt_check = BRANCH_HALT_VOTED,
2614         .hwcg_reg = 0x48178,
2615         .hwcg_bit = 1,
2616         .clkr = {
2617                 .enable_reg = 0x52000,
2618                 .enable_mask = BIT(0),
2619                 .hw.init = &(struct clk_init_data){
2620                         .name = "gcc_sys_noc_cpuss_ahb_clk",
2621                         .parent_data = &(const struct clk_parent_data){
2622                                 .hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
2623                         },
2624                         .num_parents = 1,
2625                         .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
2626                         .ops = &clk_branch2_ops,
2627                 },
2628         },
2629 };
2630
2631 static struct clk_branch gcc_throttle_pcie_ahb_clk = {
2632         .halt_reg = 0x9001c,
2633         .halt_check = BRANCH_HALT,
2634         .clkr = {
2635                 .enable_reg = 0x9001c,
2636                 .enable_mask = BIT(0),
2637                 .hw.init = &(struct clk_init_data){
2638                         .name = "gcc_throttle_pcie_ahb_clk",
2639                         .ops = &clk_branch2_ops,
2640                 },
2641         },
2642 };
2643
2644 static struct clk_branch gcc_titan_nrt_throttle_core_clk = {
2645         .halt_reg = 0x26024,
2646         .halt_check = BRANCH_HALT_SKIP,
2647         .hwcg_reg = 0x26024,
2648         .hwcg_bit = 1,
2649         .clkr = {
2650                 .enable_reg = 0x26024,
2651                 .enable_mask = BIT(0),
2652                 .hw.init = &(struct clk_init_data){
2653                         .name = "gcc_titan_nrt_throttle_core_clk",
2654                         .ops = &clk_branch2_ops,
2655                 },
2656         },
2657 };
2658
2659 static struct clk_branch gcc_titan_rt_throttle_core_clk = {
2660         .halt_reg = 0x26018,
2661         .halt_check = BRANCH_HALT_SKIP,
2662         .hwcg_reg = 0x26018,
2663         .hwcg_bit = 1,
2664         .clkr = {
2665                 .enable_reg = 0x26018,
2666                 .enable_mask = BIT(0),
2667                 .hw.init = &(struct clk_init_data){
2668                         .name = "gcc_titan_rt_throttle_core_clk",
2669                         .ops = &clk_branch2_ops,
2670                 },
2671         },
2672 };
2673
2674 static struct clk_branch gcc_ufs_1_clkref_en = {
2675         .halt_reg = 0x8c000,
2676         .halt_check = BRANCH_HALT,
2677         .clkr = {
2678                 .enable_reg = 0x8c000,
2679                 .enable_mask = BIT(0),
2680                 .hw.init = &(struct clk_init_data){
2681                         .name = "gcc_ufs_1_clkref_en",
2682                         .ops = &clk_branch2_ops,
2683                 },
2684         },
2685 };
2686
2687 static struct clk_branch gcc_ufs_phy_ahb_clk = {
2688         .halt_reg = 0x77018,
2689         .halt_check = BRANCH_HALT_VOTED,
2690         .hwcg_reg = 0x77018,
2691         .hwcg_bit = 1,
2692         .clkr = {
2693                 .enable_reg = 0x77018,
2694                 .enable_mask = BIT(0),
2695                 .hw.init = &(struct clk_init_data){
2696                         .name = "gcc_ufs_phy_ahb_clk",
2697                         .ops = &clk_branch2_ops,
2698                 },
2699         },
2700 };
2701
2702 static struct clk_branch gcc_ufs_phy_axi_clk = {
2703         .halt_reg = 0x77010,
2704         .halt_check = BRANCH_HALT_VOTED,
2705         .hwcg_reg = 0x77010,
2706         .hwcg_bit = 1,
2707         .clkr = {
2708                 .enable_reg = 0x77010,
2709                 .enable_mask = BIT(0),
2710                 .hw.init = &(struct clk_init_data){
2711                         .name = "gcc_ufs_phy_axi_clk",
2712                         .parent_data = &(const struct clk_parent_data){
2713                                 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
2714                         },
2715                         .num_parents = 1,
2716                         .flags = CLK_SET_RATE_PARENT,
2717                         .ops = &clk_branch2_ops,
2718                 },
2719         },
2720 };
2721
2722 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2723         .halt_reg = 0x77064,
2724         .halt_check = BRANCH_HALT_VOTED,
2725         .hwcg_reg = 0x77064,
2726         .hwcg_bit = 1,
2727         .clkr = {
2728                 .enable_reg = 0x77064,
2729                 .enable_mask = BIT(0),
2730                 .hw.init = &(struct clk_init_data){
2731                         .name = "gcc_ufs_phy_ice_core_clk",
2732                         .parent_data = &(const struct clk_parent_data){
2733                                 .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2734                         },
2735                         .num_parents = 1,
2736                         .flags = CLK_SET_RATE_PARENT,
2737                         .ops = &clk_branch2_ops,
2738                 },
2739         },
2740 };
2741
2742 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2743         .halt_reg = 0x7709c,
2744         .halt_check = BRANCH_HALT_VOTED,
2745         .hwcg_reg = 0x7709c,
2746         .hwcg_bit = 1,
2747         .clkr = {
2748                 .enable_reg = 0x7709c,
2749                 .enable_mask = BIT(0),
2750                 .hw.init = &(struct clk_init_data){
2751                         .name = "gcc_ufs_phy_phy_aux_clk",
2752                         .parent_data = &(const struct clk_parent_data){
2753                                 .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
2754                         },
2755                         .num_parents = 1,
2756                         .flags = CLK_SET_RATE_PARENT,
2757                         .ops = &clk_branch2_ops,
2758                 },
2759         },
2760 };
2761
2762 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
2763         .halt_reg = 0x77020,
2764         .halt_check = BRANCH_HALT_DELAY,
2765         .clkr = {
2766                 .enable_reg = 0x77020,
2767                 .enable_mask = BIT(0),
2768                 .hw.init = &(struct clk_init_data){
2769                         .name = "gcc_ufs_phy_rx_symbol_0_clk",
2770                         .parent_data = &(const struct clk_parent_data){
2771                                 .hw = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
2772                         },
2773                         .num_parents = 1,
2774                         .flags = CLK_SET_RATE_PARENT,
2775                         .ops = &clk_branch2_ops,
2776                 },
2777         },
2778 };
2779
2780 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
2781         .halt_reg = 0x770b8,
2782         .halt_check = BRANCH_HALT_DELAY,
2783         .clkr = {
2784                 .enable_reg = 0x770b8,
2785                 .enable_mask = BIT(0),
2786                 .hw.init = &(struct clk_init_data){
2787                         .name = "gcc_ufs_phy_rx_symbol_1_clk",
2788                         .parent_data = &(const struct clk_parent_data){
2789                                 .hw = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
2790                         },
2791                         .num_parents = 1,
2792                         .flags = CLK_SET_RATE_PARENT,
2793                         .ops = &clk_branch2_ops,
2794                 },
2795         },
2796 };
2797
2798 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
2799         .halt_reg = 0x7701c,
2800         .halt_check = BRANCH_HALT_DELAY,
2801         .clkr = {
2802                 .enable_reg = 0x7701c,
2803                 .enable_mask = BIT(0),
2804                 .hw.init = &(struct clk_init_data){
2805                         .name = "gcc_ufs_phy_tx_symbol_0_clk",
2806                         .parent_data = &(const struct clk_parent_data){
2807                                 .hw = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
2808                         },
2809                         .num_parents = 1,
2810                         .flags = CLK_SET_RATE_PARENT,
2811                         .ops = &clk_branch2_ops,
2812                 },
2813         },
2814 };
2815
2816 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2817         .halt_reg = 0x7705c,
2818         .halt_check = BRANCH_HALT_VOTED,
2819         .hwcg_reg = 0x7705c,
2820         .hwcg_bit = 1,
2821         .clkr = {
2822                 .enable_reg = 0x7705c,
2823                 .enable_mask = BIT(0),
2824                 .hw.init = &(struct clk_init_data){
2825                         .name = "gcc_ufs_phy_unipro_core_clk",
2826                         .parent_data = &(const struct clk_parent_data){
2827                                 .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
2828                         },
2829                         .num_parents = 1,
2830                         .flags = CLK_SET_RATE_PARENT,
2831                         .ops = &clk_branch2_ops,
2832                 },
2833         },
2834 };
2835
2836 static struct clk_branch gcc_usb30_prim_master_clk = {
2837         .halt_reg = 0xf010,
2838         .halt_check = BRANCH_HALT,
2839         .clkr = {
2840                 .enable_reg = 0xf010,
2841                 .enable_mask = BIT(0),
2842                 .hw.init = &(struct clk_init_data){
2843                         .name = "gcc_usb30_prim_master_clk",
2844                         .parent_data = &(const struct clk_parent_data){
2845                                 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
2846                         },
2847                         .num_parents = 1,
2848                         .flags = CLK_SET_RATE_PARENT,
2849                         .ops = &clk_branch2_ops,
2850                 },
2851         },
2852 };
2853
2854 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
2855         .halt_reg = 0xf01c,
2856         .halt_check = BRANCH_HALT,
2857         .clkr = {
2858                 .enable_reg = 0xf01c,
2859                 .enable_mask = BIT(0),
2860                 .hw.init = &(struct clk_init_data){
2861                         .name = "gcc_usb30_prim_mock_utmi_clk",
2862                         .parent_data = &(const struct clk_parent_data){
2863                                 .hw =
2864                                         &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
2865                         },
2866                         .num_parents = 1,
2867                         .flags = CLK_SET_RATE_PARENT,
2868                         .ops = &clk_branch2_ops,
2869                 },
2870         },
2871 };
2872
2873 static struct clk_branch gcc_usb30_prim_sleep_clk = {
2874         .halt_reg = 0xf018,
2875         .halt_check = BRANCH_HALT,
2876         .clkr = {
2877                 .enable_reg = 0xf018,
2878                 .enable_mask = BIT(0),
2879                 .hw.init = &(struct clk_init_data){
2880                         .name = "gcc_usb30_prim_sleep_clk",
2881                         .ops = &clk_branch2_ops,
2882                 },
2883         },
2884 };
2885
2886 static struct clk_branch gcc_usb30_sec_master_clk = {
2887         .halt_reg = 0x9e010,
2888         .halt_check = BRANCH_HALT,
2889         .clkr = {
2890                 .enable_reg = 0x9e010,
2891                 .enable_mask = BIT(0),
2892                 .hw.init = &(struct clk_init_data){
2893                         .name = "gcc_usb30_sec_master_clk",
2894                         .parent_data = &(const struct clk_parent_data){
2895                                 .hw = &gcc_usb30_sec_master_clk_src.clkr.hw,
2896                         },
2897                         .num_parents = 1,
2898                         .flags = CLK_SET_RATE_PARENT,
2899                         .ops = &clk_branch2_ops,
2900                 },
2901         },
2902 };
2903
2904 static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
2905         .halt_reg = 0x9e01c,
2906         .halt_check = BRANCH_HALT,
2907         .clkr = {
2908                 .enable_reg = 0x9e01c,
2909                 .enable_mask = BIT(0),
2910                 .hw.init = &(struct clk_init_data){
2911                         .name = "gcc_usb30_sec_mock_utmi_clk",
2912                         .parent_data = &(const struct clk_parent_data){
2913                                 .hw =
2914                                         &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
2915                         },
2916                         .num_parents = 1,
2917                         .flags = CLK_SET_RATE_PARENT,
2918                         .ops = &clk_branch2_ops,
2919                 },
2920         },
2921 };
2922
2923 static struct clk_branch gcc_usb30_sec_sleep_clk = {
2924         .halt_reg = 0x9e018,
2925         .halt_check = BRANCH_HALT,
2926         .clkr = {
2927                 .enable_reg = 0x9e018,
2928                 .enable_mask = BIT(0),
2929                 .hw.init = &(struct clk_init_data){
2930                         .name = "gcc_usb30_sec_sleep_clk",
2931                         .ops = &clk_branch2_ops,
2932                 },
2933         },
2934 };
2935
2936 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2937         .halt_reg = 0xf054,
2938         .halt_check = BRANCH_HALT,
2939         .clkr = {
2940                 .enable_reg = 0xf054,
2941                 .enable_mask = BIT(0),
2942                 .hw.init = &(struct clk_init_data){
2943                         .name = "gcc_usb3_prim_phy_aux_clk",
2944                         .parent_data = &(const struct clk_parent_data){
2945                                 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2946                         },
2947                         .num_parents = 1,
2948                         .flags = CLK_SET_RATE_PARENT,
2949                         .ops = &clk_branch2_ops,
2950                 },
2951         },
2952 };
2953
2954 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2955         .halt_reg = 0xf058,
2956         .halt_check = BRANCH_HALT,
2957         .clkr = {
2958                 .enable_reg = 0xf058,
2959                 .enable_mask = BIT(0),
2960                 .hw.init = &(struct clk_init_data){
2961                         .name = "gcc_usb3_prim_phy_com_aux_clk",
2962                         .parent_data = &(const struct clk_parent_data){
2963                                 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2964                         },
2965                         .num_parents = 1,
2966                         .flags = CLK_SET_RATE_PARENT,
2967                         .ops = &clk_branch2_ops,
2968                 },
2969         },
2970 };
2971
2972 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2973         .halt_reg = 0xf05c,
2974         .halt_check = BRANCH_HALT_DELAY,
2975         .hwcg_reg = 0xf05c,
2976         .hwcg_bit = 1,
2977         .clkr = {
2978                 .enable_reg = 0xf05c,
2979                 .enable_mask = BIT(0),
2980                 .hw.init = &(struct clk_init_data){
2981                         .name = "gcc_usb3_prim_phy_pipe_clk",
2982                         .parent_data = &(const struct clk_parent_data){
2983                                 .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
2984                         },
2985                         .num_parents = 1,
2986                         .flags = CLK_SET_RATE_PARENT,
2987                         .ops = &clk_branch2_ops,
2988                 },
2989         },
2990 };
2991
2992 static struct clk_branch gcc_cfg_noc_lpass_clk = {
2993         .halt_reg = 0x47020,
2994         .halt_check = BRANCH_HALT,
2995         .clkr = {
2996                 .enable_reg = 0x47020,
2997                 .enable_mask = BIT(0),
2998                 .hw.init = &(struct clk_init_data){
2999                         .name = "gcc_cfg_noc_lpass_clk",
3000                         .ops = &clk_branch2_ops,
3001                 },
3002         },
3003 };
3004 static struct clk_branch gcc_mss_cfg_ahb_clk = {
3005         .halt_reg = 0x8a000,
3006         .halt_check = BRANCH_HALT,
3007         .clkr = {
3008                 .enable_reg = 0x8a000,
3009                 .enable_mask = BIT(0),
3010                 .hw.init = &(struct clk_init_data){
3011                         .name = "gcc_mss_cfg_ahb_clk",
3012                         .ops = &clk_branch2_ops,
3013                 },
3014         },
3015 };
3016
3017 static struct clk_branch gcc_mss_offline_axi_clk = {
3018         .halt_reg = 0x8a004,
3019         .halt_check = BRANCH_HALT_DELAY,
3020         .clkr = {
3021                 .enable_reg = 0x8a004,
3022                 .enable_mask = BIT(0),
3023                 .hw.init = &(struct clk_init_data){
3024                         .name = "gcc_mss_offline_axi_clk",
3025                         .ops = &clk_branch2_ops,
3026                 },
3027         },
3028 };
3029
3030 static struct clk_branch gcc_mss_snoc_axi_clk = {
3031         .halt_reg = 0x8a154,
3032         .halt_check = BRANCH_HALT_DELAY,
3033         .clkr = {
3034                 .enable_reg = 0x8a154,
3035                 .enable_mask = BIT(0),
3036                 .hw.init = &(struct clk_init_data){
3037                         .name = "gcc_mss_snoc_axi_clk",
3038                         .ops = &clk_branch2_ops,
3039                 },
3040         },
3041 };
3042
3043 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
3044         .halt_reg = 0x8a158,
3045         .halt_check = BRANCH_HALT,
3046         .clkr = {
3047                 .enable_reg = 0x8a158,
3048                 .enable_mask = BIT(0),
3049                 .hw.init = &(struct clk_init_data){
3050                         .name = "gcc_mss_q6_memnoc_axi_clk",
3051                         .ops = &clk_branch2_ops,
3052                 },
3053         },
3054 };
3055
3056 static struct clk_regmap_mux gcc_mss_q6ss_boot_clk_src = {
3057         .reg = 0x8a2a4,
3058         .shift = 0,
3059         .width = 1,
3060         .parent_map = gcc_parent_map_15,
3061         .clkr = {
3062                 .hw.init = &(struct clk_init_data){
3063                         .name = "gcc_mss_q6ss_boot_clk_src",
3064                         .parent_data = gcc_parent_data_15,
3065                         .num_parents = ARRAY_SIZE(gcc_parent_data_15),
3066                         .ops = &clk_regmap_mux_closest_ops,
3067                 },
3068         },
3069 };
3070
3071 static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
3072         .halt_reg = 0x9e054,
3073         .halt_check = BRANCH_HALT,
3074         .clkr = {
3075                 .enable_reg = 0x9e054,
3076                 .enable_mask = BIT(0),
3077                 .hw.init = &(struct clk_init_data){
3078                         .name = "gcc_usb3_sec_phy_aux_clk",
3079                         .parent_data = &(const struct clk_parent_data){
3080                                 .hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3081                         },
3082                         .num_parents = 1,
3083                         .flags = CLK_SET_RATE_PARENT,
3084                         .ops = &clk_branch2_ops,
3085                 },
3086         },
3087 };
3088
3089 static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
3090         .halt_reg = 0x9e058,
3091         .halt_check = BRANCH_HALT,
3092         .clkr = {
3093                 .enable_reg = 0x9e058,
3094                 .enable_mask = BIT(0),
3095                 .hw.init = &(struct clk_init_data){
3096                         .name = "gcc_usb3_sec_phy_com_aux_clk",
3097                         .parent_data = &(const struct clk_parent_data){
3098                                 .hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3099                         },
3100                         .num_parents = 1,
3101                         .flags = CLK_SET_RATE_PARENT,
3102                         .ops = &clk_branch2_ops,
3103                 },
3104         },
3105 };
3106
3107 static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
3108         .halt_reg = 0x9e05c,
3109         .halt_check = BRANCH_HALT_SKIP,
3110         .hwcg_reg = 0x9e05c,
3111         .hwcg_bit = 1,
3112         .clkr = {
3113                 .enable_reg = 0x9e05c,
3114                 .enable_mask = BIT(0),
3115                 .hw.init = &(struct clk_init_data){
3116                         .name = "gcc_usb3_sec_phy_pipe_clk",
3117                         .parent_data = &(const struct clk_parent_data){
3118                                 .hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
3119                         },
3120                         .num_parents = 1,
3121                         .flags = CLK_SET_RATE_PARENT,
3122                         .ops = &clk_branch2_ops,
3123                 },
3124         },
3125 };
3126
3127 static struct clk_branch gcc_video_axi0_clk = {
3128         .halt_reg = 0x2800c,
3129         .halt_check = BRANCH_HALT_SKIP,
3130         .hwcg_reg = 0x2800c,
3131         .hwcg_bit = 1,
3132         .clkr = {
3133                 .enable_reg = 0x2800c,
3134                 .enable_mask = BIT(0),
3135                 .hw.init = &(struct clk_init_data){
3136                         .name = "gcc_video_axi0_clk",
3137                         .ops = &clk_branch2_ops,
3138                 },
3139         },
3140 };
3141
3142 static struct clk_branch gcc_video_mvp_throttle_core_clk = {
3143         .halt_reg = 0x28010,
3144         .halt_check = BRANCH_HALT_SKIP,
3145         .hwcg_reg = 0x28010,
3146         .hwcg_bit = 1,
3147         .clkr = {
3148                 .enable_reg = 0x28010,
3149                 .enable_mask = BIT(0),
3150                 .hw.init = &(struct clk_init_data){
3151                         .name = "gcc_video_mvp_throttle_core_clk",
3152                         .ops = &clk_branch2_ops,
3153                 },
3154         },
3155 };
3156
3157 static struct clk_branch gcc_wpss_ahb_clk = {
3158         .halt_reg = 0x9d154,
3159         .halt_check = BRANCH_HALT,
3160         .clkr = {
3161                 .enable_reg = 0x9d154,
3162                 .enable_mask = BIT(0),
3163                 .hw.init = &(struct clk_init_data){
3164                         .name = "gcc_wpss_ahb_clk",
3165                         .ops = &clk_branch2_ops,
3166                 },
3167         },
3168 };
3169
3170 static struct clk_branch gcc_wpss_ahb_bdg_mst_clk = {
3171         .halt_reg = 0x9d158,
3172         .halt_check = BRANCH_HALT,
3173         .clkr = {
3174                 .enable_reg = 0x9d158,
3175                 .enable_mask = BIT(0),
3176                 .hw.init = &(struct clk_init_data){
3177                         .name = "gcc_wpss_ahb_bdg_mst_clk",
3178                         .ops = &clk_branch2_ops,
3179                 },
3180         },
3181 };
3182
3183 static struct clk_branch gcc_wpss_rscp_clk = {
3184         .halt_reg = 0x9d16c,
3185         .halt_check = BRANCH_HALT,
3186         .clkr = {
3187                 .enable_reg = 0x9d16c,
3188                 .enable_mask = BIT(0),
3189                 .hw.init = &(struct clk_init_data){
3190                         .name = "gcc_wpss_rscp_clk",
3191                         .ops = &clk_branch2_ops,
3192                 },
3193         },
3194 };
3195
3196 static struct gdsc gcc_pcie_0_gdsc = {
3197         .gdscr = 0x6b004,
3198         .pd = {
3199                 .name = "gcc_pcie_0_gdsc",
3200         },
3201         .pwrsts = PWRSTS_OFF_ON,
3202         .flags = VOTABLE,
3203 };
3204
3205 static struct gdsc gcc_pcie_1_gdsc = {
3206         .gdscr = 0x8d004,
3207         .pd = {
3208                 .name = "gcc_pcie_1_gdsc",
3209         },
3210         .pwrsts = PWRSTS_OFF_ON,
3211         .flags = VOTABLE,
3212 };
3213
3214 static struct gdsc gcc_ufs_phy_gdsc = {
3215         .gdscr = 0x77004,
3216         .pd = {
3217                 .name = "gcc_ufs_phy_gdsc",
3218         },
3219         .pwrsts = PWRSTS_OFF_ON,
3220         .flags = VOTABLE,
3221 };
3222
3223 static struct gdsc gcc_usb30_prim_gdsc = {
3224         .gdscr = 0xf004,
3225         .pd = {
3226                 .name = "gcc_usb30_prim_gdsc",
3227         },
3228         .pwrsts = PWRSTS_OFF_ON,
3229         .flags = VOTABLE,
3230 };
3231
3232 static struct gdsc gcc_usb30_sec_gdsc = {
3233         .gdscr = 0x9e004,
3234         .pd = {
3235                 .name = "gcc_usb30_sec_gdsc",
3236         },
3237         .pwrsts = PWRSTS_OFF_ON,
3238         .flags = VOTABLE,
3239 };
3240
3241 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
3242         .gdscr = 0x7d050,
3243         .pd = {
3244                 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
3245         },
3246         .pwrsts = PWRSTS_OFF_ON,
3247         .flags = VOTABLE,
3248 };
3249
3250 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
3251         .gdscr = 0x7d058,
3252         .pd = {
3253                 .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
3254         },
3255         .pwrsts = PWRSTS_OFF_ON,
3256         .flags = VOTABLE,
3257 };
3258
3259 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = {
3260         .gdscr = 0x7d054,
3261         .pd = {
3262                 .name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc",
3263         },
3264         .pwrsts = PWRSTS_OFF_ON,
3265         .flags = VOTABLE,
3266 };
3267
3268 static struct gdsc hlos1_vote_turing_mmu_tbu0_gdsc = {
3269         .gdscr = 0x7d05c,
3270         .pd = {
3271                 .name = "hlos1_vote_turing_mmu_tbu0_gdsc",
3272         },
3273         .pwrsts = PWRSTS_OFF_ON,
3274         .flags = VOTABLE,
3275 };
3276
3277 static struct gdsc hlos1_vote_turing_mmu_tbu1_gdsc = {
3278         .gdscr = 0x7d060,
3279         .pd = {
3280                 .name = "hlos1_vote_turing_mmu_tbu1_gdsc",
3281         },
3282         .pwrsts = PWRSTS_OFF_ON,
3283         .flags = VOTABLE,
3284 };
3285
3286 static struct clk_regmap *gcc_sc7280_clocks[] = {
3287         [GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr,
3288         [GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr,
3289         [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3290         [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3291         [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3292         [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3293         [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3294         [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3295         [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3296         [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
3297         [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3298         [GCC_CPUSS_AHB_POSTDIV_CLK_SRC] = &gcc_cpuss_ahb_postdiv_clk_src.clkr,
3299         [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3300         [GCC_DDRSS_PCIE_SF_CLK] = &gcc_ddrss_pcie_sf_clk.clkr,
3301         [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
3302         [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3303         [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
3304         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3305         [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3306         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3307         [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3308         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3309         [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3310         [GCC_GPLL0] = &gcc_gpll0.clkr,
3311         [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
3312         [GCC_GPLL0_OUT_ODD] = &gcc_gpll0_out_odd.clkr,
3313         [GCC_GPLL1] = &gcc_gpll1.clkr,
3314         [GCC_GPLL10] = &gcc_gpll10.clkr,
3315         [GCC_GPLL4] = &gcc_gpll4.clkr,
3316         [GCC_GPLL9] = &gcc_gpll9.clkr,
3317         [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3318         [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3319         [GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr,
3320         [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3321         [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3322         [GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr,
3323         [GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr,
3324         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3325         [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3326         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3327         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3328         [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
3329         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3330         [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
3331         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3332         [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3333         [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3334         [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3335         [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3336         [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3337         [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
3338         [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3339         [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
3340         [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3341         [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3342         [GCC_PCIE_THROTTLE_CORE_CLK] = &gcc_pcie_throttle_core_clk.clkr,
3343         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3344         [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3345         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3346         [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3347         [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3348         [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3349         [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3350         [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3351         [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3352         [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3353         [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3354         [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3355         [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3356         [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3357         [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3358         [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3359         [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3360         [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3361         [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3362         [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3363         [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3364         [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3365         [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3366         [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3367         [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3368         [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3369         [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3370         [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3371         [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3372         [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
3373         [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
3374         [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3375         [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3376         [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3377         [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3378         [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3379         [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3380         [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3381         [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3382         [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3383         [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3384         [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3385         [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3386         [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
3387         [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
3388         [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
3389         [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
3390         [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3391         [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3392         [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3393         [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3394         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3395         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3396         [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
3397         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3398         [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
3399         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3400         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3401         [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3402         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3403         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3404         [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3405         [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3406         [GCC_THROTTLE_PCIE_AHB_CLK] = &gcc_throttle_pcie_ahb_clk.clkr,
3407         [GCC_TITAN_NRT_THROTTLE_CORE_CLK] =
3408                 &gcc_titan_nrt_throttle_core_clk.clkr,
3409         [GCC_TITAN_RT_THROTTLE_CORE_CLK] = &gcc_titan_rt_throttle_core_clk.clkr,
3410         [GCC_UFS_1_CLKREF_EN] = &gcc_ufs_1_clkref_en.clkr,
3411         [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3412         [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3413         [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3414         [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3415         [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3416         [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3417         [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3418         [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3419         [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] =
3420                 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
3421         [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3422         [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] =
3423                 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
3424         [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3425         [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] =
3426                 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
3427         [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3428         [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3429                 &gcc_ufs_phy_unipro_core_clk_src.clkr,
3430         [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3431         [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3432         [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3433         [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3434                 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3435         [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] =
3436                 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3437         [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3438         [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3439         [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3440         [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3441         [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
3442                         &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3443         [GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] =
3444                         &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
3445         [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3446         [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3447         [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3448         [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3449         [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3450         [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
3451         [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3452         [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3453         [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3454         [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
3455         [GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
3456         [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3457         [GCC_VIDEO_MVP_THROTTLE_CORE_CLK] =
3458                         &gcc_video_mvp_throttle_core_clk.clkr,
3459         [GCC_CFG_NOC_LPASS_CLK] = &gcc_cfg_noc_lpass_clk.clkr,
3460         [GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC] = &gcc_mss_gpll0_main_div_clk_src.clkr,
3461         [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3462         [GCC_MSS_OFFLINE_AXI_CLK] = &gcc_mss_offline_axi_clk.clkr,
3463         [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
3464         [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
3465         [GCC_MSS_Q6SS_BOOT_CLK_SRC] = &gcc_mss_q6ss_boot_clk_src.clkr,
3466         [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3467         [GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK] =
3468                                 &gcc_aggre_noc_pcie_center_sf_axi_clk.clkr,
3469         [GCC_PCIE_CLKREF_EN] = &gcc_pcie_clkref_en.clkr,
3470         [GCC_EDP_CLKREF_EN] = &gcc_edp_clkref_en.clkr,
3471         [GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr,
3472         [GCC_WPSS_AHB_CLK] = &gcc_wpss_ahb_clk.clkr,
3473         [GCC_WPSS_AHB_BDG_MST_CLK] = &gcc_wpss_ahb_bdg_mst_clk.clkr,
3474         [GCC_WPSS_RSCP_CLK] = &gcc_wpss_rscp_clk.clkr,
3475 };
3476
3477 static struct gdsc *gcc_sc7280_gdscs[] = {
3478         [GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc,
3479         [GCC_PCIE_1_GDSC] = &gcc_pcie_1_gdsc,
3480         [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc,
3481         [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
3482         [GCC_USB30_SEC_GDSC] = &gcc_usb30_sec_gdsc,
3483         [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
3484         [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
3485         [HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc,
3486         [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = &hlos1_vote_turing_mmu_tbu0_gdsc,
3487         [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = &hlos1_vote_turing_mmu_tbu1_gdsc,
3488 };
3489
3490 static const struct qcom_reset_map gcc_sc7280_resets[] = {
3491         [GCC_PCIE_0_BCR] = { 0x6b000 },
3492         [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3493         [GCC_PCIE_1_BCR] = { 0x8d000 },
3494         [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3495         [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3496         [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3497         [GCC_SDCC1_BCR] = { 0x75000 },
3498         [GCC_SDCC2_BCR] = { 0x14000 },
3499         [GCC_SDCC4_BCR] = { 0x16000 },
3500         [GCC_UFS_PHY_BCR] = { 0x77000 },
3501         [GCC_USB30_PRIM_BCR] = { 0xf000 },
3502         [GCC_USB30_SEC_BCR] = { 0x9e000 },
3503         [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3504         [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3505         [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3506         [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3507 };
3508
3509 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3510         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3511         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3512         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3513         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3514         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3515         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3516         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3517         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
3518         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3519         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3520         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3521         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3522         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3523         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3524         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
3525         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
3526 };
3527
3528 static const struct regmap_config gcc_sc7280_regmap_config = {
3529         .reg_bits = 32,
3530         .reg_stride = 4,
3531         .val_bits = 32,
3532         .max_register = 0x9f128,
3533         .fast_io = true,
3534 };
3535
3536 static const struct qcom_cc_desc gcc_sc7280_desc = {
3537         .config = &gcc_sc7280_regmap_config,
3538         .clks = gcc_sc7280_clocks,
3539         .num_clks = ARRAY_SIZE(gcc_sc7280_clocks),
3540         .resets = gcc_sc7280_resets,
3541         .num_resets = ARRAY_SIZE(gcc_sc7280_resets),
3542         .gdscs = gcc_sc7280_gdscs,
3543         .num_gdscs = ARRAY_SIZE(gcc_sc7280_gdscs),
3544 };
3545
3546 static const struct of_device_id gcc_sc7280_match_table[] = {
3547         { .compatible = "qcom,gcc-sc7280" },
3548         { }
3549 };
3550 MODULE_DEVICE_TABLE(of, gcc_sc7280_match_table);
3551
3552 static int gcc_sc7280_probe(struct platform_device *pdev)
3553 {
3554         struct regmap *regmap;
3555         int ret;
3556
3557         regmap = qcom_cc_map(pdev, &gcc_sc7280_desc);
3558         if (IS_ERR(regmap))
3559                 return PTR_ERR(regmap);
3560
3561         /*
3562          * Keep the clocks always-ON
3563          * GCC_CAMERA_AHB_CLK/XO_CLK, GCC_DISP_AHB_CLK/XO_CLK
3564          * GCC_VIDEO_AHB_CLK/XO_CLK, GCC_GPU_CFG_AHB_CLK
3565          */
3566         regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0));
3567         regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0));
3568         regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0));
3569         regmap_update_bits(regmap, 0x2701C, BIT(0), BIT(0));
3570         regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0));
3571         regmap_update_bits(regmap, 0x28014, BIT(0), BIT(0));
3572         regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
3573
3574         ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
3575                         ARRAY_SIZE(gcc_dfs_clocks));
3576         if (ret)
3577                 return ret;
3578
3579         return qcom_cc_really_probe(pdev, &gcc_sc7280_desc, regmap);
3580 }
3581
3582 static struct platform_driver gcc_sc7280_driver = {
3583         .probe = gcc_sc7280_probe,
3584         .driver = {
3585                 .name = "gcc-sc7280",
3586                 .of_match_table = gcc_sc7280_match_table,
3587         },
3588 };
3589
3590 static int __init gcc_sc7280_init(void)
3591 {
3592         return platform_driver_register(&gcc_sc7280_driver);
3593 }
3594 subsys_initcall(gcc_sc7280_init);
3595
3596 static void __exit gcc_sc7280_exit(void)
3597 {
3598         platform_driver_unregister(&gcc_sc7280_driver);
3599 }
3600 module_exit(gcc_sc7280_exit);
3601
3602 MODULE_DESCRIPTION("QTI GCC SC7280 Driver");
3603 MODULE_LICENSE("GPL v2");