1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
11 #include <linux/of_device.h>
12 #include <linux/regmap.h>
14 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
19 #include "clk-regmap.h"
26 P_CORE_BI_PLL_TEST_SE,
36 static struct clk_alpha_pll gpll0 = {
38 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
40 .enable_reg = 0x52010,
41 .enable_mask = BIT(0),
42 .hw.init = &(struct clk_init_data){
44 .parent_data = &(const struct clk_parent_data){
49 .ops = &clk_alpha_pll_fixed_fabia_ops,
54 static const struct clk_div_table post_div_table_gpll0_out_even[] = {
59 static struct clk_alpha_pll_postdiv gpll0_out_even = {
62 .post_div_table = post_div_table_gpll0_out_even,
63 .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
65 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
66 .clkr.hw.init = &(struct clk_init_data){
67 .name = "gpll0_out_even",
68 .parent_data = &(const struct clk_parent_data){
72 .ops = &clk_alpha_pll_postdiv_fabia_ops,
76 static struct clk_fixed_factor gcc_pll0_main_div_cdiv = {
79 .hw.init = &(struct clk_init_data){
80 .name = "gcc_pll0_main_div_cdiv",
81 .parent_data = &(const struct clk_parent_data){
85 .ops = &clk_fixed_factor_ops,
89 static struct clk_alpha_pll gpll1 = {
91 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
93 .enable_reg = 0x52010,
94 .enable_mask = BIT(1),
95 .hw.init = &(struct clk_init_data){
97 .parent_data = &(const struct clk_parent_data){
102 .ops = &clk_alpha_pll_fixed_fabia_ops,
107 static struct clk_alpha_pll gpll4 = {
109 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
111 .enable_reg = 0x52010,
112 .enable_mask = BIT(4),
113 .hw.init = &(struct clk_init_data){
115 .parent_data = &(const struct clk_parent_data){
116 .fw_name = "bi_tcxo",
120 .ops = &clk_alpha_pll_fixed_fabia_ops,
125 static struct clk_alpha_pll gpll6 = {
127 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
129 .enable_reg = 0x52010,
130 .enable_mask = BIT(6),
131 .hw.init = &(struct clk_init_data){
133 .parent_data = &(const struct clk_parent_data){
134 .fw_name = "bi_tcxo",
138 .ops = &clk_alpha_pll_fixed_fabia_ops,
143 static struct clk_alpha_pll gpll7 = {
145 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
147 .enable_reg = 0x52010,
148 .enable_mask = BIT(7),
149 .hw.init = &(struct clk_init_data){
151 .parent_data = &(const struct clk_parent_data){
152 .fw_name = "bi_tcxo",
156 .ops = &clk_alpha_pll_fixed_fabia_ops,
161 static const struct parent_map gcc_parent_map_0[] = {
163 { P_GPLL0_OUT_MAIN, 1 },
164 { P_GPLL0_OUT_EVEN, 6 },
165 { P_CORE_BI_PLL_TEST_SE, 7 },
168 static const struct clk_parent_data gcc_parent_data_0[] = {
169 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
170 { .hw = &gpll0.clkr.hw },
171 { .hw = &gpll0_out_even.clkr.hw },
172 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
175 static const struct clk_parent_data gcc_parent_data_0_ao[] = {
176 { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
177 { .hw = &gpll0.clkr.hw },
178 { .hw = &gpll0_out_even.clkr.hw },
179 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
182 static const struct parent_map gcc_parent_map_1[] = {
184 { P_GPLL0_OUT_MAIN, 1 },
185 { P_GPLL6_OUT_MAIN, 2 },
186 { P_GPLL0_OUT_EVEN, 6 },
187 { P_CORE_BI_PLL_TEST_SE, 7 },
190 static const struct clk_parent_data gcc_parent_data_1[] = {
191 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
192 { .hw = &gpll0.clkr.hw },
193 { .hw = &gpll6.clkr.hw },
194 { .hw = &gpll0_out_even.clkr.hw },
195 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
198 static const struct parent_map gcc_parent_map_2[] = {
200 { P_GPLL0_OUT_MAIN, 1 },
201 { P_GPLL1_OUT_MAIN, 4 },
202 { P_GPLL4_OUT_MAIN, 5 },
203 { P_GPLL0_OUT_EVEN, 6 },
204 { P_CORE_BI_PLL_TEST_SE, 7 },
207 static const struct clk_parent_data gcc_parent_data_2[] = {
208 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
209 { .hw = &gpll0.clkr.hw },
210 { .hw = &gpll1.clkr.hw },
211 { .hw = &gpll4.clkr.hw },
212 { .hw = &gpll0_out_even.clkr.hw },
213 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
216 static const struct parent_map gcc_parent_map_3[] = {
218 { P_GPLL0_OUT_MAIN, 1 },
219 { P_CORE_BI_PLL_TEST_SE, 7 },
222 static const struct clk_parent_data gcc_parent_data_3[] = {
223 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
224 { .hw = &gpll0.clkr.hw },
225 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
228 static const struct parent_map gcc_parent_map_4[] = {
230 { P_GPLL0_OUT_MAIN, 1 },
232 { P_GPLL0_OUT_EVEN, 6 },
233 { P_CORE_BI_PLL_TEST_SE, 7 },
236 static const struct clk_parent_data gcc_parent_data_4[] = {
237 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
238 { .hw = &gpll0.clkr.hw },
239 { .fw_name = "sleep_clk", .name = "sleep_clk" },
240 { .hw = &gpll0_out_even.clkr.hw },
241 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
244 static const struct parent_map gcc_parent_map_5[] = {
246 { P_GPLL0_OUT_MAIN, 1 },
247 { P_GPLL7_OUT_MAIN, 3 },
248 { P_GPLL0_OUT_EVEN, 6 },
249 { P_CORE_BI_PLL_TEST_SE, 7 },
252 static const struct clk_parent_data gcc_parent_data_5[] = {
253 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
254 { .hw = &gpll0.clkr.hw },
255 { .hw = &gpll7.clkr.hw },
256 { .hw = &gpll0_out_even.clkr.hw },
257 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
260 static const struct parent_map gcc_parent_map_6[] = {
262 { P_GPLL0_OUT_MAIN, 1 },
264 { P_CORE_BI_PLL_TEST_SE, 7 },
267 static const struct clk_parent_data gcc_parent_data_6[] = {
268 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
269 { .hw = &gpll0.clkr.hw },
270 { .fw_name = "sleep_clk", .name = "sleep_clk" },
271 { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
274 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
275 F(19200000, P_BI_TCXO, 1, 0, 0),
279 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
283 .parent_map = gcc_parent_map_0,
284 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
285 .clkr.hw.init = &(struct clk_init_data){
286 .name = "gcc_cpuss_ahb_clk_src",
287 .parent_data = gcc_parent_data_0_ao,
289 .flags = CLK_SET_RATE_PARENT,
290 .ops = &clk_rcg2_ops,
294 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
295 F(19200000, P_BI_TCXO, 1, 0, 0),
296 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
297 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
298 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
299 F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
303 static struct clk_rcg2 gcc_gp1_clk_src = {
307 .parent_map = gcc_parent_map_4,
308 .freq_tbl = ftbl_gcc_gp1_clk_src,
309 .clkr.hw.init = &(struct clk_init_data){
310 .name = "gcc_gp1_clk_src",
311 .parent_data = gcc_parent_data_4,
313 .ops = &clk_rcg2_ops,
317 static struct clk_rcg2 gcc_gp2_clk_src = {
321 .parent_map = gcc_parent_map_4,
322 .freq_tbl = ftbl_gcc_gp1_clk_src,
323 .clkr.hw.init = &(struct clk_init_data){
324 .name = "gcc_gp2_clk_src",
325 .parent_data = gcc_parent_data_4,
327 .ops = &clk_rcg2_ops,
331 static struct clk_rcg2 gcc_gp3_clk_src = {
335 .parent_map = gcc_parent_map_4,
336 .freq_tbl = ftbl_gcc_gp1_clk_src,
337 .clkr.hw.init = &(struct clk_init_data){
338 .name = "gcc_gp3_clk_src",
339 .parent_data = gcc_parent_data_4,
341 .ops = &clk_rcg2_ops,
345 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
346 F(19200000, P_BI_TCXO, 1, 0, 0),
347 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
351 static struct clk_rcg2 gcc_pdm2_clk_src = {
355 .parent_map = gcc_parent_map_0,
356 .freq_tbl = ftbl_gcc_pdm2_clk_src,
357 .clkr.hw.init = &(struct clk_init_data){
358 .name = "gcc_pdm2_clk_src",
359 .parent_data = gcc_parent_data_0,
361 .ops = &clk_rcg2_ops,
365 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
366 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
367 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
368 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
372 static struct clk_rcg2 gcc_qspi_core_clk_src = {
376 .parent_map = gcc_parent_map_2,
377 .freq_tbl = ftbl_gcc_qspi_core_clk_src,
378 .clkr.hw.init = &(struct clk_init_data){
379 .name = "gcc_qspi_core_clk_src",
380 .parent_data = gcc_parent_data_2,
382 .ops = &clk_rcg2_ops,
386 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
387 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
388 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
389 F(19200000, P_BI_TCXO, 1, 0, 0),
390 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
391 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
392 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
393 F(51200000, P_GPLL6_OUT_MAIN, 7.5, 0, 0),
394 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
395 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
396 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
397 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
398 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
399 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
400 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
401 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
402 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
403 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
407 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
408 .name = "gcc_qupv3_wrap0_s0_clk_src",
409 .parent_data = gcc_parent_data_1,
410 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
411 .ops = &clk_rcg2_ops,
414 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
418 .parent_map = gcc_parent_map_1,
419 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
420 .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
423 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
424 .name = "gcc_qupv3_wrap0_s1_clk_src",
425 .parent_data = gcc_parent_data_1,
426 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
427 .ops = &clk_rcg2_ops,
430 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
434 .parent_map = gcc_parent_map_1,
435 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
436 .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
439 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
440 .name = "gcc_qupv3_wrap0_s2_clk_src",
441 .parent_data = gcc_parent_data_1,
442 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
443 .ops = &clk_rcg2_ops,
446 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
450 .parent_map = gcc_parent_map_1,
451 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
452 .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
455 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
456 .name = "gcc_qupv3_wrap0_s3_clk_src",
457 .parent_data = gcc_parent_data_1,
458 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
459 .ops = &clk_rcg2_ops,
462 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
466 .parent_map = gcc_parent_map_1,
467 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
468 .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
471 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
472 .name = "gcc_qupv3_wrap0_s4_clk_src",
473 .parent_data = gcc_parent_data_1,
474 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
475 .ops = &clk_rcg2_ops,
478 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
482 .parent_map = gcc_parent_map_1,
483 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
484 .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
487 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
488 .name = "gcc_qupv3_wrap0_s5_clk_src",
489 .parent_data = gcc_parent_data_1,
490 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
491 .ops = &clk_rcg2_ops,
494 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
498 .parent_map = gcc_parent_map_1,
499 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
500 .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
503 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
504 .name = "gcc_qupv3_wrap1_s0_clk_src",
505 .parent_data = gcc_parent_data_1,
506 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
507 .ops = &clk_rcg2_ops,
510 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
514 .parent_map = gcc_parent_map_1,
515 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
516 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
519 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
520 .name = "gcc_qupv3_wrap1_s1_clk_src",
521 .parent_data = gcc_parent_data_1,
522 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
523 .ops = &clk_rcg2_ops,
526 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
530 .parent_map = gcc_parent_map_1,
531 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
532 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
535 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
536 .name = "gcc_qupv3_wrap1_s2_clk_src",
537 .parent_data = gcc_parent_data_1,
538 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
539 .ops = &clk_rcg2_ops,
542 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
546 .parent_map = gcc_parent_map_1,
547 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
548 .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
551 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
552 .name = "gcc_qupv3_wrap1_s3_clk_src",
553 .parent_data = gcc_parent_data_1,
554 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
555 .ops = &clk_rcg2_ops,
558 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
562 .parent_map = gcc_parent_map_1,
563 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
564 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
567 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
568 .name = "gcc_qupv3_wrap1_s4_clk_src",
569 .parent_data = gcc_parent_data_1,
570 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
571 .ops = &clk_rcg2_ops,
574 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
578 .parent_map = gcc_parent_map_1,
579 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
580 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
583 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
584 .name = "gcc_qupv3_wrap1_s5_clk_src",
585 .parent_data = gcc_parent_data_1,
586 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
587 .ops = &clk_rcg2_ops,
590 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
594 .parent_map = gcc_parent_map_1,
595 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
596 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
600 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
601 F(144000, P_BI_TCXO, 16, 3, 25),
602 F(400000, P_BI_TCXO, 12, 1, 4),
603 F(19200000, P_BI_TCXO, 1, 0, 0),
604 F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
605 F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2),
606 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
607 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
608 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
609 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
613 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
617 .parent_map = gcc_parent_map_1,
618 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
619 .clkr.hw.init = &(struct clk_init_data){
620 .name = "gcc_sdcc1_apps_clk_src",
621 .parent_data = gcc_parent_data_1,
623 .ops = &clk_rcg2_floor_ops,
627 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
628 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
629 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
630 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
631 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
635 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
639 .parent_map = gcc_parent_map_0,
640 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
641 .clkr.hw.init = &(struct clk_init_data){
642 .name = "gcc_sdcc1_ice_core_clk_src",
643 .parent_data = gcc_parent_data_0,
645 .ops = &clk_rcg2_ops,
649 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
650 F(400000, P_BI_TCXO, 12, 1, 4),
651 F(9600000, P_BI_TCXO, 2, 0, 0),
652 F(19200000, P_BI_TCXO, 1, 0, 0),
653 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
654 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
655 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
656 F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
660 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
664 .parent_map = gcc_parent_map_5,
665 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
666 .clkr.hw.init = &(struct clk_init_data){
667 .name = "gcc_sdcc2_apps_clk_src",
668 .parent_data = gcc_parent_data_5,
670 .ops = &clk_rcg2_floor_ops,
674 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
675 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
676 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
677 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
678 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
679 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
683 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
687 .parent_map = gcc_parent_map_0,
688 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
689 .clkr.hw.init = &(struct clk_init_data){
690 .name = "gcc_ufs_phy_axi_clk_src",
691 .parent_data = gcc_parent_data_0,
693 .ops = &clk_rcg2_ops,
697 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
698 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
699 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
700 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
701 F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
705 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
709 .parent_map = gcc_parent_map_0,
710 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
711 .clkr.hw.init = &(struct clk_init_data){
712 .name = "gcc_ufs_phy_ice_core_clk_src",
713 .parent_data = gcc_parent_data_0,
715 .ops = &clk_rcg2_ops,
719 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
720 F(9600000, P_BI_TCXO, 2, 0, 0),
721 F(19200000, P_BI_TCXO, 1, 0, 0),
725 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
729 .parent_map = gcc_parent_map_3,
730 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
731 .clkr.hw.init = &(struct clk_init_data){
732 .name = "gcc_ufs_phy_phy_aux_clk_src",
733 .parent_data = gcc_parent_data_3,
735 .ops = &clk_rcg2_ops,
739 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
740 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
741 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
742 F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
746 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
750 .parent_map = gcc_parent_map_0,
751 .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
752 .clkr.hw.init = &(struct clk_init_data){
753 .name = "gcc_ufs_phy_unipro_core_clk_src",
754 .parent_data = gcc_parent_data_0,
756 .ops = &clk_rcg2_ops,
760 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
761 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
762 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
763 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
764 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
768 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
772 .parent_map = gcc_parent_map_0,
773 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
774 .clkr.hw.init = &(struct clk_init_data){
775 .name = "gcc_usb30_prim_master_clk_src",
776 .parent_data = gcc_parent_data_0,
778 .ops = &clk_rcg2_ops,
782 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
783 F(19200000, P_BI_TCXO, 1, 0, 0),
784 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
788 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
792 .parent_map = gcc_parent_map_0,
793 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
794 .clkr.hw.init = &(struct clk_init_data){
795 .name = "gcc_usb30_prim_mock_utmi_clk_src",
796 .parent_data = gcc_parent_data_0,
798 .ops = &clk_rcg2_ops,
802 static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = {
803 F(19200000, P_BI_TCXO, 1, 0, 0),
807 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
811 .parent_map = gcc_parent_map_6,
812 .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src,
813 .clkr.hw.init = &(struct clk_init_data){
814 .name = "gcc_usb3_prim_phy_aux_clk_src",
815 .parent_data = gcc_parent_data_6,
817 .ops = &clk_rcg2_ops,
821 static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = {
822 F(4800000, P_BI_TCXO, 4, 0, 0),
823 F(19200000, P_BI_TCXO, 1, 0, 0),
827 static struct clk_rcg2 gcc_sec_ctrl_clk_src = {
831 .parent_map = gcc_parent_map_3,
832 .freq_tbl = ftbl_gcc_sec_ctrl_clk_src,
833 .clkr.hw.init = &(struct clk_init_data){
834 .name = "gcc_sec_ctrl_clk_src",
835 .parent_data = gcc_parent_data_3,
836 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
837 .ops = &clk_rcg2_ops,
841 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
843 .halt_check = BRANCH_HALT_DELAY,
847 .enable_reg = 0x82024,
848 .enable_mask = BIT(0),
849 .hw.init = &(struct clk_init_data){
850 .name = "gcc_aggre_ufs_phy_axi_clk",
851 .parent_data = &(const struct clk_parent_data){
852 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
855 .flags = CLK_SET_RATE_PARENT,
856 .ops = &clk_branch2_ops,
861 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
863 .halt_check = BRANCH_HALT,
865 .enable_reg = 0x8201c,
866 .enable_mask = BIT(0),
867 .hw.init = &(struct clk_init_data){
868 .name = "gcc_aggre_usb3_prim_axi_clk",
869 .parent_data = &(const struct clk_parent_data){
870 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
873 .flags = CLK_SET_RATE_PARENT,
874 .ops = &clk_branch2_ops,
879 static struct clk_branch gcc_boot_rom_ahb_clk = {
881 .halt_check = BRANCH_HALT_VOTED,
885 .enable_reg = 0x52000,
886 .enable_mask = BIT(10),
887 .hw.init = &(struct clk_init_data){
888 .name = "gcc_boot_rom_ahb_clk",
889 .ops = &clk_branch2_ops,
894 static struct clk_branch gcc_camera_hf_axi_clk = {
896 .halt_check = BRANCH_HALT,
898 .enable_reg = 0xb020,
899 .enable_mask = BIT(0),
900 .hw.init = &(struct clk_init_data){
901 .name = "gcc_camera_hf_axi_clk",
902 .ops = &clk_branch2_ops,
907 static struct clk_branch gcc_camera_throttle_hf_axi_clk = {
909 .halt_check = BRANCH_HALT,
913 .enable_reg = 0xb080,
914 .enable_mask = BIT(0),
915 .hw.init = &(struct clk_init_data){
916 .name = "gcc_camera_throttle_hf_axi_clk",
917 .ops = &clk_branch2_ops,
922 static struct clk_branch gcc_ce1_ahb_clk = {
924 .halt_check = BRANCH_HALT_VOTED,
928 .enable_reg = 0x52000,
929 .enable_mask = BIT(3),
930 .hw.init = &(struct clk_init_data){
931 .name = "gcc_ce1_ahb_clk",
932 .ops = &clk_branch2_ops,
937 static struct clk_branch gcc_ce1_axi_clk = {
939 .halt_check = BRANCH_HALT_VOTED,
941 .enable_reg = 0x52000,
942 .enable_mask = BIT(4),
943 .hw.init = &(struct clk_init_data){
944 .name = "gcc_ce1_axi_clk",
945 .ops = &clk_branch2_ops,
950 static struct clk_branch gcc_ce1_clk = {
952 .halt_check = BRANCH_HALT_VOTED,
954 .enable_reg = 0x52000,
955 .enable_mask = BIT(5),
956 .hw.init = &(struct clk_init_data){
957 .name = "gcc_ce1_clk",
958 .ops = &clk_branch2_ops,
963 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
965 .halt_check = BRANCH_HALT,
967 .enable_reg = 0x502c,
968 .enable_mask = BIT(0),
969 .hw.init = &(struct clk_init_data){
970 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
971 .parent_data = &(const struct clk_parent_data){
972 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
975 .flags = CLK_SET_RATE_PARENT,
976 .ops = &clk_branch2_ops,
981 /* For CPUSS functionality the AHB clock needs to be left enabled */
982 static struct clk_branch gcc_cpuss_ahb_clk = {
984 .halt_check = BRANCH_HALT_VOTED,
986 .enable_reg = 0x52000,
987 .enable_mask = BIT(21),
988 .hw.init = &(struct clk_init_data){
989 .name = "gcc_cpuss_ahb_clk",
990 .parent_data = &(const struct clk_parent_data){
991 .hw = &gcc_cpuss_ahb_clk_src.clkr.hw,
994 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
995 .ops = &clk_branch2_ops,
1000 static struct clk_branch gcc_cpuss_rbcpr_clk = {
1001 .halt_reg = 0x48008,
1002 .halt_check = BRANCH_HALT,
1004 .enable_reg = 0x48008,
1005 .enable_mask = BIT(0),
1006 .hw.init = &(struct clk_init_data){
1007 .name = "gcc_cpuss_rbcpr_clk",
1008 .ops = &clk_branch2_ops,
1013 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1014 .halt_reg = 0x4452c,
1015 .halt_check = BRANCH_VOTED,
1017 .enable_reg = 0x4452c,
1018 .enable_mask = BIT(0),
1019 .hw.init = &(struct clk_init_data){
1020 .name = "gcc_ddrss_gpu_axi_clk",
1021 .ops = &clk_branch2_ops,
1026 static struct clk_branch gcc_disp_gpll0_clk_src = {
1027 .halt_check = BRANCH_HALT_DELAY,
1029 .enable_reg = 0x52000,
1030 .enable_mask = BIT(18),
1031 .hw.init = &(struct clk_init_data){
1032 .name = "gcc_disp_gpll0_clk_src",
1033 .parent_data = &(const struct clk_parent_data){
1034 .hw = &gpll0.clkr.hw,
1037 .ops = &clk_branch2_aon_ops,
1042 static struct clk_branch gcc_disp_gpll0_div_clk_src = {
1043 .halt_check = BRANCH_HALT_DELAY,
1045 .enable_reg = 0x52000,
1046 .enable_mask = BIT(19),
1047 .hw.init = &(struct clk_init_data){
1048 .name = "gcc_disp_gpll0_div_clk_src",
1049 .parent_data = &(const struct clk_parent_data){
1050 .hw = &gcc_pll0_main_div_cdiv.hw,
1053 .ops = &clk_branch2_ops,
1058 static struct clk_branch gcc_disp_hf_axi_clk = {
1060 .halt_check = BRANCH_HALT,
1062 .enable_reg = 0xb024,
1063 .enable_mask = BIT(0),
1064 .hw.init = &(struct clk_init_data){
1065 .name = "gcc_disp_hf_axi_clk",
1066 .ops = &clk_branch2_ops,
1071 static struct clk_branch gcc_disp_throttle_hf_axi_clk = {
1073 .halt_check = BRANCH_HALT,
1077 .enable_reg = 0xb084,
1078 .enable_mask = BIT(0),
1079 .hw.init = &(struct clk_init_data){
1080 .name = "gcc_disp_throttle_hf_axi_clk",
1081 .ops = &clk_branch2_ops,
1086 static struct clk_branch gcc_gp1_clk = {
1087 .halt_reg = 0x64000,
1088 .halt_check = BRANCH_HALT,
1090 .enable_reg = 0x64000,
1091 .enable_mask = BIT(0),
1092 .hw.init = &(struct clk_init_data){
1093 .name = "gcc_gp1_clk",
1094 .parent_data = &(const struct clk_parent_data){
1095 .hw = &gcc_gp1_clk_src.clkr.hw,
1098 .flags = CLK_SET_RATE_PARENT,
1099 .ops = &clk_branch2_ops,
1104 static struct clk_branch gcc_gp2_clk = {
1105 .halt_reg = 0x65000,
1106 .halt_check = BRANCH_HALT,
1108 .enable_reg = 0x65000,
1109 .enable_mask = BIT(0),
1110 .hw.init = &(struct clk_init_data){
1111 .name = "gcc_gp2_clk",
1112 .parent_data = &(const struct clk_parent_data){
1113 .hw = &gcc_gp2_clk_src.clkr.hw,
1116 .flags = CLK_SET_RATE_PARENT,
1117 .ops = &clk_branch2_ops,
1122 static struct clk_branch gcc_gp3_clk = {
1123 .halt_reg = 0x66000,
1124 .halt_check = BRANCH_HALT,
1126 .enable_reg = 0x66000,
1127 .enable_mask = BIT(0),
1128 .hw.init = &(struct clk_init_data){
1129 .name = "gcc_gp3_clk",
1130 .parent_data = &(const struct clk_parent_data){
1131 .hw = &gcc_gp3_clk_src.clkr.hw,
1134 .flags = CLK_SET_RATE_PARENT,
1135 .ops = &clk_branch2_ops,
1140 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1141 .halt_check = BRANCH_HALT_DELAY,
1143 .enable_reg = 0x52000,
1144 .enable_mask = BIT(15),
1145 .hw.init = &(struct clk_init_data){
1146 .name = "gcc_gpu_gpll0_clk_src",
1147 .parent_data = &(const struct clk_parent_data){
1148 .hw = &gpll0.clkr.hw,
1151 .ops = &clk_branch2_ops,
1156 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1157 .halt_check = BRANCH_HALT_DELAY,
1159 .enable_reg = 0x52000,
1160 .enable_mask = BIT(16),
1161 .hw.init = &(struct clk_init_data){
1162 .name = "gcc_gpu_gpll0_div_clk_src",
1163 .parent_data = &(const struct clk_parent_data){
1164 .hw = &gcc_pll0_main_div_cdiv.hw,
1167 .ops = &clk_branch2_ops,
1172 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1173 .halt_reg = 0x7100c,
1174 .halt_check = BRANCH_VOTED,
1176 .enable_reg = 0x7100c,
1177 .enable_mask = BIT(0),
1178 .hw.init = &(struct clk_init_data){
1179 .name = "gcc_gpu_memnoc_gfx_clk",
1180 .ops = &clk_branch2_ops,
1185 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1186 .halt_reg = 0x71018,
1187 .halt_check = BRANCH_HALT,
1189 .enable_reg = 0x71018,
1190 .enable_mask = BIT(0),
1191 .hw.init = &(struct clk_init_data){
1192 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1193 .ops = &clk_branch2_ops,
1198 static struct clk_branch gcc_npu_axi_clk = {
1199 .halt_reg = 0x4d008,
1200 .halt_check = BRANCH_HALT,
1202 .enable_reg = 0x4d008,
1203 .enable_mask = BIT(0),
1204 .hw.init = &(struct clk_init_data){
1205 .name = "gcc_npu_axi_clk",
1206 .ops = &clk_branch2_ops,
1211 static struct clk_branch gcc_npu_bwmon_axi_clk = {
1212 .halt_reg = 0x73008,
1213 .halt_check = BRANCH_HALT,
1215 .enable_reg = 0x73008,
1216 .enable_mask = BIT(0),
1217 .hw.init = &(struct clk_init_data){
1218 .name = "gcc_npu_bwmon_axi_clk",
1219 .ops = &clk_branch2_ops,
1224 static struct clk_branch gcc_npu_bwmon_dma_cfg_ahb_clk = {
1225 .halt_reg = 0x73018,
1226 .halt_check = BRANCH_HALT,
1228 .enable_reg = 0x73018,
1229 .enable_mask = BIT(0),
1230 .hw.init = &(struct clk_init_data){
1231 .name = "gcc_npu_bwmon_dma_cfg_ahb_clk",
1232 .ops = &clk_branch2_ops,
1237 static struct clk_branch gcc_npu_bwmon_dsp_cfg_ahb_clk = {
1238 .halt_reg = 0x7301c,
1239 .halt_check = BRANCH_HALT,
1241 .enable_reg = 0x7301c,
1242 .enable_mask = BIT(0),
1243 .hw.init = &(struct clk_init_data){
1244 .name = "gcc_npu_bwmon_dsp_cfg_ahb_clk",
1245 .ops = &clk_branch2_ops,
1250 static struct clk_branch gcc_npu_cfg_ahb_clk = {
1251 .halt_reg = 0x4d004,
1252 .halt_check = BRANCH_HALT,
1253 .hwcg_reg = 0x4d004,
1256 .enable_reg = 0x4d004,
1257 .enable_mask = BIT(0),
1258 .hw.init = &(struct clk_init_data){
1259 .name = "gcc_npu_cfg_ahb_clk",
1260 .ops = &clk_branch2_ops,
1265 static struct clk_branch gcc_npu_dma_clk = {
1266 .halt_reg = 0x4d1a0,
1267 .halt_check = BRANCH_HALT,
1268 .hwcg_reg = 0x4d1a0,
1271 .enable_reg = 0x4d1a0,
1272 .enable_mask = BIT(0),
1273 .hw.init = &(struct clk_init_data){
1274 .name = "gcc_npu_dma_clk",
1275 .ops = &clk_branch2_ops,
1280 static struct clk_branch gcc_npu_gpll0_clk_src = {
1281 .halt_check = BRANCH_HALT_DELAY,
1283 .enable_reg = 0x52000,
1284 .enable_mask = BIT(25),
1285 .hw.init = &(struct clk_init_data){
1286 .name = "gcc_npu_gpll0_clk_src",
1287 .parent_data = &(const struct clk_parent_data){
1288 .hw = &gpll0.clkr.hw,
1291 .ops = &clk_branch2_ops,
1296 static struct clk_branch gcc_npu_gpll0_div_clk_src = {
1297 .halt_check = BRANCH_HALT_DELAY,
1299 .enable_reg = 0x52000,
1300 .enable_mask = BIT(26),
1301 .hw.init = &(struct clk_init_data){
1302 .name = "gcc_npu_gpll0_div_clk_src",
1303 .parent_data = &(const struct clk_parent_data){
1304 .hw = &gcc_pll0_main_div_cdiv.hw,
1307 .flags = CLK_SET_RATE_PARENT,
1308 .ops = &clk_branch2_ops,
1313 static struct clk_branch gcc_pdm2_clk = {
1314 .halt_reg = 0x3300c,
1315 .halt_check = BRANCH_HALT,
1317 .enable_reg = 0x3300c,
1318 .enable_mask = BIT(0),
1319 .hw.init = &(struct clk_init_data){
1320 .name = "gcc_pdm2_clk",
1321 .parent_data = &(const struct clk_parent_data){
1322 .hw = &gcc_pdm2_clk_src.clkr.hw,
1325 .flags = CLK_SET_RATE_PARENT,
1326 .ops = &clk_branch2_ops,
1331 static struct clk_branch gcc_pdm_ahb_clk = {
1332 .halt_reg = 0x33004,
1333 .halt_check = BRANCH_HALT,
1334 .hwcg_reg = 0x33004,
1337 .enable_reg = 0x33004,
1338 .enable_mask = BIT(0),
1339 .hw.init = &(struct clk_init_data){
1340 .name = "gcc_pdm_ahb_clk",
1341 .ops = &clk_branch2_ops,
1346 static struct clk_branch gcc_pdm_xo4_clk = {
1347 .halt_reg = 0x33008,
1348 .halt_check = BRANCH_HALT,
1350 .enable_reg = 0x33008,
1351 .enable_mask = BIT(0),
1352 .hw.init = &(struct clk_init_data){
1353 .name = "gcc_pdm_xo4_clk",
1354 .ops = &clk_branch2_ops,
1359 static struct clk_branch gcc_prng_ahb_clk = {
1360 .halt_reg = 0x34004,
1361 .halt_check = BRANCH_HALT_VOTED,
1362 .hwcg_reg = 0x34004,
1365 .enable_reg = 0x52000,
1366 .enable_mask = BIT(13),
1367 .hw.init = &(struct clk_init_data){
1368 .name = "gcc_prng_ahb_clk",
1369 .ops = &clk_branch2_ops,
1374 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
1375 .halt_reg = 0x4b004,
1376 .halt_check = BRANCH_HALT,
1377 .hwcg_reg = 0x4b004,
1380 .enable_reg = 0x4b004,
1381 .enable_mask = BIT(0),
1382 .hw.init = &(struct clk_init_data){
1383 .name = "gcc_qspi_cnoc_periph_ahb_clk",
1384 .ops = &clk_branch2_ops,
1389 static struct clk_branch gcc_qspi_core_clk = {
1390 .halt_reg = 0x4b008,
1391 .halt_check = BRANCH_HALT,
1393 .enable_reg = 0x4b008,
1394 .enable_mask = BIT(0),
1395 .hw.init = &(struct clk_init_data){
1396 .name = "gcc_qspi_core_clk",
1397 .parent_data = &(const struct clk_parent_data){
1398 .hw = &gcc_qspi_core_clk_src.clkr.hw,
1401 .flags = CLK_SET_RATE_PARENT,
1402 .ops = &clk_branch2_ops,
1407 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
1408 .halt_reg = 0x17014,
1409 .halt_check = BRANCH_HALT_VOTED,
1411 .enable_reg = 0x52008,
1412 .enable_mask = BIT(9),
1413 .hw.init = &(struct clk_init_data){
1414 .name = "gcc_qupv3_wrap0_core_2x_clk",
1415 .ops = &clk_branch2_ops,
1420 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
1421 .halt_reg = 0x1700c,
1422 .halt_check = BRANCH_HALT_VOTED,
1424 .enable_reg = 0x52008,
1425 .enable_mask = BIT(8),
1426 .hw.init = &(struct clk_init_data){
1427 .name = "gcc_qupv3_wrap0_core_clk",
1428 .ops = &clk_branch2_ops,
1433 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
1434 .halt_reg = 0x17030,
1435 .halt_check = BRANCH_HALT_VOTED,
1437 .enable_reg = 0x52008,
1438 .enable_mask = BIT(10),
1439 .hw.init = &(struct clk_init_data){
1440 .name = "gcc_qupv3_wrap0_s0_clk",
1441 .parent_data = &(const struct clk_parent_data){
1442 .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
1445 .flags = CLK_SET_RATE_PARENT,
1446 .ops = &clk_branch2_ops,
1451 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
1452 .halt_reg = 0x17160,
1453 .halt_check = BRANCH_HALT_VOTED,
1455 .enable_reg = 0x52008,
1456 .enable_mask = BIT(11),
1457 .hw.init = &(struct clk_init_data){
1458 .name = "gcc_qupv3_wrap0_s1_clk",
1459 .parent_data = &(const struct clk_parent_data){
1460 .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
1463 .flags = CLK_SET_RATE_PARENT,
1464 .ops = &clk_branch2_ops,
1469 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
1470 .halt_reg = 0x17290,
1471 .halt_check = BRANCH_HALT_VOTED,
1473 .enable_reg = 0x52008,
1474 .enable_mask = BIT(12),
1475 .hw.init = &(struct clk_init_data){
1476 .name = "gcc_qupv3_wrap0_s2_clk",
1477 .parent_data = &(const struct clk_parent_data){
1478 .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
1481 .flags = CLK_SET_RATE_PARENT,
1482 .ops = &clk_branch2_ops,
1487 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
1488 .halt_reg = 0x173c0,
1489 .halt_check = BRANCH_HALT_VOTED,
1491 .enable_reg = 0x52008,
1492 .enable_mask = BIT(13),
1493 .hw.init = &(struct clk_init_data){
1494 .name = "gcc_qupv3_wrap0_s3_clk",
1495 .parent_data = &(const struct clk_parent_data){
1496 .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
1499 .flags = CLK_SET_RATE_PARENT,
1500 .ops = &clk_branch2_ops,
1505 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
1506 .halt_reg = 0x174f0,
1507 .halt_check = BRANCH_HALT_VOTED,
1509 .enable_reg = 0x52008,
1510 .enable_mask = BIT(14),
1511 .hw.init = &(struct clk_init_data){
1512 .name = "gcc_qupv3_wrap0_s4_clk",
1513 .parent_data = &(const struct clk_parent_data){
1514 .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
1517 .flags = CLK_SET_RATE_PARENT,
1518 .ops = &clk_branch2_ops,
1523 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
1524 .halt_reg = 0x17620,
1525 .halt_check = BRANCH_HALT_VOTED,
1527 .enable_reg = 0x52008,
1528 .enable_mask = BIT(15),
1529 .hw.init = &(struct clk_init_data){
1530 .name = "gcc_qupv3_wrap0_s5_clk",
1531 .parent_data = &(const struct clk_parent_data){
1532 .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
1535 .flags = CLK_SET_RATE_PARENT,
1536 .ops = &clk_branch2_ops,
1541 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
1542 .halt_reg = 0x18004,
1543 .halt_check = BRANCH_HALT_VOTED,
1545 .enable_reg = 0x52008,
1546 .enable_mask = BIT(18),
1547 .hw.init = &(struct clk_init_data){
1548 .name = "gcc_qupv3_wrap1_core_2x_clk",
1549 .ops = &clk_branch2_ops,
1554 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
1555 .halt_reg = 0x18008,
1556 .halt_check = BRANCH_HALT_VOTED,
1558 .enable_reg = 0x52008,
1559 .enable_mask = BIT(19),
1560 .hw.init = &(struct clk_init_data){
1561 .name = "gcc_qupv3_wrap1_core_clk",
1562 .ops = &clk_branch2_ops,
1567 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
1568 .halt_reg = 0x18014,
1569 .halt_check = BRANCH_HALT_VOTED,
1571 .enable_reg = 0x52008,
1572 .enable_mask = BIT(22),
1573 .hw.init = &(struct clk_init_data){
1574 .name = "gcc_qupv3_wrap1_s0_clk",
1575 .parent_data = &(const struct clk_parent_data){
1576 .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
1579 .flags = CLK_SET_RATE_PARENT,
1580 .ops = &clk_branch2_ops,
1585 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
1586 .halt_reg = 0x18144,
1587 .halt_check = BRANCH_HALT_VOTED,
1589 .enable_reg = 0x52008,
1590 .enable_mask = BIT(23),
1591 .hw.init = &(struct clk_init_data){
1592 .name = "gcc_qupv3_wrap1_s1_clk",
1593 .parent_data = &(const struct clk_parent_data){
1594 .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
1597 .flags = CLK_SET_RATE_PARENT,
1598 .ops = &clk_branch2_ops,
1603 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
1604 .halt_reg = 0x18274,
1605 .halt_check = BRANCH_HALT_VOTED,
1607 .enable_reg = 0x52008,
1608 .enable_mask = BIT(24),
1609 .hw.init = &(struct clk_init_data){
1610 .name = "gcc_qupv3_wrap1_s2_clk",
1611 .parent_data = &(const struct clk_parent_data){
1612 .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
1615 .flags = CLK_SET_RATE_PARENT,
1616 .ops = &clk_branch2_ops,
1621 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
1622 .halt_reg = 0x183a4,
1623 .halt_check = BRANCH_HALT_VOTED,
1625 .enable_reg = 0x52008,
1626 .enable_mask = BIT(25),
1627 .hw.init = &(struct clk_init_data){
1628 .name = "gcc_qupv3_wrap1_s3_clk",
1629 .parent_data = &(const struct clk_parent_data){
1630 .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
1633 .flags = CLK_SET_RATE_PARENT,
1634 .ops = &clk_branch2_ops,
1639 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
1640 .halt_reg = 0x184d4,
1641 .halt_check = BRANCH_HALT_VOTED,
1643 .enable_reg = 0x52008,
1644 .enable_mask = BIT(26),
1645 .hw.init = &(struct clk_init_data){
1646 .name = "gcc_qupv3_wrap1_s4_clk",
1647 .parent_data = &(const struct clk_parent_data){
1648 .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
1651 .flags = CLK_SET_RATE_PARENT,
1652 .ops = &clk_branch2_ops,
1657 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
1658 .halt_reg = 0x18604,
1659 .halt_check = BRANCH_HALT_VOTED,
1661 .enable_reg = 0x52008,
1662 .enable_mask = BIT(27),
1663 .hw.init = &(struct clk_init_data){
1664 .name = "gcc_qupv3_wrap1_s5_clk",
1665 .parent_data = &(const struct clk_parent_data){
1666 .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
1669 .flags = CLK_SET_RATE_PARENT,
1670 .ops = &clk_branch2_ops,
1675 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
1676 .halt_reg = 0x17004,
1677 .halt_check = BRANCH_HALT_VOTED,
1679 .enable_reg = 0x52008,
1680 .enable_mask = BIT(6),
1681 .hw.init = &(struct clk_init_data){
1682 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
1683 .ops = &clk_branch2_ops,
1688 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
1689 .halt_reg = 0x17008,
1690 .halt_check = BRANCH_HALT_VOTED,
1691 .hwcg_reg = 0x17008,
1694 .enable_reg = 0x52008,
1695 .enable_mask = BIT(7),
1696 .hw.init = &(struct clk_init_data){
1697 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
1698 .ops = &clk_branch2_ops,
1703 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
1704 .halt_reg = 0x1800c,
1705 .halt_check = BRANCH_HALT_VOTED,
1707 .enable_reg = 0x52008,
1708 .enable_mask = BIT(20),
1709 .hw.init = &(struct clk_init_data){
1710 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
1711 .ops = &clk_branch2_ops,
1716 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
1717 .halt_reg = 0x18010,
1718 .halt_check = BRANCH_HALT_VOTED,
1719 .hwcg_reg = 0x18010,
1722 .enable_reg = 0x52008,
1723 .enable_mask = BIT(21),
1724 .hw.init = &(struct clk_init_data){
1725 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
1726 .ops = &clk_branch2_ops,
1731 static struct clk_branch gcc_sdcc1_ahb_clk = {
1732 .halt_reg = 0x12008,
1733 .halt_check = BRANCH_HALT,
1735 .enable_reg = 0x12008,
1736 .enable_mask = BIT(0),
1737 .hw.init = &(struct clk_init_data){
1738 .name = "gcc_sdcc1_ahb_clk",
1739 .ops = &clk_branch2_ops,
1744 static struct clk_branch gcc_sdcc1_apps_clk = {
1745 .halt_reg = 0x1200c,
1746 .halt_check = BRANCH_HALT,
1748 .enable_reg = 0x1200c,
1749 .enable_mask = BIT(0),
1750 .hw.init = &(struct clk_init_data){
1751 .name = "gcc_sdcc1_apps_clk",
1752 .parent_data = &(const struct clk_parent_data){
1753 .hw = &gcc_sdcc1_apps_clk_src.clkr.hw,
1756 .flags = CLK_SET_RATE_PARENT,
1757 .ops = &clk_branch2_ops,
1762 static struct clk_branch gcc_sdcc1_ice_core_clk = {
1763 .halt_reg = 0x12040,
1764 .halt_check = BRANCH_HALT,
1766 .enable_reg = 0x12040,
1767 .enable_mask = BIT(0),
1768 .hw.init = &(struct clk_init_data){
1769 .name = "gcc_sdcc1_ice_core_clk",
1770 .parent_data = &(const struct clk_parent_data){
1771 .hw = &gcc_sdcc1_ice_core_clk_src.clkr.hw,
1774 .flags = CLK_SET_RATE_PARENT,
1775 .ops = &clk_branch2_ops,
1780 static struct clk_branch gcc_sdcc2_ahb_clk = {
1781 .halt_reg = 0x14008,
1782 .halt_check = BRANCH_HALT,
1784 .enable_reg = 0x14008,
1785 .enable_mask = BIT(0),
1786 .hw.init = &(struct clk_init_data){
1787 .name = "gcc_sdcc2_ahb_clk",
1788 .ops = &clk_branch2_ops,
1793 static struct clk_branch gcc_sdcc2_apps_clk = {
1794 .halt_reg = 0x14004,
1795 .halt_check = BRANCH_HALT,
1797 .enable_reg = 0x14004,
1798 .enable_mask = BIT(0),
1799 .hw.init = &(struct clk_init_data){
1800 .name = "gcc_sdcc2_apps_clk",
1801 .parent_data = &(const struct clk_parent_data){
1802 .hw = &gcc_sdcc2_apps_clk_src.clkr.hw,
1805 .flags = CLK_SET_RATE_PARENT,
1806 .ops = &clk_branch2_ops,
1811 /* For CPUSS functionality the SYS NOC clock needs to be left enabled */
1812 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
1814 .halt_check = BRANCH_HALT_VOTED,
1816 .enable_reg = 0x52000,
1817 .enable_mask = BIT(0),
1818 .hw.init = &(struct clk_init_data){
1819 .name = "gcc_sys_noc_cpuss_ahb_clk",
1820 .parent_data = &(const struct clk_parent_data){
1821 .hw = &gcc_cpuss_ahb_clk_src.clkr.hw,
1824 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1825 .ops = &clk_branch2_ops,
1830 static struct clk_branch gcc_ufs_mem_clkref_clk = {
1831 .halt_reg = 0x8c000,
1832 .halt_check = BRANCH_HALT,
1834 .enable_reg = 0x8c000,
1835 .enable_mask = BIT(0),
1836 .hw.init = &(struct clk_init_data){
1837 .name = "gcc_ufs_mem_clkref_clk",
1838 .ops = &clk_branch2_ops,
1843 static struct clk_branch gcc_ufs_phy_ahb_clk = {
1844 .halt_reg = 0x77014,
1845 .halt_check = BRANCH_HALT,
1846 .hwcg_reg = 0x77014,
1849 .enable_reg = 0x77014,
1850 .enable_mask = BIT(0),
1851 .hw.init = &(struct clk_init_data){
1852 .name = "gcc_ufs_phy_ahb_clk",
1853 .ops = &clk_branch2_ops,
1858 static struct clk_branch gcc_ufs_phy_axi_clk = {
1859 .halt_reg = 0x77038,
1860 .halt_check = BRANCH_HALT,
1861 .hwcg_reg = 0x77038,
1864 .enable_reg = 0x77038,
1865 .enable_mask = BIT(0),
1866 .hw.init = &(struct clk_init_data){
1867 .name = "gcc_ufs_phy_axi_clk",
1868 .parent_data = &(const struct clk_parent_data){
1869 .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
1872 .flags = CLK_SET_RATE_PARENT,
1873 .ops = &clk_branch2_ops,
1878 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
1879 .halt_reg = 0x77090,
1880 .halt_check = BRANCH_HALT,
1881 .hwcg_reg = 0x77090,
1884 .enable_reg = 0x77090,
1885 .enable_mask = BIT(0),
1886 .hw.init = &(struct clk_init_data){
1887 .name = "gcc_ufs_phy_ice_core_clk",
1888 .parent_data = &(const struct clk_parent_data){
1889 .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
1892 .flags = CLK_SET_RATE_PARENT,
1893 .ops = &clk_branch2_ops,
1898 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
1899 .halt_reg = 0x77094,
1900 .halt_check = BRANCH_HALT,
1901 .hwcg_reg = 0x77094,
1904 .enable_reg = 0x77094,
1905 .enable_mask = BIT(0),
1906 .hw.init = &(struct clk_init_data){
1907 .name = "gcc_ufs_phy_phy_aux_clk",
1908 .parent_data = &(const struct clk_parent_data){
1909 .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
1912 .flags = CLK_SET_RATE_PARENT,
1913 .ops = &clk_branch2_ops,
1918 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
1919 .halt_reg = 0x7701c,
1920 .halt_check = BRANCH_HALT_SKIP,
1922 .enable_reg = 0x7701c,
1923 .enable_mask = BIT(0),
1924 .hw.init = &(struct clk_init_data){
1925 .name = "gcc_ufs_phy_rx_symbol_0_clk",
1926 .ops = &clk_branch2_ops,
1931 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
1932 .halt_reg = 0x77018,
1933 .halt_check = BRANCH_HALT_SKIP,
1935 .enable_reg = 0x77018,
1936 .enable_mask = BIT(0),
1937 .hw.init = &(struct clk_init_data){
1938 .name = "gcc_ufs_phy_tx_symbol_0_clk",
1939 .ops = &clk_branch2_ops,
1944 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
1945 .halt_reg = 0x7708c,
1946 .halt_check = BRANCH_HALT,
1947 .hwcg_reg = 0x7708c,
1950 .enable_reg = 0x7708c,
1951 .enable_mask = BIT(0),
1952 .hw.init = &(struct clk_init_data){
1953 .name = "gcc_ufs_phy_unipro_core_clk",
1954 .parent_data = &(const struct clk_parent_data){
1955 .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
1958 .flags = CLK_SET_RATE_PARENT,
1959 .ops = &clk_branch2_ops,
1964 static struct clk_branch gcc_usb30_prim_master_clk = {
1966 .halt_check = BRANCH_HALT,
1968 .enable_reg = 0xf010,
1969 .enable_mask = BIT(0),
1970 .hw.init = &(struct clk_init_data){
1971 .name = "gcc_usb30_prim_master_clk",
1972 .parent_data = &(const struct clk_parent_data){
1973 .hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
1976 .flags = CLK_SET_RATE_PARENT,
1977 .ops = &clk_branch2_ops,
1982 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
1984 .halt_check = BRANCH_HALT,
1986 .enable_reg = 0xf018,
1987 .enable_mask = BIT(0),
1988 .hw.init = &(struct clk_init_data){
1989 .name = "gcc_usb30_prim_mock_utmi_clk",
1990 .parent_data = &(const struct clk_parent_data){
1992 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1995 .flags = CLK_SET_RATE_PARENT,
1996 .ops = &clk_branch2_ops,
2001 static struct clk_branch gcc_usb30_prim_sleep_clk = {
2003 .halt_check = BRANCH_HALT,
2005 .enable_reg = 0xf014,
2006 .enable_mask = BIT(0),
2007 .hw.init = &(struct clk_init_data){
2008 .name = "gcc_usb30_prim_sleep_clk",
2009 .ops = &clk_branch2_ops,
2014 static struct clk_branch gcc_usb3_prim_clkref_clk = {
2015 .halt_reg = 0x8c010,
2016 .halt_check = BRANCH_HALT,
2018 .enable_reg = 0x8c010,
2019 .enable_mask = BIT(0),
2020 .hw.init = &(struct clk_init_data){
2021 .name = "gcc_usb3_prim_clkref_clk",
2022 .ops = &clk_branch2_ops,
2027 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2029 .halt_check = BRANCH_HALT,
2031 .enable_reg = 0xf050,
2032 .enable_mask = BIT(0),
2033 .hw.init = &(struct clk_init_data){
2034 .name = "gcc_usb3_prim_phy_aux_clk",
2035 .parent_data = &(const struct clk_parent_data){
2036 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2039 .flags = CLK_SET_RATE_PARENT,
2040 .ops = &clk_branch2_ops,
2045 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2047 .halt_check = BRANCH_HALT,
2049 .enable_reg = 0xf054,
2050 .enable_mask = BIT(0),
2051 .hw.init = &(struct clk_init_data){
2052 .name = "gcc_usb3_prim_phy_com_aux_clk",
2053 .parent_data = &(const struct clk_parent_data){
2054 .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2057 .flags = CLK_SET_RATE_PARENT,
2058 .ops = &clk_branch2_ops,
2063 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2065 .halt_check = BRANCH_HALT_SKIP,
2067 .enable_reg = 0xf058,
2068 .enable_mask = BIT(0),
2069 .hw.init = &(struct clk_init_data){
2070 .name = "gcc_usb3_prim_phy_pipe_clk",
2071 .ops = &clk_branch2_ops,
2076 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2077 .halt_reg = 0x6a004,
2078 .halt_check = BRANCH_HALT,
2079 .hwcg_reg = 0x6a004,
2082 .enable_reg = 0x6a004,
2083 .enable_mask = BIT(0),
2084 .hw.init = &(struct clk_init_data){
2085 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2086 .ops = &clk_branch2_ops,
2091 static struct clk_branch gcc_video_axi_clk = {
2093 .halt_check = BRANCH_HALT,
2095 .enable_reg = 0xb01c,
2096 .enable_mask = BIT(0),
2097 .hw.init = &(struct clk_init_data){
2098 .name = "gcc_video_axi_clk",
2099 .ops = &clk_branch2_ops,
2104 static struct clk_branch gcc_video_gpll0_div_clk_src = {
2105 .halt_check = BRANCH_HALT_DELAY,
2107 .enable_reg = 0x52000,
2108 .enable_mask = BIT(20),
2109 .hw.init = &(struct clk_init_data){
2110 .name = "gcc_video_gpll0_div_clk_src",
2111 .parent_data = &(const struct clk_parent_data){
2112 .hw = &gcc_pll0_main_div_cdiv.hw,
2115 .flags = CLK_SET_RATE_PARENT,
2116 .ops = &clk_branch2_ops,
2121 static struct clk_branch gcc_video_throttle_axi_clk = {
2123 .halt_check = BRANCH_HALT,
2127 .enable_reg = 0xb07c,
2128 .enable_mask = BIT(0),
2129 .hw.init = &(struct clk_init_data){
2130 .name = "gcc_video_throttle_axi_clk",
2131 .ops = &clk_branch2_ops,
2136 static struct clk_branch gcc_mss_cfg_ahb_clk = {
2137 .halt_reg = 0x8a000,
2138 .halt_check = BRANCH_HALT,
2140 .enable_reg = 0x8a000,
2141 .enable_mask = BIT(0),
2142 .hw.init = &(struct clk_init_data){
2143 .name = "gcc_mss_cfg_ahb_clk",
2144 .ops = &clk_branch2_ops,
2149 static struct clk_branch gcc_mss_mfab_axis_clk = {
2150 .halt_reg = 0x8a004,
2151 .halt_check = BRANCH_HALT_VOTED,
2153 .enable_reg = 0x8a004,
2154 .enable_mask = BIT(0),
2155 .hw.init = &(struct clk_init_data){
2156 .name = "gcc_mss_mfab_axis_clk",
2157 .ops = &clk_branch2_ops,
2162 static struct clk_branch gcc_mss_nav_axi_clk = {
2163 .halt_reg = 0x8a00c,
2164 .halt_check = BRANCH_HALT_VOTED,
2166 .enable_reg = 0x8a00c,
2167 .enable_mask = BIT(0),
2168 .hw.init = &(struct clk_init_data){
2169 .name = "gcc_mss_nav_axi_clk",
2170 .ops = &clk_branch2_ops,
2175 static struct clk_branch gcc_mss_snoc_axi_clk = {
2176 .halt_reg = 0x8a150,
2177 .halt_check = BRANCH_HALT,
2179 .enable_reg = 0x8a150,
2180 .enable_mask = BIT(0),
2181 .hw.init = &(struct clk_init_data){
2182 .name = "gcc_mss_snoc_axi_clk",
2183 .ops = &clk_branch2_ops,
2188 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
2189 .halt_reg = 0x8a154,
2190 .halt_check = BRANCH_HALT,
2192 .enable_reg = 0x8a154,
2193 .enable_mask = BIT(0),
2194 .hw.init = &(struct clk_init_data){
2195 .name = "gcc_mss_q6_memnoc_axi_clk",
2196 .ops = &clk_branch2_ops,
2201 static struct clk_branch gcc_lpass_cfg_noc_sway_clk = {
2202 .halt_reg = 0x47018,
2203 .halt_check = BRANCH_HALT_DELAY,
2205 .enable_reg = 0x47018,
2206 .enable_mask = BIT(0),
2207 .hw.init = &(struct clk_init_data){
2208 .name = "gcc_lpass_cfg_noc_sway_clk",
2209 .ops = &clk_branch2_ops,
2214 static struct gdsc ufs_phy_gdsc = {
2217 .name = "ufs_phy_gdsc",
2219 .pwrsts = PWRSTS_OFF_ON,
2222 static struct gdsc usb30_prim_gdsc = {
2225 .name = "usb30_prim_gdsc",
2227 .pwrsts = PWRSTS_OFF_ON,
2230 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
2233 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
2235 .pwrsts = PWRSTS_OFF_ON,
2239 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
2242 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
2244 .pwrsts = PWRSTS_OFF_ON,
2248 static struct gdsc *gcc_sc7180_gdscs[] = {
2249 [UFS_PHY_GDSC] = &ufs_phy_gdsc,
2250 [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
2251 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
2252 &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
2253 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] =
2254 &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
2258 static struct clk_hw *gcc_sc7180_hws[] = {
2259 [GCC_GPLL0_MAIN_DIV_CDIV] = &gcc_pll0_main_div_cdiv.hw,
2262 static struct clk_regmap *gcc_sc7180_clocks[] = {
2263 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
2264 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
2265 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2266 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
2267 [GCC_CAMERA_THROTTLE_HF_AXI_CLK] = &gcc_camera_throttle_hf_axi_clk.clkr,
2268 [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
2269 [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
2270 [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
2271 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
2272 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
2273 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
2274 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
2275 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
2276 [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
2277 [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
2278 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
2279 [GCC_DISP_THROTTLE_HF_AXI_CLK] = &gcc_disp_throttle_hf_axi_clk.clkr,
2280 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2281 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
2282 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2283 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
2284 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2285 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
2286 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
2287 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
2288 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
2289 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2290 [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
2291 [GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr,
2292 [GCC_NPU_BWMON_DMA_CFG_AHB_CLK] = &gcc_npu_bwmon_dma_cfg_ahb_clk.clkr,
2293 [GCC_NPU_BWMON_DSP_CFG_AHB_CLK] = &gcc_npu_bwmon_dsp_cfg_ahb_clk.clkr,
2294 [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
2295 [GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr,
2296 [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
2297 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
2298 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2299 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
2300 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2301 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2302 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2303 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
2304 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
2305 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
2306 [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
2307 [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
2308 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
2309 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
2310 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
2311 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
2312 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
2313 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
2314 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
2315 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
2316 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
2317 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
2318 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
2319 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
2320 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
2321 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
2322 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
2323 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
2324 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
2325 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
2326 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
2327 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
2328 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
2329 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
2330 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
2331 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
2332 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
2333 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
2334 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
2335 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
2336 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
2337 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
2338 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2339 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2340 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
2341 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2342 [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
2343 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2344 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2345 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
2346 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
2347 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
2348 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
2349 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
2350 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
2351 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
2352 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
2353 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
2354 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
2355 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
2356 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
2357 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
2358 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
2359 &gcc_ufs_phy_unipro_core_clk_src.clkr,
2360 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
2361 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
2362 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
2363 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
2364 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
2365 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
2366 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
2367 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
2368 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
2369 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
2370 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
2371 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2372 [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
2373 [GCC_VIDEO_GPLL0_DIV_CLK_SRC] = &gcc_video_gpll0_div_clk_src.clkr,
2374 [GCC_VIDEO_THROTTLE_AXI_CLK] = &gcc_video_throttle_axi_clk.clkr,
2375 [GPLL0] = &gpll0.clkr,
2376 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
2377 [GPLL6] = &gpll6.clkr,
2378 [GPLL7] = &gpll7.clkr,
2379 [GPLL4] = &gpll4.clkr,
2380 [GPLL1] = &gpll1.clkr,
2381 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2382 [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
2383 [GCC_MSS_NAV_AXI_CLK] = &gcc_mss_nav_axi_clk.clkr,
2384 [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
2385 [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
2386 [GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr,
2387 [GCC_LPASS_CFG_NOC_SWAY_CLK] = &gcc_lpass_cfg_noc_sway_clk.clkr,
2390 static const struct qcom_reset_map gcc_sc7180_resets[] = {
2391 [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 },
2392 [GCC_QUSB2PHY_SEC_BCR] = { 0x26004 },
2393 [GCC_UFS_PHY_BCR] = { 0x77000 },
2394 [GCC_USB30_PRIM_BCR] = { 0xf000 },
2395 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
2396 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
2397 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
2398 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
2399 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
2400 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
2401 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
2404 static struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
2405 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
2406 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
2407 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
2408 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
2409 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
2410 DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
2411 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
2412 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
2413 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
2414 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
2415 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
2416 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
2419 static const struct regmap_config gcc_sc7180_regmap_config = {
2423 .max_register = 0x18208c,
2427 static const struct qcom_cc_desc gcc_sc7180_desc = {
2428 .config = &gcc_sc7180_regmap_config,
2429 .clk_hws = gcc_sc7180_hws,
2430 .num_clk_hws = ARRAY_SIZE(gcc_sc7180_hws),
2431 .clks = gcc_sc7180_clocks,
2432 .num_clks = ARRAY_SIZE(gcc_sc7180_clocks),
2433 .resets = gcc_sc7180_resets,
2434 .num_resets = ARRAY_SIZE(gcc_sc7180_resets),
2435 .gdscs = gcc_sc7180_gdscs,
2436 .num_gdscs = ARRAY_SIZE(gcc_sc7180_gdscs),
2439 static const struct of_device_id gcc_sc7180_match_table[] = {
2440 { .compatible = "qcom,gcc-sc7180" },
2443 MODULE_DEVICE_TABLE(of, gcc_sc7180_match_table);
2445 static int gcc_sc7180_probe(struct platform_device *pdev)
2447 struct regmap *regmap;
2450 regmap = qcom_cc_map(pdev, &gcc_sc7180_desc);
2452 return PTR_ERR(regmap);
2455 * Disable the GPLL0 active input to MM blocks, NPU
2456 * and GPU via MISC registers.
2458 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
2459 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
2460 regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
2463 * Keep the clocks always-ON
2464 * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK,
2465 * GCC_DISP_AHB_CLK, GCC_GPU_CFG_AHB_CLK
2467 regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0));
2468 regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0));
2469 regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0));
2470 regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0));
2471 regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0));
2472 regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0));
2473 regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0));
2474 regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
2476 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
2477 ARRAY_SIZE(gcc_dfs_clocks));
2481 return qcom_cc_really_probe(pdev, &gcc_sc7180_desc, regmap);
2484 static struct platform_driver gcc_sc7180_driver = {
2485 .probe = gcc_sc7180_probe,
2487 .name = "gcc-sc7180",
2488 .of_match_table = gcc_sc7180_match_table,
2492 static int __init gcc_sc7180_init(void)
2494 return platform_driver_register(&gcc_sc7180_driver);
2496 core_initcall(gcc_sc7180_init);
2498 static void __exit gcc_sc7180_exit(void)
2500 platform_driver_unregister(&gcc_sc7180_driver);
2502 module_exit(gcc_sc7180_exit);
2504 MODULE_DESCRIPTION("QTI GCC SC7180 Driver");
2505 MODULE_LICENSE("GPL v2");