drivers/clk/qcom/gcc-sc7180.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk-provider.h>
   7 #include <linux/err.h>
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/of_device.h>
  12 #include <linux/regmap.h>
  13
  14 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
  15
  16 #include "clk-alpha-pll.h"
  17 #include "clk-branch.h"
  18 #include "clk-rcg.h"
  19 #include "clk-regmap.h"
  20 #include "common.h"
  21 #include "gdsc.h"
  22 #include "reset.h"
  23
  24 enum {
  25         P_BI_TCXO,
  26         P_CORE_BI_PLL_TEST_SE,
  27         P_GPLL0_OUT_EVEN,
  28         P_GPLL0_OUT_MAIN,
  29         P_GPLL1_OUT_MAIN,
  30         P_GPLL4_OUT_MAIN,
  31         P_GPLL6_OUT_MAIN,
  32         P_GPLL7_OUT_MAIN,
  33         P_SLEEP_CLK,
  34 };
  35
  36 static struct clk_alpha_pll gpll0 = {
  37         .offset = 0x0,
  38         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  39         .clkr = {
  40                 .enable_reg = 0x52010,
  41                 .enable_mask = BIT(0),
  42                 .hw.init = &(struct clk_init_data){
  43                         .name = "gpll0",
  44                         .parent_data = &(const struct clk_parent_data){
  45                                 .fw_name = "bi_tcxo",
  46                                 .name = "bi_tcxo",
  47                         },
  48                         .num_parents = 1,
  49                         .ops = &clk_alpha_pll_fixed_fabia_ops,
  50                 },
  51         },
  52 };
  53
  54 static const struct clk_div_table post_div_table_gpll0_out_even[] = {
  55         { 0x1, 2 },
  56         { }
  57 };
  58
  59 static struct clk_alpha_pll_postdiv gpll0_out_even = {
  60         .offset = 0x0,
  61         .post_div_shift = 8,
  62         .post_div_table = post_div_table_gpll0_out_even,
  63         .num_post_div = ARRAY_SIZE(post_div_table_gpll0_out_even),
  64         .width = 4,
  65         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  66         .clkr.hw.init = &(struct clk_init_data){
  67                 .name = "gpll0_out_even",
  68                 .parent_hws = (const struct clk_hw*[]){
  69                         &gpll0.clkr.hw,
  70                 },
  71                 .num_parents = 1,
  72                 .ops = &clk_alpha_pll_postdiv_fabia_ops,
  73         },
  74 };
  75
  76 static struct clk_fixed_factor gcc_pll0_main_div_cdiv = {
  77         .mult = 1,
  78         .div = 2,
  79         .hw.init = &(struct clk_init_data){
  80                 .name = "gcc_pll0_main_div_cdiv",
  81                 .parent_hws = (const struct clk_hw*[]){
  82                         &gpll0.clkr.hw,
  83                 },
  84                 .num_parents = 1,
  85                 .ops = &clk_fixed_factor_ops,
  86         },
  87 };
  88
  89 static struct clk_alpha_pll gpll1 = {
  90         .offset = 0x01000,
  91         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
  92         .clkr = {
  93                 .enable_reg = 0x52010,
  94                 .enable_mask = BIT(1),
  95                 .hw.init = &(struct clk_init_data){
  96                         .name = "gpll1",
  97                         .parent_data = &(const struct clk_parent_data){
  98                                 .fw_name = "bi_tcxo",
  99                                 .name = "bi_tcxo",
 100                         },
 101                         .num_parents = 1,
 102                         .ops = &clk_alpha_pll_fixed_fabia_ops,
 103                 },
 104         },
 105 };
 106
 107 static struct clk_alpha_pll gpll4 = {
 108         .offset = 0x76000,
 109         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 110         .clkr = {
 111                 .enable_reg = 0x52010,
 112                 .enable_mask = BIT(4),
 113                 .hw.init = &(struct clk_init_data){
 114                         .name = "gpll4",
 115                         .parent_data = &(const struct clk_parent_data){
 116                                 .fw_name = "bi_tcxo",
 117                                 .name = "bi_tcxo",
 118                         },
 119                         .num_parents = 1,
 120                         .ops = &clk_alpha_pll_fixed_fabia_ops,
 121                 },
 122         },
 123 };
 124
 125 static struct clk_alpha_pll gpll6 = {
 126         .offset = 0x13000,
 127         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 128         .clkr = {
 129                 .enable_reg = 0x52010,
 130                 .enable_mask = BIT(6),
 131                 .hw.init = &(struct clk_init_data){
 132                         .name = "gpll6",
 133                         .parent_data = &(const struct clk_parent_data){
 134                                 .fw_name = "bi_tcxo",
 135                                 .name = "bi_tcxo",
 136                         },
 137                         .num_parents = 1,
 138                         .ops = &clk_alpha_pll_fixed_fabia_ops,
 139                 },
 140         },
 141 };
 142
 143 static struct clk_alpha_pll gpll7 = {
 144         .offset = 0x27000,
 145         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 146         .clkr = {
 147                 .enable_reg = 0x52010,
 148                 .enable_mask = BIT(7),
 149                 .hw.init = &(struct clk_init_data){
 150                         .name = "gpll7",
 151                         .parent_data = &(const struct clk_parent_data){
 152                                 .fw_name = "bi_tcxo",
 153                                 .name = "bi_tcxo",
 154                         },
 155                         .num_parents = 1,
 156                         .ops = &clk_alpha_pll_fixed_fabia_ops,
 157                 },
 158         },
 159 };
 160
 161 static const struct parent_map gcc_parent_map_0[] = {
 162         { P_BI_TCXO, 0 },
 163         { P_GPLL0_OUT_MAIN, 1 },
 164         { P_GPLL0_OUT_EVEN, 6 },
 165         { P_CORE_BI_PLL_TEST_SE, 7 },
 166 };
 167
 168 static const struct clk_parent_data gcc_parent_data_0[] = {
 169         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 170         { .hw = &gpll0.clkr.hw },
 171         { .hw = &gpll0_out_even.clkr.hw },
 172         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 173 };
 174
 175 static const struct clk_parent_data gcc_parent_data_0_ao[] = {
 176         { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" },
 177         { .hw = &gpll0.clkr.hw },
 178         { .hw = &gpll0_out_even.clkr.hw },
 179         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 180 };
 181
 182 static const struct parent_map gcc_parent_map_1[] = {
 183         { P_BI_TCXO, 0 },
 184         { P_GPLL0_OUT_MAIN, 1 },
 185         { P_GPLL6_OUT_MAIN, 2 },
 186         { P_GPLL0_OUT_EVEN, 6 },
 187         { P_CORE_BI_PLL_TEST_SE, 7 },
 188 };
 189
 190 static const struct clk_parent_data gcc_parent_data_1[] = {
 191         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 192         { .hw = &gpll0.clkr.hw },
 193         { .hw = &gpll6.clkr.hw },
 194         { .hw = &gpll0_out_even.clkr.hw },
 195         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 196 };
 197
 198 static const struct parent_map gcc_parent_map_2[] = {
 199         { P_BI_TCXO, 0 },
 200         { P_GPLL0_OUT_MAIN, 1 },
 201         { P_GPLL1_OUT_MAIN, 4 },
 202         { P_GPLL4_OUT_MAIN, 5 },
 203         { P_GPLL0_OUT_EVEN, 6 },
 204         { P_CORE_BI_PLL_TEST_SE, 7 },
 205 };
 206
 207 static const struct clk_parent_data gcc_parent_data_2[] = {
 208         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 209         { .hw = &gpll0.clkr.hw },
 210         { .hw = &gpll1.clkr.hw },
 211         { .hw = &gpll4.clkr.hw },
 212         { .hw = &gpll0_out_even.clkr.hw },
 213         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 214 };
 215
 216 static const struct parent_map gcc_parent_map_3[] = {
 217         { P_BI_TCXO, 0 },
 218         { P_GPLL0_OUT_MAIN, 1 },
 219         { P_CORE_BI_PLL_TEST_SE, 7 },
 220 };
 221
 222 static const struct clk_parent_data gcc_parent_data_3[] = {
 223         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 224         { .hw = &gpll0.clkr.hw },
 225         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 226 };
 227
 228 static const struct parent_map gcc_parent_map_4[] = {
 229         { P_BI_TCXO, 0 },
 230         { P_GPLL0_OUT_MAIN, 1 },
 231         { P_SLEEP_CLK, 5 },
 232         { P_GPLL0_OUT_EVEN, 6 },
 233         { P_CORE_BI_PLL_TEST_SE, 7 },
 234 };
 235
 236 static const struct clk_parent_data gcc_parent_data_4[] = {
 237         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 238         { .hw = &gpll0.clkr.hw },
 239         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 240         { .hw = &gpll0_out_even.clkr.hw },
 241         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 242 };
 243
 244 static const struct parent_map gcc_parent_map_5[] = {
 245         { P_BI_TCXO, 0 },
 246         { P_GPLL0_OUT_MAIN, 1 },
 247         { P_GPLL7_OUT_MAIN, 3 },
 248         { P_GPLL0_OUT_EVEN, 6 },
 249         { P_CORE_BI_PLL_TEST_SE, 7 },
 250 };
 251
 252 static const struct clk_parent_data gcc_parent_data_5[] = {
 253         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 254         { .hw = &gpll0.clkr.hw },
 255         { .hw = &gpll7.clkr.hw },
 256         { .hw = &gpll0_out_even.clkr.hw },
 257         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 258 };
 259
 260 static const struct parent_map gcc_parent_map_6[] = {
 261         { P_BI_TCXO, 0 },
 262         { P_GPLL0_OUT_MAIN, 1 },
 263         { P_SLEEP_CLK, 5 },
 264         { P_CORE_BI_PLL_TEST_SE, 7 },
 265 };
 266
 267 static const struct clk_parent_data gcc_parent_data_6[] = {
 268         { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
 269         { .hw = &gpll0.clkr.hw },
 270         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 271         { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 272 };
 273
 274 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
 275         F(19200000, P_BI_TCXO, 1, 0, 0),
 276         { }
 277 };
 278
 279 static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
 280         .cmd_rcgr = 0x48014,
 281         .mnd_width = 0,
 282         .hid_width = 5,
 283         .parent_map = gcc_parent_map_0,
 284         .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
 285         .clkr.hw.init = &(struct clk_init_data){
 286                 .name = "gcc_cpuss_ahb_clk_src",
 287                 .parent_data = gcc_parent_data_0_ao,
 288                 .num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
 289                 .flags = CLK_SET_RATE_PARENT,
 290                 .ops = &clk_rcg2_ops,
 291                 },
 292 };
 293
 294 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
 295         F(19200000, P_BI_TCXO, 1, 0, 0),
 296         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 297         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 298         F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
 299         F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0),
 300         { }
 301 };
 302
 303 static struct clk_rcg2 gcc_gp1_clk_src = {
 304         .cmd_rcgr = 0x64004,
 305         .mnd_width = 8,
 306         .hid_width = 5,
 307         .parent_map = gcc_parent_map_4,
 308         .freq_tbl = ftbl_gcc_gp1_clk_src,
 309         .clkr.hw.init = &(struct clk_init_data){
 310                 .name = "gcc_gp1_clk_src",
 311                 .parent_data = gcc_parent_data_4,
 312                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 313                 .ops = &clk_rcg2_ops,
 314         },
 315 };
 316
 317 static struct clk_rcg2 gcc_gp2_clk_src = {
 318         .cmd_rcgr = 0x65004,
 319         .mnd_width = 8,
 320         .hid_width = 5,
 321         .parent_map = gcc_parent_map_4,
 322         .freq_tbl = ftbl_gcc_gp1_clk_src,
 323         .clkr.hw.init = &(struct clk_init_data){
 324                 .name = "gcc_gp2_clk_src",
 325                 .parent_data = gcc_parent_data_4,
 326                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 327                 .ops = &clk_rcg2_ops,
 328         },
 329 };
 330
 331 static struct clk_rcg2 gcc_gp3_clk_src = {
 332         .cmd_rcgr = 0x66004,
 333         .mnd_width = 8,
 334         .hid_width = 5,
 335         .parent_map = gcc_parent_map_4,
 336         .freq_tbl = ftbl_gcc_gp1_clk_src,
 337         .clkr.hw.init = &(struct clk_init_data){
 338                 .name = "gcc_gp3_clk_src",
 339                 .parent_data = gcc_parent_data_4,
 340                 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
 341                 .ops = &clk_rcg2_ops,
 342         },
 343 };
 344
 345 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
 346         F(19200000, P_BI_TCXO, 1, 0, 0),
 347         F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
 348         { }
 349 };
 350
 351 static struct clk_rcg2 gcc_pdm2_clk_src = {
 352         .cmd_rcgr = 0x33010,
 353         .mnd_width = 0,
 354         .hid_width = 5,
 355         .parent_map = gcc_parent_map_0,
 356         .freq_tbl = ftbl_gcc_pdm2_clk_src,
 357         .clkr.hw.init = &(struct clk_init_data){
 358                 .name = "gcc_pdm2_clk_src",
 359                 .parent_data = gcc_parent_data_0,
 360                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 361                 .ops = &clk_rcg2_ops,
 362         },
 363 };
 364
 365 static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
 366         F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 367         F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
 368         F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
 369         { }
 370 };
 371
 372 static struct clk_rcg2 gcc_qspi_core_clk_src = {
 373         .cmd_rcgr = 0x4b00c,
 374         .mnd_width = 0,
 375         .hid_width = 5,
 376         .parent_map = gcc_parent_map_2,
 377         .freq_tbl = ftbl_gcc_qspi_core_clk_src,
 378         .clkr.hw.init = &(struct clk_init_data){
 379                 .name = "gcc_qspi_core_clk_src",
 380                 .parent_data = gcc_parent_data_2,
 381                 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
 382                 .ops = &clk_rcg2_ops,
 383         },
 384 };
 385
 386 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
 387         F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
 388         F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
 389         F(19200000, P_BI_TCXO, 1, 0, 0),
 390         F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
 391         F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
 392         F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
 393         F(51200000, P_GPLL6_OUT_MAIN, 7.5, 0, 0),
 394         F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
 395         F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 396         F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
 397         F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
 398         F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
 399         F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
 400         F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
 401         F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
 402         F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
 403         F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
 404         { }
 405 };
 406
 407 static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
 408         .name = "gcc_qupv3_wrap0_s0_clk_src",
 409         .parent_data = gcc_parent_data_1,
 410         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 411         .ops = &clk_rcg2_ops,
 412 };
 413
 414 static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
 415         .cmd_rcgr = 0x17034,
 416         .mnd_width = 16,
 417         .hid_width = 5,
 418         .parent_map = gcc_parent_map_1,
 419         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 420         .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
 421 };
 422
 423 static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
 424         .name = "gcc_qupv3_wrap0_s1_clk_src",
 425         .parent_data = gcc_parent_data_1,
 426         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 427         .ops = &clk_rcg2_ops,
 428 };
 429
 430 static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
 431         .cmd_rcgr = 0x17164,
 432         .mnd_width = 16,
 433         .hid_width = 5,
 434         .parent_map = gcc_parent_map_1,
 435         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 436         .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
 437 };
 438
 439 static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
 440         .name = "gcc_qupv3_wrap0_s2_clk_src",
 441         .parent_data = gcc_parent_data_1,
 442         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 443         .ops = &clk_rcg2_ops,
 444 };
 445
 446 static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
 447         .cmd_rcgr = 0x17294,
 448         .mnd_width = 16,
 449         .hid_width = 5,
 450         .parent_map = gcc_parent_map_1,
 451         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 452         .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
 453 };
 454
 455 static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
 456         .name = "gcc_qupv3_wrap0_s3_clk_src",
 457         .parent_data = gcc_parent_data_1,
 458         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 459         .ops = &clk_rcg2_ops,
 460 };
 461
 462 static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
 463         .cmd_rcgr = 0x173c4,
 464         .mnd_width = 16,
 465         .hid_width = 5,
 466         .parent_map = gcc_parent_map_1,
 467         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 468         .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
 469 };
 470
 471 static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
 472         .name = "gcc_qupv3_wrap0_s4_clk_src",
 473         .parent_data = gcc_parent_data_1,
 474         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 475         .ops = &clk_rcg2_ops,
 476 };
 477
 478 static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
 479         .cmd_rcgr = 0x174f4,
 480         .mnd_width = 16,
 481         .hid_width = 5,
 482         .parent_map = gcc_parent_map_1,
 483         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 484         .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
 485 };
 486
 487 static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
 488         .name = "gcc_qupv3_wrap0_s5_clk_src",
 489         .parent_data = gcc_parent_data_1,
 490         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 491         .ops = &clk_rcg2_ops,
 492 };
 493
 494 static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
 495         .cmd_rcgr = 0x17624,
 496         .mnd_width = 16,
 497         .hid_width = 5,
 498         .parent_map = gcc_parent_map_1,
 499         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 500         .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
 501 };
 502
 503 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
 504         .name = "gcc_qupv3_wrap1_s0_clk_src",
 505         .parent_data = gcc_parent_data_1,
 506         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 507         .ops = &clk_rcg2_ops,
 508 };
 509
 510 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
 511         .cmd_rcgr = 0x18018,
 512         .mnd_width = 16,
 513         .hid_width = 5,
 514         .parent_map = gcc_parent_map_1,
 515         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 516         .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
 517 };
 518
 519 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
 520         .name = "gcc_qupv3_wrap1_s1_clk_src",
 521         .parent_data = gcc_parent_data_1,
 522         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 523         .ops = &clk_rcg2_ops,
 524 };
 525
 526 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
 527         .cmd_rcgr = 0x18148,
 528         .mnd_width = 16,
 529         .hid_width = 5,
 530         .parent_map = gcc_parent_map_1,
 531         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 532         .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
 533 };
 534
 535 static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
 536         .name = "gcc_qupv3_wrap1_s2_clk_src",
 537         .parent_data = gcc_parent_data_1,
 538         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 539         .ops = &clk_rcg2_ops,
 540 };
 541
 542 static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
 543         .cmd_rcgr = 0x18278,
 544         .mnd_width = 16,
 545         .hid_width = 5,
 546         .parent_map = gcc_parent_map_1,
 547         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 548         .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
 549 };
 550
 551 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
 552         .name = "gcc_qupv3_wrap1_s3_clk_src",
 553         .parent_data = gcc_parent_data_1,
 554         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 555         .ops = &clk_rcg2_ops,
 556 };
 557
 558 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
 559         .cmd_rcgr = 0x183a8,
 560         .mnd_width = 16,
 561         .hid_width = 5,
 562         .parent_map = gcc_parent_map_1,
 563         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 564         .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
 565 };
 566
 567 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
 568         .name = "gcc_qupv3_wrap1_s4_clk_src",
 569         .parent_data = gcc_parent_data_1,
 570         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 571         .ops = &clk_rcg2_ops,
 572 };
 573
 574 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
 575         .cmd_rcgr = 0x184d8,
 576         .mnd_width = 16,
 577         .hid_width = 5,
 578         .parent_map = gcc_parent_map_1,
 579         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 580         .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
 581 };
 582
 583 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
 584         .name = "gcc_qupv3_wrap1_s5_clk_src",
 585         .parent_data = gcc_parent_data_1,
 586         .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 587         .ops = &clk_rcg2_ops,
 588 };
 589
 590 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
 591         .cmd_rcgr = 0x18608,
 592         .mnd_width = 16,
 593         .hid_width = 5,
 594         .parent_map = gcc_parent_map_1,
 595         .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
 596         .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
 597 };
 598
 599
 600 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
 601         F(144000, P_BI_TCXO, 16, 3, 25),
 602         F(400000, P_BI_TCXO, 12, 1, 4),
 603         F(19200000, P_BI_TCXO, 1, 0, 0),
 604         F(20000000, P_GPLL0_OUT_EVEN, 5, 1, 3),
 605         F(25000000, P_GPLL0_OUT_EVEN, 6, 1, 2),
 606         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 607         F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
 608         F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
 609         F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
 610         { }
 611 };
 612
 613 static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
 614         .cmd_rcgr = 0x12028,
 615         .mnd_width = 8,
 616         .hid_width = 5,
 617         .parent_map = gcc_parent_map_1,
 618         .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
 619         .clkr.hw.init = &(struct clk_init_data){
 620                 .name = "gcc_sdcc1_apps_clk_src",
 621                 .parent_data = gcc_parent_data_1,
 622                 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
 623                 .ops = &clk_rcg2_floor_ops,
 624         },
 625 };
 626
 627 static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
 628         F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
 629         F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
 630         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 631         F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
 632         { }
 633 };
 634
 635 static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
 636         .cmd_rcgr = 0x12010,
 637         .mnd_width = 0,
 638         .hid_width = 5,
 639         .parent_map = gcc_parent_map_0,
 640         .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
 641         .clkr.hw.init = &(struct clk_init_data){
 642                 .name = "gcc_sdcc1_ice_core_clk_src",
 643                 .parent_data = gcc_parent_data_0,
 644                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 645                 .ops = &clk_rcg2_ops,
 646         },
 647 };
 648
 649 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
 650         F(400000, P_BI_TCXO, 12, 1, 4),
 651         F(9600000, P_BI_TCXO, 2, 0, 0),
 652         F(19200000, P_BI_TCXO, 1, 0, 0),
 653         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 654         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 655         F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
 656         F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
 657         { }
 658 };
 659
 660 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
 661         .cmd_rcgr = 0x1400c,
 662         .mnd_width = 8,
 663         .hid_width = 5,
 664         .parent_map = gcc_parent_map_5,
 665         .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
 666         .clkr.hw.init = &(struct clk_init_data){
 667                 .name = "gcc_sdcc2_apps_clk_src",
 668                 .parent_data = gcc_parent_data_5,
 669                 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
 670                 .ops = &clk_rcg2_floor_ops,
 671         },
 672 };
 673
 674 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
 675         F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 676         F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
 677         F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
 678         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 679         F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
 680         { }
 681 };
 682
 683 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
 684         .cmd_rcgr = 0x77020,
 685         .mnd_width = 8,
 686         .hid_width = 5,
 687         .parent_map = gcc_parent_map_0,
 688         .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
 689         .clkr.hw.init = &(struct clk_init_data){
 690                 .name = "gcc_ufs_phy_axi_clk_src",
 691                 .parent_data = gcc_parent_data_0,
 692                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 693                 .ops = &clk_rcg2_ops,
 694         },
 695 };
 696
 697 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
 698         F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
 699         F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 700         F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
 701         F(300000000, P_GPLL0_OUT_EVEN, 1, 0, 0),
 702         { }
 703 };
 704
 705 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
 706         .cmd_rcgr = 0x77048,
 707         .mnd_width = 0,
 708         .hid_width = 5,
 709         .parent_map = gcc_parent_map_0,
 710         .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
 711         .clkr.hw.init = &(struct clk_init_data){
 712                 .name = "gcc_ufs_phy_ice_core_clk_src",
 713                 .parent_data = gcc_parent_data_0,
 714                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 715                 .ops = &clk_rcg2_ops,
 716         },
 717 };
 718
 719 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
 720         F(9600000, P_BI_TCXO, 2, 0, 0),
 721         F(19200000, P_BI_TCXO, 1, 0, 0),
 722         { }
 723 };
 724
 725 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
 726         .cmd_rcgr = 0x77098,
 727         .mnd_width = 0,
 728         .hid_width = 5,
 729         .parent_map = gcc_parent_map_3,
 730         .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
 731         .clkr.hw.init = &(struct clk_init_data){
 732                 .name = "gcc_ufs_phy_phy_aux_clk_src",
 733                 .parent_data = gcc_parent_data_3,
 734                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
 735                 .ops = &clk_rcg2_ops,
 736         },
 737 };
 738
 739 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
 740         F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
 741         F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
 742         F(150000000, P_GPLL0_OUT_EVEN, 2, 0, 0),
 743         { }
 744 };
 745
 746 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
 747         .cmd_rcgr = 0x77060,
 748         .mnd_width = 0,
 749         .hid_width = 5,
 750         .parent_map = gcc_parent_map_0,
 751         .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
 752         .clkr.hw.init = &(struct clk_init_data){
 753                 .name = "gcc_ufs_phy_unipro_core_clk_src",
 754                 .parent_data = gcc_parent_data_0,
 755                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 756                 .ops = &clk_rcg2_ops,
 757         },
 758 };
 759
 760 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
 761         F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
 762         F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
 763         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 764         F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
 765         { }
 766 };
 767
 768 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
 769         .cmd_rcgr = 0xf01c,
 770         .mnd_width = 8,
 771         .hid_width = 5,
 772         .parent_map = gcc_parent_map_0,
 773         .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
 774         .clkr.hw.init = &(struct clk_init_data){
 775                 .name = "gcc_usb30_prim_master_clk_src",
 776                 .parent_data = gcc_parent_data_0,
 777                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 778                 .ops = &clk_rcg2_ops,
 779         },
 780 };
 781
 782 static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
 783         F(19200000, P_BI_TCXO, 1, 0, 0),
 784         F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
 785         { }
 786 };
 787
 788 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
 789         .cmd_rcgr = 0xf034,
 790         .mnd_width = 0,
 791         .hid_width = 5,
 792         .parent_map = gcc_parent_map_0,
 793         .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
 794         .clkr.hw.init = &(struct clk_init_data){
 795                 .name = "gcc_usb30_prim_mock_utmi_clk_src",
 796                 .parent_data = gcc_parent_data_0,
 797                 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
 798                 .ops = &clk_rcg2_ops,
 799         },
 800 };
 801
 802 static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = {
 803         F(19200000, P_BI_TCXO, 1, 0, 0),
 804         { }
 805 };
 806
 807 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
 808         .cmd_rcgr = 0xf060,
 809         .mnd_width = 0,
 810         .hid_width = 5,
 811         .parent_map = gcc_parent_map_6,
 812         .freq_tbl = ftbl_gcc_usb3_prim_phy_aux_clk_src,
 813         .clkr.hw.init = &(struct clk_init_data){
 814                 .name = "gcc_usb3_prim_phy_aux_clk_src",
 815                 .parent_data = gcc_parent_data_6,
 816                 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
 817                 .ops = &clk_rcg2_ops,
 818         },
 819 };
 820
 821 static const struct freq_tbl ftbl_gcc_sec_ctrl_clk_src[] = {
 822         F(4800000, P_BI_TCXO, 4, 0, 0),
 823         F(19200000, P_BI_TCXO, 1, 0, 0),
 824         { }
 825 };
 826
 827 static struct clk_rcg2 gcc_sec_ctrl_clk_src = {
 828         .cmd_rcgr = 0x3d030,
 829         .mnd_width = 0,
 830         .hid_width = 5,
 831         .parent_map = gcc_parent_map_3,
 832         .freq_tbl = ftbl_gcc_sec_ctrl_clk_src,
 833         .clkr.hw.init = &(struct clk_init_data){
 834                 .name = "gcc_sec_ctrl_clk_src",
 835                 .parent_data = gcc_parent_data_3,
 836                 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
 837                 .ops = &clk_rcg2_ops,
 838         },
 839 };
 840
 841 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
 842         .halt_reg = 0x82024,
 843         .halt_check = BRANCH_HALT_DELAY,
 844         .hwcg_reg = 0x82024,
 845         .hwcg_bit = 1,
 846         .clkr = {
 847                 .enable_reg = 0x82024,
 848                 .enable_mask = BIT(0),
 849                 .hw.init = &(struct clk_init_data){
 850                         .name = "gcc_aggre_ufs_phy_axi_clk",
 851                         .parent_hws = (const struct clk_hw*[]){
 852                                 &gcc_ufs_phy_axi_clk_src.clkr.hw,
 853                         },
 854                         .num_parents = 1,
 855                         .flags = CLK_SET_RATE_PARENT,
 856                         .ops = &clk_branch2_ops,
 857                 },
 858         },
 859 };
 860
 861 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
 862         .halt_reg = 0x8201c,
 863         .halt_check = BRANCH_HALT,
 864         .clkr = {
 865                 .enable_reg = 0x8201c,
 866                 .enable_mask = BIT(0),
 867                 .hw.init = &(struct clk_init_data){
 868                         .name = "gcc_aggre_usb3_prim_axi_clk",
 869                         .parent_hws = (const struct clk_hw*[]){
 870                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
 871                         },
 872                         .num_parents = 1,
 873                         .flags = CLK_SET_RATE_PARENT,
 874                         .ops = &clk_branch2_ops,
 875                 },
 876         },
 877 };
 878
 879 static struct clk_branch gcc_boot_rom_ahb_clk = {
 880         .halt_reg = 0x38004,
 881         .halt_check = BRANCH_HALT_VOTED,
 882         .hwcg_reg = 0x38004,
 883         .hwcg_bit = 1,
 884         .clkr = {
 885                 .enable_reg = 0x52000,
 886                 .enable_mask = BIT(10),
 887                 .hw.init = &(struct clk_init_data){
 888                         .name = "gcc_boot_rom_ahb_clk",
 889                         .ops = &clk_branch2_ops,
 890                 },
 891         },
 892 };
 893
 894 static struct clk_branch gcc_camera_hf_axi_clk = {
 895         .halt_reg = 0xb020,
 896         .halt_check = BRANCH_HALT,
 897         .clkr = {
 898                 .enable_reg = 0xb020,
 899                 .enable_mask = BIT(0),
 900                 .hw.init = &(struct clk_init_data){
 901                         .name = "gcc_camera_hf_axi_clk",
 902                         .ops = &clk_branch2_ops,
 903                 },
 904         },
 905 };
 906
 907 static struct clk_branch gcc_camera_throttle_hf_axi_clk = {
 908         .halt_reg = 0xb080,
 909         .halt_check = BRANCH_HALT,
 910         .hwcg_reg = 0xb080,
 911         .hwcg_bit = 1,
 912         .clkr = {
 913                 .enable_reg = 0xb080,
 914                 .enable_mask = BIT(0),
 915                 .hw.init = &(struct clk_init_data){
 916                         .name = "gcc_camera_throttle_hf_axi_clk",
 917                         .ops = &clk_branch2_ops,
 918                 },
 919         },
 920 };
 921
 922 static struct clk_branch gcc_ce1_ahb_clk = {
 923         .halt_reg = 0x4100c,
 924         .halt_check = BRANCH_HALT_VOTED,
 925         .hwcg_reg = 0x4100c,
 926         .hwcg_bit = 1,
 927         .clkr = {
 928                 .enable_reg = 0x52000,
 929                 .enable_mask = BIT(3),
 930                 .hw.init = &(struct clk_init_data){
 931                         .name = "gcc_ce1_ahb_clk",
 932                         .ops = &clk_branch2_ops,
 933                 },
 934         },
 935 };
 936
 937 static struct clk_branch gcc_ce1_axi_clk = {
 938         .halt_reg = 0x41008,
 939         .halt_check = BRANCH_HALT_VOTED,
 940         .clkr = {
 941                 .enable_reg = 0x52000,
 942                 .enable_mask = BIT(4),
 943                 .hw.init = &(struct clk_init_data){
 944                         .name = "gcc_ce1_axi_clk",
 945                         .ops = &clk_branch2_ops,
 946                 },
 947         },
 948 };
 949
 950 static struct clk_branch gcc_ce1_clk = {
 951         .halt_reg = 0x41004,
 952         .halt_check = BRANCH_HALT_VOTED,
 953         .clkr = {
 954                 .enable_reg = 0x52000,
 955                 .enable_mask = BIT(5),
 956                 .hw.init = &(struct clk_init_data){
 957                         .name = "gcc_ce1_clk",
 958                         .ops = &clk_branch2_ops,
 959                 },
 960         },
 961 };
 962
 963 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
 964         .halt_reg = 0x502c,
 965         .halt_check = BRANCH_HALT,
 966         .clkr = {
 967                 .enable_reg = 0x502c,
 968                 .enable_mask = BIT(0),
 969                 .hw.init = &(struct clk_init_data){
 970                         .name = "gcc_cfg_noc_usb3_prim_axi_clk",
 971                         .parent_hws = (const struct clk_hw*[]){
 972                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
 973                         },
 974                         .num_parents = 1,
 975                         .flags = CLK_SET_RATE_PARENT,
 976                         .ops = &clk_branch2_ops,
 977                 },
 978         },
 979 };
 980
 981 /* For CPUSS functionality the AHB clock needs to be left enabled */
 982 static struct clk_branch gcc_cpuss_ahb_clk = {
 983         .halt_reg = 0x48000,
 984         .halt_check = BRANCH_HALT_VOTED,
 985         .clkr = {
 986                 .enable_reg = 0x52000,
 987                 .enable_mask = BIT(21),
 988                 .hw.init = &(struct clk_init_data){
 989                         .name = "gcc_cpuss_ahb_clk",
 990                         .parent_hws = (const struct clk_hw*[]){
 991                                 &gcc_cpuss_ahb_clk_src.clkr.hw,
 992                         },
 993                         .num_parents = 1,
 994                         .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
 995                         .ops = &clk_branch2_ops,
 996                 },
 997         },
 998 };
 999
1000 static struct clk_branch gcc_cpuss_rbcpr_clk = {
1001         .halt_reg = 0x48008,
1002         .halt_check = BRANCH_HALT,
1003         .clkr = {
1004                 .enable_reg = 0x48008,
1005                 .enable_mask = BIT(0),
1006                 .hw.init = &(struct clk_init_data){
1007                         .name = "gcc_cpuss_rbcpr_clk",
1008                         .ops = &clk_branch2_ops,
1009                 },
1010         },
1011 };
1012
1013 static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1014         .halt_reg = 0x4452c,
1015         .halt_check = BRANCH_VOTED,
1016         .clkr = {
1017                 .enable_reg = 0x4452c,
1018                 .enable_mask = BIT(0),
1019                 .hw.init = &(struct clk_init_data){
1020                         .name = "gcc_ddrss_gpu_axi_clk",
1021                         .ops = &clk_branch2_ops,
1022                 },
1023         },
1024 };
1025
1026 static struct clk_branch gcc_disp_gpll0_clk_src = {
1027         .halt_check = BRANCH_HALT_DELAY,
1028         .clkr = {
1029                 .enable_reg = 0x52000,
1030                 .enable_mask = BIT(18),
1031                 .hw.init = &(struct clk_init_data){
1032                         .name = "gcc_disp_gpll0_clk_src",
1033                         .parent_hws = (const struct clk_hw*[]){
1034                                 &gpll0.clkr.hw,
1035                         },
1036                         .num_parents = 1,
1037                         .ops = &clk_branch2_aon_ops,
1038                 },
1039         },
1040 };
1041
1042 static struct clk_branch gcc_disp_gpll0_div_clk_src = {
1043         .halt_check = BRANCH_HALT_DELAY,
1044         .clkr = {
1045                 .enable_reg = 0x52000,
1046                 .enable_mask = BIT(19),
1047                 .hw.init = &(struct clk_init_data){
1048                         .name = "gcc_disp_gpll0_div_clk_src",
1049                         .parent_hws = (const struct clk_hw*[]){
1050                                 &gcc_pll0_main_div_cdiv.hw,
1051                         },
1052                         .num_parents = 1,
1053                         .ops = &clk_branch2_ops,
1054                 },
1055         },
1056 };
1057
1058 static struct clk_branch gcc_disp_hf_axi_clk = {
1059         .halt_reg = 0xb024,
1060         .halt_check = BRANCH_HALT,
1061         .clkr = {
1062                 .enable_reg = 0xb024,
1063                 .enable_mask = BIT(0),
1064                 .hw.init = &(struct clk_init_data){
1065                         .name = "gcc_disp_hf_axi_clk",
1066                         .ops = &clk_branch2_ops,
1067                 },
1068         },
1069 };
1070
1071 static struct clk_branch gcc_disp_throttle_hf_axi_clk = {
1072         .halt_reg = 0xb084,
1073         .halt_check = BRANCH_HALT,
1074         .hwcg_reg = 0xb084,
1075         .hwcg_bit = 1,
1076         .clkr = {
1077                 .enable_reg = 0xb084,
1078                 .enable_mask = BIT(0),
1079                 .hw.init = &(struct clk_init_data){
1080                         .name = "gcc_disp_throttle_hf_axi_clk",
1081                         .ops = &clk_branch2_ops,
1082                 },
1083         },
1084 };
1085
1086 static struct clk_branch gcc_gp1_clk = {
1087         .halt_reg = 0x64000,
1088         .halt_check = BRANCH_HALT,
1089         .clkr = {
1090                 .enable_reg = 0x64000,
1091                 .enable_mask = BIT(0),
1092                 .hw.init = &(struct clk_init_data){
1093                         .name = "gcc_gp1_clk",
1094                         .parent_hws = (const struct clk_hw*[]){
1095                                 &gcc_gp1_clk_src.clkr.hw,
1096                         },
1097                         .num_parents = 1,
1098                         .flags = CLK_SET_RATE_PARENT,
1099                         .ops = &clk_branch2_ops,
1100                 },
1101         },
1102 };
1103
1104 static struct clk_branch gcc_gp2_clk = {
1105         .halt_reg = 0x65000,
1106         .halt_check = BRANCH_HALT,
1107         .clkr = {
1108                 .enable_reg = 0x65000,
1109                 .enable_mask = BIT(0),
1110                 .hw.init = &(struct clk_init_data){
1111                         .name = "gcc_gp2_clk",
1112                         .parent_hws = (const struct clk_hw*[]){
1113                                 &gcc_gp2_clk_src.clkr.hw,
1114                         },
1115                         .num_parents = 1,
1116                         .flags = CLK_SET_RATE_PARENT,
1117                         .ops = &clk_branch2_ops,
1118                 },
1119         },
1120 };
1121
1122 static struct clk_branch gcc_gp3_clk = {
1123         .halt_reg = 0x66000,
1124         .halt_check = BRANCH_HALT,
1125         .clkr = {
1126                 .enable_reg = 0x66000,
1127                 .enable_mask = BIT(0),
1128                 .hw.init = &(struct clk_init_data){
1129                         .name = "gcc_gp3_clk",
1130                         .parent_hws = (const struct clk_hw*[]){
1131                                 &gcc_gp3_clk_src.clkr.hw,
1132                         },
1133                         .num_parents = 1,
1134                         .flags = CLK_SET_RATE_PARENT,
1135                         .ops = &clk_branch2_ops,
1136                 },
1137         },
1138 };
1139
1140 static struct clk_branch gcc_gpu_gpll0_clk_src = {
1141         .halt_check = BRANCH_HALT_DELAY,
1142         .clkr = {
1143                 .enable_reg = 0x52000,
1144                 .enable_mask = BIT(15),
1145                 .hw.init = &(struct clk_init_data){
1146                         .name = "gcc_gpu_gpll0_clk_src",
1147                         .parent_hws = (const struct clk_hw*[]){
1148                                 &gpll0.clkr.hw,
1149                         },
1150                         .num_parents = 1,
1151                         .ops = &clk_branch2_ops,
1152                 },
1153         },
1154 };
1155
1156 static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1157         .halt_check = BRANCH_HALT_DELAY,
1158         .clkr = {
1159                 .enable_reg = 0x52000,
1160                 .enable_mask = BIT(16),
1161                 .hw.init = &(struct clk_init_data){
1162                         .name = "gcc_gpu_gpll0_div_clk_src",
1163                         .parent_hws = (const struct clk_hw*[]){
1164                                 &gcc_pll0_main_div_cdiv.hw,
1165                         },
1166                         .num_parents = 1,
1167                         .ops = &clk_branch2_ops,
1168                 },
1169         },
1170 };
1171
1172 static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1173         .halt_reg = 0x7100c,
1174         .halt_check = BRANCH_VOTED,
1175         .clkr = {
1176                 .enable_reg = 0x7100c,
1177                 .enable_mask = BIT(0),
1178                 .hw.init = &(struct clk_init_data){
1179                         .name = "gcc_gpu_memnoc_gfx_clk",
1180                         .ops = &clk_branch2_ops,
1181                 },
1182         },
1183 };
1184
1185 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1186         .halt_reg = 0x71018,
1187         .halt_check = BRANCH_HALT,
1188         .clkr = {
1189                 .enable_reg = 0x71018,
1190                 .enable_mask = BIT(0),
1191                 .hw.init = &(struct clk_init_data){
1192                         .name = "gcc_gpu_snoc_dvm_gfx_clk",
1193                         .ops = &clk_branch2_ops,
1194                 },
1195         },
1196 };
1197
1198 static struct clk_branch gcc_npu_axi_clk = {
1199         .halt_reg = 0x4d008,
1200         .halt_check = BRANCH_HALT,
1201         .clkr = {
1202                 .enable_reg = 0x4d008,
1203                 .enable_mask = BIT(0),
1204                 .hw.init = &(struct clk_init_data){
1205                         .name = "gcc_npu_axi_clk",
1206                         .ops = &clk_branch2_ops,
1207                 },
1208         },
1209 };
1210
1211 static struct clk_branch gcc_npu_bwmon_axi_clk = {
1212         .halt_reg = 0x73008,
1213         .halt_check = BRANCH_HALT,
1214         .clkr = {
1215                 .enable_reg = 0x73008,
1216                 .enable_mask = BIT(0),
1217                 .hw.init = &(struct clk_init_data){
1218                         .name = "gcc_npu_bwmon_axi_clk",
1219                         .ops = &clk_branch2_ops,
1220                 },
1221         },
1222 };
1223
1224 static struct clk_branch gcc_npu_bwmon_dma_cfg_ahb_clk = {
1225         .halt_reg = 0x73018,
1226         .halt_check = BRANCH_HALT,
1227         .clkr = {
1228                 .enable_reg = 0x73018,
1229                 .enable_mask = BIT(0),
1230                 .hw.init = &(struct clk_init_data){
1231                         .name = "gcc_npu_bwmon_dma_cfg_ahb_clk",
1232                         .ops = &clk_branch2_ops,
1233                 },
1234         },
1235 };
1236
1237 static struct clk_branch gcc_npu_bwmon_dsp_cfg_ahb_clk = {
1238         .halt_reg = 0x7301c,
1239         .halt_check = BRANCH_HALT,
1240         .clkr = {
1241                 .enable_reg = 0x7301c,
1242                 .enable_mask = BIT(0),
1243                 .hw.init = &(struct clk_init_data){
1244                         .name = "gcc_npu_bwmon_dsp_cfg_ahb_clk",
1245                         .ops = &clk_branch2_ops,
1246                 },
1247         },
1248 };
1249
1250 static struct clk_branch gcc_npu_cfg_ahb_clk = {
1251         .halt_reg = 0x4d004,
1252         .halt_check = BRANCH_HALT,
1253         .hwcg_reg = 0x4d004,
1254         .hwcg_bit = 1,
1255         .clkr = {
1256                 .enable_reg = 0x4d004,
1257                 .enable_mask = BIT(0),
1258                 .hw.init = &(struct clk_init_data){
1259                         .name = "gcc_npu_cfg_ahb_clk",
1260                         .ops = &clk_branch2_ops,
1261                 },
1262         },
1263 };
1264
1265 static struct clk_branch gcc_npu_dma_clk = {
1266         .halt_reg = 0x4d1a0,
1267         .halt_check = BRANCH_HALT,
1268         .hwcg_reg = 0x4d1a0,
1269         .hwcg_bit = 1,
1270         .clkr = {
1271                 .enable_reg = 0x4d1a0,
1272                 .enable_mask = BIT(0),
1273                 .hw.init = &(struct clk_init_data){
1274                         .name = "gcc_npu_dma_clk",
1275                         .ops = &clk_branch2_ops,
1276                 },
1277         },
1278 };
1279
1280 static struct clk_branch gcc_npu_gpll0_clk_src = {
1281         .halt_check = BRANCH_HALT_DELAY,
1282         .clkr = {
1283                 .enable_reg = 0x52000,
1284                 .enable_mask = BIT(25),
1285                 .hw.init = &(struct clk_init_data){
1286                         .name = "gcc_npu_gpll0_clk_src",
1287                         .parent_hws = (const struct clk_hw*[]){
1288                                 &gpll0.clkr.hw,
1289                         },
1290                         .num_parents = 1,
1291                         .ops = &clk_branch2_ops,
1292                 },
1293         },
1294 };
1295
1296 static struct clk_branch gcc_npu_gpll0_div_clk_src = {
1297         .halt_check = BRANCH_HALT_DELAY,
1298         .clkr = {
1299                 .enable_reg = 0x52000,
1300                 .enable_mask = BIT(26),
1301                 .hw.init = &(struct clk_init_data){
1302                         .name = "gcc_npu_gpll0_div_clk_src",
1303                         .parent_hws = (const struct clk_hw*[]){
1304                                 &gcc_pll0_main_div_cdiv.hw,
1305                         },
1306                         .num_parents = 1,
1307                         .flags = CLK_SET_RATE_PARENT,
1308                         .ops = &clk_branch2_ops,
1309                 },
1310         },
1311 };
1312
1313 static struct clk_branch gcc_pdm2_clk = {
1314         .halt_reg = 0x3300c,
1315         .halt_check = BRANCH_HALT,
1316         .clkr = {
1317                 .enable_reg = 0x3300c,
1318                 .enable_mask = BIT(0),
1319                 .hw.init = &(struct clk_init_data){
1320                         .name = "gcc_pdm2_clk",
1321                         .parent_hws = (const struct clk_hw*[]){
1322                                 &gcc_pdm2_clk_src.clkr.hw,
1323                         },
1324                         .num_parents = 1,
1325                         .flags = CLK_SET_RATE_PARENT,
1326                         .ops = &clk_branch2_ops,
1327                 },
1328         },
1329 };
1330
1331 static struct clk_branch gcc_pdm_ahb_clk = {
1332         .halt_reg = 0x33004,
1333         .halt_check = BRANCH_HALT,
1334         .hwcg_reg = 0x33004,
1335         .hwcg_bit = 1,
1336         .clkr = {
1337                 .enable_reg = 0x33004,
1338                 .enable_mask = BIT(0),
1339                 .hw.init = &(struct clk_init_data){
1340                         .name = "gcc_pdm_ahb_clk",
1341                         .ops = &clk_branch2_ops,
1342                 },
1343         },
1344 };
1345
1346 static struct clk_branch gcc_pdm_xo4_clk = {
1347         .halt_reg = 0x33008,
1348         .halt_check = BRANCH_HALT,
1349         .clkr = {
1350                 .enable_reg = 0x33008,
1351                 .enable_mask = BIT(0),
1352                 .hw.init = &(struct clk_init_data){
1353                         .name = "gcc_pdm_xo4_clk",
1354                         .ops = &clk_branch2_ops,
1355                 },
1356         },
1357 };
1358
1359 static struct clk_branch gcc_prng_ahb_clk = {
1360         .halt_reg = 0x34004,
1361         .halt_check = BRANCH_HALT_VOTED,
1362         .hwcg_reg = 0x34004,
1363         .hwcg_bit = 1,
1364         .clkr = {
1365                 .enable_reg = 0x52000,
1366                 .enable_mask = BIT(13),
1367                 .hw.init = &(struct clk_init_data){
1368                         .name = "gcc_prng_ahb_clk",
1369                         .ops = &clk_branch2_ops,
1370                 },
1371         },
1372 };
1373
1374 static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
1375         .halt_reg = 0x4b004,
1376         .halt_check = BRANCH_HALT,
1377         .hwcg_reg = 0x4b004,
1378         .hwcg_bit = 1,
1379         .clkr = {
1380                 .enable_reg = 0x4b004,
1381                 .enable_mask = BIT(0),
1382                 .hw.init = &(struct clk_init_data){
1383                         .name = "gcc_qspi_cnoc_periph_ahb_clk",
1384                         .ops = &clk_branch2_ops,
1385                 },
1386         },
1387 };
1388
1389 static struct clk_branch gcc_qspi_core_clk = {
1390         .halt_reg = 0x4b008,
1391         .halt_check = BRANCH_HALT,
1392         .clkr = {
1393                 .enable_reg = 0x4b008,
1394                 .enable_mask = BIT(0),
1395                 .hw.init = &(struct clk_init_data){
1396                         .name = "gcc_qspi_core_clk",
1397                         .parent_hws = (const struct clk_hw*[]){
1398                                 &gcc_qspi_core_clk_src.clkr.hw,
1399                         },
1400                         .num_parents = 1,
1401                         .flags = CLK_SET_RATE_PARENT,
1402                         .ops = &clk_branch2_ops,
1403                 },
1404         },
1405 };
1406
1407 static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
1408         .halt_reg = 0x17014,
1409         .halt_check = BRANCH_HALT_VOTED,
1410         .clkr = {
1411                 .enable_reg = 0x52008,
1412                 .enable_mask = BIT(9),
1413                 .hw.init = &(struct clk_init_data){
1414                         .name = "gcc_qupv3_wrap0_core_2x_clk",
1415                         .ops = &clk_branch2_ops,
1416                 },
1417         },
1418 };
1419
1420 static struct clk_branch gcc_qupv3_wrap0_core_clk = {
1421         .halt_reg = 0x1700c,
1422         .halt_check = BRANCH_HALT_VOTED,
1423         .clkr = {
1424                 .enable_reg = 0x52008,
1425                 .enable_mask = BIT(8),
1426                 .hw.init = &(struct clk_init_data){
1427                         .name = "gcc_qupv3_wrap0_core_clk",
1428                         .ops = &clk_branch2_ops,
1429                 },
1430         },
1431 };
1432
1433 static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
1434         .halt_reg = 0x17030,
1435         .halt_check = BRANCH_HALT_VOTED,
1436         .clkr = {
1437                 .enable_reg = 0x52008,
1438                 .enable_mask = BIT(10),
1439                 .hw.init = &(struct clk_init_data){
1440                         .name = "gcc_qupv3_wrap0_s0_clk",
1441                         .parent_hws = (const struct clk_hw*[]){
1442                                 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
1443                         },
1444                         .num_parents = 1,
1445                         .flags = CLK_SET_RATE_PARENT,
1446                         .ops = &clk_branch2_ops,
1447                 },
1448         },
1449 };
1450
1451 static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
1452         .halt_reg = 0x17160,
1453         .halt_check = BRANCH_HALT_VOTED,
1454         .clkr = {
1455                 .enable_reg = 0x52008,
1456                 .enable_mask = BIT(11),
1457                 .hw.init = &(struct clk_init_data){
1458                         .name = "gcc_qupv3_wrap0_s1_clk",
1459                         .parent_hws = (const struct clk_hw*[]){
1460                                 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
1461                         },
1462                         .num_parents = 1,
1463                         .flags = CLK_SET_RATE_PARENT,
1464                         .ops = &clk_branch2_ops,
1465                 },
1466         },
1467 };
1468
1469 static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
1470         .halt_reg = 0x17290,
1471         .halt_check = BRANCH_HALT_VOTED,
1472         .clkr = {
1473                 .enable_reg = 0x52008,
1474                 .enable_mask = BIT(12),
1475                 .hw.init = &(struct clk_init_data){
1476                         .name = "gcc_qupv3_wrap0_s2_clk",
1477                         .parent_hws = (const struct clk_hw*[]){
1478                                 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
1479                         },
1480                         .num_parents = 1,
1481                         .flags = CLK_SET_RATE_PARENT,
1482                         .ops = &clk_branch2_ops,
1483                 },
1484         },
1485 };
1486
1487 static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
1488         .halt_reg = 0x173c0,
1489         .halt_check = BRANCH_HALT_VOTED,
1490         .clkr = {
1491                 .enable_reg = 0x52008,
1492                 .enable_mask = BIT(13),
1493                 .hw.init = &(struct clk_init_data){
1494                         .name = "gcc_qupv3_wrap0_s3_clk",
1495                         .parent_hws = (const struct clk_hw*[]){
1496                                 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
1497                         },
1498                         .num_parents = 1,
1499                         .flags = CLK_SET_RATE_PARENT,
1500                         .ops = &clk_branch2_ops,
1501                 },
1502         },
1503 };
1504
1505 static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
1506         .halt_reg = 0x174f0,
1507         .halt_check = BRANCH_HALT_VOTED,
1508         .clkr = {
1509                 .enable_reg = 0x52008,
1510                 .enable_mask = BIT(14),
1511                 .hw.init = &(struct clk_init_data){
1512                         .name = "gcc_qupv3_wrap0_s4_clk",
1513                         .parent_hws = (const struct clk_hw*[]){
1514                                 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
1515                         },
1516                         .num_parents = 1,
1517                         .flags = CLK_SET_RATE_PARENT,
1518                         .ops = &clk_branch2_ops,
1519                 },
1520         },
1521 };
1522
1523 static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
1524         .halt_reg = 0x17620,
1525         .halt_check = BRANCH_HALT_VOTED,
1526         .clkr = {
1527                 .enable_reg = 0x52008,
1528                 .enable_mask = BIT(15),
1529                 .hw.init = &(struct clk_init_data){
1530                         .name = "gcc_qupv3_wrap0_s5_clk",
1531                         .parent_hws = (const struct clk_hw*[]){
1532                                 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
1533                         },
1534                         .num_parents = 1,
1535                         .flags = CLK_SET_RATE_PARENT,
1536                         .ops = &clk_branch2_ops,
1537                 },
1538         },
1539 };
1540
1541 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
1542         .halt_reg = 0x18004,
1543         .halt_check = BRANCH_HALT_VOTED,
1544         .clkr = {
1545                 .enable_reg = 0x52008,
1546                 .enable_mask = BIT(18),
1547                 .hw.init = &(struct clk_init_data){
1548                         .name = "gcc_qupv3_wrap1_core_2x_clk",
1549                         .ops = &clk_branch2_ops,
1550                 },
1551         },
1552 };
1553
1554 static struct clk_branch gcc_qupv3_wrap1_core_clk = {
1555         .halt_reg = 0x18008,
1556         .halt_check = BRANCH_HALT_VOTED,
1557         .clkr = {
1558                 .enable_reg = 0x52008,
1559                 .enable_mask = BIT(19),
1560                 .hw.init = &(struct clk_init_data){
1561                         .name = "gcc_qupv3_wrap1_core_clk",
1562                         .ops = &clk_branch2_ops,
1563                 },
1564         },
1565 };
1566
1567 static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
1568         .halt_reg = 0x18014,
1569         .halt_check = BRANCH_HALT_VOTED,
1570         .clkr = {
1571                 .enable_reg = 0x52008,
1572                 .enable_mask = BIT(22),
1573                 .hw.init = &(struct clk_init_data){
1574                         .name = "gcc_qupv3_wrap1_s0_clk",
1575                         .parent_hws = (const struct clk_hw*[]){
1576                                 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
1577                         },
1578                         .num_parents = 1,
1579                         .flags = CLK_SET_RATE_PARENT,
1580                         .ops = &clk_branch2_ops,
1581                 },
1582         },
1583 };
1584
1585 static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
1586         .halt_reg = 0x18144,
1587         .halt_check = BRANCH_HALT_VOTED,
1588         .clkr = {
1589                 .enable_reg = 0x52008,
1590                 .enable_mask = BIT(23),
1591                 .hw.init = &(struct clk_init_data){
1592                         .name = "gcc_qupv3_wrap1_s1_clk",
1593                         .parent_hws = (const struct clk_hw*[]){
1594                                 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
1595                         },
1596                         .num_parents = 1,
1597                         .flags = CLK_SET_RATE_PARENT,
1598                         .ops = &clk_branch2_ops,
1599                 },
1600         },
1601 };
1602
1603 static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
1604         .halt_reg = 0x18274,
1605         .halt_check = BRANCH_HALT_VOTED,
1606         .clkr = {
1607                 .enable_reg = 0x52008,
1608                 .enable_mask = BIT(24),
1609                 .hw.init = &(struct clk_init_data){
1610                         .name = "gcc_qupv3_wrap1_s2_clk",
1611                         .parent_hws = (const struct clk_hw*[]){
1612                                 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
1613                         },
1614                         .num_parents = 1,
1615                         .flags = CLK_SET_RATE_PARENT,
1616                         .ops = &clk_branch2_ops,
1617                 },
1618         },
1619 };
1620
1621 static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
1622         .halt_reg = 0x183a4,
1623         .halt_check = BRANCH_HALT_VOTED,
1624         .clkr = {
1625                 .enable_reg = 0x52008,
1626                 .enable_mask = BIT(25),
1627                 .hw.init = &(struct clk_init_data){
1628                         .name = "gcc_qupv3_wrap1_s3_clk",
1629                         .parent_hws = (const struct clk_hw*[]){
1630                                 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
1631                         },
1632                         .num_parents = 1,
1633                         .flags = CLK_SET_RATE_PARENT,
1634                         .ops = &clk_branch2_ops,
1635                 },
1636         },
1637 };
1638
1639 static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
1640         .halt_reg = 0x184d4,
1641         .halt_check = BRANCH_HALT_VOTED,
1642         .clkr = {
1643                 .enable_reg = 0x52008,
1644                 .enable_mask = BIT(26),
1645                 .hw.init = &(struct clk_init_data){
1646                         .name = "gcc_qupv3_wrap1_s4_clk",
1647                         .parent_hws = (const struct clk_hw*[]){
1648                                 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
1649                         },
1650                         .num_parents = 1,
1651                         .flags = CLK_SET_RATE_PARENT,
1652                         .ops = &clk_branch2_ops,
1653                 },
1654         },
1655 };
1656
1657 static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
1658         .halt_reg = 0x18604,
1659         .halt_check = BRANCH_HALT_VOTED,
1660         .clkr = {
1661                 .enable_reg = 0x52008,
1662                 .enable_mask = BIT(27),
1663                 .hw.init = &(struct clk_init_data){
1664                         .name = "gcc_qupv3_wrap1_s5_clk",
1665                         .parent_hws = (const struct clk_hw*[]){
1666                                 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
1667                         },
1668                         .num_parents = 1,
1669                         .flags = CLK_SET_RATE_PARENT,
1670                         .ops = &clk_branch2_ops,
1671                 },
1672         },
1673 };
1674
1675 static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
1676         .halt_reg = 0x17004,
1677         .halt_check = BRANCH_HALT_VOTED,
1678         .clkr = {
1679                 .enable_reg = 0x52008,
1680                 .enable_mask = BIT(6),
1681                 .hw.init = &(struct clk_init_data){
1682                         .name = "gcc_qupv3_wrap_0_m_ahb_clk",
1683                         .ops = &clk_branch2_ops,
1684                 },
1685         },
1686 };
1687
1688 static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
1689         .halt_reg = 0x17008,
1690         .halt_check = BRANCH_HALT_VOTED,
1691         .hwcg_reg = 0x17008,
1692         .hwcg_bit = 1,
1693         .clkr = {
1694                 .enable_reg = 0x52008,
1695                 .enable_mask = BIT(7),
1696                 .hw.init = &(struct clk_init_data){
1697                         .name = "gcc_qupv3_wrap_0_s_ahb_clk",
1698                         .ops = &clk_branch2_ops,
1699                 },
1700         },
1701 };
1702
1703 static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
1704         .halt_reg = 0x1800c,
1705         .halt_check = BRANCH_HALT_VOTED,
1706         .clkr = {
1707                 .enable_reg = 0x52008,
1708                 .enable_mask = BIT(20),
1709                 .hw.init = &(struct clk_init_data){
1710                         .name = "gcc_qupv3_wrap_1_m_ahb_clk",
1711                         .ops = &clk_branch2_ops,
1712                 },
1713         },
1714 };
1715
1716 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
1717         .halt_reg = 0x18010,
1718         .halt_check = BRANCH_HALT_VOTED,
1719         .hwcg_reg = 0x18010,
1720         .hwcg_bit = 1,
1721         .clkr = {
1722                 .enable_reg = 0x52008,
1723                 .enable_mask = BIT(21),
1724                 .hw.init = &(struct clk_init_data){
1725                         .name = "gcc_qupv3_wrap_1_s_ahb_clk",
1726                         .ops = &clk_branch2_ops,
1727                 },
1728         },
1729 };
1730
1731 static struct clk_branch gcc_sdcc1_ahb_clk = {
1732         .halt_reg = 0x12008,
1733         .halt_check = BRANCH_HALT,
1734         .clkr = {
1735                 .enable_reg = 0x12008,
1736                 .enable_mask = BIT(0),
1737                 .hw.init = &(struct clk_init_data){
1738                         .name = "gcc_sdcc1_ahb_clk",
1739                         .ops = &clk_branch2_ops,
1740                 },
1741         },
1742 };
1743
1744 static struct clk_branch gcc_sdcc1_apps_clk = {
1745         .halt_reg = 0x1200c,
1746         .halt_check = BRANCH_HALT,
1747         .clkr = {
1748                 .enable_reg = 0x1200c,
1749                 .enable_mask = BIT(0),
1750                 .hw.init = &(struct clk_init_data){
1751                         .name = "gcc_sdcc1_apps_clk",
1752                         .parent_hws = (const struct clk_hw*[]){
1753                                 &gcc_sdcc1_apps_clk_src.clkr.hw,
1754                         },
1755                         .num_parents = 1,
1756                         .flags = CLK_SET_RATE_PARENT,
1757                         .ops = &clk_branch2_ops,
1758                 },
1759         },
1760 };
1761
1762 static struct clk_branch gcc_sdcc1_ice_core_clk = {
1763         .halt_reg = 0x12040,
1764         .halt_check = BRANCH_HALT,
1765         .clkr = {
1766                 .enable_reg = 0x12040,
1767                 .enable_mask = BIT(0),
1768                 .hw.init = &(struct clk_init_data){
1769                         .name = "gcc_sdcc1_ice_core_clk",
1770                         .parent_hws = (const struct clk_hw*[]){
1771                                 &gcc_sdcc1_ice_core_clk_src.clkr.hw,
1772                         },
1773                         .num_parents = 1,
1774                         .flags = CLK_SET_RATE_PARENT,
1775                         .ops = &clk_branch2_ops,
1776                 },
1777         },
1778 };
1779
1780 static struct clk_branch gcc_sdcc2_ahb_clk = {
1781         .halt_reg = 0x14008,
1782         .halt_check = BRANCH_HALT,
1783         .clkr = {
1784                 .enable_reg = 0x14008,
1785                 .enable_mask = BIT(0),
1786                 .hw.init = &(struct clk_init_data){
1787                         .name = "gcc_sdcc2_ahb_clk",
1788                         .ops = &clk_branch2_ops,
1789                 },
1790         },
1791 };
1792
1793 static struct clk_branch gcc_sdcc2_apps_clk = {
1794         .halt_reg = 0x14004,
1795         .halt_check = BRANCH_HALT,
1796         .clkr = {
1797                 .enable_reg = 0x14004,
1798                 .enable_mask = BIT(0),
1799                 .hw.init = &(struct clk_init_data){
1800                         .name = "gcc_sdcc2_apps_clk",
1801                         .parent_hws = (const struct clk_hw*[]){
1802                                 &gcc_sdcc2_apps_clk_src.clkr.hw,
1803                         },
1804                         .num_parents = 1,
1805                         .flags = CLK_SET_RATE_PARENT,
1806                         .ops = &clk_branch2_ops,
1807                 },
1808         },
1809 };
1810
1811 /* For CPUSS functionality the SYS NOC clock needs to be left enabled */
1812 static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
1813         .halt_reg = 0x4144,
1814         .halt_check = BRANCH_HALT_VOTED,
1815         .clkr = {
1816                 .enable_reg = 0x52000,
1817                 .enable_mask = BIT(0),
1818                 .hw.init = &(struct clk_init_data){
1819                         .name = "gcc_sys_noc_cpuss_ahb_clk",
1820                         .parent_hws = (const struct clk_hw*[]){
1821                                 &gcc_cpuss_ahb_clk_src.clkr.hw,
1822                         },
1823                         .num_parents = 1,
1824                         .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1825                         .ops = &clk_branch2_ops,
1826                 },
1827         },
1828 };
1829
1830 static struct clk_branch gcc_ufs_mem_clkref_clk = {
1831         .halt_reg = 0x8c000,
1832         .halt_check = BRANCH_HALT,
1833         .clkr = {
1834                 .enable_reg = 0x8c000,
1835                 .enable_mask = BIT(0),
1836                 .hw.init = &(struct clk_init_data){
1837                         .name = "gcc_ufs_mem_clkref_clk",
1838                         .ops = &clk_branch2_ops,
1839                 },
1840         },
1841 };
1842
1843 static struct clk_branch gcc_ufs_phy_ahb_clk = {
1844         .halt_reg = 0x77014,
1845         .halt_check = BRANCH_HALT,
1846         .hwcg_reg = 0x77014,
1847         .hwcg_bit = 1,
1848         .clkr = {
1849                 .enable_reg = 0x77014,
1850                 .enable_mask = BIT(0),
1851                 .hw.init = &(struct clk_init_data){
1852                         .name = "gcc_ufs_phy_ahb_clk",
1853                         .ops = &clk_branch2_ops,
1854                 },
1855         },
1856 };
1857
1858 static struct clk_branch gcc_ufs_phy_axi_clk = {
1859         .halt_reg = 0x77038,
1860         .halt_check = BRANCH_HALT,
1861         .hwcg_reg = 0x77038,
1862         .hwcg_bit = 1,
1863         .clkr = {
1864                 .enable_reg = 0x77038,
1865                 .enable_mask = BIT(0),
1866                 .hw.init = &(struct clk_init_data){
1867                         .name = "gcc_ufs_phy_axi_clk",
1868                         .parent_hws = (const struct clk_hw*[]){
1869                                 &gcc_ufs_phy_axi_clk_src.clkr.hw,
1870                         },
1871                         .num_parents = 1,
1872                         .flags = CLK_SET_RATE_PARENT,
1873                         .ops = &clk_branch2_ops,
1874                 },
1875         },
1876 };
1877
1878 static struct clk_branch gcc_ufs_phy_ice_core_clk = {
1879         .halt_reg = 0x77090,
1880         .halt_check = BRANCH_HALT,
1881         .hwcg_reg = 0x77090,
1882         .hwcg_bit = 1,
1883         .clkr = {
1884                 .enable_reg = 0x77090,
1885                 .enable_mask = BIT(0),
1886                 .hw.init = &(struct clk_init_data){
1887                         .name = "gcc_ufs_phy_ice_core_clk",
1888                         .parent_hws = (const struct clk_hw*[]){
1889                                 &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
1890                         },
1891                         .num_parents = 1,
1892                         .flags = CLK_SET_RATE_PARENT,
1893                         .ops = &clk_branch2_ops,
1894                 },
1895         },
1896 };
1897
1898 static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
1899         .halt_reg = 0x77094,
1900         .halt_check = BRANCH_HALT,
1901         .hwcg_reg = 0x77094,
1902         .hwcg_bit = 1,
1903         .clkr = {
1904                 .enable_reg = 0x77094,
1905                 .enable_mask = BIT(0),
1906                 .hw.init = &(struct clk_init_data){
1907                         .name = "gcc_ufs_phy_phy_aux_clk",
1908                         .parent_hws = (const struct clk_hw*[]){
1909                                 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
1910                         },
1911                         .num_parents = 1,
1912                         .flags = CLK_SET_RATE_PARENT,
1913                         .ops = &clk_branch2_ops,
1914                 },
1915         },
1916 };
1917
1918 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
1919         .halt_reg = 0x7701c,
1920         .halt_check = BRANCH_HALT_SKIP,
1921         .clkr = {
1922                 .enable_reg = 0x7701c,
1923                 .enable_mask = BIT(0),
1924                 .hw.init = &(struct clk_init_data){
1925                         .name = "gcc_ufs_phy_rx_symbol_0_clk",
1926                         .ops = &clk_branch2_ops,
1927                 },
1928         },
1929 };
1930
1931 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
1932         .halt_reg = 0x77018,
1933         .halt_check = BRANCH_HALT_SKIP,
1934         .clkr = {
1935                 .enable_reg = 0x77018,
1936                 .enable_mask = BIT(0),
1937                 .hw.init = &(struct clk_init_data){
1938                         .name = "gcc_ufs_phy_tx_symbol_0_clk",
1939                         .ops = &clk_branch2_ops,
1940                 },
1941         },
1942 };
1943
1944 static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
1945         .halt_reg = 0x7708c,
1946         .halt_check = BRANCH_HALT,
1947         .hwcg_reg = 0x7708c,
1948         .hwcg_bit = 1,
1949         .clkr = {
1950                 .enable_reg = 0x7708c,
1951                 .enable_mask = BIT(0),
1952                 .hw.init = &(struct clk_init_data){
1953                         .name = "gcc_ufs_phy_unipro_core_clk",
1954                         .parent_hws = (const struct clk_hw*[]){
1955                                 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
1956                         },
1957                         .num_parents = 1,
1958                         .flags = CLK_SET_RATE_PARENT,
1959                         .ops = &clk_branch2_ops,
1960                 },
1961         },
1962 };
1963
1964 static struct clk_branch gcc_usb30_prim_master_clk = {
1965         .halt_reg = 0xf010,
1966         .halt_check = BRANCH_HALT,
1967         .clkr = {
1968                 .enable_reg = 0xf010,
1969                 .enable_mask = BIT(0),
1970                 .hw.init = &(struct clk_init_data){
1971                         .name = "gcc_usb30_prim_master_clk",
1972                         .parent_hws = (const struct clk_hw*[]){
1973                                 &gcc_usb30_prim_master_clk_src.clkr.hw,
1974                         },
1975                         .num_parents = 1,
1976                         .flags = CLK_SET_RATE_PARENT,
1977                         .ops = &clk_branch2_ops,
1978                 },
1979         },
1980 };
1981
1982 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
1983         .halt_reg = 0xf018,
1984         .halt_check = BRANCH_HALT,
1985         .clkr = {
1986                 .enable_reg = 0xf018,
1987                 .enable_mask = BIT(0),
1988                 .hw.init = &(struct clk_init_data){
1989                         .name = "gcc_usb30_prim_mock_utmi_clk",
1990                         .parent_data = &(const struct clk_parent_data){
1991                                 .hw =
1992                                 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1993                         },
1994                         .num_parents = 1,
1995                         .flags = CLK_SET_RATE_PARENT,
1996                         .ops = &clk_branch2_ops,
1997                 },
1998         },
1999 };
2000
2001 static struct clk_branch gcc_usb30_prim_sleep_clk = {
2002         .halt_reg = 0xf014,
2003         .halt_check = BRANCH_HALT,
2004         .clkr = {
2005                 .enable_reg = 0xf014,
2006                 .enable_mask = BIT(0),
2007                 .hw.init = &(struct clk_init_data){
2008                         .name = "gcc_usb30_prim_sleep_clk",
2009                         .ops = &clk_branch2_ops,
2010                 },
2011         },
2012 };
2013
2014 static struct clk_branch gcc_usb3_prim_clkref_clk = {
2015         .halt_reg = 0x8c010,
2016         .halt_check = BRANCH_HALT,
2017         .clkr = {
2018                 .enable_reg = 0x8c010,
2019                 .enable_mask = BIT(0),
2020                 .hw.init = &(struct clk_init_data){
2021                         .name = "gcc_usb3_prim_clkref_clk",
2022                         .ops = &clk_branch2_ops,
2023                 },
2024         },
2025 };
2026
2027 static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
2028         .halt_reg = 0xf050,
2029         .halt_check = BRANCH_HALT,
2030         .clkr = {
2031                 .enable_reg = 0xf050,
2032                 .enable_mask = BIT(0),
2033                 .hw.init = &(struct clk_init_data){
2034                         .name = "gcc_usb3_prim_phy_aux_clk",
2035                         .parent_hws = (const struct clk_hw*[]){
2036                                 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2037                         },
2038                         .num_parents = 1,
2039                         .flags = CLK_SET_RATE_PARENT,
2040                         .ops = &clk_branch2_ops,
2041                 },
2042         },
2043 };
2044
2045 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
2046         .halt_reg = 0xf054,
2047         .halt_check = BRANCH_HALT,
2048         .clkr = {
2049                 .enable_reg = 0xf054,
2050                 .enable_mask = BIT(0),
2051                 .hw.init = &(struct clk_init_data){
2052                         .name = "gcc_usb3_prim_phy_com_aux_clk",
2053                         .parent_hws = (const struct clk_hw*[]){
2054                                 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
2055                         },
2056                         .num_parents = 1,
2057                         .flags = CLK_SET_RATE_PARENT,
2058                         .ops = &clk_branch2_ops,
2059                 },
2060         },
2061 };
2062
2063 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
2064         .halt_reg = 0xf058,
2065         .halt_check = BRANCH_HALT_SKIP,
2066         .clkr = {
2067                 .enable_reg = 0xf058,
2068                 .enable_mask = BIT(0),
2069                 .hw.init = &(struct clk_init_data){
2070                         .name = "gcc_usb3_prim_phy_pipe_clk",
2071                         .ops = &clk_branch2_ops,
2072                 },
2073         },
2074 };
2075
2076 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2077         .halt_reg = 0x6a004,
2078         .halt_check = BRANCH_HALT,
2079         .hwcg_reg = 0x6a004,
2080         .hwcg_bit = 1,
2081         .clkr = {
2082                 .enable_reg = 0x6a004,
2083                 .enable_mask = BIT(0),
2084                 .hw.init = &(struct clk_init_data){
2085                         .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2086                         .ops = &clk_branch2_ops,
2087                 },
2088         },
2089 };
2090
2091 static struct clk_branch gcc_video_axi_clk = {
2092         .halt_reg = 0xb01c,
2093         .halt_check = BRANCH_HALT,
2094         .clkr = {
2095                 .enable_reg = 0xb01c,
2096                 .enable_mask = BIT(0),
2097                 .hw.init = &(struct clk_init_data){
2098                         .name = "gcc_video_axi_clk",
2099                         .ops = &clk_branch2_ops,
2100                 },
2101         },
2102 };
2103
2104 static struct clk_branch gcc_video_gpll0_div_clk_src = {
2105         .halt_check = BRANCH_HALT_DELAY,
2106         .clkr = {
2107                 .enable_reg = 0x52000,
2108                 .enable_mask = BIT(20),
2109                 .hw.init = &(struct clk_init_data){
2110                         .name = "gcc_video_gpll0_div_clk_src",
2111                         .parent_hws = (const struct clk_hw*[]){
2112                                 &gcc_pll0_main_div_cdiv.hw,
2113                         },
2114                         .num_parents = 1,
2115                         .flags = CLK_SET_RATE_PARENT,
2116                         .ops = &clk_branch2_ops,
2117                 },
2118         },
2119 };
2120
2121 static struct clk_branch gcc_video_throttle_axi_clk = {
2122         .halt_reg = 0xb07c,
2123         .halt_check = BRANCH_HALT,
2124         .hwcg_reg = 0xb07c,
2125         .hwcg_bit = 1,
2126         .clkr = {
2127                 .enable_reg = 0xb07c,
2128                 .enable_mask = BIT(0),
2129                 .hw.init = &(struct clk_init_data){
2130                         .name = "gcc_video_throttle_axi_clk",
2131                         .ops = &clk_branch2_ops,
2132                 },
2133         },
2134 };
2135
2136 static struct clk_branch gcc_mss_cfg_ahb_clk = {
2137         .halt_reg = 0x8a000,
2138         .halt_check = BRANCH_HALT,
2139         .clkr = {
2140                 .enable_reg = 0x8a000,
2141                 .enable_mask = BIT(0),
2142                 .hw.init = &(struct clk_init_data){
2143                         .name = "gcc_mss_cfg_ahb_clk",
2144                         .ops = &clk_branch2_ops,
2145                 },
2146         },
2147 };
2148
2149 static struct clk_branch gcc_mss_mfab_axis_clk = {
2150         .halt_reg = 0x8a004,
2151         .halt_check = BRANCH_HALT_VOTED,
2152         .clkr = {
2153                 .enable_reg = 0x8a004,
2154                 .enable_mask = BIT(0),
2155                 .hw.init = &(struct clk_init_data){
2156                         .name = "gcc_mss_mfab_axis_clk",
2157                         .ops = &clk_branch2_ops,
2158                 },
2159         },
2160 };
2161
2162 static struct clk_branch gcc_mss_nav_axi_clk = {
2163         .halt_reg = 0x8a00c,
2164         .halt_check = BRANCH_HALT_VOTED,
2165         .clkr = {
2166                 .enable_reg = 0x8a00c,
2167                 .enable_mask = BIT(0),
2168                 .hw.init = &(struct clk_init_data){
2169                         .name = "gcc_mss_nav_axi_clk",
2170                         .ops = &clk_branch2_ops,
2171                 },
2172         },
2173 };
2174
2175 static struct clk_branch gcc_mss_snoc_axi_clk = {
2176         .halt_reg = 0x8a150,
2177         .halt_check = BRANCH_HALT,
2178         .clkr = {
2179                 .enable_reg = 0x8a150,
2180                 .enable_mask = BIT(0),
2181                 .hw.init = &(struct clk_init_data){
2182                         .name = "gcc_mss_snoc_axi_clk",
2183                         .ops = &clk_branch2_ops,
2184                 },
2185         },
2186 };
2187
2188 static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
2189         .halt_reg = 0x8a154,
2190         .halt_check = BRANCH_HALT,
2191         .clkr = {
2192                 .enable_reg = 0x8a154,
2193                 .enable_mask = BIT(0),
2194                 .hw.init = &(struct clk_init_data){
2195                         .name = "gcc_mss_q6_memnoc_axi_clk",
2196                         .ops = &clk_branch2_ops,
2197                 },
2198         },
2199 };
2200
2201 static struct clk_branch gcc_lpass_cfg_noc_sway_clk = {
2202         .halt_reg = 0x47018,
2203         .halt_check = BRANCH_HALT_DELAY,
2204         .clkr = {
2205                 .enable_reg = 0x47018,
2206                 .enable_mask = BIT(0),
2207                 .hw.init = &(struct clk_init_data){
2208                         .name = "gcc_lpass_cfg_noc_sway_clk",
2209                         .ops = &clk_branch2_ops,
2210                 },
2211         },
2212 };
2213
2214 static struct gdsc ufs_phy_gdsc = {
2215         .gdscr = 0x77004,
2216         .pd = {
2217                 .name = "ufs_phy_gdsc",
2218         },
2219         .pwrsts = PWRSTS_OFF_ON,
2220 };
2221
2222 static struct gdsc usb30_prim_gdsc = {
2223         .gdscr = 0x0f004,
2224         .pd = {
2225                 .name = "usb30_prim_gdsc",
2226         },
2227         .pwrsts = PWRSTS_OFF_ON,
2228 };
2229
2230 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
2231         .gdscr = 0x7d040,
2232         .pd = {
2233                 .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
2234         },
2235         .pwrsts = PWRSTS_OFF_ON,
2236         .flags = VOTABLE,
2237 };
2238
2239 static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf_gdsc = {
2240         .gdscr = 0x7d044,
2241         .pd = {
2242                 .name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc",
2243         },
2244         .pwrsts = PWRSTS_OFF_ON,
2245         .flags = VOTABLE,
2246 };
2247
2248 static struct gdsc *gcc_sc7180_gdscs[] = {
2249         [UFS_PHY_GDSC] = &ufs_phy_gdsc,
2250         [USB30_PRIM_GDSC] = &usb30_prim_gdsc,
2251         [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] =
2252                                         &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
2253         [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] =
2254                                         &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc,
2255 };
2256
2257
2258 static struct clk_hw *gcc_sc7180_hws[] = {
2259         [GCC_GPLL0_MAIN_DIV_CDIV] = &gcc_pll0_main_div_cdiv.hw,
2260 };
2261
2262 static struct clk_regmap *gcc_sc7180_clocks[] = {
2263         [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
2264         [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
2265         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2266         [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
2267         [GCC_CAMERA_THROTTLE_HF_AXI_CLK] = &gcc_camera_throttle_hf_axi_clk.clkr,
2268         [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
2269         [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
2270         [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
2271         [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
2272         [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
2273         [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
2274         [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
2275         [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
2276         [GCC_DISP_GPLL0_CLK_SRC] = &gcc_disp_gpll0_clk_src.clkr,
2277         [GCC_DISP_GPLL0_DIV_CLK_SRC] = &gcc_disp_gpll0_div_clk_src.clkr,
2278         [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
2279         [GCC_DISP_THROTTLE_HF_AXI_CLK] = &gcc_disp_throttle_hf_axi_clk.clkr,
2280         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2281         [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
2282         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2283         [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
2284         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2285         [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
2286         [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
2287         [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
2288         [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
2289         [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2290         [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
2291         [GCC_NPU_BWMON_AXI_CLK] = &gcc_npu_bwmon_axi_clk.clkr,
2292         [GCC_NPU_BWMON_DMA_CFG_AHB_CLK] = &gcc_npu_bwmon_dma_cfg_ahb_clk.clkr,
2293         [GCC_NPU_BWMON_DSP_CFG_AHB_CLK] = &gcc_npu_bwmon_dsp_cfg_ahb_clk.clkr,
2294         [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
2295         [GCC_NPU_DMA_CLK] = &gcc_npu_dma_clk.clkr,
2296         [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
2297         [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
2298         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2299         [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
2300         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2301         [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2302         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2303         [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
2304         [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
2305         [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
2306         [GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
2307         [GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
2308         [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
2309         [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
2310         [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
2311         [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
2312         [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
2313         [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
2314         [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
2315         [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
2316         [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
2317         [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
2318         [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
2319         [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
2320         [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
2321         [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
2322         [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
2323         [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
2324         [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
2325         [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
2326         [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
2327         [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
2328         [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
2329         [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
2330         [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
2331         [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
2332         [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
2333         [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
2334         [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
2335         [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
2336         [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
2337         [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
2338         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2339         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2340         [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
2341         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2342         [GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
2343         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2344         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2345         [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
2346         [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
2347         [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
2348         [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
2349         [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
2350         [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
2351         [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
2352         [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
2353         [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
2354         [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
2355         [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
2356         [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
2357         [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
2358         [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
2359                 &gcc_ufs_phy_unipro_core_clk_src.clkr,
2360         [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
2361         [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
2362         [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
2363         [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
2364                 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
2365         [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
2366         [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
2367         [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
2368         [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
2369         [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
2370         [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
2371         [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2372         [GCC_VIDEO_AXI_CLK] = &gcc_video_axi_clk.clkr,
2373         [GCC_VIDEO_GPLL0_DIV_CLK_SRC] = &gcc_video_gpll0_div_clk_src.clkr,
2374         [GCC_VIDEO_THROTTLE_AXI_CLK] = &gcc_video_throttle_axi_clk.clkr,
2375         [GPLL0] = &gpll0.clkr,
2376         [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
2377         [GPLL6] = &gpll6.clkr,
2378         [GPLL7] = &gpll7.clkr,
2379         [GPLL4] = &gpll4.clkr,
2380         [GPLL1] = &gpll1.clkr,
2381         [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2382         [GCC_MSS_MFAB_AXIS_CLK] = &gcc_mss_mfab_axis_clk.clkr,
2383         [GCC_MSS_NAV_AXI_CLK] = &gcc_mss_nav_axi_clk.clkr,
2384         [GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
2385         [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
2386         [GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr,
2387         [GCC_LPASS_CFG_NOC_SWAY_CLK] = &gcc_lpass_cfg_noc_sway_clk.clkr,
2388 };
2389
2390 static const struct qcom_reset_map gcc_sc7180_resets[] = {
2391         [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 },
2392         [GCC_QUSB2PHY_SEC_BCR] = { 0x26004 },
2393         [GCC_UFS_PHY_BCR] = { 0x77000 },
2394         [GCC_USB30_PRIM_BCR] = { 0xf000 },
2395         [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
2396         [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
2397         [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
2398         [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
2399         [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
2400         [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
2401         [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
2402 };
2403
2404 static struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
2405         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
2406         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
2407         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
2408         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
2409         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
2410         DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
2411         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
2412         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
2413         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
2414         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
2415         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
2416         DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
2417 };
2418
2419 static const struct regmap_config gcc_sc7180_regmap_config = {
2420         .reg_bits = 32,
2421         .reg_stride = 4,
2422         .val_bits = 32,
2423         .max_register = 0x18208c,
2424         .fast_io = true,
2425 };
2426
2427 static const struct qcom_cc_desc gcc_sc7180_desc = {
2428         .config = &gcc_sc7180_regmap_config,
2429         .clk_hws = gcc_sc7180_hws,
2430         .num_clk_hws = ARRAY_SIZE(gcc_sc7180_hws),
2431         .clks = gcc_sc7180_clocks,
2432         .num_clks = ARRAY_SIZE(gcc_sc7180_clocks),
2433         .resets = gcc_sc7180_resets,
2434         .num_resets = ARRAY_SIZE(gcc_sc7180_resets),
2435         .gdscs = gcc_sc7180_gdscs,
2436         .num_gdscs = ARRAY_SIZE(gcc_sc7180_gdscs),
2437 };
2438
2439 static const struct of_device_id gcc_sc7180_match_table[] = {
2440         { .compatible = "qcom,gcc-sc7180" },
2441         { }
2442 };
2443 MODULE_DEVICE_TABLE(of, gcc_sc7180_match_table);
2444
2445 static int gcc_sc7180_probe(struct platform_device *pdev)
2446 {
2447         struct regmap *regmap;
2448         int ret;
2449
2450         regmap = qcom_cc_map(pdev, &gcc_sc7180_desc);
2451         if (IS_ERR(regmap))
2452                 return PTR_ERR(regmap);
2453
2454         /*
2455          * Disable the GPLL0 active input to MM blocks, NPU
2456          * and GPU via MISC registers.
2457          */
2458         regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
2459         regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
2460         regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
2461
2462         /*
2463          * Keep the clocks always-ON
2464          * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK,
2465          * GCC_DISP_AHB_CLK, GCC_GPU_CFG_AHB_CLK
2466          */
2467         regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0));
2468         regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0));
2469         regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0));
2470         regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0));
2471         regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0));
2472         regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0));
2473         regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0));
2474         regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
2475
2476         ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
2477                                         ARRAY_SIZE(gcc_dfs_clocks));
2478         if (ret)
2479                 return ret;
2480
2481         return qcom_cc_really_probe(pdev, &gcc_sc7180_desc, regmap);
2482 }
2483
2484 static struct platform_driver gcc_sc7180_driver = {
2485         .probe = gcc_sc7180_probe,
2486         .driver = {
2487                 .name = "gcc-sc7180",
2488                 .of_match_table = gcc_sc7180_match_table,
2489         },
2490 };
2491
2492 static int __init gcc_sc7180_init(void)
2493 {
2494         return platform_driver_register(&gcc_sc7180_driver);
2495 }
2496 core_initcall(gcc_sc7180_init);
2497
2498 static void __exit gcc_sc7180_exit(void)
2499 {
2500         platform_driver_unregister(&gcc_sc7180_driver);
2501 }
2502 module_exit(gcc_sc7180_exit);
2503
2504 MODULE_DESCRIPTION("QTI GCC SC7180 Driver");
2505 MODULE_LICENSE("GPL v2");