drivers/clk/qcom/gcc-msm8998.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2016, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset-controller.h>
  16
  17 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
  18
  19 #include "common.h"
  20 #include "clk-regmap.h"
  21 #include "clk-alpha-pll.h"
  22 #include "clk-pll.h"
  23 #include "clk-rcg.h"
  24 #include "clk-branch.h"
  25 #include "reset.h"
  26 #include "gdsc.h"
  27
  28 enum {
  29         P_AUD_REF_CLK,
  30         P_CORE_BI_PLL_TEST_SE,
  31         P_GPLL0_OUT_MAIN,
  32         P_GPLL4_OUT_MAIN,
  33         P_PLL0_EARLY_DIV_CLK_SRC,
  34         P_SLEEP_CLK,
  35         P_XO,
  36 };
  37
  38 static const struct parent_map gcc_parent_map_0[] = {
  39         { P_XO, 0 },
  40         { P_GPLL0_OUT_MAIN, 1 },
  41         { P_PLL0_EARLY_DIV_CLK_SRC, 6 },
  42         { P_CORE_BI_PLL_TEST_SE, 7 },
  43 };
  44
  45 static const char * const gcc_parent_names_0[] = {
  46         "xo",
  47         "gpll0_out_main",
  48         "gpll0_out_main",
  49         "core_bi_pll_test_se",
  50 };
  51
  52 static const struct parent_map gcc_parent_map_1[] = {
  53         { P_XO, 0 },
  54         { P_GPLL0_OUT_MAIN, 1 },
  55         { P_CORE_BI_PLL_TEST_SE, 7 },
  56 };
  57
  58 static const char * const gcc_parent_names_1[] = {
  59         "xo",
  60         "gpll0_out_main",
  61         "core_bi_pll_test_se",
  62 };
  63
  64 static const struct parent_map gcc_parent_map_2[] = {
  65         { P_XO, 0 },
  66         { P_GPLL0_OUT_MAIN, 1 },
  67         { P_SLEEP_CLK, 5 },
  68         { P_PLL0_EARLY_DIV_CLK_SRC, 6 },
  69         { P_CORE_BI_PLL_TEST_SE, 7 },
  70 };
  71
  72 static const char * const gcc_parent_names_2[] = {
  73         "xo",
  74         "gpll0_out_main",
  75         "core_pi_sleep_clk",
  76         "gpll0_out_main",
  77         "core_bi_pll_test_se",
  78 };
  79
  80 static const struct parent_map gcc_parent_map_3[] = {
  81         { P_XO, 0 },
  82         { P_SLEEP_CLK, 5 },
  83         { P_CORE_BI_PLL_TEST_SE, 7 },
  84 };
  85
  86 static const char * const gcc_parent_names_3[] = {
  87         "xo",
  88         "core_pi_sleep_clk",
  89         "core_bi_pll_test_se",
  90 };
  91
  92 static const struct parent_map gcc_parent_map_4[] = {
  93         { P_XO, 0 },
  94         { P_GPLL0_OUT_MAIN, 1 },
  95         { P_GPLL4_OUT_MAIN, 5 },
  96         { P_CORE_BI_PLL_TEST_SE, 7 },
  97 };
  98
  99 static const char * const gcc_parent_names_4[] = {
 100         "xo",
 101         "gpll0_out_main",
 102         "gpll4_out_main",
 103         "core_bi_pll_test_se",
 104 };
 105
 106 static const struct parent_map gcc_parent_map_5[] = {
 107         { P_XO, 0 },
 108         { P_GPLL0_OUT_MAIN, 1 },
 109         { P_AUD_REF_CLK, 2 },
 110         { P_CORE_BI_PLL_TEST_SE, 7 },
 111 };
 112
 113 static const char * const gcc_parent_names_5[] = {
 114         "xo",
 115         "gpll0_out_main",
 116         "aud_ref_clk",
 117         "core_bi_pll_test_se",
 118 };
 119
 120 static struct clk_fixed_factor xo = {
 121         .mult = 1,
 122         .div = 1,
 123         .hw.init = &(struct clk_init_data){
 124                 .name = "xo",
 125                 .parent_names = (const char *[]){ "xo_board" },
 126                 .num_parents = 1,
 127                 .ops = &clk_fixed_factor_ops,
 128         },
 129 };
 130
 131 static struct pll_vco fabia_vco[] = {
 132         { 250000000, 2000000000, 0 },
 133         { 125000000, 1000000000, 1 },
 134 };
 135
 136 static struct clk_alpha_pll gpll0 = {
 137         .offset = 0x0,
 138         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 139         .vco_table = fabia_vco,
 140         .num_vco = ARRAY_SIZE(fabia_vco),
 141         .clkr = {
 142                 .enable_reg = 0x52000,
 143                 .enable_mask = BIT(0),
 144                 .hw.init = &(struct clk_init_data){
 145                         .name = "gpll0",
 146                         .parent_names = (const char *[]){ "xo" },
 147                         .num_parents = 1,
 148                         .ops = &clk_alpha_pll_ops,
 149                 }
 150         },
 151 };
 152
 153 static struct clk_alpha_pll_postdiv gpll0_out_even = {
 154         .offset = 0x0,
 155         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 156         .clkr.hw.init = &(struct clk_init_data){
 157                 .name = "gpll0_out_even",
 158                 .parent_names = (const char *[]){ "gpll0" },
 159                 .num_parents = 1,
 160                 .ops = &clk_alpha_pll_postdiv_ops,
 161         },
 162 };
 163
 164 static struct clk_alpha_pll_postdiv gpll0_out_main = {
 165         .offset = 0x0,
 166         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 167         .clkr.hw.init = &(struct clk_init_data){
 168                 .name = "gpll0_out_main",
 169                 .parent_names = (const char *[]){ "gpll0" },
 170                 .num_parents = 1,
 171                 .ops = &clk_alpha_pll_postdiv_ops,
 172         },
 173 };
 174
 175 static struct clk_alpha_pll_postdiv gpll0_out_odd = {
 176         .offset = 0x0,
 177         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 178         .clkr.hw.init = &(struct clk_init_data){
 179                 .name = "gpll0_out_odd",
 180                 .parent_names = (const char *[]){ "gpll0" },
 181                 .num_parents = 1,
 182                 .ops = &clk_alpha_pll_postdiv_ops,
 183         },
 184 };
 185
 186 static struct clk_alpha_pll_postdiv gpll0_out_test = {
 187         .offset = 0x0,
 188         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 189         .clkr.hw.init = &(struct clk_init_data){
 190                 .name = "gpll0_out_test",
 191                 .parent_names = (const char *[]){ "gpll0" },
 192                 .num_parents = 1,
 193                 .ops = &clk_alpha_pll_postdiv_ops,
 194         },
 195 };
 196
 197 static struct clk_alpha_pll gpll1 = {
 198         .offset = 0x1000,
 199         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 200         .vco_table = fabia_vco,
 201         .num_vco = ARRAY_SIZE(fabia_vco),
 202         .clkr = {
 203                 .enable_reg = 0x52000,
 204                 .enable_mask = BIT(1),
 205                 .hw.init = &(struct clk_init_data){
 206                         .name = "gpll1",
 207                         .parent_names = (const char *[]){ "xo" },
 208                         .num_parents = 1,
 209                         .ops = &clk_alpha_pll_ops,
 210                 }
 211         },
 212 };
 213
 214 static struct clk_alpha_pll_postdiv gpll1_out_even = {
 215         .offset = 0x1000,
 216         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 217         .clkr.hw.init = &(struct clk_init_data){
 218                 .name = "gpll1_out_even",
 219                 .parent_names = (const char *[]){ "gpll1" },
 220                 .num_parents = 1,
 221                 .ops = &clk_alpha_pll_postdiv_ops,
 222         },
 223 };
 224
 225 static struct clk_alpha_pll_postdiv gpll1_out_main = {
 226         .offset = 0x1000,
 227         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 228         .clkr.hw.init = &(struct clk_init_data){
 229                 .name = "gpll1_out_main",
 230                 .parent_names = (const char *[]){ "gpll1" },
 231                 .num_parents = 1,
 232                 .ops = &clk_alpha_pll_postdiv_ops,
 233         },
 234 };
 235
 236 static struct clk_alpha_pll_postdiv gpll1_out_odd = {
 237         .offset = 0x1000,
 238         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 239         .clkr.hw.init = &(struct clk_init_data){
 240                 .name = "gpll1_out_odd",
 241                 .parent_names = (const char *[]){ "gpll1" },
 242                 .num_parents = 1,
 243                 .ops = &clk_alpha_pll_postdiv_ops,
 244         },
 245 };
 246
 247 static struct clk_alpha_pll_postdiv gpll1_out_test = {
 248         .offset = 0x1000,
 249         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 250         .clkr.hw.init = &(struct clk_init_data){
 251                 .name = "gpll1_out_test",
 252                 .parent_names = (const char *[]){ "gpll1" },
 253                 .num_parents = 1,
 254                 .ops = &clk_alpha_pll_postdiv_ops,
 255         },
 256 };
 257
 258 static struct clk_alpha_pll gpll2 = {
 259         .offset = 0x2000,
 260         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 261         .vco_table = fabia_vco,
 262         .num_vco = ARRAY_SIZE(fabia_vco),
 263         .clkr = {
 264                 .enable_reg = 0x52000,
 265                 .enable_mask = BIT(2),
 266                 .hw.init = &(struct clk_init_data){
 267                         .name = "gpll2",
 268                         .parent_names = (const char *[]){ "xo" },
 269                         .num_parents = 1,
 270                         .ops = &clk_alpha_pll_ops,
 271                 }
 272         },
 273 };
 274
 275 static struct clk_alpha_pll_postdiv gpll2_out_even = {
 276         .offset = 0x2000,
 277         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 278         .clkr.hw.init = &(struct clk_init_data){
 279                 .name = "gpll2_out_even",
 280                 .parent_names = (const char *[]){ "gpll2" },
 281                 .num_parents = 1,
 282                 .ops = &clk_alpha_pll_postdiv_ops,
 283         },
 284 };
 285
 286 static struct clk_alpha_pll_postdiv gpll2_out_main = {
 287         .offset = 0x2000,
 288         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 289         .clkr.hw.init = &(struct clk_init_data){
 290                 .name = "gpll2_out_main",
 291                 .parent_names = (const char *[]){ "gpll2" },
 292                 .num_parents = 1,
 293                 .ops = &clk_alpha_pll_postdiv_ops,
 294         },
 295 };
 296
 297 static struct clk_alpha_pll_postdiv gpll2_out_odd = {
 298         .offset = 0x2000,
 299         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 300         .clkr.hw.init = &(struct clk_init_data){
 301                 .name = "gpll2_out_odd",
 302                 .parent_names = (const char *[]){ "gpll2" },
 303                 .num_parents = 1,
 304                 .ops = &clk_alpha_pll_postdiv_ops,
 305         },
 306 };
 307
 308 static struct clk_alpha_pll_postdiv gpll2_out_test = {
 309         .offset = 0x2000,
 310         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 311         .clkr.hw.init = &(struct clk_init_data){
 312                 .name = "gpll2_out_test",
 313                 .parent_names = (const char *[]){ "gpll2" },
 314                 .num_parents = 1,
 315                 .ops = &clk_alpha_pll_postdiv_ops,
 316         },
 317 };
 318
 319 static struct clk_alpha_pll gpll3 = {
 320         .offset = 0x3000,
 321         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 322         .vco_table = fabia_vco,
 323         .num_vco = ARRAY_SIZE(fabia_vco),
 324         .clkr = {
 325                 .enable_reg = 0x52000,
 326                 .enable_mask = BIT(3),
 327                 .hw.init = &(struct clk_init_data){
 328                         .name = "gpll3",
 329                         .parent_names = (const char *[]){ "xo" },
 330                         .num_parents = 1,
 331                         .ops = &clk_alpha_pll_ops,
 332                 }
 333         },
 334 };
 335
 336 static struct clk_alpha_pll_postdiv gpll3_out_even = {
 337         .offset = 0x3000,
 338         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 339         .clkr.hw.init = &(struct clk_init_data){
 340                 .name = "gpll3_out_even",
 341                 .parent_names = (const char *[]){ "gpll3" },
 342                 .num_parents = 1,
 343                 .ops = &clk_alpha_pll_postdiv_ops,
 344         },
 345 };
 346
 347 static struct clk_alpha_pll_postdiv gpll3_out_main = {
 348         .offset = 0x3000,
 349         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 350         .clkr.hw.init = &(struct clk_init_data){
 351                 .name = "gpll3_out_main",
 352                 .parent_names = (const char *[]){ "gpll3" },
 353                 .num_parents = 1,
 354                 .ops = &clk_alpha_pll_postdiv_ops,
 355         },
 356 };
 357
 358 static struct clk_alpha_pll_postdiv gpll3_out_odd = {
 359         .offset = 0x3000,
 360         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 361         .clkr.hw.init = &(struct clk_init_data){
 362                 .name = "gpll3_out_odd",
 363                 .parent_names = (const char *[]){ "gpll3" },
 364                 .num_parents = 1,
 365                 .ops = &clk_alpha_pll_postdiv_ops,
 366         },
 367 };
 368
 369 static struct clk_alpha_pll_postdiv gpll3_out_test = {
 370         .offset = 0x3000,
 371         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 372         .clkr.hw.init = &(struct clk_init_data){
 373                 .name = "gpll3_out_test",
 374                 .parent_names = (const char *[]){ "gpll3" },
 375                 .num_parents = 1,
 376                 .ops = &clk_alpha_pll_postdiv_ops,
 377         },
 378 };
 379
 380 static struct clk_alpha_pll gpll4 = {
 381         .offset = 0x77000,
 382         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 383         .vco_table = fabia_vco,
 384         .num_vco = ARRAY_SIZE(fabia_vco),
 385         .clkr = {
 386                 .enable_reg = 0x52000,
 387                 .enable_mask = BIT(4),
 388                 .hw.init = &(struct clk_init_data){
 389                         .name = "gpll4",
 390                         .parent_names = (const char *[]){ "xo" },
 391                         .num_parents = 1,
 392                         .ops = &clk_alpha_pll_ops,
 393                 }
 394         },
 395 };
 396
 397 static struct clk_alpha_pll_postdiv gpll4_out_even = {
 398         .offset = 0x77000,
 399         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 400         .clkr.hw.init = &(struct clk_init_data){
 401                 .name = "gpll4_out_even",
 402                 .parent_names = (const char *[]){ "gpll4" },
 403                 .num_parents = 1,
 404                 .ops = &clk_alpha_pll_postdiv_ops,
 405         },
 406 };
 407
 408 static struct clk_alpha_pll_postdiv gpll4_out_main = {
 409         .offset = 0x77000,
 410         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 411         .clkr.hw.init = &(struct clk_init_data){
 412                 .name = "gpll4_out_main",
 413                 .parent_names = (const char *[]){ "gpll4" },
 414                 .num_parents = 1,
 415                 .ops = &clk_alpha_pll_postdiv_ops,
 416         },
 417 };
 418
 419 static struct clk_alpha_pll_postdiv gpll4_out_odd = {
 420         .offset = 0x77000,
 421         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 422         .clkr.hw.init = &(struct clk_init_data){
 423                 .name = "gpll4_out_odd",
 424                 .parent_names = (const char *[]){ "gpll4" },
 425                 .num_parents = 1,
 426                 .ops = &clk_alpha_pll_postdiv_ops,
 427         },
 428 };
 429
 430 static struct clk_alpha_pll_postdiv gpll4_out_test = {
 431         .offset = 0x77000,
 432         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 433         .clkr.hw.init = &(struct clk_init_data){
 434                 .name = "gpll4_out_test",
 435                 .parent_names = (const char *[]){ "gpll4" },
 436                 .num_parents = 1,
 437                 .ops = &clk_alpha_pll_postdiv_ops,
 438         },
 439 };
 440
 441 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
 442         F(19200000, P_XO, 1, 0, 0),
 443         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 444         { }
 445 };
 446
 447 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 448         .cmd_rcgr = 0x19020,
 449         .mnd_width = 0,
 450         .hid_width = 5,
 451         .parent_map = gcc_parent_map_1,
 452         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 453         .clkr.hw.init = &(struct clk_init_data){
 454                 .name = "blsp1_qup1_i2c_apps_clk_src",
 455                 .parent_names = gcc_parent_names_1,
 456                 .num_parents = 3,
 457                 .ops = &clk_rcg2_ops,
 458         },
 459 };
 460
 461 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
 462         F(960000, P_XO, 10, 1, 2),
 463         F(4800000, P_XO, 4, 0, 0),
 464         F(9600000, P_XO, 2, 0, 0),
 465         F(15000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
 466         F(19200000, P_XO, 1, 0, 0),
 467         F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
 468         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
 469         { }
 470 };
 471
 472 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 473         .cmd_rcgr = 0x1900c,
 474         .mnd_width = 8,
 475         .hid_width = 5,
 476         .parent_map = gcc_parent_map_0,
 477         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 478         .clkr.hw.init = &(struct clk_init_data){
 479                 .name = "blsp1_qup1_spi_apps_clk_src",
 480                 .parent_names = gcc_parent_names_0,
 481                 .num_parents = 4,
 482                 .ops = &clk_rcg2_ops,
 483         },
 484 };
 485
 486 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 487         .cmd_rcgr = 0x1b020,
 488         .mnd_width = 0,
 489         .hid_width = 5,
 490         .parent_map = gcc_parent_map_1,
 491         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 492         .clkr.hw.init = &(struct clk_init_data){
 493                 .name = "blsp1_qup2_i2c_apps_clk_src",
 494                 .parent_names = gcc_parent_names_1,
 495                 .num_parents = 3,
 496                 .ops = &clk_rcg2_ops,
 497         },
 498 };
 499
 500 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 501         .cmd_rcgr = 0x1b00c,
 502         .mnd_width = 8,
 503         .hid_width = 5,
 504         .parent_map = gcc_parent_map_0,
 505         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 506         .clkr.hw.init = &(struct clk_init_data){
 507                 .name = "blsp1_qup2_spi_apps_clk_src",
 508                 .parent_names = gcc_parent_names_0,
 509                 .num_parents = 4,
 510                 .ops = &clk_rcg2_ops,
 511         },
 512 };
 513
 514 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 515         .cmd_rcgr = 0x1d020,
 516         .mnd_width = 0,
 517         .hid_width = 5,
 518         .parent_map = gcc_parent_map_1,
 519         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 520         .clkr.hw.init = &(struct clk_init_data){
 521                 .name = "blsp1_qup3_i2c_apps_clk_src",
 522                 .parent_names = gcc_parent_names_1,
 523                 .num_parents = 3,
 524                 .ops = &clk_rcg2_ops,
 525         },
 526 };
 527
 528 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 529         .cmd_rcgr = 0x1d00c,
 530         .mnd_width = 8,
 531         .hid_width = 5,
 532         .parent_map = gcc_parent_map_0,
 533         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 534         .clkr.hw.init = &(struct clk_init_data){
 535                 .name = "blsp1_qup3_spi_apps_clk_src",
 536                 .parent_names = gcc_parent_names_0,
 537                 .num_parents = 4,
 538                 .ops = &clk_rcg2_ops,
 539         },
 540 };
 541
 542 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 543         .cmd_rcgr = 0x1f020,
 544         .mnd_width = 0,
 545         .hid_width = 5,
 546         .parent_map = gcc_parent_map_1,
 547         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 548         .clkr.hw.init = &(struct clk_init_data){
 549                 .name = "blsp1_qup4_i2c_apps_clk_src",
 550                 .parent_names = gcc_parent_names_1,
 551                 .num_parents = 3,
 552                 .ops = &clk_rcg2_ops,
 553         },
 554 };
 555
 556 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 557         .cmd_rcgr = 0x1f00c,
 558         .mnd_width = 8,
 559         .hid_width = 5,
 560         .parent_map = gcc_parent_map_0,
 561         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 562         .clkr.hw.init = &(struct clk_init_data){
 563                 .name = "blsp1_qup4_spi_apps_clk_src",
 564                 .parent_names = gcc_parent_names_0,
 565                 .num_parents = 4,
 566                 .ops = &clk_rcg2_ops,
 567         },
 568 };
 569
 570 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 571         .cmd_rcgr = 0x21020,
 572         .mnd_width = 0,
 573         .hid_width = 5,
 574         .parent_map = gcc_parent_map_1,
 575         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 576         .clkr.hw.init = &(struct clk_init_data){
 577                 .name = "blsp1_qup5_i2c_apps_clk_src",
 578                 .parent_names = gcc_parent_names_1,
 579                 .num_parents = 3,
 580                 .ops = &clk_rcg2_ops,
 581         },
 582 };
 583
 584 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 585         .cmd_rcgr = 0x2100c,
 586         .mnd_width = 8,
 587         .hid_width = 5,
 588         .parent_map = gcc_parent_map_0,
 589         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 590         .clkr.hw.init = &(struct clk_init_data){
 591                 .name = "blsp1_qup5_spi_apps_clk_src",
 592                 .parent_names = gcc_parent_names_0,
 593                 .num_parents = 4,
 594                 .ops = &clk_rcg2_ops,
 595         },
 596 };
 597
 598 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 599         .cmd_rcgr = 0x23020,
 600         .mnd_width = 0,
 601         .hid_width = 5,
 602         .parent_map = gcc_parent_map_1,
 603         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 604         .clkr.hw.init = &(struct clk_init_data){
 605                 .name = "blsp1_qup6_i2c_apps_clk_src",
 606                 .parent_names = gcc_parent_names_1,
 607                 .num_parents = 3,
 608                 .ops = &clk_rcg2_ops,
 609         },
 610 };
 611
 612 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 613         .cmd_rcgr = 0x2300c,
 614         .mnd_width = 8,
 615         .hid_width = 5,
 616         .parent_map = gcc_parent_map_0,
 617         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 618         .clkr.hw.init = &(struct clk_init_data){
 619                 .name = "blsp1_qup6_spi_apps_clk_src",
 620                 .parent_names = gcc_parent_names_0,
 621                 .num_parents = 4,
 622                 .ops = &clk_rcg2_ops,
 623         },
 624 };
 625
 626 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
 627         F(3686400, P_GPLL0_OUT_MAIN, 1, 96, 15625),
 628         F(7372800, P_GPLL0_OUT_MAIN, 1, 192, 15625),
 629         F(14745600, P_GPLL0_OUT_MAIN, 1, 384, 15625),
 630         F(16000000, P_GPLL0_OUT_MAIN, 5, 2, 15),
 631         F(19200000, P_XO, 1, 0, 0),
 632         F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5),
 633         F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75),
 634         F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
 635         F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375),
 636         F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
 637         F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375),
 638         F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75),
 639         F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625),
 640         F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
 641         F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
 642         { }
 643 };
 644
 645 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 646         .cmd_rcgr = 0x1a00c,
 647         .mnd_width = 16,
 648         .hid_width = 5,
 649         .parent_map = gcc_parent_map_0,
 650         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 651         .clkr.hw.init = &(struct clk_init_data){
 652                 .name = "blsp1_uart1_apps_clk_src",
 653                 .parent_names = gcc_parent_names_0,
 654                 .num_parents = 4,
 655                 .ops = &clk_rcg2_ops,
 656         },
 657 };
 658
 659 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 660         .cmd_rcgr = 0x1c00c,
 661         .mnd_width = 16,
 662         .hid_width = 5,
 663         .parent_map = gcc_parent_map_0,
 664         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 665         .clkr.hw.init = &(struct clk_init_data){
 666                 .name = "blsp1_uart2_apps_clk_src",
 667                 .parent_names = gcc_parent_names_0,
 668                 .num_parents = 4,
 669                 .ops = &clk_rcg2_ops,
 670         },
 671 };
 672
 673 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 674         .cmd_rcgr = 0x1e00c,
 675         .mnd_width = 16,
 676         .hid_width = 5,
 677         .parent_map = gcc_parent_map_0,
 678         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 679         .clkr.hw.init = &(struct clk_init_data){
 680                 .name = "blsp1_uart3_apps_clk_src",
 681                 .parent_names = gcc_parent_names_0,
 682                 .num_parents = 4,
 683                 .ops = &clk_rcg2_ops,
 684         },
 685 };
 686
 687 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 688         .cmd_rcgr = 0x26020,
 689         .mnd_width = 0,
 690         .hid_width = 5,
 691         .parent_map = gcc_parent_map_1,
 692         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 693         .clkr.hw.init = &(struct clk_init_data){
 694                 .name = "blsp2_qup1_i2c_apps_clk_src",
 695                 .parent_names = gcc_parent_names_1,
 696                 .num_parents = 3,
 697                 .ops = &clk_rcg2_ops,
 698         },
 699 };
 700
 701 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 702         .cmd_rcgr = 0x2600c,
 703         .mnd_width = 8,
 704         .hid_width = 5,
 705         .parent_map = gcc_parent_map_0,
 706         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 707         .clkr.hw.init = &(struct clk_init_data){
 708                 .name = "blsp2_qup1_spi_apps_clk_src",
 709                 .parent_names = gcc_parent_names_0,
 710                 .num_parents = 4,
 711                 .ops = &clk_rcg2_ops,
 712         },
 713 };
 714
 715 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 716         .cmd_rcgr = 0x28020,
 717         .mnd_width = 0,
 718         .hid_width = 5,
 719         .parent_map = gcc_parent_map_1,
 720         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 721         .clkr.hw.init = &(struct clk_init_data){
 722                 .name = "blsp2_qup2_i2c_apps_clk_src",
 723                 .parent_names = gcc_parent_names_1,
 724                 .num_parents = 3,
 725                 .ops = &clk_rcg2_ops,
 726         },
 727 };
 728
 729 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 730         .cmd_rcgr = 0x2800c,
 731         .mnd_width = 8,
 732         .hid_width = 5,
 733         .parent_map = gcc_parent_map_0,
 734         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 735         .clkr.hw.init = &(struct clk_init_data){
 736                 .name = "blsp2_qup2_spi_apps_clk_src",
 737                 .parent_names = gcc_parent_names_0,
 738                 .num_parents = 4,
 739                 .ops = &clk_rcg2_ops,
 740         },
 741 };
 742
 743 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 744         .cmd_rcgr = 0x2a020,
 745         .mnd_width = 0,
 746         .hid_width = 5,
 747         .parent_map = gcc_parent_map_1,
 748         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 749         .clkr.hw.init = &(struct clk_init_data){
 750                 .name = "blsp2_qup3_i2c_apps_clk_src",
 751                 .parent_names = gcc_parent_names_1,
 752                 .num_parents = 3,
 753                 .ops = &clk_rcg2_ops,
 754         },
 755 };
 756
 757 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 758         .cmd_rcgr = 0x2a00c,
 759         .mnd_width = 8,
 760         .hid_width = 5,
 761         .parent_map = gcc_parent_map_0,
 762         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 763         .clkr.hw.init = &(struct clk_init_data){
 764                 .name = "blsp2_qup3_spi_apps_clk_src",
 765                 .parent_names = gcc_parent_names_0,
 766                 .num_parents = 4,
 767                 .ops = &clk_rcg2_ops,
 768         },
 769 };
 770
 771 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 772         .cmd_rcgr = 0x2c020,
 773         .mnd_width = 0,
 774         .hid_width = 5,
 775         .parent_map = gcc_parent_map_1,
 776         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 777         .clkr.hw.init = &(struct clk_init_data){
 778                 .name = "blsp2_qup4_i2c_apps_clk_src",
 779                 .parent_names = gcc_parent_names_1,
 780                 .num_parents = 3,
 781                 .ops = &clk_rcg2_ops,
 782         },
 783 };
 784
 785 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 786         .cmd_rcgr = 0x2c00c,
 787         .mnd_width = 8,
 788         .hid_width = 5,
 789         .parent_map = gcc_parent_map_0,
 790         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 791         .clkr.hw.init = &(struct clk_init_data){
 792                 .name = "blsp2_qup4_spi_apps_clk_src",
 793                 .parent_names = gcc_parent_names_0,
 794                 .num_parents = 4,
 795                 .ops = &clk_rcg2_ops,
 796         },
 797 };
 798
 799 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 800         .cmd_rcgr = 0x2e020,
 801         .mnd_width = 0,
 802         .hid_width = 5,
 803         .parent_map = gcc_parent_map_1,
 804         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 805         .clkr.hw.init = &(struct clk_init_data){
 806                 .name = "blsp2_qup5_i2c_apps_clk_src",
 807                 .parent_names = gcc_parent_names_1,
 808                 .num_parents = 3,
 809                 .ops = &clk_rcg2_ops,
 810         },
 811 };
 812
 813 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 814         .cmd_rcgr = 0x2e00c,
 815         .mnd_width = 8,
 816         .hid_width = 5,
 817         .parent_map = gcc_parent_map_0,
 818         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 819         .clkr.hw.init = &(struct clk_init_data){
 820                 .name = "blsp2_qup5_spi_apps_clk_src",
 821                 .parent_names = gcc_parent_names_0,
 822                 .num_parents = 4,
 823                 .ops = &clk_rcg2_ops,
 824         },
 825 };
 826
 827 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
 828         .cmd_rcgr = 0x30020,
 829         .mnd_width = 0,
 830         .hid_width = 5,
 831         .parent_map = gcc_parent_map_1,
 832         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 833         .clkr.hw.init = &(struct clk_init_data){
 834                 .name = "blsp2_qup6_i2c_apps_clk_src",
 835                 .parent_names = gcc_parent_names_1,
 836                 .num_parents = 3,
 837                 .ops = &clk_rcg2_ops,
 838         },
 839 };
 840
 841 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
 842         .cmd_rcgr = 0x3000c,
 843         .mnd_width = 8,
 844         .hid_width = 5,
 845         .parent_map = gcc_parent_map_0,
 846         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 847         .clkr.hw.init = &(struct clk_init_data){
 848                 .name = "blsp2_qup6_spi_apps_clk_src",
 849                 .parent_names = gcc_parent_names_0,
 850                 .num_parents = 4,
 851                 .ops = &clk_rcg2_ops,
 852         },
 853 };
 854
 855 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 856         .cmd_rcgr = 0x2700c,
 857         .mnd_width = 16,
 858         .hid_width = 5,
 859         .parent_map = gcc_parent_map_0,
 860         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 861         .clkr.hw.init = &(struct clk_init_data){
 862                 .name = "blsp2_uart1_apps_clk_src",
 863                 .parent_names = gcc_parent_names_0,
 864                 .num_parents = 4,
 865                 .ops = &clk_rcg2_ops,
 866         },
 867 };
 868
 869 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 870         .cmd_rcgr = 0x2900c,
 871         .mnd_width = 16,
 872         .hid_width = 5,
 873         .parent_map = gcc_parent_map_0,
 874         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 875         .clkr.hw.init = &(struct clk_init_data){
 876                 .name = "blsp2_uart2_apps_clk_src",
 877                 .parent_names = gcc_parent_names_0,
 878                 .num_parents = 4,
 879                 .ops = &clk_rcg2_ops,
 880         },
 881 };
 882
 883 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 884         .cmd_rcgr = 0x2b00c,
 885         .mnd_width = 16,
 886         .hid_width = 5,
 887         .parent_map = gcc_parent_map_0,
 888         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 889         .clkr.hw.init = &(struct clk_init_data){
 890                 .name = "blsp2_uart3_apps_clk_src",
 891                 .parent_names = gcc_parent_names_0,
 892                 .num_parents = 4,
 893                 .ops = &clk_rcg2_ops,
 894         },
 895 };
 896
 897 static const struct freq_tbl ftbl_gp1_clk_src[] = {
 898         F(19200000, P_XO, 1, 0, 0),
 899         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
 900         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
 901         { }
 902 };
 903
 904 static struct clk_rcg2 gp1_clk_src = {
 905         .cmd_rcgr = 0x64004,
 906         .mnd_width = 8,
 907         .hid_width = 5,
 908         .parent_map = gcc_parent_map_2,
 909         .freq_tbl = ftbl_gp1_clk_src,
 910         .clkr.hw.init = &(struct clk_init_data){
 911                 .name = "gp1_clk_src",
 912                 .parent_names = gcc_parent_names_2,
 913                 .num_parents = 5,
 914                 .ops = &clk_rcg2_ops,
 915         },
 916 };
 917
 918 static struct clk_rcg2 gp2_clk_src = {
 919         .cmd_rcgr = 0x65004,
 920         .mnd_width = 8,
 921         .hid_width = 5,
 922         .parent_map = gcc_parent_map_2,
 923         .freq_tbl = ftbl_gp1_clk_src,
 924         .clkr.hw.init = &(struct clk_init_data){
 925                 .name = "gp2_clk_src",
 926                 .parent_names = gcc_parent_names_2,
 927                 .num_parents = 5,
 928                 .ops = &clk_rcg2_ops,
 929         },
 930 };
 931
 932 static struct clk_rcg2 gp3_clk_src = {
 933         .cmd_rcgr = 0x66004,
 934         .mnd_width = 8,
 935         .hid_width = 5,
 936         .parent_map = gcc_parent_map_2,
 937         .freq_tbl = ftbl_gp1_clk_src,
 938         .clkr.hw.init = &(struct clk_init_data){
 939                 .name = "gp3_clk_src",
 940                 .parent_names = gcc_parent_names_2,
 941                 .num_parents = 5,
 942                 .ops = &clk_rcg2_ops,
 943         },
 944 };
 945
 946 static const struct freq_tbl ftbl_hmss_ahb_clk_src[] = {
 947         F(19200000, P_XO, 1, 0, 0),
 948         F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 949         F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 950         { }
 951 };
 952
 953 static struct clk_rcg2 hmss_ahb_clk_src = {
 954         .cmd_rcgr = 0x48014,
 955         .mnd_width = 0,
 956         .hid_width = 5,
 957         .parent_map = gcc_parent_map_1,
 958         .freq_tbl = ftbl_hmss_ahb_clk_src,
 959         .clkr.hw.init = &(struct clk_init_data){
 960                 .name = "hmss_ahb_clk_src",
 961                 .parent_names = gcc_parent_names_1,
 962                 .num_parents = 3,
 963                 .ops = &clk_rcg2_ops,
 964         },
 965 };
 966
 967 static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
 968         F(19200000, P_XO, 1, 0, 0),
 969         { }
 970 };
 971
 972 static struct clk_rcg2 hmss_rbcpr_clk_src = {
 973         .cmd_rcgr = 0x48044,
 974         .mnd_width = 0,
 975         .hid_width = 5,
 976         .parent_map = gcc_parent_map_1,
 977         .freq_tbl = ftbl_hmss_rbcpr_clk_src,
 978         .clkr.hw.init = &(struct clk_init_data){
 979                 .name = "hmss_rbcpr_clk_src",
 980                 .parent_names = gcc_parent_names_1,
 981                 .num_parents = 3,
 982                 .ops = &clk_rcg2_ops,
 983         },
 984 };
 985
 986 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
 987         F(1010526, P_XO, 1, 1, 19),
 988         { }
 989 };
 990
 991 static struct clk_rcg2 pcie_aux_clk_src = {
 992         .cmd_rcgr = 0x6c000,
 993         .mnd_width = 16,
 994         .hid_width = 5,
 995         .parent_map = gcc_parent_map_3,
 996         .freq_tbl = ftbl_pcie_aux_clk_src,
 997         .clkr.hw.init = &(struct clk_init_data){
 998                 .name = "pcie_aux_clk_src",
 999                 .parent_names = gcc_parent_names_3,
1000                 .num_parents = 3,
1001                 .ops = &clk_rcg2_ops,
1002         },
1003 };
1004
1005 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1006         F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1007         { }
1008 };
1009
1010 static struct clk_rcg2 pdm2_clk_src = {
1011         .cmd_rcgr = 0x33010,
1012         .mnd_width = 0,
1013         .hid_width = 5,
1014         .parent_map = gcc_parent_map_1,
1015         .freq_tbl = ftbl_pdm2_clk_src,
1016         .clkr.hw.init = &(struct clk_init_data){
1017                 .name = "pdm2_clk_src",
1018                 .parent_names = gcc_parent_names_1,
1019                 .num_parents = 3,
1020                 .ops = &clk_rcg2_ops,
1021         },
1022 };
1023
1024 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
1025         F(144000, P_XO, 16, 3, 25),
1026         F(400000, P_XO, 12, 1, 4),
1027         F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
1028         F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
1029         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
1030         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1031         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1032         { }
1033 };
1034
1035 static struct clk_rcg2 sdcc2_apps_clk_src = {
1036         .cmd_rcgr = 0x14010,
1037         .mnd_width = 8,
1038         .hid_width = 5,
1039         .parent_map = gcc_parent_map_4,
1040         .freq_tbl = ftbl_sdcc2_apps_clk_src,
1041         .clkr.hw.init = &(struct clk_init_data){
1042                 .name = "sdcc2_apps_clk_src",
1043                 .parent_names = gcc_parent_names_4,
1044                 .num_parents = 4,
1045                 .ops = &clk_rcg2_floor_ops,
1046         },
1047 };
1048
1049 static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
1050         F(144000, P_XO, 16, 3, 25),
1051         F(400000, P_XO, 12, 1, 4),
1052         F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2),
1053         F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
1054         F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
1055         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1056         { }
1057 };
1058
1059 static struct clk_rcg2 sdcc4_apps_clk_src = {
1060         .cmd_rcgr = 0x16010,
1061         .mnd_width = 8,
1062         .hid_width = 5,
1063         .parent_map = gcc_parent_map_1,
1064         .freq_tbl = ftbl_sdcc4_apps_clk_src,
1065         .clkr.hw.init = &(struct clk_init_data){
1066                 .name = "sdcc4_apps_clk_src",
1067                 .parent_names = gcc_parent_names_1,
1068                 .num_parents = 3,
1069                 .ops = &clk_rcg2_floor_ops,
1070         },
1071 };
1072
1073 static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1074         F(105495, P_XO, 1, 1, 182),
1075         { }
1076 };
1077
1078 static struct clk_rcg2 tsif_ref_clk_src = {
1079         .cmd_rcgr = 0x36010,
1080         .mnd_width = 8,
1081         .hid_width = 5,
1082         .parent_map = gcc_parent_map_5,
1083         .freq_tbl = ftbl_tsif_ref_clk_src,
1084         .clkr.hw.init = &(struct clk_init_data){
1085                 .name = "tsif_ref_clk_src",
1086                 .parent_names = gcc_parent_names_5,
1087                 .num_parents = 4,
1088                 .ops = &clk_rcg2_ops,
1089         },
1090 };
1091
1092 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
1093         F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1094         F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1095         F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1096         { }
1097 };
1098
1099 static struct clk_rcg2 ufs_axi_clk_src = {
1100         .cmd_rcgr = 0x75018,
1101         .mnd_width = 8,
1102         .hid_width = 5,
1103         .parent_map = gcc_parent_map_0,
1104         .freq_tbl = ftbl_ufs_axi_clk_src,
1105         .clkr.hw.init = &(struct clk_init_data){
1106                 .name = "ufs_axi_clk_src",
1107                 .parent_names = gcc_parent_names_0,
1108                 .num_parents = 4,
1109                 .ops = &clk_rcg2_ops,
1110         },
1111 };
1112
1113 static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = {
1114         F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1115         F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1116         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1117         { }
1118 };
1119
1120 static struct clk_rcg2 ufs_unipro_core_clk_src = {
1121         .cmd_rcgr = 0x76028,
1122         .mnd_width = 8,
1123         .hid_width = 5,
1124         .parent_map = gcc_parent_map_0,
1125         .freq_tbl = ftbl_ufs_unipro_core_clk_src,
1126         .clkr.hw.init = &(struct clk_init_data){
1127                 .name = "ufs_unipro_core_clk_src",
1128                 .parent_names = gcc_parent_names_0,
1129                 .num_parents = 4,
1130                 .ops = &clk_rcg2_ops,
1131         },
1132 };
1133
1134 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
1135         F(19200000, P_XO, 1, 0, 0),
1136         F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1137         F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1138         F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1139         { }
1140 };
1141
1142 static struct clk_rcg2 usb30_master_clk_src = {
1143         .cmd_rcgr = 0xf014,
1144         .mnd_width = 8,
1145         .hid_width = 5,
1146         .parent_map = gcc_parent_map_0,
1147         .freq_tbl = ftbl_usb30_master_clk_src,
1148         .clkr.hw.init = &(struct clk_init_data){
1149                 .name = "usb30_master_clk_src",
1150                 .parent_names = gcc_parent_names_0,
1151                 .num_parents = 4,
1152                 .ops = &clk_rcg2_ops,
1153         },
1154 };
1155
1156 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1157         .cmd_rcgr = 0xf028,
1158         .mnd_width = 0,
1159         .hid_width = 5,
1160         .parent_map = gcc_parent_map_0,
1161         .freq_tbl = ftbl_hmss_rbcpr_clk_src,
1162         .clkr.hw.init = &(struct clk_init_data){
1163                 .name = "usb30_mock_utmi_clk_src",
1164                 .parent_names = gcc_parent_names_0,
1165                 .num_parents = 4,
1166                 .ops = &clk_rcg2_ops,
1167         },
1168 };
1169
1170 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
1171         F(1200000, P_XO, 16, 0, 0),
1172         { }
1173 };
1174
1175 static struct clk_rcg2 usb3_phy_aux_clk_src = {
1176         .cmd_rcgr = 0x5000c,
1177         .mnd_width = 0,
1178         .hid_width = 5,
1179         .parent_map = gcc_parent_map_3,
1180         .freq_tbl = ftbl_usb3_phy_aux_clk_src,
1181         .clkr.hw.init = &(struct clk_init_data){
1182                 .name = "usb3_phy_aux_clk_src",
1183                 .parent_names = gcc_parent_names_3,
1184                 .num_parents = 3,
1185                 .ops = &clk_rcg2_ops,
1186         },
1187 };
1188
1189 static struct clk_branch gcc_aggre1_noc_xo_clk = {
1190         .halt_reg = 0x8202c,
1191         .halt_check = BRANCH_HALT,
1192         .clkr = {
1193                 .enable_reg = 0x8202c,
1194                 .enable_mask = BIT(0),
1195                 .hw.init = &(struct clk_init_data){
1196                         .name = "gcc_aggre1_noc_xo_clk",
1197                         .ops = &clk_branch2_ops,
1198                 },
1199         },
1200 };
1201
1202 static struct clk_branch gcc_aggre1_ufs_axi_clk = {
1203         .halt_reg = 0x82028,
1204         .halt_check = BRANCH_HALT,
1205         .clkr = {
1206                 .enable_reg = 0x82028,
1207                 .enable_mask = BIT(0),
1208                 .hw.init = &(struct clk_init_data){
1209                         .name = "gcc_aggre1_ufs_axi_clk",
1210                         .parent_names = (const char *[]){
1211                                 "ufs_axi_clk_src",
1212                         },
1213                         .num_parents = 1,
1214                         .flags = CLK_SET_RATE_PARENT,
1215                         .ops = &clk_branch2_ops,
1216                 },
1217         },
1218 };
1219
1220 static struct clk_branch gcc_aggre1_usb3_axi_clk = {
1221         .halt_reg = 0x82024,
1222         .halt_check = BRANCH_HALT,
1223         .clkr = {
1224                 .enable_reg = 0x82024,
1225                 .enable_mask = BIT(0),
1226                 .hw.init = &(struct clk_init_data){
1227                         .name = "gcc_aggre1_usb3_axi_clk",
1228                         .parent_names = (const char *[]){
1229                                 "usb30_master_clk_src",
1230                         },
1231                         .num_parents = 1,
1232                         .flags = CLK_SET_RATE_PARENT,
1233                         .ops = &clk_branch2_ops,
1234                 },
1235         },
1236 };
1237
1238 static struct clk_branch gcc_apss_qdss_tsctr_div2_clk = {
1239         .halt_reg = 0x48090,
1240         .halt_check = BRANCH_HALT,
1241         .clkr = {
1242                 .enable_reg = 0x48090,
1243                 .enable_mask = BIT(0),
1244                 .hw.init = &(struct clk_init_data){
1245                         .name = "gcc_apss_qdss_tsctr_div2_clk",
1246                         .ops = &clk_branch2_ops,
1247                 },
1248         },
1249 };
1250
1251 static struct clk_branch gcc_apss_qdss_tsctr_div8_clk = {
1252         .halt_reg = 0x48094,
1253         .halt_check = BRANCH_HALT,
1254         .clkr = {
1255                 .enable_reg = 0x48094,
1256                 .enable_mask = BIT(0),
1257                 .hw.init = &(struct clk_init_data){
1258                         .name = "gcc_apss_qdss_tsctr_div8_clk",
1259                         .ops = &clk_branch2_ops,
1260                 },
1261         },
1262 };
1263
1264 static struct clk_branch gcc_bimc_hmss_axi_clk = {
1265         .halt_reg = 0x48004,
1266         .halt_check = BRANCH_HALT_VOTED,
1267         .clkr = {
1268                 .enable_reg = 0x52004,
1269                 .enable_mask = BIT(22),
1270                 .hw.init = &(struct clk_init_data){
1271                         .name = "gcc_bimc_hmss_axi_clk",
1272                         .ops = &clk_branch2_ops,
1273                 },
1274         },
1275 };
1276
1277 static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
1278         .halt_reg = 0x4401c,
1279         .halt_check = BRANCH_HALT,
1280         .clkr = {
1281                 .enable_reg = 0x4401c,
1282                 .enable_mask = BIT(0),
1283                 .hw.init = &(struct clk_init_data){
1284                         .name = "gcc_bimc_mss_q6_axi_clk",
1285                         .ops = &clk_branch2_ops,
1286                 },
1287         },
1288 };
1289
1290 static struct clk_branch gcc_mss_cfg_ahb_clk = {
1291         .halt_reg = 0x8a000,
1292         .halt_check = BRANCH_HALT,
1293         .clkr = {
1294                 .enable_reg = 0x8a000,
1295                 .enable_mask = BIT(0),
1296                 .hw.init = &(struct clk_init_data){
1297                         .name = "gcc_mss_cfg_ahb_clk",
1298                         .ops = &clk_branch2_ops,
1299                 },
1300         },
1301 };
1302
1303 static struct clk_branch gcc_mss_snoc_axi_clk = {
1304         .halt_reg = 0x8a03c,
1305         .halt_check = BRANCH_HALT,
1306         .clkr = {
1307                 .enable_reg = 0x8a03c,
1308                 .enable_mask = BIT(0),
1309                 .hw.init = &(struct clk_init_data){
1310                         .name = "gcc_mss_snoc_axi_clk",
1311                         .ops = &clk_branch2_ops,
1312                 },
1313         },
1314 };
1315
1316 static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
1317         .halt_reg = 0x8a004,
1318         .halt_check = BRANCH_HALT,
1319         .clkr = {
1320                 .enable_reg = 0x8a004,
1321                 .enable_mask = BIT(0),
1322                 .hw.init = &(struct clk_init_data){
1323                         .name = "gcc_mss_mnoc_bimc_axi_clk",
1324                         .ops = &clk_branch2_ops,
1325                 },
1326         },
1327 };
1328
1329 static struct clk_branch gcc_boot_rom_ahb_clk = {
1330         .halt_reg = 0x38004,
1331         .halt_check = BRANCH_HALT_VOTED,
1332         .hwcg_reg = 0x38004,
1333         .hwcg_bit = 1,
1334         .clkr = {
1335                 .enable_reg = 0x52004,
1336                 .enable_mask = BIT(10),
1337                 .hw.init = &(struct clk_init_data){
1338                         .name = "gcc_boot_rom_ahb_clk",
1339                         .ops = &clk_branch2_ops,
1340                 },
1341         },
1342 };
1343
1344 static struct clk_branch gcc_mss_gpll0_div_clk_src = {
1345         .halt_check = BRANCH_HALT_DELAY,
1346         .clkr = {
1347                 .enable_reg = 0x5200c,
1348                 .enable_mask = BIT(2),
1349                 .hw.init = &(struct clk_init_data){
1350                         .name = "gcc_mss_gpll0_div_clk_src",
1351                         .ops = &clk_branch2_ops,
1352                 },
1353         },
1354 };
1355
1356 static struct clk_branch gcc_blsp1_ahb_clk = {
1357         .halt_reg = 0x17004,
1358         .halt_check = BRANCH_HALT_VOTED,
1359         .clkr = {
1360                 .enable_reg = 0x52004,
1361                 .enable_mask = BIT(17),
1362                 .hw.init = &(struct clk_init_data){
1363                         .name = "gcc_blsp1_ahb_clk",
1364                         .ops = &clk_branch2_ops,
1365                 },
1366         },
1367 };
1368
1369 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1370         .halt_reg = 0x19008,
1371         .halt_check = BRANCH_HALT,
1372         .clkr = {
1373                 .enable_reg = 0x19008,
1374                 .enable_mask = BIT(0),
1375                 .hw.init = &(struct clk_init_data){
1376                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1377                         .parent_names = (const char *[]){
1378                                 "blsp1_qup1_i2c_apps_clk_src",
1379                         },
1380                         .num_parents = 1,
1381                         .flags = CLK_SET_RATE_PARENT,
1382                         .ops = &clk_branch2_ops,
1383                 },
1384         },
1385 };
1386
1387 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1388         .halt_reg = 0x19004,
1389         .halt_check = BRANCH_HALT,
1390         .clkr = {
1391                 .enable_reg = 0x19004,
1392                 .enable_mask = BIT(0),
1393                 .hw.init = &(struct clk_init_data){
1394                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1395                         .parent_names = (const char *[]){
1396                                 "blsp1_qup1_spi_apps_clk_src",
1397                         },
1398                         .num_parents = 1,
1399                         .flags = CLK_SET_RATE_PARENT,
1400                         .ops = &clk_branch2_ops,
1401                 },
1402         },
1403 };
1404
1405 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1406         .halt_reg = 0x1b008,
1407         .halt_check = BRANCH_HALT,
1408         .clkr = {
1409                 .enable_reg = 0x1b008,
1410                 .enable_mask = BIT(0),
1411                 .hw.init = &(struct clk_init_data){
1412                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1413                         .parent_names = (const char *[]){
1414                                 "blsp1_qup2_i2c_apps_clk_src",
1415                         },
1416                         .num_parents = 1,
1417                         .flags = CLK_SET_RATE_PARENT,
1418                         .ops = &clk_branch2_ops,
1419                 },
1420         },
1421 };
1422
1423 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1424         .halt_reg = 0x1b004,
1425         .halt_check = BRANCH_HALT,
1426         .clkr = {
1427                 .enable_reg = 0x1b004,
1428                 .enable_mask = BIT(0),
1429                 .hw.init = &(struct clk_init_data){
1430                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1431                         .parent_names = (const char *[]){
1432                                 "blsp1_qup2_spi_apps_clk_src",
1433                         },
1434                         .num_parents = 1,
1435                         .flags = CLK_SET_RATE_PARENT,
1436                         .ops = &clk_branch2_ops,
1437                 },
1438         },
1439 };
1440
1441 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1442         .halt_reg = 0x1d008,
1443         .halt_check = BRANCH_HALT,
1444         .clkr = {
1445                 .enable_reg = 0x1d008,
1446                 .enable_mask = BIT(0),
1447                 .hw.init = &(struct clk_init_data){
1448                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1449                         .parent_names = (const char *[]){
1450                                 "blsp1_qup3_i2c_apps_clk_src",
1451                         },
1452                         .num_parents = 1,
1453                         .flags = CLK_SET_RATE_PARENT,
1454                         .ops = &clk_branch2_ops,
1455                 },
1456         },
1457 };
1458
1459 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1460         .halt_reg = 0x1d004,
1461         .halt_check = BRANCH_HALT,
1462         .clkr = {
1463                 .enable_reg = 0x1d004,
1464                 .enable_mask = BIT(0),
1465                 .hw.init = &(struct clk_init_data){
1466                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1467                         .parent_names = (const char *[]){
1468                                 "blsp1_qup3_spi_apps_clk_src",
1469                         },
1470                         .num_parents = 1,
1471                         .flags = CLK_SET_RATE_PARENT,
1472                         .ops = &clk_branch2_ops,
1473                 },
1474         },
1475 };
1476
1477 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1478         .halt_reg = 0x1f008,
1479         .halt_check = BRANCH_HALT,
1480         .clkr = {
1481                 .enable_reg = 0x1f008,
1482                 .enable_mask = BIT(0),
1483                 .hw.init = &(struct clk_init_data){
1484                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1485                         .parent_names = (const char *[]){
1486                                 "blsp1_qup4_i2c_apps_clk_src",
1487                         },
1488                         .num_parents = 1,
1489                         .flags = CLK_SET_RATE_PARENT,
1490                         .ops = &clk_branch2_ops,
1491                 },
1492         },
1493 };
1494
1495 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1496         .halt_reg = 0x1f004,
1497         .halt_check = BRANCH_HALT,
1498         .clkr = {
1499                 .enable_reg = 0x1f004,
1500                 .enable_mask = BIT(0),
1501                 .hw.init = &(struct clk_init_data){
1502                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1503                         .parent_names = (const char *[]){
1504                                 "blsp1_qup4_spi_apps_clk_src",
1505                         },
1506                         .num_parents = 1,
1507                         .flags = CLK_SET_RATE_PARENT,
1508                         .ops = &clk_branch2_ops,
1509                 },
1510         },
1511 };
1512
1513 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1514         .halt_reg = 0x21008,
1515         .halt_check = BRANCH_HALT,
1516         .clkr = {
1517                 .enable_reg = 0x21008,
1518                 .enable_mask = BIT(0),
1519                 .hw.init = &(struct clk_init_data){
1520                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
1521                         .parent_names = (const char *[]){
1522                                 "blsp1_qup5_i2c_apps_clk_src",
1523                         },
1524                         .num_parents = 1,
1525                         .flags = CLK_SET_RATE_PARENT,
1526                         .ops = &clk_branch2_ops,
1527                 },
1528         },
1529 };
1530
1531 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1532         .halt_reg = 0x21004,
1533         .halt_check = BRANCH_HALT,
1534         .clkr = {
1535                 .enable_reg = 0x21004,
1536                 .enable_mask = BIT(0),
1537                 .hw.init = &(struct clk_init_data){
1538                         .name = "gcc_blsp1_qup5_spi_apps_clk",
1539                         .parent_names = (const char *[]){
1540                                 "blsp1_qup5_spi_apps_clk_src",
1541                         },
1542                         .num_parents = 1,
1543                         .flags = CLK_SET_RATE_PARENT,
1544                         .ops = &clk_branch2_ops,
1545                 },
1546         },
1547 };
1548
1549 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1550         .halt_reg = 0x23008,
1551         .halt_check = BRANCH_HALT,
1552         .clkr = {
1553                 .enable_reg = 0x23008,
1554                 .enable_mask = BIT(0),
1555                 .hw.init = &(struct clk_init_data){
1556                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
1557                         .parent_names = (const char *[]){
1558                                 "blsp1_qup6_i2c_apps_clk_src",
1559                         },
1560                         .num_parents = 1,
1561                         .flags = CLK_SET_RATE_PARENT,
1562                         .ops = &clk_branch2_ops,
1563                 },
1564         },
1565 };
1566
1567 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1568         .halt_reg = 0x23004,
1569         .halt_check = BRANCH_HALT,
1570         .clkr = {
1571                 .enable_reg = 0x23004,
1572                 .enable_mask = BIT(0),
1573                 .hw.init = &(struct clk_init_data){
1574                         .name = "gcc_blsp1_qup6_spi_apps_clk",
1575                         .parent_names = (const char *[]){
1576                                 "blsp1_qup6_spi_apps_clk_src",
1577                         },
1578                         .num_parents = 1,
1579                         .flags = CLK_SET_RATE_PARENT,
1580                         .ops = &clk_branch2_ops,
1581                 },
1582         },
1583 };
1584
1585 static struct clk_branch gcc_blsp1_sleep_clk = {
1586         .halt_reg = 0x17008,
1587         .halt_check = BRANCH_HALT_VOTED,
1588         .clkr = {
1589                 .enable_reg = 0x52004,
1590                 .enable_mask = BIT(16),
1591                 .hw.init = &(struct clk_init_data){
1592                         .name = "gcc_blsp1_sleep_clk",
1593                         .ops = &clk_branch2_ops,
1594                 },
1595         },
1596 };
1597
1598 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1599         .halt_reg = 0x1a004,
1600         .halt_check = BRANCH_HALT,
1601         .clkr = {
1602                 .enable_reg = 0x1a004,
1603                 .enable_mask = BIT(0),
1604                 .hw.init = &(struct clk_init_data){
1605                         .name = "gcc_blsp1_uart1_apps_clk",
1606                         .parent_names = (const char *[]){
1607                                 "blsp1_uart1_apps_clk_src",
1608                         },
1609                         .num_parents = 1,
1610                         .flags = CLK_SET_RATE_PARENT,
1611                         .ops = &clk_branch2_ops,
1612                 },
1613         },
1614 };
1615
1616 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1617         .halt_reg = 0x1c004,
1618         .halt_check = BRANCH_HALT,
1619         .clkr = {
1620                 .enable_reg = 0x1c004,
1621                 .enable_mask = BIT(0),
1622                 .hw.init = &(struct clk_init_data){
1623                         .name = "gcc_blsp1_uart2_apps_clk",
1624                         .parent_names = (const char *[]){
1625                                 "blsp1_uart2_apps_clk_src",
1626                         },
1627                         .num_parents = 1,
1628                         .flags = CLK_SET_RATE_PARENT,
1629                         .ops = &clk_branch2_ops,
1630                 },
1631         },
1632 };
1633
1634 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1635         .halt_reg = 0x1e004,
1636         .halt_check = BRANCH_HALT,
1637         .clkr = {
1638                 .enable_reg = 0x1e004,
1639                 .enable_mask = BIT(0),
1640                 .hw.init = &(struct clk_init_data){
1641                         .name = "gcc_blsp1_uart3_apps_clk",
1642                         .parent_names = (const char *[]){
1643                                 "blsp1_uart3_apps_clk_src",
1644                         },
1645                         .num_parents = 1,
1646                         .flags = CLK_SET_RATE_PARENT,
1647                         .ops = &clk_branch2_ops,
1648                 },
1649         },
1650 };
1651
1652 static struct clk_branch gcc_blsp2_ahb_clk = {
1653         .halt_reg = 0x25004,
1654         .halt_check = BRANCH_HALT_VOTED,
1655         .clkr = {
1656                 .enable_reg = 0x52004,
1657                 .enable_mask = BIT(15),
1658                 .hw.init = &(struct clk_init_data){
1659                         .name = "gcc_blsp2_ahb_clk",
1660                         .ops = &clk_branch2_ops,
1661                 },
1662         },
1663 };
1664
1665 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1666         .halt_reg = 0x26008,
1667         .halt_check = BRANCH_HALT,
1668         .clkr = {
1669                 .enable_reg = 0x26008,
1670                 .enable_mask = BIT(0),
1671                 .hw.init = &(struct clk_init_data){
1672                         .name = "gcc_blsp2_qup1_i2c_apps_clk",
1673                         .parent_names = (const char *[]){
1674                                 "blsp2_qup1_i2c_apps_clk_src",
1675                         },
1676                         .num_parents = 1,
1677                         .flags = CLK_SET_RATE_PARENT,
1678                         .ops = &clk_branch2_ops,
1679                 },
1680         },
1681 };
1682
1683 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1684         .halt_reg = 0x26004,
1685         .halt_check = BRANCH_HALT,
1686         .clkr = {
1687                 .enable_reg = 0x26004,
1688                 .enable_mask = BIT(0),
1689                 .hw.init = &(struct clk_init_data){
1690                         .name = "gcc_blsp2_qup1_spi_apps_clk",
1691                         .parent_names = (const char *[]){
1692                                 "blsp2_qup1_spi_apps_clk_src",
1693                         },
1694                         .num_parents = 1,
1695                         .flags = CLK_SET_RATE_PARENT,
1696                         .ops = &clk_branch2_ops,
1697                 },
1698         },
1699 };
1700
1701 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1702         .halt_reg = 0x28008,
1703         .halt_check = BRANCH_HALT,
1704         .clkr = {
1705                 .enable_reg = 0x28008,
1706                 .enable_mask = BIT(0),
1707                 .hw.init = &(struct clk_init_data){
1708                         .name = "gcc_blsp2_qup2_i2c_apps_clk",
1709                         .parent_names = (const char *[]){
1710                                 "blsp2_qup2_i2c_apps_clk_src",
1711                         },
1712                         .num_parents = 1,
1713                         .flags = CLK_SET_RATE_PARENT,
1714                         .ops = &clk_branch2_ops,
1715                 },
1716         },
1717 };
1718
1719 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1720         .halt_reg = 0x28004,
1721         .halt_check = BRANCH_HALT,
1722         .clkr = {
1723                 .enable_reg = 0x28004,
1724                 .enable_mask = BIT(0),
1725                 .hw.init = &(struct clk_init_data){
1726                         .name = "gcc_blsp2_qup2_spi_apps_clk",
1727                         .parent_names = (const char *[]){
1728                                 "blsp2_qup2_spi_apps_clk_src",
1729                         },
1730                         .num_parents = 1,
1731                         .flags = CLK_SET_RATE_PARENT,
1732                         .ops = &clk_branch2_ops,
1733                 },
1734         },
1735 };
1736
1737 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1738         .halt_reg = 0x2a008,
1739         .halt_check = BRANCH_HALT,
1740         .clkr = {
1741                 .enable_reg = 0x2a008,
1742                 .enable_mask = BIT(0),
1743                 .hw.init = &(struct clk_init_data){
1744                         .name = "gcc_blsp2_qup3_i2c_apps_clk",
1745                         .parent_names = (const char *[]){
1746                                 "blsp2_qup3_i2c_apps_clk_src",
1747                         },
1748                         .num_parents = 1,
1749                         .flags = CLK_SET_RATE_PARENT,
1750                         .ops = &clk_branch2_ops,
1751                 },
1752         },
1753 };
1754
1755 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1756         .halt_reg = 0x2a004,
1757         .halt_check = BRANCH_HALT,
1758         .clkr = {
1759                 .enable_reg = 0x2a004,
1760                 .enable_mask = BIT(0),
1761                 .hw.init = &(struct clk_init_data){
1762                         .name = "gcc_blsp2_qup3_spi_apps_clk",
1763                         .parent_names = (const char *[]){
1764                                 "blsp2_qup3_spi_apps_clk_src",
1765                         },
1766                         .num_parents = 1,
1767                         .flags = CLK_SET_RATE_PARENT,
1768                         .ops = &clk_branch2_ops,
1769                 },
1770         },
1771 };
1772
1773 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1774         .halt_reg = 0x2c008,
1775         .halt_check = BRANCH_HALT,
1776         .clkr = {
1777                 .enable_reg = 0x2c008,
1778                 .enable_mask = BIT(0),
1779                 .hw.init = &(struct clk_init_data){
1780                         .name = "gcc_blsp2_qup4_i2c_apps_clk",
1781                         .parent_names = (const char *[]){
1782                                 "blsp2_qup4_i2c_apps_clk_src",
1783                         },
1784                         .num_parents = 1,
1785                         .flags = CLK_SET_RATE_PARENT,
1786                         .ops = &clk_branch2_ops,
1787                 },
1788         },
1789 };
1790
1791 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1792         .halt_reg = 0x2c004,
1793         .halt_check = BRANCH_HALT,
1794         .clkr = {
1795                 .enable_reg = 0x2c004,
1796                 .enable_mask = BIT(0),
1797                 .hw.init = &(struct clk_init_data){
1798                         .name = "gcc_blsp2_qup4_spi_apps_clk",
1799                         .parent_names = (const char *[]){
1800                                 "blsp2_qup4_spi_apps_clk_src",
1801                         },
1802                         .num_parents = 1,
1803                         .flags = CLK_SET_RATE_PARENT,
1804                         .ops = &clk_branch2_ops,
1805                 },
1806         },
1807 };
1808
1809 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1810         .halt_reg = 0x2e008,
1811         .halt_check = BRANCH_HALT,
1812         .clkr = {
1813                 .enable_reg = 0x2e008,
1814                 .enable_mask = BIT(0),
1815                 .hw.init = &(struct clk_init_data){
1816                         .name = "gcc_blsp2_qup5_i2c_apps_clk",
1817                         .parent_names = (const char *[]){
1818                                 "blsp2_qup5_i2c_apps_clk_src",
1819                         },
1820                         .num_parents = 1,
1821                         .flags = CLK_SET_RATE_PARENT,
1822                         .ops = &clk_branch2_ops,
1823                 },
1824         },
1825 };
1826
1827 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1828         .halt_reg = 0x2e004,
1829         .halt_check = BRANCH_HALT,
1830         .clkr = {
1831                 .enable_reg = 0x2e004,
1832                 .enable_mask = BIT(0),
1833                 .hw.init = &(struct clk_init_data){
1834                         .name = "gcc_blsp2_qup5_spi_apps_clk",
1835                         .parent_names = (const char *[]){
1836                                 "blsp2_qup5_spi_apps_clk_src",
1837                         },
1838                         .num_parents = 1,
1839                         .flags = CLK_SET_RATE_PARENT,
1840                         .ops = &clk_branch2_ops,
1841                 },
1842         },
1843 };
1844
1845 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1846         .halt_reg = 0x30008,
1847         .halt_check = BRANCH_HALT,
1848         .clkr = {
1849                 .enable_reg = 0x30008,
1850                 .enable_mask = BIT(0),
1851                 .hw.init = &(struct clk_init_data){
1852                         .name = "gcc_blsp2_qup6_i2c_apps_clk",
1853                         .parent_names = (const char *[]){
1854                                 "blsp2_qup6_i2c_apps_clk_src",
1855                         },
1856                         .num_parents = 1,
1857                         .flags = CLK_SET_RATE_PARENT,
1858                         .ops = &clk_branch2_ops,
1859                 },
1860         },
1861 };
1862
1863 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1864         .halt_reg = 0x30004,
1865         .halt_check = BRANCH_HALT,
1866         .clkr = {
1867                 .enable_reg = 0x30004,
1868                 .enable_mask = BIT(0),
1869                 .hw.init = &(struct clk_init_data){
1870                         .name = "gcc_blsp2_qup6_spi_apps_clk",
1871                         .parent_names = (const char *[]){
1872                                 "blsp2_qup6_spi_apps_clk_src",
1873                         },
1874                         .num_parents = 1,
1875                         .flags = CLK_SET_RATE_PARENT,
1876                         .ops = &clk_branch2_ops,
1877                 },
1878         },
1879 };
1880
1881 static struct clk_branch gcc_blsp2_sleep_clk = {
1882         .halt_reg = 0x25008,
1883         .halt_check = BRANCH_HALT_VOTED,
1884         .clkr = {
1885                 .enable_reg = 0x52004,
1886                 .enable_mask = BIT(14),
1887                 .hw.init = &(struct clk_init_data){
1888                         .name = "gcc_blsp2_sleep_clk",
1889                         .ops = &clk_branch2_ops,
1890                 },
1891         },
1892 };
1893
1894 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1895         .halt_reg = 0x27004,
1896         .halt_check = BRANCH_HALT,
1897         .clkr = {
1898                 .enable_reg = 0x27004,
1899                 .enable_mask = BIT(0),
1900                 .hw.init = &(struct clk_init_data){
1901                         .name = "gcc_blsp2_uart1_apps_clk",
1902                         .parent_names = (const char *[]){
1903                                 "blsp2_uart1_apps_clk_src",
1904                         },
1905                         .num_parents = 1,
1906                         .flags = CLK_SET_RATE_PARENT,
1907                         .ops = &clk_branch2_ops,
1908                 },
1909         },
1910 };
1911
1912 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1913         .halt_reg = 0x29004,
1914         .halt_check = BRANCH_HALT,
1915         .clkr = {
1916                 .enable_reg = 0x29004,
1917                 .enable_mask = BIT(0),
1918                 .hw.init = &(struct clk_init_data){
1919                         .name = "gcc_blsp2_uart2_apps_clk",
1920                         .parent_names = (const char *[]){
1921                                 "blsp2_uart2_apps_clk_src",
1922                         },
1923                         .num_parents = 1,
1924                         .flags = CLK_SET_RATE_PARENT,
1925                         .ops = &clk_branch2_ops,
1926                 },
1927         },
1928 };
1929
1930 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1931         .halt_reg = 0x2b004,
1932         .halt_check = BRANCH_HALT,
1933         .clkr = {
1934                 .enable_reg = 0x2b004,
1935                 .enable_mask = BIT(0),
1936                 .hw.init = &(struct clk_init_data){
1937                         .name = "gcc_blsp2_uart3_apps_clk",
1938                         .parent_names = (const char *[]){
1939                                 "blsp2_uart3_apps_clk_src",
1940                         },
1941                         .num_parents = 1,
1942                         .flags = CLK_SET_RATE_PARENT,
1943                         .ops = &clk_branch2_ops,
1944                 },
1945         },
1946 };
1947
1948 static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
1949         .halt_reg = 0x5018,
1950         .halt_check = BRANCH_HALT,
1951         .clkr = {
1952                 .enable_reg = 0x5018,
1953                 .enable_mask = BIT(0),
1954                 .hw.init = &(struct clk_init_data){
1955                         .name = "gcc_cfg_noc_usb3_axi_clk",
1956                         .parent_names = (const char *[]){
1957                                 "usb30_master_clk_src",
1958                         },
1959                         .num_parents = 1,
1960                         .flags = CLK_SET_RATE_PARENT,
1961                         .ops = &clk_branch2_ops,
1962                 },
1963         },
1964 };
1965
1966 static struct clk_branch gcc_gp1_clk = {
1967         .halt_reg = 0x64000,
1968         .halt_check = BRANCH_HALT,
1969         .clkr = {
1970                 .enable_reg = 0x64000,
1971                 .enable_mask = BIT(0),
1972                 .hw.init = &(struct clk_init_data){
1973                         .name = "gcc_gp1_clk",
1974                         .parent_names = (const char *[]){
1975                                 "gp1_clk_src",
1976                         },
1977                         .num_parents = 1,
1978                         .flags = CLK_SET_RATE_PARENT,
1979                         .ops = &clk_branch2_ops,
1980                 },
1981         },
1982 };
1983
1984 static struct clk_branch gcc_gp2_clk = {
1985         .halt_reg = 0x65000,
1986         .halt_check = BRANCH_HALT,
1987         .clkr = {
1988                 .enable_reg = 0x65000,
1989                 .enable_mask = BIT(0),
1990                 .hw.init = &(struct clk_init_data){
1991                         .name = "gcc_gp2_clk",
1992                         .parent_names = (const char *[]){
1993                                 "gp2_clk_src",
1994                         },
1995                         .num_parents = 1,
1996                         .flags = CLK_SET_RATE_PARENT,
1997                         .ops = &clk_branch2_ops,
1998                 },
1999         },
2000 };
2001
2002 static struct clk_branch gcc_gp3_clk = {
2003         .halt_reg = 0x66000,
2004         .halt_check = BRANCH_HALT,
2005         .clkr = {
2006                 .enable_reg = 0x66000,
2007                 .enable_mask = BIT(0),
2008                 .hw.init = &(struct clk_init_data){
2009                         .name = "gcc_gp3_clk",
2010                         .parent_names = (const char *[]){
2011                                 "gp3_clk_src",
2012                         },
2013                         .num_parents = 1,
2014                         .flags = CLK_SET_RATE_PARENT,
2015                         .ops = &clk_branch2_ops,
2016                 },
2017         },
2018 };
2019
2020 static struct clk_branch gcc_bimc_gfx_clk = {
2021         .halt_reg = 0x46040,
2022         .halt_check = BRANCH_HALT,
2023         .clkr = {
2024                 .enable_reg = 0x46040,
2025                 .enable_mask = BIT(0),
2026                 .hw.init = &(struct clk_init_data){
2027                         .name = "gcc_bimc_gfx_clk",
2028                         .ops = &clk_branch2_ops,
2029                 },
2030         },
2031 };
2032
2033 static struct clk_branch gcc_gpu_bimc_gfx_clk = {
2034         .halt_reg = 0x71010,
2035         .halt_check = BRANCH_HALT,
2036         .clkr = {
2037                 .enable_reg = 0x71010,
2038                 .enable_mask = BIT(0),
2039                 .hw.init = &(struct clk_init_data){
2040                         .name = "gcc_gpu_bimc_gfx_clk",
2041                         .ops = &clk_branch2_ops,
2042                 },
2043         },
2044 };
2045
2046 static struct clk_branch gcc_gpu_bimc_gfx_src_clk = {
2047         .halt_reg = 0x7100c,
2048         .halt_check = BRANCH_HALT,
2049         .clkr = {
2050                 .enable_reg = 0x7100c,
2051                 .enable_mask = BIT(0),
2052                 .hw.init = &(struct clk_init_data){
2053                         .name = "gcc_gpu_bimc_gfx_src_clk",
2054                         .ops = &clk_branch2_ops,
2055                 },
2056         },
2057 };
2058
2059 static struct clk_branch gcc_gpu_cfg_ahb_clk = {
2060         .halt_reg = 0x71004,
2061         .halt_check = BRANCH_HALT,
2062         .clkr = {
2063                 .enable_reg = 0x71004,
2064                 .enable_mask = BIT(0),
2065                 .hw.init = &(struct clk_init_data){
2066                         .name = "gcc_gpu_cfg_ahb_clk",
2067                         .ops = &clk_branch2_ops,
2068                 },
2069         },
2070 };
2071
2072 static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
2073         .halt_reg = 0x71018,
2074         .halt_check = BRANCH_HALT,
2075         .clkr = {
2076                 .enable_reg = 0x71018,
2077                 .enable_mask = BIT(0),
2078                 .hw.init = &(struct clk_init_data){
2079                         .name = "gcc_gpu_snoc_dvm_gfx_clk",
2080                         .ops = &clk_branch2_ops,
2081                 },
2082         },
2083 };
2084
2085 static struct clk_branch gcc_hmss_ahb_clk = {
2086         .halt_reg = 0x48000,
2087         .halt_check = BRANCH_HALT_VOTED,
2088         .clkr = {
2089                 .enable_reg = 0x52004,
2090                 .enable_mask = BIT(21),
2091                 .hw.init = &(struct clk_init_data){
2092                         .name = "gcc_hmss_ahb_clk",
2093                         .parent_names = (const char *[]){
2094                                 "hmss_ahb_clk_src",
2095                         },
2096                         .num_parents = 1,
2097                         .flags = CLK_SET_RATE_PARENT,
2098                         .ops = &clk_branch2_ops,
2099                 },
2100         },
2101 };
2102
2103 static struct clk_branch gcc_hmss_at_clk = {
2104         .halt_reg = 0x48010,
2105         .halt_check = BRANCH_HALT,
2106         .clkr = {
2107                 .enable_reg = 0x48010,
2108                 .enable_mask = BIT(0),
2109                 .hw.init = &(struct clk_init_data){
2110                         .name = "gcc_hmss_at_clk",
2111                         .ops = &clk_branch2_ops,
2112                 },
2113         },
2114 };
2115
2116 static struct clk_branch gcc_hmss_rbcpr_clk = {
2117         .halt_reg = 0x48008,
2118         .halt_check = BRANCH_HALT,
2119         .clkr = {
2120                 .enable_reg = 0x48008,
2121                 .enable_mask = BIT(0),
2122                 .hw.init = &(struct clk_init_data){
2123                         .name = "gcc_hmss_rbcpr_clk",
2124                         .parent_names = (const char *[]){
2125                                 "hmss_rbcpr_clk_src",
2126                         },
2127                         .num_parents = 1,
2128                         .flags = CLK_SET_RATE_PARENT,
2129                         .ops = &clk_branch2_ops,
2130                 },
2131         },
2132 };
2133
2134 static struct clk_branch gcc_hmss_trig_clk = {
2135         .halt_reg = 0x4800c,
2136         .halt_check = BRANCH_HALT,
2137         .clkr = {
2138                 .enable_reg = 0x4800c,
2139                 .enable_mask = BIT(0),
2140                 .hw.init = &(struct clk_init_data){
2141                         .name = "gcc_hmss_trig_clk",
2142                         .ops = &clk_branch2_ops,
2143                 },
2144         },
2145 };
2146
2147 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
2148         .halt_reg = 0x9004,
2149         .halt_check = BRANCH_HALT,
2150         .clkr = {
2151                 .enable_reg = 0x9004,
2152                 .enable_mask = BIT(0),
2153                 .hw.init = &(struct clk_init_data){
2154                         .name = "gcc_mmss_noc_cfg_ahb_clk",
2155                         .ops = &clk_branch2_ops,
2156                         /*
2157                          * Any access to mmss depends on this clock.
2158                          * Gating this clock has been shown to crash the system
2159                          * when mmssnoc_axi_rpm_clk is inited in rpmcc.
2160                          */
2161                         .flags = CLK_IS_CRITICAL,
2162                 },
2163         },
2164 };
2165
2166 static struct clk_branch gcc_mmss_qm_ahb_clk = {
2167         .halt_reg = 0x9030,
2168         .halt_check = BRANCH_HALT,
2169         .clkr = {
2170                 .enable_reg = 0x9030,
2171                 .enable_mask = BIT(0),
2172                 .hw.init = &(struct clk_init_data){
2173                         .name = "gcc_mmss_qm_ahb_clk",
2174                         .ops = &clk_branch2_ops,
2175                 },
2176         },
2177 };
2178
2179 static struct clk_branch gcc_mmss_qm_core_clk = {
2180         .halt_reg = 0x900c,
2181         .halt_check = BRANCH_HALT,
2182         .clkr = {
2183                 .enable_reg = 0x900c,
2184                 .enable_mask = BIT(0),
2185                 .hw.init = &(struct clk_init_data){
2186                         .name = "gcc_mmss_qm_core_clk",
2187                         .ops = &clk_branch2_ops,
2188                 },
2189         },
2190 };
2191
2192 static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
2193         .halt_reg = 0x9000,
2194         .halt_check = BRANCH_HALT,
2195         .clkr = {
2196                 .enable_reg = 0x9000,
2197                 .enable_mask = BIT(0),
2198                 .hw.init = &(struct clk_init_data){
2199                         .name = "gcc_mmss_sys_noc_axi_clk",
2200                         .ops = &clk_branch2_ops,
2201                 },
2202         },
2203 };
2204
2205 static struct clk_branch gcc_mss_at_clk = {
2206         .halt_reg = 0x8a00c,
2207         .halt_check = BRANCH_HALT,
2208         .clkr = {
2209                 .enable_reg = 0x8a00c,
2210                 .enable_mask = BIT(0),
2211                 .hw.init = &(struct clk_init_data){
2212                         .name = "gcc_mss_at_clk",
2213                         .ops = &clk_branch2_ops,
2214                 },
2215         },
2216 };
2217
2218 static struct clk_branch gcc_pcie_0_aux_clk = {
2219         .halt_reg = 0x6b014,
2220         .halt_check = BRANCH_HALT,
2221         .clkr = {
2222                 .enable_reg = 0x6b014,
2223                 .enable_mask = BIT(0),
2224                 .hw.init = &(struct clk_init_data){
2225                         .name = "gcc_pcie_0_aux_clk",
2226                         .parent_names = (const char *[]){
2227                                 "pcie_aux_clk_src",
2228                         },
2229                         .num_parents = 1,
2230                         .flags = CLK_SET_RATE_PARENT,
2231                         .ops = &clk_branch2_ops,
2232                 },
2233         },
2234 };
2235
2236 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2237         .halt_reg = 0x6b010,
2238         .halt_check = BRANCH_HALT,
2239         .clkr = {
2240                 .enable_reg = 0x6b010,
2241                 .enable_mask = BIT(0),
2242                 .hw.init = &(struct clk_init_data){
2243                         .name = "gcc_pcie_0_cfg_ahb_clk",
2244                         .ops = &clk_branch2_ops,
2245                 },
2246         },
2247 };
2248
2249 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2250         .halt_reg = 0x6b00c,
2251         .halt_check = BRANCH_HALT,
2252         .clkr = {
2253                 .enable_reg = 0x6b00c,
2254                 .enable_mask = BIT(0),
2255                 .hw.init = &(struct clk_init_data){
2256                         .name = "gcc_pcie_0_mstr_axi_clk",
2257                         .ops = &clk_branch2_ops,
2258                 },
2259         },
2260 };
2261
2262 static struct clk_branch gcc_pcie_0_pipe_clk = {
2263         .halt_reg = 0x6b018,
2264         .halt_check = BRANCH_HALT_SKIP,
2265         .clkr = {
2266                 .enable_reg = 0x6b018,
2267                 .enable_mask = BIT(0),
2268                 .hw.init = &(struct clk_init_data){
2269                         .name = "gcc_pcie_0_pipe_clk",
2270                         .ops = &clk_branch2_ops,
2271                 },
2272         },
2273 };
2274
2275 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2276         .halt_reg = 0x6b008,
2277         .halt_check = BRANCH_HALT,
2278         .clkr = {
2279                 .enable_reg = 0x6b008,
2280                 .enable_mask = BIT(0),
2281                 .hw.init = &(struct clk_init_data){
2282                         .name = "gcc_pcie_0_slv_axi_clk",
2283                         .ops = &clk_branch2_ops,
2284                 },
2285         },
2286 };
2287
2288 static struct clk_branch gcc_pcie_phy_aux_clk = {
2289         .halt_reg = 0x6f004,
2290         .halt_check = BRANCH_HALT,
2291         .clkr = {
2292                 .enable_reg = 0x6f004,
2293                 .enable_mask = BIT(0),
2294                 .hw.init = &(struct clk_init_data){
2295                         .name = "gcc_pcie_phy_aux_clk",
2296                         .parent_names = (const char *[]){
2297                                 "pcie_aux_clk_src",
2298                         },
2299                         .num_parents = 1,
2300                         .flags = CLK_SET_RATE_PARENT,
2301                         .ops = &clk_branch2_ops,
2302                 },
2303         },
2304 };
2305
2306 static struct clk_branch gcc_pdm2_clk = {
2307         .halt_reg = 0x3300c,
2308         .halt_check = BRANCH_HALT,
2309         .clkr = {
2310                 .enable_reg = 0x3300c,
2311                 .enable_mask = BIT(0),
2312                 .hw.init = &(struct clk_init_data){
2313                         .name = "gcc_pdm2_clk",
2314                         .parent_names = (const char *[]){
2315                                 "pdm2_clk_src",
2316                         },
2317                         .num_parents = 1,
2318                         .flags = CLK_SET_RATE_PARENT,
2319                         .ops = &clk_branch2_ops,
2320                 },
2321         },
2322 };
2323
2324 static struct clk_branch gcc_pdm_ahb_clk = {
2325         .halt_reg = 0x33004,
2326         .halt_check = BRANCH_HALT,
2327         .clkr = {
2328                 .enable_reg = 0x33004,
2329                 .enable_mask = BIT(0),
2330                 .hw.init = &(struct clk_init_data){
2331                         .name = "gcc_pdm_ahb_clk",
2332                         .ops = &clk_branch2_ops,
2333                 },
2334         },
2335 };
2336
2337 static struct clk_branch gcc_pdm_xo4_clk = {
2338         .halt_reg = 0x33008,
2339         .halt_check = BRANCH_HALT,
2340         .clkr = {
2341                 .enable_reg = 0x33008,
2342                 .enable_mask = BIT(0),
2343                 .hw.init = &(struct clk_init_data){
2344                         .name = "gcc_pdm_xo4_clk",
2345                         .ops = &clk_branch2_ops,
2346                 },
2347         },
2348 };
2349
2350 static struct clk_branch gcc_prng_ahb_clk = {
2351         .halt_reg = 0x34004,
2352         .halt_check = BRANCH_HALT_VOTED,
2353         .clkr = {
2354                 .enable_reg = 0x52004,
2355                 .enable_mask = BIT(13),
2356                 .hw.init = &(struct clk_init_data){
2357                         .name = "gcc_prng_ahb_clk",
2358                         .ops = &clk_branch2_ops,
2359                 },
2360         },
2361 };
2362
2363 static struct clk_branch gcc_sdcc2_ahb_clk = {
2364         .halt_reg = 0x14008,
2365         .halt_check = BRANCH_HALT,
2366         .clkr = {
2367                 .enable_reg = 0x14008,
2368                 .enable_mask = BIT(0),
2369                 .hw.init = &(struct clk_init_data){
2370                         .name = "gcc_sdcc2_ahb_clk",
2371                         .ops = &clk_branch2_ops,
2372                 },
2373         },
2374 };
2375
2376 static struct clk_branch gcc_sdcc2_apps_clk = {
2377         .halt_reg = 0x14004,
2378         .halt_check = BRANCH_HALT,
2379         .clkr = {
2380                 .enable_reg = 0x14004,
2381                 .enable_mask = BIT(0),
2382                 .hw.init = &(struct clk_init_data){
2383                         .name = "gcc_sdcc2_apps_clk",
2384                         .parent_names = (const char *[]){
2385                                 "sdcc2_apps_clk_src",
2386                         },
2387                         .num_parents = 1,
2388                         .flags = CLK_SET_RATE_PARENT,
2389                         .ops = &clk_branch2_ops,
2390                 },
2391         },
2392 };
2393
2394 static struct clk_branch gcc_sdcc4_ahb_clk = {
2395         .halt_reg = 0x16008,
2396         .halt_check = BRANCH_HALT,
2397         .clkr = {
2398                 .enable_reg = 0x16008,
2399                 .enable_mask = BIT(0),
2400                 .hw.init = &(struct clk_init_data){
2401                         .name = "gcc_sdcc4_ahb_clk",
2402                         .ops = &clk_branch2_ops,
2403                 },
2404         },
2405 };
2406
2407 static struct clk_branch gcc_sdcc4_apps_clk = {
2408         .halt_reg = 0x16004,
2409         .halt_check = BRANCH_HALT,
2410         .clkr = {
2411                 .enable_reg = 0x16004,
2412                 .enable_mask = BIT(0),
2413                 .hw.init = &(struct clk_init_data){
2414                         .name = "gcc_sdcc4_apps_clk",
2415                         .parent_names = (const char *[]){
2416                                 "sdcc4_apps_clk_src",
2417                         },
2418                         .num_parents = 1,
2419                         .flags = CLK_SET_RATE_PARENT,
2420                         .ops = &clk_branch2_ops,
2421                 },
2422         },
2423 };
2424
2425 static struct clk_branch gcc_tsif_ahb_clk = {
2426         .halt_reg = 0x36004,
2427         .halt_check = BRANCH_HALT,
2428         .clkr = {
2429                 .enable_reg = 0x36004,
2430                 .enable_mask = BIT(0),
2431                 .hw.init = &(struct clk_init_data){
2432                         .name = "gcc_tsif_ahb_clk",
2433                         .ops = &clk_branch2_ops,
2434                 },
2435         },
2436 };
2437
2438 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2439         .halt_reg = 0x3600c,
2440         .halt_check = BRANCH_HALT,
2441         .clkr = {
2442                 .enable_reg = 0x3600c,
2443                 .enable_mask = BIT(0),
2444                 .hw.init = &(struct clk_init_data){
2445                         .name = "gcc_tsif_inactivity_timers_clk",
2446                         .ops = &clk_branch2_ops,
2447                 },
2448         },
2449 };
2450
2451 static struct clk_branch gcc_tsif_ref_clk = {
2452         .halt_reg = 0x36008,
2453         .halt_check = BRANCH_HALT,
2454         .clkr = {
2455                 .enable_reg = 0x36008,
2456                 .enable_mask = BIT(0),
2457                 .hw.init = &(struct clk_init_data){
2458                         .name = "gcc_tsif_ref_clk",
2459                         .parent_names = (const char *[]){
2460                                 "tsif_ref_clk_src",
2461                         },
2462                         .num_parents = 1,
2463                         .flags = CLK_SET_RATE_PARENT,
2464                         .ops = &clk_branch2_ops,
2465                 },
2466         },
2467 };
2468
2469 static struct clk_branch gcc_ufs_ahb_clk = {
2470         .halt_reg = 0x7500c,
2471         .halt_check = BRANCH_HALT,
2472         .clkr = {
2473                 .enable_reg = 0x7500c,
2474                 .enable_mask = BIT(0),
2475                 .hw.init = &(struct clk_init_data){
2476                         .name = "gcc_ufs_ahb_clk",
2477                         .ops = &clk_branch2_ops,
2478                 },
2479         },
2480 };
2481
2482 static struct clk_branch gcc_ufs_axi_clk = {
2483         .halt_reg = 0x75008,
2484         .halt_check = BRANCH_HALT,
2485         .clkr = {
2486                 .enable_reg = 0x75008,
2487                 .enable_mask = BIT(0),
2488                 .hw.init = &(struct clk_init_data){
2489                         .name = "gcc_ufs_axi_clk",
2490                         .parent_names = (const char *[]){
2491                                 "ufs_axi_clk_src",
2492                         },
2493                         .num_parents = 1,
2494                         .flags = CLK_SET_RATE_PARENT,
2495                         .ops = &clk_branch2_ops,
2496                 },
2497         },
2498 };
2499
2500 static struct clk_branch gcc_ufs_ice_core_clk = {
2501         .halt_reg = 0x7600c,
2502         .halt_check = BRANCH_HALT,
2503         .clkr = {
2504                 .enable_reg = 0x7600c,
2505                 .enable_mask = BIT(0),
2506                 .hw.init = &(struct clk_init_data){
2507                         .name = "gcc_ufs_ice_core_clk",
2508                         .ops = &clk_branch2_ops,
2509                 },
2510         },
2511 };
2512
2513 static struct clk_branch gcc_ufs_phy_aux_clk = {
2514         .halt_reg = 0x76040,
2515         .halt_check = BRANCH_HALT,
2516         .clkr = {
2517                 .enable_reg = 0x76040,
2518                 .enable_mask = BIT(0),
2519                 .hw.init = &(struct clk_init_data){
2520                         .name = "gcc_ufs_phy_aux_clk",
2521                         .ops = &clk_branch2_ops,
2522                 },
2523         },
2524 };
2525
2526 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2527         .halt_reg = 0x75014,
2528         .halt_check = BRANCH_HALT_SKIP,
2529         .clkr = {
2530                 .enable_reg = 0x75014,
2531                 .enable_mask = BIT(0),
2532                 .hw.init = &(struct clk_init_data){
2533                         .name = "gcc_ufs_rx_symbol_0_clk",
2534                         .ops = &clk_branch2_ops,
2535                 },
2536         },
2537 };
2538
2539 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2540         .halt_reg = 0x7605c,
2541         .halt_check = BRANCH_HALT_SKIP,
2542         .clkr = {
2543                 .enable_reg = 0x7605c,
2544                 .enable_mask = BIT(0),
2545                 .hw.init = &(struct clk_init_data){
2546                         .name = "gcc_ufs_rx_symbol_1_clk",
2547                         .ops = &clk_branch2_ops,
2548                 },
2549         },
2550 };
2551
2552 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2553         .halt_reg = 0x75010,
2554         .halt_check = BRANCH_HALT_SKIP,
2555         .clkr = {
2556                 .enable_reg = 0x75010,
2557                 .enable_mask = BIT(0),
2558                 .hw.init = &(struct clk_init_data){
2559                         .name = "gcc_ufs_tx_symbol_0_clk",
2560                         .ops = &clk_branch2_ops,
2561                 },
2562         },
2563 };
2564
2565 static struct clk_branch gcc_ufs_unipro_core_clk = {
2566         .halt_reg = 0x76008,
2567         .halt_check = BRANCH_HALT,
2568         .clkr = {
2569                 .enable_reg = 0x76008,
2570                 .enable_mask = BIT(0),
2571                 .hw.init = &(struct clk_init_data){
2572                         .name = "gcc_ufs_unipro_core_clk",
2573                         .parent_names = (const char *[]){
2574                                 "ufs_unipro_core_clk_src",
2575                         },
2576                         .num_parents = 1,
2577                         .flags = CLK_SET_RATE_PARENT,
2578                         .ops = &clk_branch2_ops,
2579                 },
2580         },
2581 };
2582
2583 static struct clk_branch gcc_usb30_master_clk = {
2584         .halt_reg = 0xf008,
2585         .halt_check = BRANCH_HALT,
2586         .clkr = {
2587                 .enable_reg = 0xf008,
2588                 .enable_mask = BIT(0),
2589                 .hw.init = &(struct clk_init_data){
2590                         .name = "gcc_usb30_master_clk",
2591                         .parent_names = (const char *[]){
2592                                 "usb30_master_clk_src",
2593                         },
2594                         .num_parents = 1,
2595                         .flags = CLK_SET_RATE_PARENT,
2596                         .ops = &clk_branch2_ops,
2597                 },
2598         },
2599 };
2600
2601 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2602         .halt_reg = 0xf010,
2603         .halt_check = BRANCH_HALT,
2604         .clkr = {
2605                 .enable_reg = 0xf010,
2606                 .enable_mask = BIT(0),
2607                 .hw.init = &(struct clk_init_data){
2608                         .name = "gcc_usb30_mock_utmi_clk",
2609                         .parent_names = (const char *[]){
2610                                 "usb30_mock_utmi_clk_src",
2611                         },
2612                         .num_parents = 1,
2613                         .flags = CLK_SET_RATE_PARENT,
2614                         .ops = &clk_branch2_ops,
2615                 },
2616         },
2617 };
2618
2619 static struct clk_branch gcc_usb30_sleep_clk = {
2620         .halt_reg = 0xf00c,
2621         .halt_check = BRANCH_HALT,
2622         .clkr = {
2623                 .enable_reg = 0xf00c,
2624                 .enable_mask = BIT(0),
2625                 .hw.init = &(struct clk_init_data){
2626                         .name = "gcc_usb30_sleep_clk",
2627                         .ops = &clk_branch2_ops,
2628                 },
2629         },
2630 };
2631
2632 static struct clk_branch gcc_usb3_phy_aux_clk = {
2633         .halt_reg = 0x50000,
2634         .halt_check = BRANCH_HALT,
2635         .clkr = {
2636                 .enable_reg = 0x50000,
2637                 .enable_mask = BIT(0),
2638                 .hw.init = &(struct clk_init_data){
2639                         .name = "gcc_usb3_phy_aux_clk",
2640                         .parent_names = (const char *[]){
2641                                 "usb3_phy_aux_clk_src",
2642                         },
2643                         .num_parents = 1,
2644                         .flags = CLK_SET_RATE_PARENT,
2645                         .ops = &clk_branch2_ops,
2646                 },
2647         },
2648 };
2649
2650 static struct clk_branch gcc_usb3_phy_pipe_clk = {
2651         .halt_reg = 0x50004,
2652         .halt_check = BRANCH_HALT_SKIP,
2653         .clkr = {
2654                 .enable_reg = 0x50004,
2655                 .enable_mask = BIT(0),
2656                 .hw.init = &(struct clk_init_data){
2657                         .name = "gcc_usb3_phy_pipe_clk",
2658                         .ops = &clk_branch2_ops,
2659                 },
2660         },
2661 };
2662
2663 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2664         .halt_reg = 0x6a004,
2665         .halt_check = BRANCH_HALT,
2666         .clkr = {
2667                 .enable_reg = 0x6a004,
2668                 .enable_mask = BIT(0),
2669                 .hw.init = &(struct clk_init_data){
2670                         .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2671                         .ops = &clk_branch2_ops,
2672                 },
2673         },
2674 };
2675
2676 static struct clk_branch gcc_hdmi_clkref_clk = {
2677         .halt_reg = 0x88000,
2678         .clkr = {
2679                 .enable_reg = 0x88000,
2680                 .enable_mask = BIT(0),
2681                 .hw.init = &(struct clk_init_data){
2682                         .name = "gcc_hdmi_clkref_clk",
2683                         .parent_names = (const char *[]){ "xo" },
2684                         .num_parents = 1,
2685                         .ops = &clk_branch2_ops,
2686                 },
2687         },
2688 };
2689
2690 static struct clk_branch gcc_ufs_clkref_clk = {
2691         .halt_reg = 0x88004,
2692         .clkr = {
2693                 .enable_reg = 0x88004,
2694                 .enable_mask = BIT(0),
2695                 .hw.init = &(struct clk_init_data){
2696                         .name = "gcc_ufs_clkref_clk",
2697                         .parent_names = (const char *[]){ "xo" },
2698                         .num_parents = 1,
2699                         .ops = &clk_branch2_ops,
2700                 },
2701         },
2702 };
2703
2704 static struct clk_branch gcc_usb3_clkref_clk = {
2705         .halt_reg = 0x88008,
2706         .clkr = {
2707                 .enable_reg = 0x88008,
2708                 .enable_mask = BIT(0),
2709                 .hw.init = &(struct clk_init_data){
2710                         .name = "gcc_usb3_clkref_clk",
2711                         .parent_names = (const char *[]){ "xo" },
2712                         .num_parents = 1,
2713                         .ops = &clk_branch2_ops,
2714                 },
2715         },
2716 };
2717
2718 static struct clk_branch gcc_pcie_clkref_clk = {
2719         .halt_reg = 0x8800c,
2720         .clkr = {
2721                 .enable_reg = 0x8800c,
2722                 .enable_mask = BIT(0),
2723                 .hw.init = &(struct clk_init_data){
2724                         .name = "gcc_pcie_clkref_clk",
2725                         .parent_names = (const char *[]){ "xo" },
2726                         .num_parents = 1,
2727                         .ops = &clk_branch2_ops,
2728                 },
2729         },
2730 };
2731
2732 static struct clk_branch gcc_rx1_usb2_clkref_clk = {
2733         .halt_reg = 0x88014,
2734         .clkr = {
2735                 .enable_reg = 0x88014,
2736                 .enable_mask = BIT(0),
2737                 .hw.init = &(struct clk_init_data){
2738                         .name = "gcc_rx1_usb2_clkref_clk",
2739                         .parent_names = (const char *[]){ "xo" },
2740                         .num_parents = 1,
2741                         .ops = &clk_branch2_ops,
2742                 },
2743         },
2744 };
2745
2746 static struct gdsc pcie_0_gdsc = {
2747         .gdscr = 0x6b004,
2748         .gds_hw_ctrl = 0x0,
2749         .pd = {
2750                 .name = "pcie_0_gdsc",
2751         },
2752         .pwrsts = PWRSTS_OFF_ON,
2753         .flags = VOTABLE,
2754 };
2755
2756 static struct gdsc ufs_gdsc = {
2757         .gdscr = 0x75004,
2758         .gds_hw_ctrl = 0x0,
2759         .pd = {
2760                 .name = "ufs_gdsc",
2761         },
2762         .pwrsts = PWRSTS_OFF_ON,
2763         .flags = VOTABLE,
2764 };
2765
2766 static struct gdsc usb_30_gdsc = {
2767         .gdscr = 0xf004,
2768         .gds_hw_ctrl = 0x0,
2769         .pd = {
2770                 .name = "usb_30_gdsc",
2771         },
2772         .pwrsts = PWRSTS_OFF_ON,
2773         .flags = VOTABLE,
2774 };
2775
2776 static struct clk_regmap *gcc_msm8998_clocks[] = {
2777         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2778         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2779         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2780         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2781         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2782         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2783         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2784         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2785         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2786         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2787         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2788         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2789         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2790         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2791         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2792         [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2793         [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2794         [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2795         [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2796         [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2797         [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2798         [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2799         [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2800         [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2801         [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2802         [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2803         [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2804         [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2805         [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2806         [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2807         [GCC_AGGRE1_NOC_XO_CLK] = &gcc_aggre1_noc_xo_clk.clkr,
2808         [GCC_AGGRE1_UFS_AXI_CLK] = &gcc_aggre1_ufs_axi_clk.clkr,
2809         [GCC_AGGRE1_USB3_AXI_CLK] = &gcc_aggre1_usb3_axi_clk.clkr,
2810         [GCC_APSS_QDSS_TSCTR_DIV2_CLK] = &gcc_apss_qdss_tsctr_div2_clk.clkr,
2811         [GCC_APSS_QDSS_TSCTR_DIV8_CLK] = &gcc_apss_qdss_tsctr_div8_clk.clkr,
2812         [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
2813         [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
2814         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2815         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2816         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2817         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2818         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2819         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2820         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2821         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2822         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2823         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2824         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2825         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2826         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2827         [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
2828         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2829         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2830         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2831         [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2832         [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2833         [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2834         [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2835         [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2836         [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2837         [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2838         [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2839         [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2840         [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2841         [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2842         [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2843         [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2844         [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
2845         [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2846         [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2847         [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2848         [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
2849         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2850         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2851         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2852         [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
2853         [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
2854         [GCC_GPU_BIMC_GFX_SRC_CLK] = &gcc_gpu_bimc_gfx_src_clk.clkr,
2855         [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
2856         [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
2857         [GCC_HMSS_AHB_CLK] = &gcc_hmss_ahb_clk.clkr,
2858         [GCC_HMSS_AT_CLK] = &gcc_hmss_at_clk.clkr,
2859         [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
2860         [GCC_HMSS_TRIG_CLK] = &gcc_hmss_trig_clk.clkr,
2861         [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
2862         [GCC_MMSS_QM_AHB_CLK] = &gcc_mmss_qm_ahb_clk.clkr,
2863         [GCC_MMSS_QM_CORE_CLK] = &gcc_mmss_qm_core_clk.clkr,
2864         [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
2865         [GCC_MSS_AT_CLK] = &gcc_mss_at_clk.clkr,
2866         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2867         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2868         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2869         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2870         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2871         [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
2872         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2873         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2874         [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2875         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2876         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2877         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2878         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2879         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2880         [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2881         [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
2882         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2883         [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
2884         [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2885         [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
2886         [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
2887         [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
2888         [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
2889         [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
2890         [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
2891         [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2892         [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2893         [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2894         [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2895         [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2896         [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2897         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2898         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2899         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2900         [GPLL0] = &gpll0.clkr,
2901         [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
2902         [GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
2903         [GPLL0_OUT_ODD] = &gpll0_out_odd.clkr,
2904         [GPLL0_OUT_TEST] = &gpll0_out_test.clkr,
2905         [GPLL1] = &gpll1.clkr,
2906         [GPLL1_OUT_EVEN] = &gpll1_out_even.clkr,
2907         [GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,
2908         [GPLL1_OUT_ODD] = &gpll1_out_odd.clkr,
2909         [GPLL1_OUT_TEST] = &gpll1_out_test.clkr,
2910         [GPLL2] = &gpll2.clkr,
2911         [GPLL2_OUT_EVEN] = &gpll2_out_even.clkr,
2912         [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr,
2913         [GPLL2_OUT_ODD] = &gpll2_out_odd.clkr,
2914         [GPLL2_OUT_TEST] = &gpll2_out_test.clkr,
2915         [GPLL3] = &gpll3.clkr,
2916         [GPLL3_OUT_EVEN] = &gpll3_out_even.clkr,
2917         [GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
2918         [GPLL3_OUT_ODD] = &gpll3_out_odd.clkr,
2919         [GPLL3_OUT_TEST] = &gpll3_out_test.clkr,
2920         [GPLL4] = &gpll4.clkr,
2921         [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr,
2922         [GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
2923         [GPLL4_OUT_ODD] = &gpll4_out_odd.clkr,
2924         [GPLL4_OUT_TEST] = &gpll4_out_test.clkr,
2925         [HMSS_AHB_CLK_SRC] = &hmss_ahb_clk_src.clkr,
2926         [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
2927         [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
2928         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2929         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2930         [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2931         [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2932         [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2933         [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr,
2934         [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2935         [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2936         [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2937         [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
2938         [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
2939         [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
2940         [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
2941         [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
2942         [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2943         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2944         [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
2945         [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
2946         [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
2947 };
2948
2949 static struct gdsc *gcc_msm8998_gdscs[] = {
2950         [PCIE_0_GDSC] = &pcie_0_gdsc,
2951         [UFS_GDSC] = &ufs_gdsc,
2952         [USB_30_GDSC] = &usb_30_gdsc,
2953 };
2954
2955 static const struct qcom_reset_map gcc_msm8998_resets[] = {
2956         [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
2957         [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
2958         [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
2959         [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
2960         [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
2961         [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
2962         [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
2963         [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
2964         [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
2965         [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
2966         [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
2967         [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
2968         [GCC_PCIE_0_BCR] = { 0x6b000 },
2969         [GCC_PDM_BCR] = { 0x33000 },
2970         [GCC_SDCC2_BCR] = { 0x14000 },
2971         [GCC_SDCC4_BCR] = { 0x16000 },
2972         [GCC_TSIF_BCR] = { 0x36000 },
2973         [GCC_UFS_BCR] = { 0x75000 },
2974         [GCC_USB_30_BCR] = { 0xf000 },
2975         [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
2976         [GCC_CONFIG_NOC_BCR] = { 0x5000 },
2977         [GCC_AHB2PHY_EAST_BCR] = { 0x7000 },
2978         [GCC_IMEM_BCR] = { 0x8000 },
2979         [GCC_PIMEM_BCR] = { 0xa000 },
2980         [GCC_MMSS_BCR] = { 0xb000 },
2981         [GCC_QDSS_BCR] = { 0xc000 },
2982         [GCC_WCSS_BCR] = { 0x11000 },
2983         [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
2984         [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
2985         [GCC_BLSP1_BCR] = { 0x17000 },
2986         [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
2987         [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
2988         [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
2989         [GCC_CM_PHY_REFGEN1_BCR] = { 0x22000 },
2990         [GCC_CM_PHY_REFGEN2_BCR] = { 0x24000 },
2991         [GCC_BLSP2_BCR] = { 0x25000 },
2992         [GCC_BLSP2_UART1_BCR] = { 0x27000 },
2993         [GCC_BLSP2_UART2_BCR] = { 0x29000 },
2994         [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
2995         [GCC_SRAM_SENSOR_BCR] = { 0x2d000 },
2996         [GCC_PRNG_BCR] = { 0x34000 },
2997         [GCC_TSIF_0_RESET] = { 0x36024 },
2998         [GCC_TSIF_1_RESET] = { 0x36028 },
2999         [GCC_TCSR_BCR] = { 0x37000 },
3000         [GCC_BOOT_ROM_BCR] = { 0x38000 },
3001         [GCC_MSG_RAM_BCR] = { 0x39000 },
3002         [GCC_TLMM_BCR] = { 0x3a000 },
3003         [GCC_MPM_BCR] = { 0x3b000 },
3004         [GCC_SEC_CTRL_BCR] = { 0x3d000 },
3005         [GCC_SPMI_BCR] = { 0x3f000 },
3006         [GCC_SPDM_BCR] = { 0x40000 },
3007         [GCC_CE1_BCR] = { 0x41000 },
3008         [GCC_BIMC_BCR] = { 0x44000 },
3009         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
3010         [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49008 },
3011         [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49010 },
3012         [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49018 },
3013         [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
3014         [GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR] = { 0x4a004 },
3015         [GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR] = { 0x4a00c },
3016         [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
3017         [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
3018         [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
3019         [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
3020         [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
3021         [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
3022         [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
3023         [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
3024         [GCC_APB2JTAG_BCR] = { 0x4c000 },
3025         [GCC_RBCPR_CX_BCR] = { 0x4e000 },
3026         [GCC_RBCPR_MX_BCR] = { 0x4f000 },
3027         [GCC_USB3_PHY_BCR] = { 0x50020 },
3028         [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
3029         [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
3030         [GCC_SSC_BCR] = { 0x63000 },
3031         [GCC_SSC_RESET] = { 0x63020 },
3032         [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3033         [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3034         [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3035         [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3036         [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3037         [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00c },
3038         [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f010 },
3039         [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
3040         [GCC_GPU_BCR] = { 0x71000 },
3041         [GCC_SPSS_BCR] = { 0x72000 },
3042         [GCC_OBT_ODT_BCR] = { 0x73000 },
3043         [GCC_MSS_RESTART] = { 0x79000 },
3044         [GCC_VS_BCR] = { 0x7a000 },
3045         [GCC_MSS_VS_RESET] = { 0x7a100 },
3046         [GCC_GPU_VS_RESET] = { 0x7a104 },
3047         [GCC_APC0_VS_RESET] = { 0x7a108 },
3048         [GCC_APC1_VS_RESET] = { 0x7a10c },
3049         [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
3050         [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
3051         [GCC_CNOC_BUS_TIMEOUT10_BCR] = { 0x80010 },
3052         [GCC_CNOC_BUS_TIMEOUT11_BCR] = { 0x80018 },
3053         [GCC_CNOC_BUS_TIMEOUT12_BCR] = { 0x80020 },
3054         [GCC_CNOC_BUS_TIMEOUT13_BCR] = { 0x80028 },
3055         [GCC_CNOC_BUS_TIMEOUT14_BCR] = { 0x80030 },
3056         [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80038 },
3057         [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
3058         [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
3059         [GCC_DCC_BCR] = { 0x84000 },
3060         [GCC_QREFS_VBG_CAL_BCR] = { 0x88028 },
3061         [GCC_IPA_BCR] = { 0x89000 },
3062         [GCC_GLM_BCR] = { 0x8b000 },
3063         [GCC_SKL_BCR] = { 0x8c000 },
3064         [GCC_MSMPU_BCR] = { 0x8d000 },
3065 };
3066
3067 static const struct regmap_config gcc_msm8998_regmap_config = {
3068         .reg_bits       = 32,
3069         .reg_stride     = 4,
3070         .val_bits       = 32,
3071         .max_register   = 0x8f000,
3072         .fast_io        = true,
3073 };
3074
3075 static struct clk_hw *gcc_msm8998_hws[] = {
3076         &xo.hw,
3077 };
3078
3079 static const struct qcom_cc_desc gcc_msm8998_desc = {
3080         .config = &gcc_msm8998_regmap_config,
3081         .clks = gcc_msm8998_clocks,
3082         .num_clks = ARRAY_SIZE(gcc_msm8998_clocks),
3083         .resets = gcc_msm8998_resets,
3084         .num_resets = ARRAY_SIZE(gcc_msm8998_resets),
3085         .gdscs = gcc_msm8998_gdscs,
3086         .num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs),
3087         .clk_hws = gcc_msm8998_hws,
3088         .num_clk_hws = ARRAY_SIZE(gcc_msm8998_hws),
3089 };
3090
3091 static int gcc_msm8998_probe(struct platform_device *pdev)
3092 {
3093         struct regmap *regmap;
3094         int ret;
3095
3096         regmap = qcom_cc_map(pdev, &gcc_msm8998_desc);
3097         if (IS_ERR(regmap))
3098                 return PTR_ERR(regmap);
3099
3100         /*
3101          * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
3102          * turned off by hardware during certain apps low power modes.
3103          */
3104         ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
3105         if (ret)
3106                 return ret;
3107
3108         return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap);
3109 }
3110
3111 static const struct of_device_id gcc_msm8998_match_table[] = {
3112         { .compatible = "qcom,gcc-msm8998" },
3113         { }
3114 };
3115 MODULE_DEVICE_TABLE(of, gcc_msm8998_match_table);
3116
3117 static struct platform_driver gcc_msm8998_driver = {
3118         .probe          = gcc_msm8998_probe,
3119         .driver         = {
3120                 .name   = "gcc-msm8998",
3121                 .of_match_table = gcc_msm8998_match_table,
3122         },
3123 };
3124
3125 static int __init gcc_msm8998_init(void)
3126 {
3127         return platform_driver_register(&gcc_msm8998_driver);
3128 }
3129 core_initcall(gcc_msm8998_init);
3130
3131 static void __exit gcc_msm8998_exit(void)
3132 {
3133         platform_driver_unregister(&gcc_msm8998_driver);
3134 }
3135 module_exit(gcc_msm8998_exit);
3136
3137 MODULE_DESCRIPTION("QCOM GCC msm8998 Driver");
3138 MODULE_LICENSE("GPL v2");
3139 MODULE_ALIAS("platform:gcc-msm8998");