drivers/clk/qcom/gcc-msm8996.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset-controller.h>
  16
  17 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
  18
  19 #include "common.h"
  20 #include "clk-regmap.h"
  21 #include "clk-alpha-pll.h"
  22 #include "clk-rcg.h"
  23 #include "clk-branch.h"
  24 #include "reset.h"
  25 #include "gdsc.h"
  26
  27 enum {
  28         P_XO,
  29         P_GPLL0,
  30         P_GPLL0_EARLY_DIV,
  31         P_SLEEP_CLK,
  32         P_GPLL4,
  33         P_AUD_REF_CLK,
  34 };
  35
  36 static struct clk_fixed_factor xo = {
  37         .mult = 1,
  38         .div = 1,
  39         .hw.init = &(struct clk_init_data){
  40                 .name = "xo",
  41                 .parent_data = &(const struct clk_parent_data){
  42                         .fw_name = "cxo", .name = "xo_board",
  43                 },
  44                 .num_parents = 1,
  45                 .ops = &clk_fixed_factor_ops,
  46         },
  47 };
  48
  49 static struct clk_alpha_pll gpll0_early = {
  50         .offset = 0x00000,
  51         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  52         .clkr = {
  53                 .enable_reg = 0x52000,
  54                 .enable_mask = BIT(0),
  55                 .hw.init = &(struct clk_init_data){
  56                         .name = "gpll0_early",
  57                         .parent_data = &(const struct clk_parent_data){
  58                                 .fw_name = "cxo", .name = "xo_board",
  59                         },
  60                         .num_parents = 1,
  61                         .ops = &clk_alpha_pll_ops,
  62                 },
  63         },
  64 };
  65
  66 static struct clk_fixed_factor gpll0_early_div = {
  67         .mult = 1,
  68         .div = 2,
  69         .hw.init = &(struct clk_init_data){
  70                 .name = "gpll0_early_div",
  71                 .parent_hws = (const struct clk_hw*[]){
  72                         &gpll0_early.clkr.hw,
  73                 },
  74                 .num_parents = 1,
  75                 .ops = &clk_fixed_factor_ops,
  76         },
  77 };
  78
  79 static struct clk_alpha_pll_postdiv gpll0 = {
  80         .offset = 0x00000,
  81         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  82         .clkr.hw.init = &(struct clk_init_data){
  83                 .name = "gpll0",
  84                 .parent_hws = (const struct clk_hw*[]){
  85                         &gpll0_early.clkr.hw,
  86                 },
  87                 .num_parents = 1,
  88                 .ops = &clk_alpha_pll_postdiv_ops,
  89         },
  90 };
  91
  92 static struct clk_branch gcc_mmss_gpll0_div_clk = {
  93         .halt_check = BRANCH_HALT_DELAY,
  94         .clkr = {
  95                 .enable_reg = 0x5200c,
  96                 .enable_mask = BIT(0),
  97                 .hw.init = &(struct clk_init_data){
  98                         .name = "gcc_mmss_gpll0_div_clk",
  99                         .parent_hws = (const struct clk_hw*[]){
 100                                 &gpll0.clkr.hw,
 101                         },
 102                         .num_parents = 1,
 103                         .flags = CLK_SET_RATE_PARENT,
 104                         .ops = &clk_branch2_ops,
 105                 },
 106         },
 107 };
 108
 109 static struct clk_branch gcc_mss_gpll0_div_clk = {
 110         .halt_check = BRANCH_HALT_DELAY,
 111         .clkr = {
 112                 .enable_reg = 0x5200c,
 113                 .enable_mask = BIT(2),
 114                 .hw.init = &(struct clk_init_data){
 115                         .name = "gcc_mss_gpll0_div_clk",
 116                         .parent_hws = (const struct clk_hw*[]){
 117                                 &gpll0.clkr.hw,
 118                         },
 119                         .num_parents = 1,
 120                         .flags = CLK_SET_RATE_PARENT,
 121                         .ops = &clk_branch2_ops
 122                 },
 123         },
 124 };
 125
 126 static struct clk_alpha_pll gpll4_early = {
 127         .offset = 0x77000,
 128         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 129         .clkr = {
 130                 .enable_reg = 0x52000,
 131                 .enable_mask = BIT(4),
 132                 .hw.init = &(struct clk_init_data){
 133                         .name = "gpll4_early",
 134                         .parent_data = &(const struct clk_parent_data){
 135                                 .fw_name = "cxo", .name = "xo_board",
 136                         },
 137                         .num_parents = 1,
 138                         .ops = &clk_alpha_pll_ops,
 139                 },
 140         },
 141 };
 142
 143 static struct clk_alpha_pll_postdiv gpll4 = {
 144         .offset = 0x77000,
 145         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 146         .clkr.hw.init = &(struct clk_init_data){
 147                 .name = "gpll4",
 148                 .parent_hws = (const struct clk_hw*[]){
 149                         &gpll4_early.clkr.hw,
 150                 },
 151                 .num_parents = 1,
 152                 .ops = &clk_alpha_pll_postdiv_ops,
 153         },
 154 };
 155
 156 static const struct parent_map gcc_sleep_clk_map[] = {
 157         { P_SLEEP_CLK, 5 }
 158 };
 159
 160 static const struct clk_parent_data gcc_sleep_clk[] = {
 161         { .fw_name = "sleep_clk", .name = "sleep_clk" }
 162 };
 163
 164 static const struct parent_map gcc_xo_gpll0_map[] = {
 165         { P_XO, 0 },
 166         { P_GPLL0, 1 }
 167 };
 168
 169 static const struct clk_parent_data gcc_xo_gpll0[] = {
 170         { .fw_name = "cxo", .name = "xo_board" },
 171         { .hw = &gpll0.clkr.hw }
 172 };
 173
 174 static const struct parent_map gcc_xo_sleep_clk_map[] = {
 175         { P_XO, 0 },
 176         { P_SLEEP_CLK, 5 }
 177 };
 178
 179 static const struct clk_parent_data gcc_xo_sleep_clk[] = {
 180         { .fw_name = "cxo", .name = "xo_board" },
 181         { .fw_name = "sleep_clk", .name = "sleep_clk" }
 182 };
 183
 184 static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
 185         { P_XO, 0 },
 186         { P_GPLL0, 1 },
 187         { P_GPLL0_EARLY_DIV, 6 }
 188 };
 189
 190 static const struct clk_parent_data gcc_xo_gpll0_gpll0_early_div[] = {
 191         { .fw_name = "cxo", .name = "xo_board" },
 192         { .hw = &gpll0.clkr.hw },
 193         { .hw = &gpll0_early_div.hw }
 194 };
 195
 196 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
 197         { P_XO, 0 },
 198         { P_GPLL0, 1 },
 199         { P_GPLL4, 5 }
 200 };
 201
 202 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
 203         { .fw_name = "cxo", .name = "xo_board" },
 204         { .hw = &gpll0.clkr.hw },
 205         { .hw = &gpll4.clkr.hw }
 206 };
 207
 208 static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
 209         { P_XO, 0 },
 210         { P_GPLL0, 1 },
 211         { P_AUD_REF_CLK, 2 }
 212 };
 213
 214 static const struct clk_parent_data gcc_xo_gpll0_aud_ref_clk[] = {
 215         { .fw_name = "cxo", .name = "xo_board" },
 216         { .hw = &gpll0.clkr.hw },
 217         { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }
 218 };
 219
 220 static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
 221         { P_XO, 0 },
 222         { P_GPLL0, 1 },
 223         { P_SLEEP_CLK, 5 },
 224         { P_GPLL0_EARLY_DIV, 6 }
 225 };
 226
 227 static const struct clk_parent_data gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
 228         { .fw_name = "cxo", .name = "xo_board" },
 229         { .hw = &gpll0.clkr.hw },
 230         { .fw_name = "sleep_clk", .name = "sleep_clk" },
 231         { .hw = &gpll0_early_div.hw }
 232 };
 233
 234 static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
 235         { P_XO, 0 },
 236         { P_GPLL0, 1 },
 237         { P_GPLL4, 5 },
 238         { P_GPLL0_EARLY_DIV, 6 }
 239 };
 240
 241 static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
 242         { .fw_name = "cxo", .name = "xo_board" },
 243         { .hw = &gpll0.clkr.hw },
 244         { .hw = &gpll4.clkr.hw },
 245         { .hw = &gpll0_early_div.hw }
 246 };
 247
 248 static const struct freq_tbl ftbl_system_noc_clk_src[] = {
 249         F(19200000, P_XO, 1, 0, 0),
 250         F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
 251         F(100000000, P_GPLL0, 6, 0, 0),
 252         F(150000000, P_GPLL0, 4, 0, 0),
 253         F(200000000, P_GPLL0, 3, 0, 0),
 254         F(240000000, P_GPLL0, 2.5, 0, 0),
 255         { }
 256 };
 257
 258 static struct clk_rcg2 system_noc_clk_src = {
 259         .cmd_rcgr = 0x0401c,
 260         .hid_width = 5,
 261         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 262         .freq_tbl = ftbl_system_noc_clk_src,
 263         .clkr.hw.init = &(struct clk_init_data){
 264                 .name = "system_noc_clk_src",
 265                 .parent_data = gcc_xo_gpll0_gpll0_early_div,
 266                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
 267                 .ops = &clk_rcg2_ops,
 268         },
 269 };
 270
 271 static const struct freq_tbl ftbl_config_noc_clk_src[] = {
 272         F(19200000, P_XO, 1, 0, 0),
 273         F(37500000, P_GPLL0, 16, 0, 0),
 274         F(75000000, P_GPLL0, 8, 0, 0),
 275         { }
 276 };
 277
 278 static struct clk_rcg2 config_noc_clk_src = {
 279         .cmd_rcgr = 0x0500c,
 280         .hid_width = 5,
 281         .parent_map = gcc_xo_gpll0_map,
 282         .freq_tbl = ftbl_config_noc_clk_src,
 283         .clkr.hw.init = &(struct clk_init_data){
 284                 .name = "config_noc_clk_src",
 285                 .parent_data = gcc_xo_gpll0,
 286                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 287                 .ops = &clk_rcg2_ops,
 288         },
 289 };
 290
 291 static const struct freq_tbl ftbl_periph_noc_clk_src[] = {
 292         F(19200000, P_XO, 1, 0, 0),
 293         F(37500000, P_GPLL0, 16, 0, 0),
 294         F(50000000, P_GPLL0, 12, 0, 0),
 295         F(75000000, P_GPLL0, 8, 0, 0),
 296         F(100000000, P_GPLL0, 6, 0, 0),
 297         { }
 298 };
 299
 300 static struct clk_rcg2 periph_noc_clk_src = {
 301         .cmd_rcgr = 0x06014,
 302         .hid_width = 5,
 303         .parent_map = gcc_xo_gpll0_map,
 304         .freq_tbl = ftbl_periph_noc_clk_src,
 305         .clkr.hw.init = &(struct clk_init_data){
 306                 .name = "periph_noc_clk_src",
 307                 .parent_data = gcc_xo_gpll0,
 308                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 309                 .ops = &clk_rcg2_ops,
 310         },
 311 };
 312
 313 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
 314         F(19200000, P_XO, 1, 0, 0),
 315         F(120000000, P_GPLL0, 5, 0, 0),
 316         F(150000000, P_GPLL0, 4, 0, 0),
 317         { }
 318 };
 319
 320 static struct clk_rcg2 usb30_master_clk_src = {
 321         .cmd_rcgr = 0x0f014,
 322         .mnd_width = 8,
 323         .hid_width = 5,
 324         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 325         .freq_tbl = ftbl_usb30_master_clk_src,
 326         .clkr.hw.init = &(struct clk_init_data){
 327                 .name = "usb30_master_clk_src",
 328                 .parent_data = gcc_xo_gpll0_gpll0_early_div,
 329                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
 330                 .ops = &clk_rcg2_ops,
 331         },
 332 };
 333
 334 static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
 335         F(19200000, P_XO, 1, 0, 0),
 336         { }
 337 };
 338
 339 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
 340         .cmd_rcgr = 0x0f028,
 341         .hid_width = 5,
 342         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 343         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
 344         .clkr.hw.init = &(struct clk_init_data){
 345                 .name = "usb30_mock_utmi_clk_src",
 346                 .parent_data = gcc_xo_gpll0_gpll0_early_div,
 347                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
 348                 .ops = &clk_rcg2_ops,
 349         },
 350 };
 351
 352 static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
 353         F(1200000, P_XO, 16, 0, 0),
 354         { }
 355 };
 356
 357 static struct clk_rcg2 usb3_phy_aux_clk_src = {
 358         .cmd_rcgr = 0x5000c,
 359         .hid_width = 5,
 360         .parent_map = gcc_xo_sleep_clk_map,
 361         .freq_tbl = ftbl_usb3_phy_aux_clk_src,
 362         .clkr.hw.init = &(struct clk_init_data){
 363                 .name = "usb3_phy_aux_clk_src",
 364                 .parent_data = gcc_xo_sleep_clk,
 365                 .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
 366                 .ops = &clk_rcg2_ops,
 367         },
 368 };
 369
 370 static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
 371         F(120000000, P_GPLL0, 5, 0, 0),
 372         { }
 373 };
 374
 375 static struct clk_rcg2 usb20_master_clk_src = {
 376         .cmd_rcgr = 0x12010,
 377         .mnd_width = 8,
 378         .hid_width = 5,
 379         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 380         .freq_tbl = ftbl_usb20_master_clk_src,
 381         .clkr.hw.init = &(struct clk_init_data){
 382                 .name = "usb20_master_clk_src",
 383                 .parent_data = gcc_xo_gpll0_gpll0_early_div,
 384                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
 385                 .ops = &clk_rcg2_ops,
 386         },
 387 };
 388
 389 static struct clk_rcg2 usb20_mock_utmi_clk_src = {
 390         .cmd_rcgr = 0x12024,
 391         .hid_width = 5,
 392         .parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 393         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
 394         .clkr.hw.init = &(struct clk_init_data){
 395                 .name = "usb20_mock_utmi_clk_src",
 396                 .parent_data = gcc_xo_gpll0_gpll0_early_div,
 397                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
 398                 .ops = &clk_rcg2_ops,
 399         },
 400 };
 401
 402 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
 403         F(144000, P_XO, 16, 3, 25),
 404         F(400000, P_XO, 12, 1, 4),
 405         F(20000000, P_GPLL0, 15, 1, 2),
 406         F(25000000, P_GPLL0, 12, 1, 2),
 407         F(50000000, P_GPLL0, 12, 0, 0),
 408         F(96000000, P_GPLL4, 4, 0, 0),
 409         F(192000000, P_GPLL4, 2, 0, 0),
 410         F(384000000, P_GPLL4, 1, 0, 0),
 411         { }
 412 };
 413
 414 static struct clk_rcg2 sdcc1_apps_clk_src = {
 415         .cmd_rcgr = 0x13010,
 416         .mnd_width = 8,
 417         .hid_width = 5,
 418         .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
 419         .freq_tbl = ftbl_sdcc1_apps_clk_src,
 420         .clkr.hw.init = &(struct clk_init_data){
 421                 .name = "sdcc1_apps_clk_src",
 422                 .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
 423                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
 424                 .ops = &clk_rcg2_floor_ops,
 425         },
 426 };
 427
 428 static struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
 429         F(19200000, P_XO, 1, 0, 0),
 430         F(150000000, P_GPLL0, 4, 0, 0),
 431         F(300000000, P_GPLL0, 2, 0, 0),
 432         { }
 433 };
 434
 435 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
 436         .cmd_rcgr = 0x13024,
 437         .hid_width = 5,
 438         .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
 439         .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
 440         .clkr.hw.init = &(struct clk_init_data){
 441                 .name = "sdcc1_ice_core_clk_src",
 442                 .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
 443                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
 444                 .ops = &clk_rcg2_ops,
 445         },
 446 };
 447
 448 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
 449         F(144000, P_XO, 16, 3, 25),
 450         F(400000, P_XO, 12, 1, 4),
 451         F(20000000, P_GPLL0, 15, 1, 2),
 452         F(25000000, P_GPLL0, 12, 1, 2),
 453         F(50000000, P_GPLL0, 12, 0, 0),
 454         F(100000000, P_GPLL0, 6, 0, 0),
 455         F(200000000, P_GPLL0, 3, 0, 0),
 456         { }
 457 };
 458
 459 static struct clk_rcg2 sdcc2_apps_clk_src = {
 460         .cmd_rcgr = 0x14010,
 461         .mnd_width = 8,
 462         .hid_width = 5,
 463         .parent_map = gcc_xo_gpll0_gpll4_map,
 464         .freq_tbl = ftbl_sdcc2_apps_clk_src,
 465         .clkr.hw.init = &(struct clk_init_data){
 466                 .name = "sdcc2_apps_clk_src",
 467                 .parent_data = gcc_xo_gpll0_gpll4,
 468                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
 469                 .ops = &clk_rcg2_floor_ops,
 470         },
 471 };
 472
 473 static struct clk_rcg2 sdcc3_apps_clk_src = {
 474         .cmd_rcgr = 0x15010,
 475         .mnd_width = 8,
 476         .hid_width = 5,
 477         .parent_map = gcc_xo_gpll0_gpll4_map,
 478         .freq_tbl = ftbl_sdcc2_apps_clk_src,
 479         .clkr.hw.init = &(struct clk_init_data){
 480                 .name = "sdcc3_apps_clk_src",
 481                 .parent_data = gcc_xo_gpll0_gpll4,
 482                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
 483                 .ops = &clk_rcg2_floor_ops,
 484         },
 485 };
 486
 487 static const struct freq_tbl ftbl_sdcc4_apps_clk_src[] = {
 488         F(144000, P_XO, 16, 3, 25),
 489         F(400000, P_XO, 12, 1, 4),
 490         F(20000000, P_GPLL0, 15, 1, 2),
 491         F(25000000, P_GPLL0, 12, 1, 2),
 492         F(50000000, P_GPLL0, 12, 0, 0),
 493         F(100000000, P_GPLL0, 6, 0, 0),
 494         { }
 495 };
 496
 497 static struct clk_rcg2 sdcc4_apps_clk_src = {
 498         .cmd_rcgr = 0x16010,
 499         .mnd_width = 8,
 500         .hid_width = 5,
 501         .parent_map = gcc_xo_gpll0_map,
 502         .freq_tbl = ftbl_sdcc4_apps_clk_src,
 503         .clkr.hw.init = &(struct clk_init_data){
 504                 .name = "sdcc4_apps_clk_src",
 505                 .parent_data = gcc_xo_gpll0,
 506                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 507                 .ops = &clk_rcg2_floor_ops,
 508         },
 509 };
 510
 511 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
 512         F(960000, P_XO, 10, 1, 2),
 513         F(4800000, P_XO, 4, 0, 0),
 514         F(9600000, P_XO, 2, 0, 0),
 515         F(15000000, P_GPLL0, 10, 1, 4),
 516         F(19200000, P_XO, 1, 0, 0),
 517         F(25000000, P_GPLL0, 12, 1, 2),
 518         F(50000000, P_GPLL0, 12, 0, 0),
 519         { }
 520 };
 521
 522 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 523         .cmd_rcgr = 0x1900c,
 524         .mnd_width = 8,
 525         .hid_width = 5,
 526         .parent_map = gcc_xo_gpll0_map,
 527         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 528         .clkr.hw.init = &(struct clk_init_data){
 529                 .name = "blsp1_qup1_spi_apps_clk_src",
 530                 .parent_data = gcc_xo_gpll0,
 531                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 532                 .ops = &clk_rcg2_ops,
 533         },
 534 };
 535
 536 static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
 537         F(19200000, P_XO, 1, 0, 0),
 538         F(50000000, P_GPLL0, 12, 0, 0),
 539         { }
 540 };
 541
 542 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 543         .cmd_rcgr = 0x19020,
 544         .hid_width = 5,
 545         .parent_map = gcc_xo_gpll0_map,
 546         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 547         .clkr.hw.init = &(struct clk_init_data){
 548                 .name = "blsp1_qup1_i2c_apps_clk_src",
 549                 .parent_data = gcc_xo_gpll0,
 550                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 551                 .ops = &clk_rcg2_ops,
 552         },
 553 };
 554
 555 static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
 556         F(3686400, P_GPLL0, 1, 96, 15625),
 557         F(7372800, P_GPLL0, 1, 192, 15625),
 558         F(14745600, P_GPLL0, 1, 384, 15625),
 559         F(16000000, P_GPLL0, 5, 2, 15),
 560         F(19200000, P_XO, 1, 0, 0),
 561         F(24000000, P_GPLL0, 5, 1, 5),
 562         F(32000000, P_GPLL0, 1, 4, 75),
 563         F(40000000, P_GPLL0, 15, 0, 0),
 564         F(46400000, P_GPLL0, 1, 29, 375),
 565         F(48000000, P_GPLL0, 12.5, 0, 0),
 566         F(51200000, P_GPLL0, 1, 32, 375),
 567         F(56000000, P_GPLL0, 1, 7, 75),
 568         F(58982400, P_GPLL0, 1, 1536, 15625),
 569         F(60000000, P_GPLL0, 10, 0, 0),
 570         F(63157895, P_GPLL0, 9.5, 0, 0),
 571         { }
 572 };
 573
 574 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 575         .cmd_rcgr = 0x1a00c,
 576         .mnd_width = 16,
 577         .hid_width = 5,
 578         .parent_map = gcc_xo_gpll0_map,
 579         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 580         .clkr.hw.init = &(struct clk_init_data){
 581                 .name = "blsp1_uart1_apps_clk_src",
 582                 .parent_data = gcc_xo_gpll0,
 583                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 584                 .ops = &clk_rcg2_ops,
 585         },
 586 };
 587
 588 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 589         .cmd_rcgr = 0x1b00c,
 590         .mnd_width = 8,
 591         .hid_width = 5,
 592         .parent_map = gcc_xo_gpll0_map,
 593         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 594         .clkr.hw.init = &(struct clk_init_data){
 595                 .name = "blsp1_qup2_spi_apps_clk_src",
 596                 .parent_data = gcc_xo_gpll0,
 597                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 598                 .ops = &clk_rcg2_ops,
 599         },
 600 };
 601
 602 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 603         .cmd_rcgr = 0x1b020,
 604         .hid_width = 5,
 605         .parent_map = gcc_xo_gpll0_map,
 606         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 607         .clkr.hw.init = &(struct clk_init_data){
 608                 .name = "blsp1_qup2_i2c_apps_clk_src",
 609                 .parent_data = gcc_xo_gpll0,
 610                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 611                 .ops = &clk_rcg2_ops,
 612         },
 613 };
 614
 615 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 616         .cmd_rcgr = 0x1c00c,
 617         .mnd_width = 16,
 618         .hid_width = 5,
 619         .parent_map = gcc_xo_gpll0_map,
 620         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 621         .clkr.hw.init = &(struct clk_init_data){
 622                 .name = "blsp1_uart2_apps_clk_src",
 623                 .parent_data = gcc_xo_gpll0,
 624                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 625                 .ops = &clk_rcg2_ops,
 626         },
 627 };
 628
 629 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 630         .cmd_rcgr = 0x1d00c,
 631         .mnd_width = 8,
 632         .hid_width = 5,
 633         .parent_map = gcc_xo_gpll0_map,
 634         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 635         .clkr.hw.init = &(struct clk_init_data){
 636                 .name = "blsp1_qup3_spi_apps_clk_src",
 637                 .parent_data = gcc_xo_gpll0,
 638                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 639                 .ops = &clk_rcg2_ops,
 640         },
 641 };
 642
 643 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 644         .cmd_rcgr = 0x1d020,
 645         .hid_width = 5,
 646         .parent_map = gcc_xo_gpll0_map,
 647         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 648         .clkr.hw.init = &(struct clk_init_data){
 649                 .name = "blsp1_qup3_i2c_apps_clk_src",
 650                 .parent_data = gcc_xo_gpll0,
 651                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 652                 .ops = &clk_rcg2_ops,
 653         },
 654 };
 655
 656 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 657         .cmd_rcgr = 0x1e00c,
 658         .mnd_width = 16,
 659         .hid_width = 5,
 660         .parent_map = gcc_xo_gpll0_map,
 661         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 662         .clkr.hw.init = &(struct clk_init_data){
 663                 .name = "blsp1_uart3_apps_clk_src",
 664                 .parent_data = gcc_xo_gpll0,
 665                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 666                 .ops = &clk_rcg2_ops,
 667         },
 668 };
 669
 670 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 671         .cmd_rcgr = 0x1f00c,
 672         .mnd_width = 8,
 673         .hid_width = 5,
 674         .parent_map = gcc_xo_gpll0_map,
 675         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 676         .clkr.hw.init = &(struct clk_init_data){
 677                 .name = "blsp1_qup4_spi_apps_clk_src",
 678                 .parent_data = gcc_xo_gpll0,
 679                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 680                 .ops = &clk_rcg2_ops,
 681         },
 682 };
 683
 684 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 685         .cmd_rcgr = 0x1f020,
 686         .hid_width = 5,
 687         .parent_map = gcc_xo_gpll0_map,
 688         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 689         .clkr.hw.init = &(struct clk_init_data){
 690                 .name = "blsp1_qup4_i2c_apps_clk_src",
 691                 .parent_data = gcc_xo_gpll0,
 692                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 693                 .ops = &clk_rcg2_ops,
 694         },
 695 };
 696
 697 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 698         .cmd_rcgr = 0x2000c,
 699         .mnd_width = 16,
 700         .hid_width = 5,
 701         .parent_map = gcc_xo_gpll0_map,
 702         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 703         .clkr.hw.init = &(struct clk_init_data){
 704                 .name = "blsp1_uart4_apps_clk_src",
 705                 .parent_data = gcc_xo_gpll0,
 706                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 707                 .ops = &clk_rcg2_ops,
 708         },
 709 };
 710
 711 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 712         .cmd_rcgr = 0x2100c,
 713         .mnd_width = 8,
 714         .hid_width = 5,
 715         .parent_map = gcc_xo_gpll0_map,
 716         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 717         .clkr.hw.init = &(struct clk_init_data){
 718                 .name = "blsp1_qup5_spi_apps_clk_src",
 719                 .parent_data = gcc_xo_gpll0,
 720                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 721                 .ops = &clk_rcg2_ops,
 722         },
 723 };
 724
 725 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 726         .cmd_rcgr = 0x21020,
 727         .hid_width = 5,
 728         .parent_map = gcc_xo_gpll0_map,
 729         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 730         .clkr.hw.init = &(struct clk_init_data){
 731                 .name = "blsp1_qup5_i2c_apps_clk_src",
 732                 .parent_data = gcc_xo_gpll0,
 733                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 734                 .ops = &clk_rcg2_ops,
 735         },
 736 };
 737
 738 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 739         .cmd_rcgr = 0x2200c,
 740         .mnd_width = 16,
 741         .hid_width = 5,
 742         .parent_map = gcc_xo_gpll0_map,
 743         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 744         .clkr.hw.init = &(struct clk_init_data){
 745                 .name = "blsp1_uart5_apps_clk_src",
 746                 .parent_data = gcc_xo_gpll0,
 747                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 748                 .ops = &clk_rcg2_ops,
 749         },
 750 };
 751
 752 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 753         .cmd_rcgr = 0x2300c,
 754         .mnd_width = 8,
 755         .hid_width = 5,
 756         .parent_map = gcc_xo_gpll0_map,
 757         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 758         .clkr.hw.init = &(struct clk_init_data){
 759                 .name = "blsp1_qup6_spi_apps_clk_src",
 760                 .parent_data = gcc_xo_gpll0,
 761                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 762                 .ops = &clk_rcg2_ops,
 763         },
 764 };
 765
 766 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 767         .cmd_rcgr = 0x23020,
 768         .hid_width = 5,
 769         .parent_map = gcc_xo_gpll0_map,
 770         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 771         .clkr.hw.init = &(struct clk_init_data){
 772                 .name = "blsp1_qup6_i2c_apps_clk_src",
 773                 .parent_data = gcc_xo_gpll0,
 774                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 775                 .ops = &clk_rcg2_ops,
 776         },
 777 };
 778
 779 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 780         .cmd_rcgr = 0x2400c,
 781         .mnd_width = 16,
 782         .hid_width = 5,
 783         .parent_map = gcc_xo_gpll0_map,
 784         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 785         .clkr.hw.init = &(struct clk_init_data){
 786                 .name = "blsp1_uart6_apps_clk_src",
 787                 .parent_data = gcc_xo_gpll0,
 788                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 789                 .ops = &clk_rcg2_ops,
 790         },
 791 };
 792
 793 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 794         .cmd_rcgr = 0x2600c,
 795         .mnd_width = 8,
 796         .hid_width = 5,
 797         .parent_map = gcc_xo_gpll0_map,
 798         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 799         .clkr.hw.init = &(struct clk_init_data){
 800                 .name = "blsp2_qup1_spi_apps_clk_src",
 801                 .parent_data = gcc_xo_gpll0,
 802                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 803                 .ops = &clk_rcg2_ops,
 804         },
 805 };
 806
 807 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 808         .cmd_rcgr = 0x26020,
 809         .hid_width = 5,
 810         .parent_map = gcc_xo_gpll0_map,
 811         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 812         .clkr.hw.init = &(struct clk_init_data){
 813                 .name = "blsp2_qup1_i2c_apps_clk_src",
 814                 .parent_data = gcc_xo_gpll0,
 815                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 816                 .ops = &clk_rcg2_ops,
 817         },
 818 };
 819
 820 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 821         .cmd_rcgr = 0x2700c,
 822         .mnd_width = 16,
 823         .hid_width = 5,
 824         .parent_map = gcc_xo_gpll0_map,
 825         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 826         .clkr.hw.init = &(struct clk_init_data){
 827                 .name = "blsp2_uart1_apps_clk_src",
 828                 .parent_data = gcc_xo_gpll0,
 829                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 830                 .ops = &clk_rcg2_ops,
 831         },
 832 };
 833
 834 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 835         .cmd_rcgr = 0x2800c,
 836         .mnd_width = 8,
 837         .hid_width = 5,
 838         .parent_map = gcc_xo_gpll0_map,
 839         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 840         .clkr.hw.init = &(struct clk_init_data){
 841                 .name = "blsp2_qup2_spi_apps_clk_src",
 842                 .parent_data = gcc_xo_gpll0,
 843                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 844                 .ops = &clk_rcg2_ops,
 845         },
 846 };
 847
 848 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 849         .cmd_rcgr = 0x28020,
 850         .hid_width = 5,
 851         .parent_map = gcc_xo_gpll0_map,
 852         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 853         .clkr.hw.init = &(struct clk_init_data){
 854                 .name = "blsp2_qup2_i2c_apps_clk_src",
 855                 .parent_data = gcc_xo_gpll0,
 856                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 857                 .ops = &clk_rcg2_ops,
 858         },
 859 };
 860
 861 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 862         .cmd_rcgr = 0x2900c,
 863         .mnd_width = 16,
 864         .hid_width = 5,
 865         .parent_map = gcc_xo_gpll0_map,
 866         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 867         .clkr.hw.init = &(struct clk_init_data){
 868                 .name = "blsp2_uart2_apps_clk_src",
 869                 .parent_data = gcc_xo_gpll0,
 870                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 871                 .ops = &clk_rcg2_ops,
 872         },
 873 };
 874
 875 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 876         .cmd_rcgr = 0x2a00c,
 877         .mnd_width = 8,
 878         .hid_width = 5,
 879         .parent_map = gcc_xo_gpll0_map,
 880         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 881         .clkr.hw.init = &(struct clk_init_data){
 882                 .name = "blsp2_qup3_spi_apps_clk_src",
 883                 .parent_data = gcc_xo_gpll0,
 884                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 885                 .ops = &clk_rcg2_ops,
 886         },
 887 };
 888
 889 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 890         .cmd_rcgr = 0x2a020,
 891         .hid_width = 5,
 892         .parent_map = gcc_xo_gpll0_map,
 893         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 894         .clkr.hw.init = &(struct clk_init_data){
 895                 .name = "blsp2_qup3_i2c_apps_clk_src",
 896                 .parent_data = gcc_xo_gpll0,
 897                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 898                 .ops = &clk_rcg2_ops,
 899         },
 900 };
 901
 902 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 903         .cmd_rcgr = 0x2b00c,
 904         .mnd_width = 16,
 905         .hid_width = 5,
 906         .parent_map = gcc_xo_gpll0_map,
 907         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 908         .clkr.hw.init = &(struct clk_init_data){
 909                 .name = "blsp2_uart3_apps_clk_src",
 910                 .parent_data = gcc_xo_gpll0,
 911                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 912                 .ops = &clk_rcg2_ops,
 913         },
 914 };
 915
 916 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 917         .cmd_rcgr = 0x2c00c,
 918         .mnd_width = 8,
 919         .hid_width = 5,
 920         .parent_map = gcc_xo_gpll0_map,
 921         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 922         .clkr.hw.init = &(struct clk_init_data){
 923                 .name = "blsp2_qup4_spi_apps_clk_src",
 924                 .parent_data = gcc_xo_gpll0,
 925                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 926                 .ops = &clk_rcg2_ops,
 927         },
 928 };
 929
 930 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 931         .cmd_rcgr = 0x2c020,
 932         .hid_width = 5,
 933         .parent_map = gcc_xo_gpll0_map,
 934         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 935         .clkr.hw.init = &(struct clk_init_data){
 936                 .name = "blsp2_qup4_i2c_apps_clk_src",
 937                 .parent_data = gcc_xo_gpll0,
 938                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 939                 .ops = &clk_rcg2_ops,
 940         },
 941 };
 942
 943 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
 944         .cmd_rcgr = 0x2d00c,
 945         .mnd_width = 16,
 946         .hid_width = 5,
 947         .parent_map = gcc_xo_gpll0_map,
 948         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 949         .clkr.hw.init = &(struct clk_init_data){
 950                 .name = "blsp2_uart4_apps_clk_src",
 951                 .parent_data = gcc_xo_gpll0,
 952                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 953                 .ops = &clk_rcg2_ops,
 954         },
 955 };
 956
 957 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 958         .cmd_rcgr = 0x2e00c,
 959         .mnd_width = 8,
 960         .hid_width = 5,
 961         .parent_map = gcc_xo_gpll0_map,
 962         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 963         .clkr.hw.init = &(struct clk_init_data){
 964                 .name = "blsp2_qup5_spi_apps_clk_src",
 965                 .parent_data = gcc_xo_gpll0,
 966                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 967                 .ops = &clk_rcg2_ops,
 968         },
 969 };
 970
 971 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 972         .cmd_rcgr = 0x2e020,
 973         .hid_width = 5,
 974         .parent_map = gcc_xo_gpll0_map,
 975         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 976         .clkr.hw.init = &(struct clk_init_data){
 977                 .name = "blsp2_qup5_i2c_apps_clk_src",
 978                 .parent_data = gcc_xo_gpll0,
 979                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 980                 .ops = &clk_rcg2_ops,
 981         },
 982 };
 983
 984 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
 985         .cmd_rcgr = 0x2f00c,
 986         .mnd_width = 16,
 987         .hid_width = 5,
 988         .parent_map = gcc_xo_gpll0_map,
 989         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 990         .clkr.hw.init = &(struct clk_init_data){
 991                 .name = "blsp2_uart5_apps_clk_src",
 992                 .parent_data = gcc_xo_gpll0,
 993                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 994                 .ops = &clk_rcg2_ops,
 995         },
 996 };
 997
 998 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
 999         .cmd_rcgr = 0x3000c,
1000         .mnd_width = 8,
1001         .hid_width = 5,
1002         .parent_map = gcc_xo_gpll0_map,
1003         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
1004         .clkr.hw.init = &(struct clk_init_data){
1005                 .name = "blsp2_qup6_spi_apps_clk_src",
1006                 .parent_data = gcc_xo_gpll0,
1007                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1008                 .ops = &clk_rcg2_ops,
1009         },
1010 };
1011
1012 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
1013         .cmd_rcgr = 0x30020,
1014         .hid_width = 5,
1015         .parent_map = gcc_xo_gpll0_map,
1016         .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
1017         .clkr.hw.init = &(struct clk_init_data){
1018                 .name = "blsp2_qup6_i2c_apps_clk_src",
1019                 .parent_data = gcc_xo_gpll0,
1020                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1021                 .ops = &clk_rcg2_ops,
1022         },
1023 };
1024
1025 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
1026         .cmd_rcgr = 0x3100c,
1027         .mnd_width = 16,
1028         .hid_width = 5,
1029         .parent_map = gcc_xo_gpll0_map,
1030         .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
1031         .clkr.hw.init = &(struct clk_init_data){
1032                 .name = "blsp2_uart6_apps_clk_src",
1033                 .parent_data = gcc_xo_gpll0,
1034                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1035                 .ops = &clk_rcg2_ops,
1036         },
1037 };
1038
1039 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1040         F(60000000, P_GPLL0, 10, 0, 0),
1041         { }
1042 };
1043
1044 static struct clk_rcg2 pdm2_clk_src = {
1045         .cmd_rcgr = 0x33010,
1046         .hid_width = 5,
1047         .parent_map = gcc_xo_gpll0_map,
1048         .freq_tbl = ftbl_pdm2_clk_src,
1049         .clkr.hw.init = &(struct clk_init_data){
1050                 .name = "pdm2_clk_src",
1051                 .parent_data = gcc_xo_gpll0,
1052                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1053                 .ops = &clk_rcg2_ops,
1054         },
1055 };
1056
1057 static const struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1058         F(105495, P_XO, 1, 1, 182),
1059         { }
1060 };
1061
1062 static struct clk_rcg2 tsif_ref_clk_src = {
1063         .cmd_rcgr = 0x36010,
1064         .mnd_width = 8,
1065         .hid_width = 5,
1066         .parent_map = gcc_xo_gpll0_aud_ref_clk_map,
1067         .freq_tbl = ftbl_tsif_ref_clk_src,
1068         .clkr.hw.init = &(struct clk_init_data){
1069                 .name = "tsif_ref_clk_src",
1070                 .parent_data = gcc_xo_gpll0_aud_ref_clk,
1071                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_aud_ref_clk),
1072                 .ops = &clk_rcg2_ops,
1073         },
1074 };
1075
1076 static struct clk_rcg2 gcc_sleep_clk_src = {
1077         .cmd_rcgr = 0x43014,
1078         .hid_width = 5,
1079         .parent_map = gcc_sleep_clk_map,
1080         .clkr.hw.init = &(struct clk_init_data){
1081                 .name = "gcc_sleep_clk_src",
1082                 .parent_data = gcc_sleep_clk,
1083                 .num_parents = ARRAY_SIZE(gcc_sleep_clk),
1084                 .ops = &clk_rcg2_ops,
1085         },
1086 };
1087
1088 static struct clk_rcg2 hmss_rbcpr_clk_src = {
1089         .cmd_rcgr = 0x48040,
1090         .hid_width = 5,
1091         .parent_map = gcc_xo_gpll0_map,
1092         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1093         .clkr.hw.init = &(struct clk_init_data){
1094                 .name = "hmss_rbcpr_clk_src",
1095                 .parent_data = gcc_xo_gpll0,
1096                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1097                 .ops = &clk_rcg2_ops,
1098         },
1099 };
1100
1101 static struct clk_rcg2 hmss_gpll0_clk_src = {
1102         .cmd_rcgr = 0x48058,
1103         .hid_width = 5,
1104         .parent_map = gcc_xo_gpll0_map,
1105         .clkr.hw.init = &(struct clk_init_data){
1106                 .name = "hmss_gpll0_clk_src",
1107                 .parent_data = gcc_xo_gpll0,
1108                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1109                 .ops = &clk_rcg2_ops,
1110         },
1111 };
1112
1113 static const struct freq_tbl ftbl_gp1_clk_src[] = {
1114         F(19200000, P_XO, 1, 0, 0),
1115         F(100000000, P_GPLL0, 6, 0, 0),
1116         F(200000000, P_GPLL0, 3, 0, 0),
1117         { }
1118 };
1119
1120 static struct clk_rcg2 gp1_clk_src = {
1121         .cmd_rcgr = 0x64004,
1122         .mnd_width = 8,
1123         .hid_width = 5,
1124         .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1125         .freq_tbl = ftbl_gp1_clk_src,
1126         .clkr.hw.init = &(struct clk_init_data){
1127                 .name = "gp1_clk_src",
1128                 .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1129                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
1130                 .ops = &clk_rcg2_ops,
1131         },
1132 };
1133
1134 static struct clk_rcg2 gp2_clk_src = {
1135         .cmd_rcgr = 0x65004,
1136         .mnd_width = 8,
1137         .hid_width = 5,
1138         .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1139         .freq_tbl = ftbl_gp1_clk_src,
1140         .clkr.hw.init = &(struct clk_init_data){
1141                 .name = "gp2_clk_src",
1142                 .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1143                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
1144                 .ops = &clk_rcg2_ops,
1145         },
1146 };
1147
1148 static struct clk_rcg2 gp3_clk_src = {
1149         .cmd_rcgr = 0x66004,
1150         .mnd_width = 8,
1151         .hid_width = 5,
1152         .parent_map = gcc_xo_gpll0_sleep_clk_gpll0_early_div_map,
1153         .freq_tbl = ftbl_gp1_clk_src,
1154         .clkr.hw.init = &(struct clk_init_data){
1155                 .name = "gp3_clk_src",
1156                 .parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
1157                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
1158                 .ops = &clk_rcg2_ops,
1159         },
1160 };
1161
1162 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
1163         F(1010526, P_XO, 1, 1, 19),
1164         { }
1165 };
1166
1167 static struct clk_rcg2 pcie_aux_clk_src = {
1168         .cmd_rcgr = 0x6c000,
1169         .mnd_width = 16,
1170         .hid_width = 5,
1171         .parent_map = gcc_xo_sleep_clk_map,
1172         .freq_tbl = ftbl_pcie_aux_clk_src,
1173         .clkr.hw.init = &(struct clk_init_data){
1174                 .name = "pcie_aux_clk_src",
1175                 .parent_data = gcc_xo_sleep_clk,
1176                 .num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
1177                 .ops = &clk_rcg2_ops,
1178         },
1179 };
1180
1181 static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
1182         F(100000000, P_GPLL0, 6, 0, 0),
1183         F(200000000, P_GPLL0, 3, 0, 0),
1184         F(240000000, P_GPLL0, 2.5, 0, 0),
1185         { }
1186 };
1187
1188 static struct clk_rcg2 ufs_axi_clk_src = {
1189         .cmd_rcgr = 0x75024,
1190         .mnd_width = 8,
1191         .hid_width = 5,
1192         .parent_map = gcc_xo_gpll0_map,
1193         .freq_tbl = ftbl_ufs_axi_clk_src,
1194         .clkr.hw.init = &(struct clk_init_data){
1195                 .name = "ufs_axi_clk_src",
1196                 .parent_data = gcc_xo_gpll0,
1197                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1198                 .ops = &clk_rcg2_ops,
1199         },
1200 };
1201
1202 static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
1203         F(19200000, P_XO, 1, 0, 0),
1204         F(150000000, P_GPLL0, 4, 0, 0),
1205         F(300000000, P_GPLL0, 2, 0, 0),
1206         { }
1207 };
1208
1209 static struct clk_rcg2 ufs_ice_core_clk_src = {
1210         .cmd_rcgr = 0x76014,
1211         .hid_width = 5,
1212         .parent_map = gcc_xo_gpll0_map,
1213         .freq_tbl = ftbl_ufs_ice_core_clk_src,
1214         .clkr.hw.init = &(struct clk_init_data){
1215                 .name = "ufs_ice_core_clk_src",
1216                 .parent_data = gcc_xo_gpll0,
1217                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1218                 .ops = &clk_rcg2_ops,
1219         },
1220 };
1221
1222 static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
1223         F(75000000, P_GPLL0, 8, 0, 0),
1224         F(150000000, P_GPLL0, 4, 0, 0),
1225         F(256000000, P_GPLL4, 1.5, 0, 0),
1226         F(300000000, P_GPLL0, 2, 0, 0),
1227         { }
1228 };
1229
1230 static struct clk_rcg2 qspi_ser_clk_src = {
1231         .cmd_rcgr = 0x8b00c,
1232         .hid_width = 5,
1233         .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
1234         .freq_tbl = ftbl_qspi_ser_clk_src,
1235         .clkr.hw.init = &(struct clk_init_data){
1236                 .name = "qspi_ser_clk_src",
1237                 .parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
1238                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
1239                 .ops = &clk_rcg2_ops,
1240         },
1241 };
1242
1243 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
1244         .halt_reg = 0x0f03c,
1245         .clkr = {
1246                 .enable_reg = 0x0f03c,
1247                 .enable_mask = BIT(0),
1248                 .hw.init = &(struct clk_init_data){
1249                         .name = "gcc_sys_noc_usb3_axi_clk",
1250                         .parent_hws = (const struct clk_hw*[]){
1251                                 &usb30_master_clk_src.clkr.hw,
1252                         },
1253                         .num_parents = 1,
1254                         .flags = CLK_SET_RATE_PARENT,
1255                         .ops = &clk_branch2_ops,
1256                 },
1257         },
1258 };
1259
1260 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
1261         .halt_reg = 0x75038,
1262         .clkr = {
1263                 .enable_reg = 0x75038,
1264                 .enable_mask = BIT(0),
1265                 .hw.init = &(struct clk_init_data){
1266                         .name = "gcc_sys_noc_ufs_axi_clk",
1267                         .parent_hws = (const struct clk_hw*[]){
1268                                 &ufs_axi_clk_src.clkr.hw,
1269                         },
1270                         .num_parents = 1,
1271                         .flags = CLK_SET_RATE_PARENT,
1272                         .ops = &clk_branch2_ops,
1273                 },
1274         },
1275 };
1276
1277 static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
1278         .halt_reg = 0x6010,
1279         .clkr = {
1280                 .enable_reg = 0x6010,
1281                 .enable_mask = BIT(0),
1282                 .hw.init = &(struct clk_init_data){
1283                         .name = "gcc_periph_noc_usb20_ahb_clk",
1284                         .parent_hws = (const struct clk_hw*[]){
1285                                 &usb20_master_clk_src.clkr.hw,
1286                         },
1287                         .num_parents = 1,
1288                         .flags = CLK_SET_RATE_PARENT,
1289                         .ops = &clk_branch2_ops,
1290                 },
1291         },
1292 };
1293
1294 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
1295         .halt_reg = 0x9008,
1296         .clkr = {
1297                 .enable_reg = 0x9008,
1298                 .enable_mask = BIT(0),
1299                 .hw.init = &(struct clk_init_data){
1300                         .name = "gcc_mmss_noc_cfg_ahb_clk",
1301                         .parent_hws = (const struct clk_hw*[]){
1302                                 &config_noc_clk_src.clkr.hw,
1303                         },
1304                         .num_parents = 1,
1305                         .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1306                         .ops = &clk_branch2_ops,
1307                 },
1308         },
1309 };
1310
1311 static struct clk_branch gcc_mmss_bimc_gfx_clk = {
1312         .halt_reg = 0x9010,
1313         .clkr = {
1314                 .enable_reg = 0x9010,
1315                 .enable_mask = BIT(0),
1316                 .hw.init = &(struct clk_init_data){
1317                         .name = "gcc_mmss_bimc_gfx_clk",
1318                         .flags = CLK_SET_RATE_PARENT,
1319                         .ops = &clk_branch2_ops,
1320                 },
1321         },
1322 };
1323
1324 static struct clk_branch gcc_usb30_master_clk = {
1325         .halt_reg = 0x0f008,
1326         .clkr = {
1327                 .enable_reg = 0x0f008,
1328                 .enable_mask = BIT(0),
1329                 .hw.init = &(struct clk_init_data){
1330                         .name = "gcc_usb30_master_clk",
1331                         .parent_hws = (const struct clk_hw*[]){
1332                                 &usb30_master_clk_src.clkr.hw,
1333                         },
1334                         .num_parents = 1,
1335                         .flags = CLK_SET_RATE_PARENT,
1336                         .ops = &clk_branch2_ops,
1337                 },
1338         },
1339 };
1340
1341 static struct clk_branch gcc_usb30_sleep_clk = {
1342         .halt_reg = 0x0f00c,
1343         .clkr = {
1344                 .enable_reg = 0x0f00c,
1345                 .enable_mask = BIT(0),
1346                 .hw.init = &(struct clk_init_data){
1347                         .name = "gcc_usb30_sleep_clk",
1348                         .parent_hws = (const struct clk_hw*[]){
1349                                 &gcc_sleep_clk_src.clkr.hw,
1350                         },
1351                         .num_parents = 1,
1352                         .flags = CLK_SET_RATE_PARENT,
1353                         .ops = &clk_branch2_ops,
1354                 },
1355         },
1356 };
1357
1358 static struct clk_branch gcc_usb30_mock_utmi_clk = {
1359         .halt_reg = 0x0f010,
1360         .clkr = {
1361                 .enable_reg = 0x0f010,
1362                 .enable_mask = BIT(0),
1363                 .hw.init = &(struct clk_init_data){
1364                         .name = "gcc_usb30_mock_utmi_clk",
1365                         .parent_hws = (const struct clk_hw*[]){
1366                                 &usb30_mock_utmi_clk_src.clkr.hw,
1367                         },
1368                         .num_parents = 1,
1369                         .flags = CLK_SET_RATE_PARENT,
1370                         .ops = &clk_branch2_ops,
1371                 },
1372         },
1373 };
1374
1375 static struct clk_branch gcc_usb3_phy_aux_clk = {
1376         .halt_reg = 0x50000,
1377         .clkr = {
1378                 .enable_reg = 0x50000,
1379                 .enable_mask = BIT(0),
1380                 .hw.init = &(struct clk_init_data){
1381                         .name = "gcc_usb3_phy_aux_clk",
1382                         .parent_hws = (const struct clk_hw*[]){
1383                                 &usb3_phy_aux_clk_src.clkr.hw,
1384                         },
1385                         .num_parents = 1,
1386                         .flags = CLK_SET_RATE_PARENT,
1387                         .ops = &clk_branch2_ops,
1388                 },
1389         },
1390 };
1391
1392 static struct clk_branch gcc_usb3_phy_pipe_clk = {
1393         .halt_reg = 0x50004,
1394         .halt_check = BRANCH_HALT_SKIP,
1395         .clkr = {
1396                 .enable_reg = 0x50004,
1397                 .enable_mask = BIT(0),
1398                 .hw.init = &(struct clk_init_data){
1399                         .name = "gcc_usb3_phy_pipe_clk",
1400                         .parent_data = &(const struct clk_parent_data){
1401                                 .fw_name = "usb3_phy_pipe_clk_src", .name = "usb3_phy_pipe_clk_src",
1402                         },
1403                         .num_parents = 1,
1404                         .flags = CLK_SET_RATE_PARENT,
1405                         .ops = &clk_branch2_ops,
1406                 },
1407         },
1408 };
1409
1410 static struct clk_branch gcc_usb20_master_clk = {
1411         .halt_reg = 0x12004,
1412         .clkr = {
1413                 .enable_reg = 0x12004,
1414                 .enable_mask = BIT(0),
1415                 .hw.init = &(struct clk_init_data){
1416                         .name = "gcc_usb20_master_clk",
1417                         .parent_hws = (const struct clk_hw*[]){
1418                                 &usb20_master_clk_src.clkr.hw,
1419                         },
1420                         .num_parents = 1,
1421                         .flags = CLK_SET_RATE_PARENT,
1422                         .ops = &clk_branch2_ops,
1423                 },
1424         },
1425 };
1426
1427 static struct clk_branch gcc_usb20_sleep_clk = {
1428         .halt_reg = 0x12008,
1429         .clkr = {
1430                 .enable_reg = 0x12008,
1431                 .enable_mask = BIT(0),
1432                 .hw.init = &(struct clk_init_data){
1433                         .name = "gcc_usb20_sleep_clk",
1434                         .parent_hws = (const struct clk_hw*[]){
1435                                 &gcc_sleep_clk_src.clkr.hw,
1436                         },
1437                         .num_parents = 1,
1438                         .flags = CLK_SET_RATE_PARENT,
1439                         .ops = &clk_branch2_ops,
1440                 },
1441         },
1442 };
1443
1444 static struct clk_branch gcc_usb20_mock_utmi_clk = {
1445         .halt_reg = 0x1200c,
1446         .clkr = {
1447                 .enable_reg = 0x1200c,
1448                 .enable_mask = BIT(0),
1449                 .hw.init = &(struct clk_init_data){
1450                         .name = "gcc_usb20_mock_utmi_clk",
1451                         .parent_hws = (const struct clk_hw*[]){
1452                                 &usb20_mock_utmi_clk_src.clkr.hw,
1453                         },
1454                         .num_parents = 1,
1455                         .flags = CLK_SET_RATE_PARENT,
1456                         .ops = &clk_branch2_ops,
1457                 },
1458         },
1459 };
1460
1461 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
1462         .halt_reg = 0x6a004,
1463         .clkr = {
1464                 .enable_reg = 0x6a004,
1465                 .enable_mask = BIT(0),
1466                 .hw.init = &(struct clk_init_data){
1467                         .name = "gcc_usb_phy_cfg_ahb2phy_clk",
1468                         .parent_hws = (const struct clk_hw*[]){
1469                                 &periph_noc_clk_src.clkr.hw,
1470                         },
1471                         .num_parents = 1,
1472                         .flags = CLK_SET_RATE_PARENT,
1473                         .ops = &clk_branch2_ops,
1474                 },
1475         },
1476 };
1477
1478 static struct clk_branch gcc_sdcc1_apps_clk = {
1479         .halt_reg = 0x13004,
1480         .clkr = {
1481                 .enable_reg = 0x13004,
1482                 .enable_mask = BIT(0),
1483                 .hw.init = &(struct clk_init_data){
1484                         .name = "gcc_sdcc1_apps_clk",
1485                         .parent_hws = (const struct clk_hw*[]){
1486                                 &sdcc1_apps_clk_src.clkr.hw,
1487                         },
1488                         .num_parents = 1,
1489                         .flags = CLK_SET_RATE_PARENT,
1490                         .ops = &clk_branch2_ops,
1491                 },
1492         },
1493 };
1494
1495 static struct clk_branch gcc_sdcc1_ahb_clk = {
1496         .halt_reg = 0x13008,
1497         .clkr = {
1498                 .enable_reg = 0x13008,
1499                 .enable_mask = BIT(0),
1500                 .hw.init = &(struct clk_init_data){
1501                         .name = "gcc_sdcc1_ahb_clk",
1502                         .parent_hws = (const struct clk_hw*[]){
1503                                 &periph_noc_clk_src.clkr.hw,
1504                         },
1505                         .num_parents = 1,
1506                         .flags = CLK_SET_RATE_PARENT,
1507                         .ops = &clk_branch2_ops,
1508                 },
1509         },
1510 };
1511
1512 static struct clk_branch gcc_sdcc1_ice_core_clk = {
1513         .halt_reg = 0x13038,
1514         .clkr = {
1515                 .enable_reg = 0x13038,
1516                 .enable_mask = BIT(0),
1517                 .hw.init = &(struct clk_init_data){
1518                         .name = "gcc_sdcc1_ice_core_clk",
1519                         .parent_hws = (const struct clk_hw*[]){
1520                                 &sdcc1_ice_core_clk_src.clkr.hw,
1521                         },
1522                         .num_parents = 1,
1523                         .flags = CLK_SET_RATE_PARENT,
1524                         .ops = &clk_branch2_ops,
1525                 },
1526         },
1527 };
1528
1529 static struct clk_branch gcc_sdcc2_apps_clk = {
1530         .halt_reg = 0x14004,
1531         .clkr = {
1532                 .enable_reg = 0x14004,
1533                 .enable_mask = BIT(0),
1534                 .hw.init = &(struct clk_init_data){
1535                         .name = "gcc_sdcc2_apps_clk",
1536                         .parent_hws = (const struct clk_hw*[]){
1537                                 &sdcc2_apps_clk_src.clkr.hw,
1538                         },
1539                         .num_parents = 1,
1540                         .flags = CLK_SET_RATE_PARENT,
1541                         .ops = &clk_branch2_ops,
1542                 },
1543         },
1544 };
1545
1546 static struct clk_branch gcc_sdcc2_ahb_clk = {
1547         .halt_reg = 0x14008,
1548         .clkr = {
1549                 .enable_reg = 0x14008,
1550                 .enable_mask = BIT(0),
1551                 .hw.init = &(struct clk_init_data){
1552                         .name = "gcc_sdcc2_ahb_clk",
1553                         .parent_hws = (const struct clk_hw*[]){
1554                                 &periph_noc_clk_src.clkr.hw,
1555                         },
1556                         .num_parents = 1,
1557                         .flags = CLK_SET_RATE_PARENT,
1558                         .ops = &clk_branch2_ops,
1559                 },
1560         },
1561 };
1562
1563 static struct clk_branch gcc_sdcc3_apps_clk = {
1564         .halt_reg = 0x15004,
1565         .clkr = {
1566                 .enable_reg = 0x15004,
1567                 .enable_mask = BIT(0),
1568                 .hw.init = &(struct clk_init_data){
1569                         .name = "gcc_sdcc3_apps_clk",
1570                         .parent_hws = (const struct clk_hw*[]){
1571                                 &sdcc3_apps_clk_src.clkr.hw,
1572                         },
1573                         .num_parents = 1,
1574                         .flags = CLK_SET_RATE_PARENT,
1575                         .ops = &clk_branch2_ops,
1576                 },
1577         },
1578 };
1579
1580 static struct clk_branch gcc_sdcc3_ahb_clk = {
1581         .halt_reg = 0x15008,
1582         .clkr = {
1583                 .enable_reg = 0x15008,
1584                 .enable_mask = BIT(0),
1585                 .hw.init = &(struct clk_init_data){
1586                         .name = "gcc_sdcc3_ahb_clk",
1587                         .parent_hws = (const struct clk_hw*[]){
1588                                 &periph_noc_clk_src.clkr.hw,
1589                         },
1590                         .num_parents = 1,
1591                         .flags = CLK_SET_RATE_PARENT,
1592                         .ops = &clk_branch2_ops,
1593                 },
1594         },
1595 };
1596
1597 static struct clk_branch gcc_sdcc4_apps_clk = {
1598         .halt_reg = 0x16004,
1599         .clkr = {
1600                 .enable_reg = 0x16004,
1601                 .enable_mask = BIT(0),
1602                 .hw.init = &(struct clk_init_data){
1603                         .name = "gcc_sdcc4_apps_clk",
1604                         .parent_hws = (const struct clk_hw*[]){
1605                                 &sdcc4_apps_clk_src.clkr.hw,
1606                         },
1607                         .num_parents = 1,
1608                         .flags = CLK_SET_RATE_PARENT,
1609                         .ops = &clk_branch2_ops,
1610                 },
1611         },
1612 };
1613
1614 static struct clk_branch gcc_sdcc4_ahb_clk = {
1615         .halt_reg = 0x16008,
1616         .clkr = {
1617                 .enable_reg = 0x16008,
1618                 .enable_mask = BIT(0),
1619                 .hw.init = &(struct clk_init_data){
1620                         .name = "gcc_sdcc4_ahb_clk",
1621                         .parent_hws = (const struct clk_hw*[]){
1622                                 &periph_noc_clk_src.clkr.hw,
1623                         },
1624                         .num_parents = 1,
1625                         .flags = CLK_SET_RATE_PARENT,
1626                         .ops = &clk_branch2_ops,
1627                 },
1628         },
1629 };
1630
1631 static struct clk_branch gcc_blsp1_ahb_clk = {
1632         .halt_reg = 0x17004,
1633         .halt_check = BRANCH_HALT_VOTED,
1634         .clkr = {
1635                 .enable_reg = 0x52004,
1636                 .enable_mask = BIT(17),
1637                 .hw.init = &(struct clk_init_data){
1638                         .name = "gcc_blsp1_ahb_clk",
1639                         .parent_hws = (const struct clk_hw*[]){
1640                                 &periph_noc_clk_src.clkr.hw,
1641                         },
1642                         .num_parents = 1,
1643                         .flags = CLK_SET_RATE_PARENT,
1644                         .ops = &clk_branch2_ops,
1645                 },
1646         },
1647 };
1648
1649 static struct clk_branch gcc_blsp1_sleep_clk = {
1650         .halt_reg = 0x17008,
1651         .halt_check = BRANCH_HALT_VOTED,
1652         .clkr = {
1653                 .enable_reg = 0x52004,
1654                 .enable_mask = BIT(16),
1655                 .hw.init = &(struct clk_init_data){
1656                         .name = "gcc_blsp1_sleep_clk",
1657                         .parent_hws = (const struct clk_hw*[]){
1658                                 &gcc_sleep_clk_src.clkr.hw,
1659                         },
1660                         .num_parents = 1,
1661                         .flags = CLK_SET_RATE_PARENT,
1662                         .ops = &clk_branch2_ops,
1663                 },
1664         },
1665 };
1666
1667 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1668         .halt_reg = 0x19004,
1669         .clkr = {
1670                 .enable_reg = 0x19004,
1671                 .enable_mask = BIT(0),
1672                 .hw.init = &(struct clk_init_data){
1673                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1674                         .parent_hws = (const struct clk_hw*[]){
1675                                 &blsp1_qup1_spi_apps_clk_src.clkr.hw,
1676                         },
1677                         .num_parents = 1,
1678                         .flags = CLK_SET_RATE_PARENT,
1679                         .ops = &clk_branch2_ops,
1680                 },
1681         },
1682 };
1683
1684 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1685         .halt_reg = 0x19008,
1686         .clkr = {
1687                 .enable_reg = 0x19008,
1688                 .enable_mask = BIT(0),
1689                 .hw.init = &(struct clk_init_data){
1690                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1691                         .parent_hws = (const struct clk_hw*[]){
1692                                 &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
1693                         },
1694                         .num_parents = 1,
1695                         .flags = CLK_SET_RATE_PARENT,
1696                         .ops = &clk_branch2_ops,
1697                 },
1698         },
1699 };
1700
1701 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1702         .halt_reg = 0x1a004,
1703         .clkr = {
1704                 .enable_reg = 0x1a004,
1705                 .enable_mask = BIT(0),
1706                 .hw.init = &(struct clk_init_data){
1707                         .name = "gcc_blsp1_uart1_apps_clk",
1708                         .parent_hws = (const struct clk_hw*[]){
1709                                 &blsp1_uart1_apps_clk_src.clkr.hw,
1710                         },
1711                         .num_parents = 1,
1712                         .flags = CLK_SET_RATE_PARENT,
1713                         .ops = &clk_branch2_ops,
1714                 },
1715         },
1716 };
1717
1718 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1719         .halt_reg = 0x1b004,
1720         .clkr = {
1721                 .enable_reg = 0x1b004,
1722                 .enable_mask = BIT(0),
1723                 .hw.init = &(struct clk_init_data){
1724                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1725                         .parent_hws = (const struct clk_hw*[]){
1726                                 &blsp1_qup2_spi_apps_clk_src.clkr.hw,
1727                         },
1728                         .num_parents = 1,
1729                         .flags = CLK_SET_RATE_PARENT,
1730                         .ops = &clk_branch2_ops,
1731                 },
1732         },
1733 };
1734
1735 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1736         .halt_reg = 0x1b008,
1737         .clkr = {
1738                 .enable_reg = 0x1b008,
1739                 .enable_mask = BIT(0),
1740                 .hw.init = &(struct clk_init_data){
1741                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1742                         .parent_hws = (const struct clk_hw*[]){
1743                                 &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
1744                         },
1745                         .num_parents = 1,
1746                         .flags = CLK_SET_RATE_PARENT,
1747                         .ops = &clk_branch2_ops,
1748                 },
1749         },
1750 };
1751
1752 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1753         .halt_reg = 0x1c004,
1754         .clkr = {
1755                 .enable_reg = 0x1c004,
1756                 .enable_mask = BIT(0),
1757                 .hw.init = &(struct clk_init_data){
1758                         .name = "gcc_blsp1_uart2_apps_clk",
1759                         .parent_hws = (const struct clk_hw*[]){
1760                                 &blsp1_uart2_apps_clk_src.clkr.hw,
1761                         },
1762                         .num_parents = 1,
1763                         .flags = CLK_SET_RATE_PARENT,
1764                         .ops = &clk_branch2_ops,
1765                 },
1766         },
1767 };
1768
1769 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1770         .halt_reg = 0x1d004,
1771         .clkr = {
1772                 .enable_reg = 0x1d004,
1773                 .enable_mask = BIT(0),
1774                 .hw.init = &(struct clk_init_data){
1775                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1776                         .parent_hws = (const struct clk_hw*[]){
1777                                 &blsp1_qup3_spi_apps_clk_src.clkr.hw,
1778                         },
1779                         .num_parents = 1,
1780                         .flags = CLK_SET_RATE_PARENT,
1781                         .ops = &clk_branch2_ops,
1782                 },
1783         },
1784 };
1785
1786 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1787         .halt_reg = 0x1d008,
1788         .clkr = {
1789                 .enable_reg = 0x1d008,
1790                 .enable_mask = BIT(0),
1791                 .hw.init = &(struct clk_init_data){
1792                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1793                         .parent_hws = (const struct clk_hw*[]){
1794                                 &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
1795                         },
1796                         .num_parents = 1,
1797                         .flags = CLK_SET_RATE_PARENT,
1798                         .ops = &clk_branch2_ops,
1799                 },
1800         },
1801 };
1802
1803 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1804         .halt_reg = 0x1e004,
1805         .clkr = {
1806                 .enable_reg = 0x1e004,
1807                 .enable_mask = BIT(0),
1808                 .hw.init = &(struct clk_init_data){
1809                         .name = "gcc_blsp1_uart3_apps_clk",
1810                         .parent_hws = (const struct clk_hw*[]){
1811                                 &blsp1_uart3_apps_clk_src.clkr.hw,
1812                         },
1813                         .num_parents = 1,
1814                         .flags = CLK_SET_RATE_PARENT,
1815                         .ops = &clk_branch2_ops,
1816                 },
1817         },
1818 };
1819
1820 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1821         .halt_reg = 0x1f004,
1822         .clkr = {
1823                 .enable_reg = 0x1f004,
1824                 .enable_mask = BIT(0),
1825                 .hw.init = &(struct clk_init_data){
1826                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1827                         .parent_hws = (const struct clk_hw*[]){
1828                                 &blsp1_qup4_spi_apps_clk_src.clkr.hw,
1829                         },
1830                         .num_parents = 1,
1831                         .flags = CLK_SET_RATE_PARENT,
1832                         .ops = &clk_branch2_ops,
1833                 },
1834         },
1835 };
1836
1837 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1838         .halt_reg = 0x1f008,
1839         .clkr = {
1840                 .enable_reg = 0x1f008,
1841                 .enable_mask = BIT(0),
1842                 .hw.init = &(struct clk_init_data){
1843                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1844                         .parent_hws = (const struct clk_hw*[]){
1845                                 &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
1846                         },
1847                         .num_parents = 1,
1848                         .flags = CLK_SET_RATE_PARENT,
1849                         .ops = &clk_branch2_ops,
1850                 },
1851         },
1852 };
1853
1854 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1855         .halt_reg = 0x20004,
1856         .clkr = {
1857                 .enable_reg = 0x20004,
1858                 .enable_mask = BIT(0),
1859                 .hw.init = &(struct clk_init_data){
1860                         .name = "gcc_blsp1_uart4_apps_clk",
1861                         .parent_hws = (const struct clk_hw*[]){
1862                                 &blsp1_uart4_apps_clk_src.clkr.hw,
1863                         },
1864                         .num_parents = 1,
1865                         .flags = CLK_SET_RATE_PARENT,
1866                         .ops = &clk_branch2_ops,
1867                 },
1868         },
1869 };
1870
1871 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1872         .halt_reg = 0x21004,
1873         .clkr = {
1874                 .enable_reg = 0x21004,
1875                 .enable_mask = BIT(0),
1876                 .hw.init = &(struct clk_init_data){
1877                         .name = "gcc_blsp1_qup5_spi_apps_clk",
1878                         .parent_hws = (const struct clk_hw*[]){
1879                                 &blsp1_qup5_spi_apps_clk_src.clkr.hw,
1880                         },
1881                         .num_parents = 1,
1882                         .flags = CLK_SET_RATE_PARENT,
1883                         .ops = &clk_branch2_ops,
1884                 },
1885         },
1886 };
1887
1888 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1889         .halt_reg = 0x21008,
1890         .clkr = {
1891                 .enable_reg = 0x21008,
1892                 .enable_mask = BIT(0),
1893                 .hw.init = &(struct clk_init_data){
1894                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
1895                         .parent_hws = (const struct clk_hw*[]){
1896                                 &blsp1_qup5_i2c_apps_clk_src.clkr.hw,
1897                         },
1898                         .num_parents = 1,
1899                         .flags = CLK_SET_RATE_PARENT,
1900                         .ops = &clk_branch2_ops,
1901                 },
1902         },
1903 };
1904
1905 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1906         .halt_reg = 0x22004,
1907         .clkr = {
1908                 .enable_reg = 0x22004,
1909                 .enable_mask = BIT(0),
1910                 .hw.init = &(struct clk_init_data){
1911                         .name = "gcc_blsp1_uart5_apps_clk",
1912                         .parent_hws = (const struct clk_hw*[]){
1913                                 &blsp1_uart5_apps_clk_src.clkr.hw,
1914                         },
1915                         .num_parents = 1,
1916                         .flags = CLK_SET_RATE_PARENT,
1917                         .ops = &clk_branch2_ops,
1918                 },
1919         },
1920 };
1921
1922 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1923         .halt_reg = 0x23004,
1924         .clkr = {
1925                 .enable_reg = 0x23004,
1926                 .enable_mask = BIT(0),
1927                 .hw.init = &(struct clk_init_data){
1928                         .name = "gcc_blsp1_qup6_spi_apps_clk",
1929                         .parent_hws = (const struct clk_hw*[]){
1930                                 &blsp1_qup6_spi_apps_clk_src.clkr.hw,
1931                         },
1932                         .num_parents = 1,
1933                         .flags = CLK_SET_RATE_PARENT,
1934                         .ops = &clk_branch2_ops,
1935                 },
1936         },
1937 };
1938
1939 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1940         .halt_reg = 0x23008,
1941         .clkr = {
1942                 .enable_reg = 0x23008,
1943                 .enable_mask = BIT(0),
1944                 .hw.init = &(struct clk_init_data){
1945                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
1946                         .parent_hws = (const struct clk_hw*[]){
1947                                 &blsp1_qup6_i2c_apps_clk_src.clkr.hw,
1948                         },
1949                         .num_parents = 1,
1950                         .flags = CLK_SET_RATE_PARENT,
1951                         .ops = &clk_branch2_ops,
1952                 },
1953         },
1954 };
1955
1956 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1957         .halt_reg = 0x24004,
1958         .clkr = {
1959                 .enable_reg = 0x24004,
1960                 .enable_mask = BIT(0),
1961                 .hw.init = &(struct clk_init_data){
1962                         .name = "gcc_blsp1_uart6_apps_clk",
1963                         .parent_hws = (const struct clk_hw*[]){
1964                                 &blsp1_uart6_apps_clk_src.clkr.hw,
1965                         },
1966                         .num_parents = 1,
1967                         .flags = CLK_SET_RATE_PARENT,
1968                         .ops = &clk_branch2_ops,
1969                 },
1970         },
1971 };
1972
1973 static struct clk_branch gcc_blsp2_ahb_clk = {
1974         .halt_reg = 0x25004,
1975         .halt_check = BRANCH_HALT_VOTED,
1976         .clkr = {
1977                 .enable_reg = 0x52004,
1978                 .enable_mask = BIT(15),
1979                 .hw.init = &(struct clk_init_data){
1980                         .name = "gcc_blsp2_ahb_clk",
1981                         .parent_hws = (const struct clk_hw*[]){
1982                                 &periph_noc_clk_src.clkr.hw,
1983                         },
1984                         .num_parents = 1,
1985                         .flags = CLK_SET_RATE_PARENT,
1986                         .ops = &clk_branch2_ops,
1987                 },
1988         },
1989 };
1990
1991 static struct clk_branch gcc_blsp2_sleep_clk = {
1992         .halt_reg = 0x25008,
1993         .halt_check = BRANCH_HALT_VOTED,
1994         .clkr = {
1995                 .enable_reg = 0x52004,
1996                 .enable_mask = BIT(14),
1997                 .hw.init = &(struct clk_init_data){
1998                         .name = "gcc_blsp2_sleep_clk",
1999                         .parent_hws = (const struct clk_hw*[]){
2000                                 &gcc_sleep_clk_src.clkr.hw,
2001                         },
2002                         .num_parents = 1,
2003                         .flags = CLK_SET_RATE_PARENT,
2004                         .ops = &clk_branch2_ops,
2005                 },
2006         },
2007 };
2008
2009 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
2010         .halt_reg = 0x26004,
2011         .clkr = {
2012                 .enable_reg = 0x26004,
2013                 .enable_mask = BIT(0),
2014                 .hw.init = &(struct clk_init_data){
2015                         .name = "gcc_blsp2_qup1_spi_apps_clk",
2016                         .parent_hws = (const struct clk_hw*[]){
2017                                 &blsp2_qup1_spi_apps_clk_src.clkr.hw,
2018                         },
2019                         .num_parents = 1,
2020                         .flags = CLK_SET_RATE_PARENT,
2021                         .ops = &clk_branch2_ops,
2022                 },
2023         },
2024 };
2025
2026 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
2027         .halt_reg = 0x26008,
2028         .clkr = {
2029                 .enable_reg = 0x26008,
2030                 .enable_mask = BIT(0),
2031                 .hw.init = &(struct clk_init_data){
2032                         .name = "gcc_blsp2_qup1_i2c_apps_clk",
2033                         .parent_hws = (const struct clk_hw*[]){
2034                                 &blsp2_qup1_i2c_apps_clk_src.clkr.hw,
2035                         },
2036                         .num_parents = 1,
2037                         .flags = CLK_SET_RATE_PARENT,
2038                         .ops = &clk_branch2_ops,
2039                 },
2040         },
2041 };
2042
2043 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
2044         .halt_reg = 0x27004,
2045         .clkr = {
2046                 .enable_reg = 0x27004,
2047                 .enable_mask = BIT(0),
2048                 .hw.init = &(struct clk_init_data){
2049                         .name = "gcc_blsp2_uart1_apps_clk",
2050                         .parent_hws = (const struct clk_hw*[]){
2051                                 &blsp2_uart1_apps_clk_src.clkr.hw,
2052                         },
2053                         .num_parents = 1,
2054                         .flags = CLK_SET_RATE_PARENT,
2055                         .ops = &clk_branch2_ops,
2056                 },
2057         },
2058 };
2059
2060 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
2061         .halt_reg = 0x28004,
2062         .clkr = {
2063                 .enable_reg = 0x28004,
2064                 .enable_mask = BIT(0),
2065                 .hw.init = &(struct clk_init_data){
2066                         .name = "gcc_blsp2_qup2_spi_apps_clk",
2067                         .parent_hws = (const struct clk_hw*[]){
2068                                 &blsp2_qup2_spi_apps_clk_src.clkr.hw,
2069                         },
2070                         .num_parents = 1,
2071                         .flags = CLK_SET_RATE_PARENT,
2072                         .ops = &clk_branch2_ops,
2073                 },
2074         },
2075 };
2076
2077 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
2078         .halt_reg = 0x28008,
2079         .clkr = {
2080                 .enable_reg = 0x28008,
2081                 .enable_mask = BIT(0),
2082                 .hw.init = &(struct clk_init_data){
2083                         .name = "gcc_blsp2_qup2_i2c_apps_clk",
2084                         .parent_hws = (const struct clk_hw*[]){
2085                                 &blsp2_qup2_i2c_apps_clk_src.clkr.hw,
2086                         },
2087                         .num_parents = 1,
2088                         .flags = CLK_SET_RATE_PARENT,
2089                         .ops = &clk_branch2_ops,
2090                 },
2091         },
2092 };
2093
2094 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
2095         .halt_reg = 0x29004,
2096         .clkr = {
2097                 .enable_reg = 0x29004,
2098                 .enable_mask = BIT(0),
2099                 .hw.init = &(struct clk_init_data){
2100                         .name = "gcc_blsp2_uart2_apps_clk",
2101                         .parent_hws = (const struct clk_hw*[]){
2102                                 &blsp2_uart2_apps_clk_src.clkr.hw,
2103                         },
2104                         .num_parents = 1,
2105                         .flags = CLK_SET_RATE_PARENT,
2106                         .ops = &clk_branch2_ops,
2107                 },
2108         },
2109 };
2110
2111 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
2112         .halt_reg = 0x2a004,
2113         .clkr = {
2114                 .enable_reg = 0x2a004,
2115                 .enable_mask = BIT(0),
2116                 .hw.init = &(struct clk_init_data){
2117                         .name = "gcc_blsp2_qup3_spi_apps_clk",
2118                         .parent_hws = (const struct clk_hw*[]){
2119                                 &blsp2_qup3_spi_apps_clk_src.clkr.hw,
2120                         },
2121                         .num_parents = 1,
2122                         .flags = CLK_SET_RATE_PARENT,
2123                         .ops = &clk_branch2_ops,
2124                 },
2125         },
2126 };
2127
2128 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
2129         .halt_reg = 0x2a008,
2130         .clkr = {
2131                 .enable_reg = 0x2a008,
2132                 .enable_mask = BIT(0),
2133                 .hw.init = &(struct clk_init_data){
2134                         .name = "gcc_blsp2_qup3_i2c_apps_clk",
2135                         .parent_hws = (const struct clk_hw*[]){
2136                                 &blsp2_qup3_i2c_apps_clk_src.clkr.hw,
2137                         },
2138                         .num_parents = 1,
2139                         .flags = CLK_SET_RATE_PARENT,
2140                         .ops = &clk_branch2_ops,
2141                 },
2142         },
2143 };
2144
2145 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
2146         .halt_reg = 0x2b004,
2147         .clkr = {
2148                 .enable_reg = 0x2b004,
2149                 .enable_mask = BIT(0),
2150                 .hw.init = &(struct clk_init_data){
2151                         .name = "gcc_blsp2_uart3_apps_clk",
2152                         .parent_hws = (const struct clk_hw*[]){
2153                                 &blsp2_uart3_apps_clk_src.clkr.hw,
2154                         },
2155                         .num_parents = 1,
2156                         .flags = CLK_SET_RATE_PARENT,
2157                         .ops = &clk_branch2_ops,
2158                 },
2159         },
2160 };
2161
2162 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
2163         .halt_reg = 0x2c004,
2164         .clkr = {
2165                 .enable_reg = 0x2c004,
2166                 .enable_mask = BIT(0),
2167                 .hw.init = &(struct clk_init_data){
2168                         .name = "gcc_blsp2_qup4_spi_apps_clk",
2169                         .parent_hws = (const struct clk_hw*[]){
2170                                 &blsp2_qup4_spi_apps_clk_src.clkr.hw,
2171                         },
2172                         .num_parents = 1,
2173                         .flags = CLK_SET_RATE_PARENT,
2174                         .ops = &clk_branch2_ops,
2175                 },
2176         },
2177 };
2178
2179 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
2180         .halt_reg = 0x2c008,
2181         .clkr = {
2182                 .enable_reg = 0x2c008,
2183                 .enable_mask = BIT(0),
2184                 .hw.init = &(struct clk_init_data){
2185                         .name = "gcc_blsp2_qup4_i2c_apps_clk",
2186                         .parent_hws = (const struct clk_hw*[]){
2187                                 &blsp2_qup4_i2c_apps_clk_src.clkr.hw,
2188                         },
2189                         .num_parents = 1,
2190                         .flags = CLK_SET_RATE_PARENT,
2191                         .ops = &clk_branch2_ops,
2192                 },
2193         },
2194 };
2195
2196 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
2197         .halt_reg = 0x2d004,
2198         .clkr = {
2199                 .enable_reg = 0x2d004,
2200                 .enable_mask = BIT(0),
2201                 .hw.init = &(struct clk_init_data){
2202                         .name = "gcc_blsp2_uart4_apps_clk",
2203                         .parent_hws = (const struct clk_hw*[]){
2204                                 &blsp2_uart4_apps_clk_src.clkr.hw,
2205                         },
2206                         .num_parents = 1,
2207                         .flags = CLK_SET_RATE_PARENT,
2208                         .ops = &clk_branch2_ops,
2209                 },
2210         },
2211 };
2212
2213 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
2214         .halt_reg = 0x2e004,
2215         .clkr = {
2216                 .enable_reg = 0x2e004,
2217                 .enable_mask = BIT(0),
2218                 .hw.init = &(struct clk_init_data){
2219                         .name = "gcc_blsp2_qup5_spi_apps_clk",
2220                         .parent_hws = (const struct clk_hw*[]){
2221                                 &blsp2_qup5_spi_apps_clk_src.clkr.hw,
2222                         },
2223                         .num_parents = 1,
2224                         .flags = CLK_SET_RATE_PARENT,
2225                         .ops = &clk_branch2_ops,
2226                 },
2227         },
2228 };
2229
2230 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
2231         .halt_reg = 0x2e008,
2232         .clkr = {
2233                 .enable_reg = 0x2e008,
2234                 .enable_mask = BIT(0),
2235                 .hw.init = &(struct clk_init_data){
2236                         .name = "gcc_blsp2_qup5_i2c_apps_clk",
2237                         .parent_hws = (const struct clk_hw*[]){
2238                                 &blsp2_qup5_i2c_apps_clk_src.clkr.hw,
2239                         },
2240                         .num_parents = 1,
2241                         .flags = CLK_SET_RATE_PARENT,
2242                         .ops = &clk_branch2_ops,
2243                 },
2244         },
2245 };
2246
2247 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
2248         .halt_reg = 0x2f004,
2249         .clkr = {
2250                 .enable_reg = 0x2f004,
2251                 .enable_mask = BIT(0),
2252                 .hw.init = &(struct clk_init_data){
2253                         .name = "gcc_blsp2_uart5_apps_clk",
2254                         .parent_hws = (const struct clk_hw*[]){
2255                                 &blsp2_uart5_apps_clk_src.clkr.hw,
2256                         },
2257                         .num_parents = 1,
2258                         .flags = CLK_SET_RATE_PARENT,
2259                         .ops = &clk_branch2_ops,
2260                 },
2261         },
2262 };
2263
2264 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
2265         .halt_reg = 0x30004,
2266         .clkr = {
2267                 .enable_reg = 0x30004,
2268                 .enable_mask = BIT(0),
2269                 .hw.init = &(struct clk_init_data){
2270                         .name = "gcc_blsp2_qup6_spi_apps_clk",
2271                         .parent_hws = (const struct clk_hw*[]){
2272                                 &blsp2_qup6_spi_apps_clk_src.clkr.hw,
2273                         },
2274                         .num_parents = 1,
2275                         .flags = CLK_SET_RATE_PARENT,
2276                         .ops = &clk_branch2_ops,
2277                 },
2278         },
2279 };
2280
2281 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
2282         .halt_reg = 0x30008,
2283         .clkr = {
2284                 .enable_reg = 0x30008,
2285                 .enable_mask = BIT(0),
2286                 .hw.init = &(struct clk_init_data){
2287                         .name = "gcc_blsp2_qup6_i2c_apps_clk",
2288                         .parent_hws = (const struct clk_hw*[]){
2289                                 &blsp2_qup6_i2c_apps_clk_src.clkr.hw,
2290                         },
2291                         .num_parents = 1,
2292                         .flags = CLK_SET_RATE_PARENT,
2293                         .ops = &clk_branch2_ops,
2294                 },
2295         },
2296 };
2297
2298 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
2299         .halt_reg = 0x31004,
2300         .clkr = {
2301                 .enable_reg = 0x31004,
2302                 .enable_mask = BIT(0),
2303                 .hw.init = &(struct clk_init_data){
2304                         .name = "gcc_blsp2_uart6_apps_clk",
2305                         .parent_hws = (const struct clk_hw*[]){
2306                                 &blsp2_uart6_apps_clk_src.clkr.hw,
2307                         },
2308                         .num_parents = 1,
2309                         .flags = CLK_SET_RATE_PARENT,
2310                         .ops = &clk_branch2_ops,
2311                 },
2312         },
2313 };
2314
2315 static struct clk_branch gcc_pdm_ahb_clk = {
2316         .halt_reg = 0x33004,
2317         .clkr = {
2318                 .enable_reg = 0x33004,
2319                 .enable_mask = BIT(0),
2320                 .hw.init = &(struct clk_init_data){
2321                         .name = "gcc_pdm_ahb_clk",
2322                         .parent_hws = (const struct clk_hw*[]){
2323                                 &periph_noc_clk_src.clkr.hw,
2324                         },
2325                         .num_parents = 1,
2326                         .flags = CLK_SET_RATE_PARENT,
2327                         .ops = &clk_branch2_ops,
2328                 },
2329         },
2330 };
2331
2332 static struct clk_branch gcc_pdm2_clk = {
2333         .halt_reg = 0x3300c,
2334         .clkr = {
2335                 .enable_reg = 0x3300c,
2336                 .enable_mask = BIT(0),
2337                 .hw.init = &(struct clk_init_data){
2338                         .name = "gcc_pdm2_clk",
2339                         .parent_hws = (const struct clk_hw*[]){
2340                                 &pdm2_clk_src.clkr.hw,
2341                         },
2342                         .num_parents = 1,
2343                         .flags = CLK_SET_RATE_PARENT,
2344                         .ops = &clk_branch2_ops,
2345                 },
2346         },
2347 };
2348
2349 static struct clk_branch gcc_prng_ahb_clk = {
2350         .halt_reg = 0x34004,
2351         .halt_check = BRANCH_HALT_VOTED,
2352         .clkr = {
2353                 .enable_reg = 0x52004,
2354                 .enable_mask = BIT(13),
2355                 .hw.init = &(struct clk_init_data){
2356                         .name = "gcc_prng_ahb_clk",
2357                         .parent_hws = (const struct clk_hw*[]){
2358                                 &config_noc_clk_src.clkr.hw,
2359                         },
2360                         .num_parents = 1,
2361                         .flags = CLK_SET_RATE_PARENT,
2362                         .ops = &clk_branch2_ops,
2363                 },
2364         },
2365 };
2366
2367 static struct clk_branch gcc_tsif_ahb_clk = {
2368         .halt_reg = 0x36004,
2369         .clkr = {
2370                 .enable_reg = 0x36004,
2371                 .enable_mask = BIT(0),
2372                 .hw.init = &(struct clk_init_data){
2373                         .name = "gcc_tsif_ahb_clk",
2374                         .parent_hws = (const struct clk_hw*[]){
2375                                 &periph_noc_clk_src.clkr.hw,
2376                         },
2377                         .num_parents = 1,
2378                         .flags = CLK_SET_RATE_PARENT,
2379                         .ops = &clk_branch2_ops,
2380                 },
2381         },
2382 };
2383
2384 static struct clk_branch gcc_tsif_ref_clk = {
2385         .halt_reg = 0x36008,
2386         .clkr = {
2387                 .enable_reg = 0x36008,
2388                 .enable_mask = BIT(0),
2389                 .hw.init = &(struct clk_init_data){
2390                         .name = "gcc_tsif_ref_clk",
2391                         .parent_hws = (const struct clk_hw*[]){
2392                                 &tsif_ref_clk_src.clkr.hw,
2393                         },
2394                         .num_parents = 1,
2395                         .flags = CLK_SET_RATE_PARENT,
2396                         .ops = &clk_branch2_ops,
2397                 },
2398         },
2399 };
2400
2401 static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2402         .halt_reg = 0x3600c,
2403         .clkr = {
2404                 .enable_reg = 0x3600c,
2405                 .enable_mask = BIT(0),
2406                 .hw.init = &(struct clk_init_data){
2407                         .name = "gcc_tsif_inactivity_timers_clk",
2408                         .parent_hws = (const struct clk_hw*[]){
2409                                 &gcc_sleep_clk_src.clkr.hw,
2410                         },
2411                         .num_parents = 1,
2412                         .flags = CLK_SET_RATE_PARENT,
2413                         .ops = &clk_branch2_ops,
2414                 },
2415         },
2416 };
2417
2418 static struct clk_branch gcc_boot_rom_ahb_clk = {
2419         .halt_reg = 0x38004,
2420         .halt_check = BRANCH_HALT_VOTED,
2421         .clkr = {
2422                 .enable_reg = 0x52004,
2423                 .enable_mask = BIT(10),
2424                 .hw.init = &(struct clk_init_data){
2425                         .name = "gcc_boot_rom_ahb_clk",
2426                         .parent_hws = (const struct clk_hw*[]){
2427                                 &config_noc_clk_src.clkr.hw,
2428                         },
2429                         .num_parents = 1,
2430                         .flags = CLK_SET_RATE_PARENT,
2431                         .ops = &clk_branch2_ops,
2432                 },
2433         },
2434 };
2435
2436 static struct clk_branch gcc_bimc_gfx_clk = {
2437         .halt_reg = 0x46018,
2438         .clkr = {
2439                 .enable_reg = 0x46018,
2440                 .enable_mask = BIT(0),
2441                 .hw.init = &(struct clk_init_data){
2442                         .name = "gcc_bimc_gfx_clk",
2443                         .flags = CLK_SET_RATE_PARENT,
2444                         .ops = &clk_branch2_ops,
2445                 },
2446         },
2447 };
2448
2449 static struct clk_branch gcc_hmss_rbcpr_clk = {
2450         .halt_reg = 0x4800c,
2451         .clkr = {
2452                 .enable_reg = 0x4800c,
2453                 .enable_mask = BIT(0),
2454                 .hw.init = &(struct clk_init_data){
2455                         .name = "gcc_hmss_rbcpr_clk",
2456                         .parent_hws = (const struct clk_hw*[]){
2457                                 &hmss_rbcpr_clk_src.clkr.hw,
2458                         },
2459                         .num_parents = 1,
2460                         .flags = CLK_SET_RATE_PARENT,
2461                         .ops = &clk_branch2_ops,
2462                 },
2463         },
2464 };
2465
2466 static struct clk_branch gcc_gp1_clk = {
2467         .halt_reg = 0x64000,
2468         .clkr = {
2469                 .enable_reg = 0x64000,
2470                 .enable_mask = BIT(0),
2471                 .hw.init = &(struct clk_init_data){
2472                         .name = "gcc_gp1_clk",
2473                         .parent_hws = (const struct clk_hw*[]){
2474                                 &gp1_clk_src.clkr.hw,
2475                         },
2476                         .num_parents = 1,
2477                         .flags = CLK_SET_RATE_PARENT,
2478                         .ops = &clk_branch2_ops,
2479                 },
2480         },
2481 };
2482
2483 static struct clk_branch gcc_gp2_clk = {
2484         .halt_reg = 0x65000,
2485         .clkr = {
2486                 .enable_reg = 0x65000,
2487                 .enable_mask = BIT(0),
2488                 .hw.init = &(struct clk_init_data){
2489                         .name = "gcc_gp2_clk",
2490                         .parent_hws = (const struct clk_hw*[]){
2491                                 &gp2_clk_src.clkr.hw,
2492                         },
2493                         .num_parents = 1,
2494                         .flags = CLK_SET_RATE_PARENT,
2495                         .ops = &clk_branch2_ops,
2496                 },
2497         },
2498 };
2499
2500 static struct clk_branch gcc_gp3_clk = {
2501         .halt_reg = 0x66000,
2502         .clkr = {
2503                 .enable_reg = 0x66000,
2504                 .enable_mask = BIT(0),
2505                 .hw.init = &(struct clk_init_data){
2506                         .name = "gcc_gp3_clk",
2507                         .parent_hws = (const struct clk_hw*[]){
2508                                 &gp3_clk_src.clkr.hw,
2509                         },
2510                         .num_parents = 1,
2511                         .flags = CLK_SET_RATE_PARENT,
2512                         .ops = &clk_branch2_ops,
2513                 },
2514         },
2515 };
2516
2517 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2518         .halt_reg = 0x6b008,
2519         .clkr = {
2520                 .enable_reg = 0x6b008,
2521                 .enable_mask = BIT(0),
2522                 .hw.init = &(struct clk_init_data){
2523                         .name = "gcc_pcie_0_slv_axi_clk",
2524                         .parent_hws = (const struct clk_hw*[]){
2525                                 &system_noc_clk_src.clkr.hw,
2526                         },
2527                         .num_parents = 1,
2528                         .flags = CLK_SET_RATE_PARENT,
2529                         .ops = &clk_branch2_ops,
2530                 },
2531         },
2532 };
2533
2534 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2535         .halt_reg = 0x6b00c,
2536         .clkr = {
2537                 .enable_reg = 0x6b00c,
2538                 .enable_mask = BIT(0),
2539                 .hw.init = &(struct clk_init_data){
2540                         .name = "gcc_pcie_0_mstr_axi_clk",
2541                         .parent_hws = (const struct clk_hw*[]){
2542                                 &system_noc_clk_src.clkr.hw,
2543                         },
2544                         .num_parents = 1,
2545                         .flags = CLK_SET_RATE_PARENT,
2546                         .ops = &clk_branch2_ops,
2547                 },
2548         },
2549 };
2550
2551 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2552         .halt_reg = 0x6b010,
2553         .clkr = {
2554                 .enable_reg = 0x6b010,
2555                 .enable_mask = BIT(0),
2556                 .hw.init = &(struct clk_init_data){
2557                         .name = "gcc_pcie_0_cfg_ahb_clk",
2558                         .parent_hws = (const struct clk_hw*[]){
2559                                 &config_noc_clk_src.clkr.hw,
2560                         },
2561                         .num_parents = 1,
2562                         .flags = CLK_SET_RATE_PARENT,
2563                         .ops = &clk_branch2_ops,
2564                 },
2565         },
2566 };
2567
2568 static struct clk_branch gcc_pcie_0_aux_clk = {
2569         .halt_reg = 0x6b014,
2570         .clkr = {
2571                 .enable_reg = 0x6b014,
2572                 .enable_mask = BIT(0),
2573                 .hw.init = &(struct clk_init_data){
2574                         .name = "gcc_pcie_0_aux_clk",
2575                         .parent_hws = (const struct clk_hw*[]){
2576                                 &pcie_aux_clk_src.clkr.hw,
2577                         },
2578                         .num_parents = 1,
2579                         .flags = CLK_SET_RATE_PARENT,
2580                         .ops = &clk_branch2_ops,
2581                 },
2582         },
2583 };
2584
2585 static struct clk_branch gcc_pcie_0_pipe_clk = {
2586         .halt_reg = 0x6b018,
2587         .halt_check = BRANCH_HALT_SKIP,
2588         .clkr = {
2589                 .enable_reg = 0x6b018,
2590                 .enable_mask = BIT(0),
2591                 .hw.init = &(struct clk_init_data){
2592                         .name = "gcc_pcie_0_pipe_clk",
2593                         .parent_data = &(const struct clk_parent_data){
2594                                 .fw_name = "pcie_0_pipe_clk_src", .name = "pcie_0_pipe_clk_src",
2595                         },
2596                         .num_parents = 1,
2597                         .flags = CLK_SET_RATE_PARENT,
2598                         .ops = &clk_branch2_ops,
2599                 },
2600         },
2601 };
2602
2603 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2604         .halt_reg = 0x6d008,
2605         .clkr = {
2606                 .enable_reg = 0x6d008,
2607                 .enable_mask = BIT(0),
2608                 .hw.init = &(struct clk_init_data){
2609                         .name = "gcc_pcie_1_slv_axi_clk",
2610                         .parent_hws = (const struct clk_hw*[]){
2611                                 &system_noc_clk_src.clkr.hw,
2612                         },
2613                         .num_parents = 1,
2614                         .flags = CLK_SET_RATE_PARENT,
2615                         .ops = &clk_branch2_ops,
2616                 },
2617         },
2618 };
2619
2620 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2621         .halt_reg = 0x6d00c,
2622         .clkr = {
2623                 .enable_reg = 0x6d00c,
2624                 .enable_mask = BIT(0),
2625                 .hw.init = &(struct clk_init_data){
2626                         .name = "gcc_pcie_1_mstr_axi_clk",
2627                         .parent_hws = (const struct clk_hw*[]){
2628                                 &system_noc_clk_src.clkr.hw,
2629                         },
2630                         .num_parents = 1,
2631                         .flags = CLK_SET_RATE_PARENT,
2632                         .ops = &clk_branch2_ops,
2633                 },
2634         },
2635 };
2636
2637 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2638         .halt_reg = 0x6d010,
2639         .clkr = {
2640                 .enable_reg = 0x6d010,
2641                 .enable_mask = BIT(0),
2642                 .hw.init = &(struct clk_init_data){
2643                         .name = "gcc_pcie_1_cfg_ahb_clk",
2644                         .parent_hws = (const struct clk_hw*[]){
2645                                 &config_noc_clk_src.clkr.hw,
2646                         },
2647                         .num_parents = 1,
2648                         .flags = CLK_SET_RATE_PARENT,
2649                         .ops = &clk_branch2_ops,
2650                 },
2651         },
2652 };
2653
2654 static struct clk_branch gcc_pcie_1_aux_clk = {
2655         .halt_reg = 0x6d014,
2656         .clkr = {
2657                 .enable_reg = 0x6d014,
2658                 .enable_mask = BIT(0),
2659                 .hw.init = &(struct clk_init_data){
2660                         .name = "gcc_pcie_1_aux_clk",
2661                         .parent_hws = (const struct clk_hw*[]){
2662                                 &pcie_aux_clk_src.clkr.hw,
2663                         },
2664                         .num_parents = 1,
2665                         .flags = CLK_SET_RATE_PARENT,
2666                         .ops = &clk_branch2_ops,
2667                 },
2668         },
2669 };
2670
2671 static struct clk_branch gcc_pcie_1_pipe_clk = {
2672         .halt_reg = 0x6d018,
2673         .halt_check = BRANCH_HALT_SKIP,
2674         .clkr = {
2675                 .enable_reg = 0x6d018,
2676                 .enable_mask = BIT(0),
2677                 .hw.init = &(struct clk_init_data){
2678                         .name = "gcc_pcie_1_pipe_clk",
2679                         .parent_data = &(const struct clk_parent_data){
2680                                 .fw_name = "pcie_1_pipe_clk_src", .name = "pcie_1_pipe_clk_src",
2681                         },
2682                         .num_parents = 1,
2683                         .flags = CLK_SET_RATE_PARENT,
2684                         .ops = &clk_branch2_ops,
2685                 },
2686         },
2687 };
2688
2689 static struct clk_branch gcc_pcie_2_slv_axi_clk = {
2690         .halt_reg = 0x6e008,
2691         .clkr = {
2692                 .enable_reg = 0x6e008,
2693                 .enable_mask = BIT(0),
2694                 .hw.init = &(struct clk_init_data){
2695                         .name = "gcc_pcie_2_slv_axi_clk",
2696                         .parent_hws = (const struct clk_hw*[]){
2697                                 &system_noc_clk_src.clkr.hw,
2698                         },
2699                         .num_parents = 1,
2700                         .flags = CLK_SET_RATE_PARENT,
2701                         .ops = &clk_branch2_ops,
2702                 },
2703         },
2704 };
2705
2706 static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
2707         .halt_reg = 0x6e00c,
2708         .clkr = {
2709                 .enable_reg = 0x6e00c,
2710                 .enable_mask = BIT(0),
2711                 .hw.init = &(struct clk_init_data){
2712                         .name = "gcc_pcie_2_mstr_axi_clk",
2713                         .parent_hws = (const struct clk_hw*[]){
2714                                 &system_noc_clk_src.clkr.hw,
2715                         },
2716                         .num_parents = 1,
2717                         .flags = CLK_SET_RATE_PARENT,
2718                         .ops = &clk_branch2_ops,
2719                 },
2720         },
2721 };
2722
2723 static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
2724         .halt_reg = 0x6e010,
2725         .clkr = {
2726                 .enable_reg = 0x6e010,
2727                 .enable_mask = BIT(0),
2728                 .hw.init = &(struct clk_init_data){
2729                         .name = "gcc_pcie_2_cfg_ahb_clk",
2730                         .parent_hws = (const struct clk_hw*[]){
2731                                 &config_noc_clk_src.clkr.hw,
2732                         },
2733                         .num_parents = 1,
2734                         .flags = CLK_SET_RATE_PARENT,
2735                         .ops = &clk_branch2_ops,
2736                 },
2737         },
2738 };
2739
2740 static struct clk_branch gcc_pcie_2_aux_clk = {
2741         .halt_reg = 0x6e014,
2742         .clkr = {
2743                 .enable_reg = 0x6e014,
2744                 .enable_mask = BIT(0),
2745                 .hw.init = &(struct clk_init_data){
2746                         .name = "gcc_pcie_2_aux_clk",
2747                         .parent_hws = (const struct clk_hw*[]){
2748                                 &pcie_aux_clk_src.clkr.hw,
2749                         },
2750                         .num_parents = 1,
2751                         .flags = CLK_SET_RATE_PARENT,
2752                         .ops = &clk_branch2_ops,
2753                 },
2754         },
2755 };
2756
2757 static struct clk_branch gcc_pcie_2_pipe_clk = {
2758         .halt_reg = 0x6e018,
2759         .halt_check = BRANCH_HALT_SKIP,
2760         .clkr = {
2761                 .enable_reg = 0x6e018,
2762                 .enable_mask = BIT(0),
2763                 .hw.init = &(struct clk_init_data){
2764                         .name = "gcc_pcie_2_pipe_clk",
2765                         .parent_data = &(const struct clk_parent_data){
2766                                 .fw_name = "pcie_2_pipe_clk_src", .name = "pcie_2_pipe_clk_src",
2767                         },
2768                         .num_parents = 1,
2769                         .flags = CLK_SET_RATE_PARENT,
2770                         .ops = &clk_branch2_ops,
2771                 },
2772         },
2773 };
2774
2775 static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
2776         .halt_reg = 0x6f004,
2777         .clkr = {
2778                 .enable_reg = 0x6f004,
2779                 .enable_mask = BIT(0),
2780                 .hw.init = &(struct clk_init_data){
2781                         .name = "gcc_pcie_phy_cfg_ahb_clk",
2782                         .parent_hws = (const struct clk_hw*[]){
2783                                 &config_noc_clk_src.clkr.hw,
2784                         },
2785                         .num_parents = 1,
2786                         .flags = CLK_SET_RATE_PARENT,
2787                         .ops = &clk_branch2_ops,
2788                 },
2789         },
2790 };
2791
2792 static struct clk_branch gcc_pcie_phy_aux_clk = {
2793         .halt_reg = 0x6f008,
2794         .clkr = {
2795                 .enable_reg = 0x6f008,
2796                 .enable_mask = BIT(0),
2797                 .hw.init = &(struct clk_init_data){
2798                         .name = "gcc_pcie_phy_aux_clk",
2799                         .parent_hws = (const struct clk_hw*[]){
2800                                 &pcie_aux_clk_src.clkr.hw,
2801                         },
2802                         .num_parents = 1,
2803                         .flags = CLK_SET_RATE_PARENT,
2804                         .ops = &clk_branch2_ops,
2805                 },
2806         },
2807 };
2808
2809 static struct clk_branch gcc_ufs_axi_clk = {
2810         .halt_reg = 0x75008,
2811         .clkr = {
2812                 .enable_reg = 0x75008,
2813                 .enable_mask = BIT(0),
2814                 .hw.init = &(struct clk_init_data){
2815                         .name = "gcc_ufs_axi_clk",
2816                         .parent_hws = (const struct clk_hw*[]){
2817                                 &ufs_axi_clk_src.clkr.hw,
2818                         },
2819                         .num_parents = 1,
2820                         .flags = CLK_SET_RATE_PARENT,
2821                         .ops = &clk_branch2_ops,
2822                 },
2823         },
2824 };
2825
2826 static struct clk_branch gcc_ufs_ahb_clk = {
2827         .halt_reg = 0x7500c,
2828         .clkr = {
2829                 .enable_reg = 0x7500c,
2830                 .enable_mask = BIT(0),
2831                 .hw.init = &(struct clk_init_data){
2832                         .name = "gcc_ufs_ahb_clk",
2833                         .parent_hws = (const struct clk_hw*[]){
2834                                 &config_noc_clk_src.clkr.hw,
2835                         },
2836                         .num_parents = 1,
2837                         .flags = CLK_SET_RATE_PARENT,
2838                         .ops = &clk_branch2_ops,
2839                 },
2840         },
2841 };
2842
2843 static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
2844         .mult = 1,
2845         .div = 16,
2846         .hw.init = &(struct clk_init_data){
2847                 .name = "ufs_tx_cfg_clk_src",
2848                 .parent_hws = (const struct clk_hw*[]){
2849                         &ufs_axi_clk_src.clkr.hw,
2850                 },
2851                 .num_parents = 1,
2852                 .flags = CLK_SET_RATE_PARENT,
2853                 .ops = &clk_fixed_factor_ops,
2854         },
2855 };
2856
2857 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2858         .halt_reg = 0x75010,
2859         .clkr = {
2860                 .enable_reg = 0x75010,
2861                 .enable_mask = BIT(0),
2862                 .hw.init = &(struct clk_init_data){
2863                         .name = "gcc_ufs_tx_cfg_clk",
2864                         .parent_hws = (const struct clk_hw*[]){
2865                                 &ufs_tx_cfg_clk_src.hw,
2866                         },
2867                         .num_parents = 1,
2868                         .flags = CLK_SET_RATE_PARENT,
2869                         .ops = &clk_branch2_ops,
2870                 },
2871         },
2872 };
2873
2874 static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
2875         .mult = 1,
2876         .div = 16,
2877         .hw.init = &(struct clk_init_data){
2878                 .name = "ufs_rx_cfg_clk_src",
2879                 .parent_hws = (const struct clk_hw*[]){
2880                         &ufs_axi_clk_src.clkr.hw,
2881                 },
2882                 .num_parents = 1,
2883                 .flags = CLK_SET_RATE_PARENT,
2884                 .ops = &clk_fixed_factor_ops,
2885         },
2886 };
2887
2888 static struct clk_branch gcc_hlos1_vote_lpass_core_smmu_clk = {
2889         .halt_reg = 0x7d010,
2890         .halt_check = BRANCH_HALT_VOTED,
2891         .clkr = {
2892                 .enable_reg = 0x7d010,
2893                 .enable_mask = BIT(0),
2894                 .hw.init = &(struct clk_init_data){
2895                         .name = "hlos1_vote_lpass_core_smmu_clk",
2896                         .ops = &clk_branch2_ops,
2897                 },
2898         },
2899 };
2900
2901 static struct clk_branch gcc_hlos1_vote_lpass_adsp_smmu_clk = {
2902         .halt_reg = 0x7d014,
2903         .halt_check = BRANCH_HALT_VOTED,
2904         .clkr = {
2905                 .enable_reg = 0x7d014,
2906                 .enable_mask = BIT(0),
2907                 .hw.init = &(struct clk_init_data){
2908                         .name = "hlos1_vote_lpass_adsp_smmu_clk",
2909                         .ops = &clk_branch2_ops,
2910                 },
2911         },
2912 };
2913
2914 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2915         .halt_reg = 0x75014,
2916         .clkr = {
2917                 .enable_reg = 0x75014,
2918                 .enable_mask = BIT(0),
2919                 .hw.init = &(struct clk_init_data){
2920                         .name = "gcc_ufs_rx_cfg_clk",
2921                         .parent_hws = (const struct clk_hw*[]){
2922                                 &ufs_rx_cfg_clk_src.hw,
2923                         },
2924                         .num_parents = 1,
2925                         .flags = CLK_SET_RATE_PARENT,
2926                         .ops = &clk_branch2_ops,
2927                 },
2928         },
2929 };
2930
2931 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2932         .halt_reg = 0x75018,
2933         .halt_check = BRANCH_HALT_SKIP,
2934         .clkr = {
2935                 .enable_reg = 0x75018,
2936                 .enable_mask = BIT(0),
2937                 .hw.init = &(struct clk_init_data){
2938                         .name = "gcc_ufs_tx_symbol_0_clk",
2939                         .parent_data = &(const struct clk_parent_data){
2940                                 .fw_name = "ufs_tx_symbol_0_clk_src", .name = "ufs_tx_symbol_0_clk_src",
2941                         },
2942                         .num_parents = 1,
2943                         .flags = CLK_SET_RATE_PARENT,
2944                         .ops = &clk_branch2_ops,
2945                 },
2946         },
2947 };
2948
2949 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2950         .halt_reg = 0x7501c,
2951         .halt_check = BRANCH_HALT_SKIP,
2952         .clkr = {
2953                 .enable_reg = 0x7501c,
2954                 .enable_mask = BIT(0),
2955                 .hw.init = &(struct clk_init_data){
2956                         .name = "gcc_ufs_rx_symbol_0_clk",
2957                         .parent_data = &(const struct clk_parent_data){
2958                                 .fw_name = "ufs_rx_symbol_0_clk_src", .name = "ufs_rx_symbol_0_clk_src",
2959                         },
2960                         .num_parents = 1,
2961                         .flags = CLK_SET_RATE_PARENT,
2962                         .ops = &clk_branch2_ops,
2963                 },
2964         },
2965 };
2966
2967 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2968         .halt_reg = 0x75020,
2969         .halt_check = BRANCH_HALT_SKIP,
2970         .clkr = {
2971                 .enable_reg = 0x75020,
2972                 .enable_mask = BIT(0),
2973                 .hw.init = &(struct clk_init_data){
2974                         .name = "gcc_ufs_rx_symbol_1_clk",
2975                         .parent_data = &(const struct clk_parent_data){
2976                                 .fw_name = "ufs_rx_symbol_1_clk_src", .name = "ufs_rx_symbol_1_clk_src",
2977                         },
2978                         .num_parents = 1,
2979                         .flags = CLK_SET_RATE_PARENT,
2980                         .ops = &clk_branch2_ops,
2981                 },
2982         },
2983 };
2984
2985 static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
2986         .mult = 1,
2987         .div = 2,
2988         .hw.init = &(struct clk_init_data){
2989                 .name = "ufs_ice_core_postdiv_clk_src",
2990                 .parent_hws = (const struct clk_hw*[]){
2991                         &ufs_ice_core_clk_src.clkr.hw,
2992                 },
2993                 .num_parents = 1,
2994                 .flags = CLK_SET_RATE_PARENT,
2995                 .ops = &clk_fixed_factor_ops,
2996         },
2997 };
2998
2999 static struct clk_branch gcc_ufs_unipro_core_clk = {
3000         .halt_reg = 0x7600c,
3001         .clkr = {
3002                 .enable_reg = 0x7600c,
3003                 .enable_mask = BIT(0),
3004                 .hw.init = &(struct clk_init_data){
3005                         .name = "gcc_ufs_unipro_core_clk",
3006                         .parent_hws = (const struct clk_hw*[]){
3007                                 &ufs_ice_core_postdiv_clk_src.hw,
3008                         },
3009                         .num_parents = 1,
3010                         .flags = CLK_SET_RATE_PARENT,
3011                         .ops = &clk_branch2_ops,
3012                 },
3013         },
3014 };
3015
3016 static struct clk_branch gcc_ufs_ice_core_clk = {
3017         .halt_reg = 0x76010,
3018         .clkr = {
3019                 .enable_reg = 0x76010,
3020                 .enable_mask = BIT(0),
3021                 .hw.init = &(struct clk_init_data){
3022                         .name = "gcc_ufs_ice_core_clk",
3023                         .parent_hws = (const struct clk_hw*[]){
3024                                 &ufs_ice_core_clk_src.clkr.hw,
3025                         },
3026                         .num_parents = 1,
3027                         .flags = CLK_SET_RATE_PARENT,
3028                         .ops = &clk_branch2_ops,
3029                 },
3030         },
3031 };
3032
3033 static struct clk_branch gcc_ufs_sys_clk_core_clk = {
3034         .halt_check = BRANCH_HALT_DELAY,
3035         .clkr = {
3036                 .enable_reg = 0x76030,
3037                 .enable_mask = BIT(0),
3038                 .hw.init = &(struct clk_init_data){
3039                         .name = "gcc_ufs_sys_clk_core_clk",
3040                         .ops = &clk_branch2_ops,
3041                 },
3042         },
3043 };
3044
3045 static struct clk_branch gcc_ufs_tx_symbol_clk_core_clk = {
3046         .halt_check = BRANCH_HALT_DELAY,
3047         .clkr = {
3048                 .enable_reg = 0x76034,
3049                 .enable_mask = BIT(0),
3050                 .hw.init = &(struct clk_init_data){
3051                         .name = "gcc_ufs_tx_symbol_clk_core_clk",
3052                         .ops = &clk_branch2_ops,
3053                 },
3054         },
3055 };
3056
3057 static struct clk_branch gcc_aggre0_snoc_axi_clk = {
3058         .halt_reg = 0x81008,
3059         .clkr = {
3060                 .enable_reg = 0x81008,
3061                 .enable_mask = BIT(0),
3062                 .hw.init = &(struct clk_init_data){
3063                         .name = "gcc_aggre0_snoc_axi_clk",
3064                         .parent_hws = (const struct clk_hw*[]){
3065                                 &system_noc_clk_src.clkr.hw,
3066                         },
3067                         .num_parents = 1,
3068                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
3069                         .ops = &clk_branch2_ops,
3070                 },
3071         },
3072 };
3073
3074 static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
3075         .halt_reg = 0x8100c,
3076         .clkr = {
3077                 .enable_reg = 0x8100c,
3078                 .enable_mask = BIT(0),
3079                 .hw.init = &(struct clk_init_data){
3080                         .name = "gcc_aggre0_cnoc_ahb_clk",
3081                         .parent_hws = (const struct clk_hw*[]){
3082                                 &config_noc_clk_src.clkr.hw,
3083                         },
3084                         .num_parents = 1,
3085                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
3086                         .ops = &clk_branch2_ops,
3087                 },
3088         },
3089 };
3090
3091 static struct clk_branch gcc_smmu_aggre0_axi_clk = {
3092         .halt_reg = 0x81014,
3093         .clkr = {
3094                 .enable_reg = 0x81014,
3095                 .enable_mask = BIT(0),
3096                 .hw.init = &(struct clk_init_data){
3097                         .name = "gcc_smmu_aggre0_axi_clk",
3098                         .parent_hws = (const struct clk_hw*[]){
3099                                 &system_noc_clk_src.clkr.hw,
3100                         },
3101                         .num_parents = 1,
3102                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
3103                         .ops = &clk_branch2_ops,
3104                 },
3105         },
3106 };
3107
3108 static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
3109         .halt_reg = 0x81018,
3110         .clkr = {
3111                 .enable_reg = 0x81018,
3112                 .enable_mask = BIT(0),
3113                 .hw.init = &(struct clk_init_data){
3114                         .name = "gcc_smmu_aggre0_ahb_clk",
3115                         .parent_hws = (const struct clk_hw*[]){
3116                                 &config_noc_clk_src.clkr.hw,
3117                         },
3118                         .num_parents = 1,
3119                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
3120                         .ops = &clk_branch2_ops,
3121                 },
3122         },
3123 };
3124
3125 static struct clk_branch gcc_aggre2_ufs_axi_clk = {
3126         .halt_reg = 0x83014,
3127         .clkr = {
3128                 .enable_reg = 0x83014,
3129                 .enable_mask = BIT(0),
3130                 .hw.init = &(struct clk_init_data){
3131                         .name = "gcc_aggre2_ufs_axi_clk",
3132                         .parent_hws = (const struct clk_hw*[]){
3133                                 &ufs_axi_clk_src.clkr.hw,
3134                         },
3135                         .num_parents = 1,
3136                         .flags = CLK_SET_RATE_PARENT,
3137                         .ops = &clk_branch2_ops,
3138                 },
3139         },
3140 };
3141
3142 static struct clk_branch gcc_aggre2_usb3_axi_clk = {
3143         .halt_reg = 0x83018,
3144         .clkr = {
3145                 .enable_reg = 0x83018,
3146                 .enable_mask = BIT(0),
3147                 .hw.init = &(struct clk_init_data){
3148                         .name = "gcc_aggre2_usb3_axi_clk",
3149                         .parent_hws = (const struct clk_hw*[]){
3150                                 &usb30_master_clk_src.clkr.hw,
3151                         },
3152                         .num_parents = 1,
3153                         .flags = CLK_SET_RATE_PARENT,
3154                         .ops = &clk_branch2_ops,
3155                 },
3156         },
3157 };
3158
3159 static struct clk_branch gcc_dcc_ahb_clk = {
3160         .halt_reg = 0x84004,
3161         .clkr = {
3162                 .enable_reg = 0x84004,
3163                 .enable_mask = BIT(0),
3164                 .hw.init = &(struct clk_init_data){
3165                         .name = "gcc_dcc_ahb_clk",
3166                         .parent_hws = (const struct clk_hw*[]){
3167                                 &config_noc_clk_src.clkr.hw,
3168                         },
3169                         .num_parents = 1,
3170                         .ops = &clk_branch2_ops,
3171                 },
3172         },
3173 };
3174
3175 static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
3176         .halt_reg = 0x85000,
3177         .clkr = {
3178                 .enable_reg = 0x85000,
3179                 .enable_mask = BIT(0),
3180                 .hw.init = &(struct clk_init_data){
3181                         .name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
3182                         .parent_hws = (const struct clk_hw*[]){
3183                                 &config_noc_clk_src.clkr.hw,
3184                         },
3185                         .num_parents = 1,
3186                         .ops = &clk_branch2_ops,
3187                 },
3188         },
3189 };
3190
3191 static struct clk_branch gcc_qspi_ahb_clk = {
3192         .halt_reg = 0x8b004,
3193         .clkr = {
3194                 .enable_reg = 0x8b004,
3195                 .enable_mask = BIT(0),
3196                 .hw.init = &(struct clk_init_data){
3197                         .name = "gcc_qspi_ahb_clk",
3198                         .parent_hws = (const struct clk_hw*[]){
3199                                 &periph_noc_clk_src.clkr.hw,
3200                         },
3201                         .num_parents = 1,
3202                         .flags = CLK_SET_RATE_PARENT,
3203                         .ops = &clk_branch2_ops,
3204                 },
3205         },
3206 };
3207
3208 static struct clk_branch gcc_qspi_ser_clk = {
3209         .halt_reg = 0x8b008,
3210         .clkr = {
3211                 .enable_reg = 0x8b008,
3212                 .enable_mask = BIT(0),
3213                 .hw.init = &(struct clk_init_data){
3214                         .name = "gcc_qspi_ser_clk",
3215                         .parent_hws = (const struct clk_hw*[]){
3216                                 &qspi_ser_clk_src.clkr.hw,
3217                         },
3218                         .num_parents = 1,
3219                         .flags = CLK_SET_RATE_PARENT,
3220                         .ops = &clk_branch2_ops,
3221                 },
3222         },
3223 };
3224
3225 static struct clk_branch gcc_usb3_clkref_clk = {
3226         .halt_reg = 0x8800C,
3227         .clkr = {
3228                 .enable_reg = 0x8800C,
3229                 .enable_mask = BIT(0),
3230                 .hw.init = &(struct clk_init_data){
3231                         .name = "gcc_usb3_clkref_clk",
3232                         .parent_data = &(const struct clk_parent_data){
3233                                 .fw_name = "cxo2",
3234                                 .name = "xo",
3235                         },
3236                         .num_parents = 1,
3237                         .ops = &clk_branch2_ops,
3238                 },
3239         },
3240 };
3241
3242 static struct clk_branch gcc_hdmi_clkref_clk = {
3243         .halt_reg = 0x88000,
3244         .clkr = {
3245                 .enable_reg = 0x88000,
3246                 .enable_mask = BIT(0),
3247                 .hw.init = &(struct clk_init_data){
3248                         .name = "gcc_hdmi_clkref_clk",
3249                         .parent_data = &(const struct clk_parent_data){
3250                                 .fw_name = "cxo2",
3251                                 .name = "xo",
3252                         },
3253                         .num_parents = 1,
3254                         .ops = &clk_branch2_ops,
3255                 },
3256         },
3257 };
3258
3259 static struct clk_branch gcc_edp_clkref_clk = {
3260         .halt_reg = 0x88004,
3261         .clkr = {
3262                 .enable_reg = 0x88004,
3263                 .enable_mask = BIT(0),
3264                 .hw.init = &(struct clk_init_data){
3265                         .name = "gcc_edp_clkref_clk",
3266                         .parent_data = &(const struct clk_parent_data){
3267                                 .fw_name = "cxo2",
3268                                 .name = "xo",
3269                         },
3270                         .num_parents = 1,
3271                         .ops = &clk_branch2_ops,
3272                 },
3273         },
3274 };
3275
3276 static struct clk_branch gcc_ufs_clkref_clk = {
3277         .halt_reg = 0x88008,
3278         .clkr = {
3279                 .enable_reg = 0x88008,
3280                 .enable_mask = BIT(0),
3281                 .hw.init = &(struct clk_init_data){
3282                         .name = "gcc_ufs_clkref_clk",
3283                         .parent_data = &(const struct clk_parent_data){
3284                                 .fw_name = "cxo2",
3285                                 .name = "xo",
3286                         },
3287                         .num_parents = 1,
3288                         .ops = &clk_branch2_ops,
3289                 },
3290         },
3291 };
3292
3293 static struct clk_branch gcc_pcie_clkref_clk = {
3294         .halt_reg = 0x88010,
3295         .clkr = {
3296                 .enable_reg = 0x88010,
3297                 .enable_mask = BIT(0),
3298                 .hw.init = &(struct clk_init_data){
3299                         .name = "gcc_pcie_clkref_clk",
3300                         .parent_data = &(const struct clk_parent_data){
3301                                 .fw_name = "cxo2",
3302                                 .name = "xo",
3303                         },
3304                         .num_parents = 1,
3305                         .ops = &clk_branch2_ops,
3306                 },
3307         },
3308 };
3309
3310 static struct clk_branch gcc_rx2_usb2_clkref_clk = {
3311         .halt_reg = 0x88014,
3312         .clkr = {
3313                 .enable_reg = 0x88014,
3314                 .enable_mask = BIT(0),
3315                 .hw.init = &(struct clk_init_data){
3316                         .name = "gcc_rx2_usb2_clkref_clk",
3317                         .parent_data = &(const struct clk_parent_data){
3318                                 .fw_name = "cxo2",
3319                                 .name = "xo",
3320                         },
3321                         .num_parents = 1,
3322                         .ops = &clk_branch2_ops,
3323                 },
3324         },
3325 };
3326
3327 static struct clk_branch gcc_rx1_usb2_clkref_clk = {
3328         .halt_reg = 0x88018,
3329         .clkr = {
3330                 .enable_reg = 0x88018,
3331                 .enable_mask = BIT(0),
3332                 .hw.init = &(struct clk_init_data){
3333                         .name = "gcc_rx1_usb2_clkref_clk",
3334                         .parent_data = &(const struct clk_parent_data){
3335                                 .fw_name = "cxo2",
3336                                 .name = "xo",
3337                         },
3338                         .num_parents = 1,
3339                         .ops = &clk_branch2_ops,
3340                 },
3341         },
3342 };
3343
3344 static struct clk_branch gcc_mss_cfg_ahb_clk = {
3345         .halt_reg = 0x8a000,
3346         .clkr = {
3347                 .enable_reg = 0x8a000,
3348                 .enable_mask = BIT(0),
3349                 .hw.init = &(struct clk_init_data){
3350                         .name = "gcc_mss_cfg_ahb_clk",
3351                         .parent_hws = (const struct clk_hw*[]){
3352                                 &config_noc_clk_src.clkr.hw,
3353                         },
3354                         .num_parents = 1,
3355                         .ops = &clk_branch2_ops,
3356                 },
3357         },
3358 };
3359
3360 static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
3361         .halt_reg = 0x8a004,
3362         .clkr = {
3363                 .enable_reg = 0x8a004,
3364                 .enable_mask = BIT(0),
3365                 .hw.init = &(struct clk_init_data){
3366                         .name = "gcc_mss_mnoc_bimc_axi_clk",
3367                         .parent_hws = (const struct clk_hw*[]){
3368                                 &system_noc_clk_src.clkr.hw,
3369                         },
3370                         .num_parents = 1,
3371                         .ops = &clk_branch2_ops,
3372                 },
3373         },
3374 };
3375
3376 static struct clk_branch gcc_mss_snoc_axi_clk = {
3377         .halt_reg = 0x8a024,
3378         .clkr = {
3379                 .enable_reg = 0x8a024,
3380                 .enable_mask = BIT(0),
3381                 .hw.init = &(struct clk_init_data){
3382                         .name = "gcc_mss_snoc_axi_clk",
3383                         .parent_hws = (const struct clk_hw*[]){
3384                                 &system_noc_clk_src.clkr.hw,
3385                         },
3386                         .num_parents = 1,
3387                         .ops = &clk_branch2_ops,
3388                 },
3389         },
3390 };
3391
3392 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
3393         .halt_reg = 0x8a028,
3394         .clkr = {
3395                 .enable_reg = 0x8a028,
3396                 .enable_mask = BIT(0),
3397                 .hw.init = &(struct clk_init_data){
3398                         .name = "gcc_mss_q6_bimc_axi_clk",
3399                         .parent_hws = (const struct clk_hw*[]){
3400                                 &system_noc_clk_src.clkr.hw,
3401                         },
3402                         .num_parents = 1,
3403                         .ops = &clk_branch2_ops,
3404                 },
3405         },
3406 };
3407
3408 static struct clk_hw *gcc_msm8996_hws[] = {
3409         &xo.hw,
3410         &gpll0_early_div.hw,
3411         &ufs_tx_cfg_clk_src.hw,
3412         &ufs_rx_cfg_clk_src.hw,
3413         &ufs_ice_core_postdiv_clk_src.hw,
3414 };
3415
3416 static struct gdsc aggre0_noc_gdsc = {
3417         .gdscr = 0x81004,
3418         .gds_hw_ctrl = 0x81028,
3419         .pd = {
3420                 .name = "aggre0_noc",
3421         },
3422         .pwrsts = PWRSTS_OFF_ON,
3423         .flags = VOTABLE | ALWAYS_ON,
3424 };
3425
3426 static struct gdsc hlos1_vote_aggre0_noc_gdsc = {
3427         .gdscr = 0x7d024,
3428         .pd = {
3429                 .name = "hlos1_vote_aggre0_noc",
3430         },
3431         .pwrsts = PWRSTS_OFF_ON,
3432         .flags = VOTABLE,
3433 };
3434
3435 static struct gdsc hlos1_vote_lpass_adsp_gdsc = {
3436         .gdscr = 0x7d034,
3437         .pd = {
3438                 .name = "hlos1_vote_lpass_adsp",
3439         },
3440         .pwrsts = PWRSTS_OFF_ON,
3441         .flags = VOTABLE,
3442 };
3443
3444 static struct gdsc hlos1_vote_lpass_core_gdsc = {
3445         .gdscr = 0x7d038,
3446         .pd = {
3447                 .name = "hlos1_vote_lpass_core",
3448         },
3449         .pwrsts = PWRSTS_OFF_ON,
3450         .flags = VOTABLE,
3451 };
3452
3453 static struct gdsc usb30_gdsc = {
3454         .gdscr = 0xf004,
3455         .pd = {
3456                 .name = "usb30",
3457         },
3458         .pwrsts = PWRSTS_OFF_ON,
3459 };
3460
3461 static struct gdsc pcie0_gdsc = {
3462         .gdscr = 0x6b004,
3463         .pd = {
3464                 .name = "pcie0",
3465         },
3466         .pwrsts = PWRSTS_OFF_ON,
3467 };
3468
3469 static struct gdsc pcie1_gdsc = {
3470         .gdscr = 0x6d004,
3471         .pd = {
3472                 .name = "pcie1",
3473         },
3474         .pwrsts = PWRSTS_OFF_ON,
3475 };
3476
3477 static struct gdsc pcie2_gdsc = {
3478         .gdscr = 0x6e004,
3479         .pd = {
3480                 .name = "pcie2",
3481         },
3482         .pwrsts = PWRSTS_OFF_ON,
3483 };
3484
3485 static struct gdsc ufs_gdsc = {
3486         .gdscr = 0x75004,
3487         .pd = {
3488                 .name = "ufs",
3489         },
3490         .pwrsts = PWRSTS_OFF_ON,
3491 };
3492
3493 static struct clk_regmap *gcc_msm8996_clocks[] = {
3494         [GPLL0_EARLY] = &gpll0_early.clkr,
3495         [GPLL0] = &gpll0.clkr,
3496         [GPLL4_EARLY] = &gpll4_early.clkr,
3497         [GPLL4] = &gpll4.clkr,
3498         [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
3499         [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
3500         [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
3501         [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
3502         [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
3503         [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
3504         [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
3505         [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
3506         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
3507         [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
3508         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
3509         [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
3510         [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
3511         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3512         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3513         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3514         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3515         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3516         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3517         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3518         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3519         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
3520         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3521         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3522         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
3523         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3524         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3525         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
3526         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3527         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3528         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
3529         [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
3530         [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
3531         [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
3532         [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
3533         [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
3534         [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
3535         [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
3536         [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
3537         [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
3538         [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
3539         [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
3540         [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
3541         [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
3542         [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
3543         [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
3544         [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
3545         [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
3546         [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
3547         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
3548         [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
3549         [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3550         [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
3551         [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
3552         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
3553         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
3554         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
3555         [PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
3556         [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
3557         [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
3558         [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
3559         [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
3560         [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
3561         [GCC_PERIPH_NOC_USB20_AHB_CLK] = &gcc_periph_noc_usb20_ahb_clk.clkr,
3562         [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
3563         [GCC_MMSS_BIMC_GFX_CLK] = &gcc_mmss_bimc_gfx_clk.clkr,
3564         [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
3565         [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
3566         [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
3567         [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
3568         [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
3569         [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
3570         [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
3571         [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
3572         [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
3573         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3574         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3575         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3576         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3577         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3578         [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
3579         [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
3580         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3581         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3582         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3583         [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3584         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3585         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3586         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3587         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3588         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3589         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3590         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3591         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3592         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3593         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3594         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3595         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3596         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3597         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3598         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3599         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3600         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3601         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3602         [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
3603         [GCC_BLSP2_SLEEP_CLK] = &gcc_blsp2_sleep_clk.clkr,
3604         [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
3605         [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
3606         [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
3607         [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
3608         [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
3609         [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
3610         [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
3611         [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
3612         [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
3613         [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
3614         [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
3615         [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
3616         [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
3617         [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
3618         [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
3619         [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
3620         [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
3621         [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
3622         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3623         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3624         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3625         [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3626         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3627         [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3628         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3629         [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
3630         [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
3631         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3632         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3633         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3634         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3635         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3636         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3637         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3638         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3639         [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3640         [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3641         [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3642         [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3643         [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3644         [GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
3645         [GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
3646         [GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
3647         [GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
3648         [GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
3649         [GCC_PCIE_PHY_CFG_AHB_CLK] = &gcc_pcie_phy_cfg_ahb_clk.clkr,
3650         [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3651         [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
3652         [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
3653         [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
3654         [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
3655         [GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK] = &gcc_hlos1_vote_lpass_core_smmu_clk.clkr,
3656         [GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK] = &gcc_hlos1_vote_lpass_adsp_smmu_clk.clkr,
3657         [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
3658         [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
3659         [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
3660         [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
3661         [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
3662         [GCC_UFS_SYS_CLK_CORE_CLK] = &gcc_ufs_sys_clk_core_clk.clkr,
3663         [GCC_UFS_TX_SYMBOL_CLK_CORE_CLK] = &gcc_ufs_tx_symbol_clk_core_clk.clkr,
3664         [GCC_AGGRE0_SNOC_AXI_CLK] = &gcc_aggre0_snoc_axi_clk.clkr,
3665         [GCC_AGGRE0_CNOC_AHB_CLK] = &gcc_aggre0_cnoc_ahb_clk.clkr,
3666         [GCC_SMMU_AGGRE0_AXI_CLK] = &gcc_smmu_aggre0_axi_clk.clkr,
3667         [GCC_SMMU_AGGRE0_AHB_CLK] = &gcc_smmu_aggre0_ahb_clk.clkr,
3668         [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
3669         [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
3670         [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
3671         [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
3672         [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
3673         [GCC_HDMI_CLKREF_CLK] = &gcc_hdmi_clkref_clk.clkr,
3674         [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
3675         [GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
3676         [GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,
3677         [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
3678         [GCC_EDP_CLKREF_CLK] = &gcc_edp_clkref_clk.clkr,
3679         [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3680         [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3681         [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
3682         [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
3683         [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
3684         [GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK] = &gcc_aggre0_noc_mpu_cfg_ahb_clk.clkr,
3685         [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
3686         [GCC_MSS_GPLL0_DIV_CLK] = &gcc_mss_gpll0_div_clk.clkr,
3687 };
3688
3689 static struct gdsc *gcc_msm8996_gdscs[] = {
3690         [AGGRE0_NOC_GDSC] = &aggre0_noc_gdsc,
3691         [HLOS1_VOTE_AGGRE0_NOC_GDSC] = &hlos1_vote_aggre0_noc_gdsc,
3692         [HLOS1_VOTE_LPASS_ADSP_GDSC] = &hlos1_vote_lpass_adsp_gdsc,
3693         [HLOS1_VOTE_LPASS_CORE_GDSC] = &hlos1_vote_lpass_core_gdsc,
3694         [USB30_GDSC] = &usb30_gdsc,
3695         [PCIE0_GDSC] = &pcie0_gdsc,
3696         [PCIE1_GDSC] = &pcie1_gdsc,
3697         [PCIE2_GDSC] = &pcie2_gdsc,
3698         [UFS_GDSC] = &ufs_gdsc,
3699 };
3700
3701 static const struct qcom_reset_map gcc_msm8996_resets[] = {
3702         [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
3703         [GCC_CONFIG_NOC_BCR] = { 0x5000 },
3704         [GCC_PERIPH_NOC_BCR] = { 0x6000 },
3705         [GCC_IMEM_BCR] = { 0x8000 },
3706         [GCC_MMSS_BCR] = { 0x9000 },
3707         [GCC_PIMEM_BCR] = { 0x0a000 },
3708         [GCC_QDSS_BCR] = { 0x0c000 },
3709         [GCC_USB_30_BCR] = { 0x0f000 },
3710         [GCC_USB_20_BCR] = { 0x12000 },
3711         [GCC_QUSB2PHY_PRIM_BCR] = { 0x12038 },
3712         [GCC_QUSB2PHY_SEC_BCR] = { 0x1203c },
3713         [GCC_USB3_PHY_BCR] = { 0x50020 },
3714         [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
3715         [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3716         [GCC_SDCC1_BCR] = { 0x13000 },
3717         [GCC_SDCC2_BCR] = { 0x14000 },
3718         [GCC_SDCC3_BCR] = { 0x15000 },
3719         [GCC_SDCC4_BCR] = { 0x16000 },
3720         [GCC_BLSP1_BCR] = { 0x17000 },
3721         [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
3722         [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
3723         [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
3724         [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
3725         [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
3726         [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
3727         [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
3728         [GCC_BLSP1_UART4_BCR] = { 0x20000 },
3729         [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
3730         [GCC_BLSP1_UART5_BCR] = { 0x22000 },
3731         [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
3732         [GCC_BLSP1_UART6_BCR] = { 0x24000 },
3733         [GCC_BLSP2_BCR] = { 0x25000 },
3734         [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
3735         [GCC_BLSP2_UART1_BCR] = { 0x27000 },
3736         [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
3737         [GCC_BLSP2_UART2_BCR] = { 0x29000 },
3738         [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
3739         [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
3740         [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
3741         [GCC_BLSP2_UART4_BCR] = { 0x2d000 },
3742         [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
3743         [GCC_BLSP2_UART5_BCR] = { 0x2f000 },
3744         [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
3745         [GCC_BLSP2_UART6_BCR] = { 0x31000 },
3746         [GCC_PDM_BCR] = { 0x33000 },
3747         [GCC_PRNG_BCR] = { 0x34000 },
3748         [GCC_TSIF_BCR] = { 0x36000 },
3749         [GCC_TCSR_BCR] = { 0x37000 },
3750         [GCC_BOOT_ROM_BCR] = { 0x38000 },
3751         [GCC_MSG_RAM_BCR] = { 0x39000 },
3752         [GCC_TLMM_BCR] = { 0x3a000 },
3753         [GCC_MPM_BCR] = { 0x3b000 },
3754         [GCC_SEC_CTRL_BCR] = { 0x3d000 },
3755         [GCC_SPMI_BCR] = { 0x3f000 },
3756         [GCC_SPDM_BCR] = { 0x40000 },
3757         [GCC_CE1_BCR] = { 0x41000 },
3758         [GCC_BIMC_BCR] = { 0x44000 },
3759         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
3760         [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x49008 },
3761         [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49010 },
3762         [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49018 },
3763         [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49020 },
3764         [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
3765         [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x4a008 },
3766         [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x4a010 },
3767         [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x4a018 },
3768         [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x4a020 },
3769         [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
3770         [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
3771         [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
3772         [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
3773         [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
3774         [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
3775         [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
3776         [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
3777         [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
3778         [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
3779         [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80010 },
3780         [GCC_APB2JTAG_BCR] = { 0x4c000 },
3781         [GCC_RBCPR_CX_BCR] = { 0x4e000 },
3782         [GCC_RBCPR_MX_BCR] = { 0x4f000 },
3783         [GCC_PCIE_0_BCR] = { 0x6b000 },
3784         [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3785         [GCC_PCIE_1_BCR] = { 0x6d000 },
3786         [GCC_PCIE_1_PHY_BCR] = { 0x6d038 },
3787         [GCC_PCIE_2_BCR] = { 0x6e000 },
3788         [GCC_PCIE_2_PHY_BCR] = { 0x6e038 },
3789         [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3790         [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
3791         [GCC_PCIE_PHY_COM_NOCSR_BCR] = { 0x6f00c },
3792         [GCC_DCD_BCR] = { 0x70000 },
3793         [GCC_OBT_ODT_BCR] = { 0x73000 },
3794         [GCC_UFS_BCR] = { 0x75000 },
3795         [GCC_SSC_BCR] = { 0x63000 },
3796         [GCC_VS_BCR] = { 0x7a000 },
3797         [GCC_AGGRE0_NOC_BCR] = { 0x81000 },
3798         [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
3799         [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
3800         [GCC_DCC_BCR] = { 0x84000 },
3801         [GCC_IPA_BCR] = { 0x89000 },
3802         [GCC_QSPI_BCR] = { 0x8b000 },
3803         [GCC_SKL_BCR] = { 0x8c000 },
3804         [GCC_MSMPU_BCR] = { 0x8d000 },
3805         [GCC_MSS_Q6_BCR] = { 0x8e000 },
3806         [GCC_QREFS_VBG_CAL_BCR] = { 0x88020 },
3807         [GCC_MSS_RESTART] = { 0x8f008 },
3808 };
3809
3810 static const struct regmap_config gcc_msm8996_regmap_config = {
3811         .reg_bits       = 32,
3812         .reg_stride     = 4,
3813         .val_bits       = 32,
3814         .max_register   = 0x8f010,
3815         .fast_io        = true,
3816 };
3817
3818 static const struct qcom_cc_desc gcc_msm8996_desc = {
3819         .config = &gcc_msm8996_regmap_config,
3820         .clks = gcc_msm8996_clocks,
3821         .num_clks = ARRAY_SIZE(gcc_msm8996_clocks),
3822         .resets = gcc_msm8996_resets,
3823         .num_resets = ARRAY_SIZE(gcc_msm8996_resets),
3824         .gdscs = gcc_msm8996_gdscs,
3825         .num_gdscs = ARRAY_SIZE(gcc_msm8996_gdscs),
3826         .clk_hws = gcc_msm8996_hws,
3827         .num_clk_hws = ARRAY_SIZE(gcc_msm8996_hws),
3828 };
3829
3830 static const struct of_device_id gcc_msm8996_match_table[] = {
3831         { .compatible = "qcom,gcc-msm8996" },
3832         { }
3833 };
3834 MODULE_DEVICE_TABLE(of, gcc_msm8996_match_table);
3835
3836 static int gcc_msm8996_probe(struct platform_device *pdev)
3837 {
3838         struct regmap *regmap;
3839
3840         regmap = qcom_cc_map(pdev, &gcc_msm8996_desc);
3841         if (IS_ERR(regmap))
3842                 return PTR_ERR(regmap);
3843
3844         /*
3845          * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
3846          * turned off by hardware during certain apps low power modes.
3847          */
3848         regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
3849
3850         return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
3851 }
3852
3853 static struct platform_driver gcc_msm8996_driver = {
3854         .probe          = gcc_msm8996_probe,
3855         .driver         = {
3856                 .name   = "gcc-msm8996",
3857                 .of_match_table = gcc_msm8996_match_table,
3858         },
3859 };
3860
3861 static int __init gcc_msm8996_init(void)
3862 {
3863         return platform_driver_register(&gcc_msm8996_driver);
3864 }
3865 core_initcall(gcc_msm8996_init);
3866
3867 static void __exit gcc_msm8996_exit(void)
3868 {
3869         platform_driver_unregister(&gcc_msm8996_driver);
3870 }
3871 module_exit(gcc_msm8996_exit);
3872
3873 MODULE_DESCRIPTION("QCOM GCC MSM8996 Driver");
3874 MODULE_LICENSE("GPL v2");
3875 MODULE_ALIAS("platform:gcc-msm8996");