1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
5 #include <linux/clk-provider.h>
6 #include <linux/kernel.h>
7 #include <linux/init.h>
9 #include <linux/ctype.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/module.h>
15 #include <linux/regmap.h>
17 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
20 #include "clk-regmap.h"
21 #include "clk-alpha-pll.h"
23 #include "clk-branch.h"
33 static struct clk_alpha_pll gpll0_early = {
35 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
38 .enable_mask = BIT(0),
39 .hw.init = &(struct clk_init_data){
40 .name = "gpll0_early",
41 .parent_data = &(const struct clk_parent_data){
45 .ops = &clk_alpha_pll_ops,
50 static struct clk_alpha_pll_postdiv gpll0 = {
52 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
53 .clkr.hw.init = &(struct clk_init_data){
55 .parent_names = (const char *[]) { "gpll0_early" },
57 .ops = &clk_alpha_pll_postdiv_ops,
61 static struct clk_alpha_pll gpll4_early = {
63 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
66 .enable_mask = BIT(4),
67 .hw.init = &(struct clk_init_data){
68 .name = "gpll4_early",
69 .parent_data = &(const struct clk_parent_data){
73 .ops = &clk_alpha_pll_ops,
78 static struct clk_alpha_pll_postdiv gpll4 = {
80 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
81 .clkr.hw.init = &(struct clk_init_data){
83 .parent_names = (const char *[]) { "gpll4_early" },
85 .ops = &clk_alpha_pll_postdiv_ops,
89 static const struct parent_map gcc_xo_gpll0_map[] = {
94 static const struct clk_parent_data gcc_xo_gpll0[] = {
96 { .hw = &gpll0.clkr.hw },
99 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
105 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
107 { .hw = &gpll0.clkr.hw },
108 { .hw = &gpll4.clkr.hw },
111 static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
112 F(50000000, P_GPLL0, 12, 0, 0),
113 F(100000000, P_GPLL0, 6, 0, 0),
114 F(150000000, P_GPLL0, 4, 0, 0),
115 F(171430000, P_GPLL0, 3.5, 0, 0),
116 F(200000000, P_GPLL0, 3, 0, 0),
117 F(240000000, P_GPLL0, 2.5, 0, 0),
121 static struct clk_rcg2 ufs_axi_clk_src = {
125 .parent_map = gcc_xo_gpll0_map,
126 .freq_tbl = ftbl_ufs_axi_clk_src,
127 .clkr.hw.init = &(struct clk_init_data){
128 .name = "ufs_axi_clk_src",
129 .parent_data = gcc_xo_gpll0,
130 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
131 .ops = &clk_rcg2_ops,
135 static struct freq_tbl ftbl_usb30_master_clk_src[] = {
136 F(19200000, P_XO, 1, 0, 0),
137 F(125000000, P_GPLL0, 1, 5, 24),
141 static struct clk_rcg2 usb30_master_clk_src = {
145 .parent_map = gcc_xo_gpll0_map,
146 .freq_tbl = ftbl_usb30_master_clk_src,
147 .clkr.hw.init = &(struct clk_init_data){
148 .name = "usb30_master_clk_src",
149 .parent_data = gcc_xo_gpll0,
150 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
151 .ops = &clk_rcg2_ops,
155 static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
156 F(19200000, P_XO, 1, 0, 0),
157 F(50000000, P_GPLL0, 12, 0, 0),
161 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
164 .parent_map = gcc_xo_gpll0_map,
165 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
166 .clkr.hw.init = &(struct clk_init_data){
167 .name = "blsp1_qup1_i2c_apps_clk_src",
168 .parent_data = gcc_xo_gpll0,
169 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
170 .ops = &clk_rcg2_ops,
174 static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
175 F(960000, P_XO, 10, 1, 2),
176 F(4800000, P_XO, 4, 0, 0),
177 F(9600000, P_XO, 2, 0, 0),
178 F(15000000, P_GPLL0, 10, 1, 4),
179 F(19200000, P_XO, 1, 0, 0),
180 F(24000000, P_GPLL0, 12.5, 1, 2),
181 F(25000000, P_GPLL0, 12, 1, 2),
182 F(48000000, P_GPLL0, 12.5, 0, 0),
183 F(50000000, P_GPLL0, 12, 0, 0),
187 static struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src_8992[] = {
188 F(960000, P_XO, 10, 1, 2),
189 F(4800000, P_XO, 4, 0, 0),
190 F(9600000, P_XO, 2, 0, 0),
191 F(15000000, P_GPLL0, 10, 1, 4),
192 F(19200000, P_XO, 1, 0, 0),
193 F(25000000, P_GPLL0, 12, 1, 2),
194 F(50000000, P_GPLL0, 12, 0, 0),
198 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
202 .parent_map = gcc_xo_gpll0_map,
203 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
204 .clkr.hw.init = &(struct clk_init_data){
205 .name = "blsp1_qup1_spi_apps_clk_src",
206 .parent_data = gcc_xo_gpll0,
207 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
208 .ops = &clk_rcg2_ops,
212 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
215 .parent_map = gcc_xo_gpll0_map,
216 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
217 .clkr.hw.init = &(struct clk_init_data){
218 .name = "blsp1_qup2_i2c_apps_clk_src",
219 .parent_data = gcc_xo_gpll0,
220 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
221 .ops = &clk_rcg2_ops,
225 static struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
226 F(960000, P_XO, 10, 1, 2),
227 F(4800000, P_XO, 4, 0, 0),
228 F(9600000, P_XO, 2, 0, 0),
229 F(15000000, P_GPLL0, 10, 1, 4),
230 F(19200000, P_XO, 1, 0, 0),
231 F(24000000, P_GPLL0, 12.5, 1, 2),
232 F(25000000, P_GPLL0, 12, 1, 2),
233 F(42860000, P_GPLL0, 14, 0, 0),
234 F(46150000, P_GPLL0, 13, 0, 0),
238 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
242 .parent_map = gcc_xo_gpll0_map,
243 .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
244 .clkr.hw.init = &(struct clk_init_data){
245 .name = "blsp1_qup2_spi_apps_clk_src",
246 .parent_data = gcc_xo_gpll0,
247 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
248 .ops = &clk_rcg2_ops,
252 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
255 .parent_map = gcc_xo_gpll0_map,
256 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
257 .clkr.hw.init = &(struct clk_init_data){
258 .name = "blsp1_qup3_i2c_apps_clk_src",
259 .parent_data = gcc_xo_gpll0,
260 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
261 .ops = &clk_rcg2_ops,
265 static struct freq_tbl ftbl_blsp1_qup3_4_spi_apps_clk_src[] = {
266 F(960000, P_XO, 10, 1, 2),
267 F(4800000, P_XO, 4, 0, 0),
268 F(9600000, P_XO, 2, 0, 0),
269 F(15000000, P_GPLL0, 10, 1, 4),
270 F(19200000, P_XO, 1, 0, 0),
271 F(24000000, P_GPLL0, 12.5, 1, 2),
272 F(25000000, P_GPLL0, 12, 1, 2),
273 F(42860000, P_GPLL0, 14, 0, 0),
274 F(44440000, P_GPLL0, 13.5, 0, 0),
278 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
282 .parent_map = gcc_xo_gpll0_map,
283 .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src,
284 .clkr.hw.init = &(struct clk_init_data){
285 .name = "blsp1_qup3_spi_apps_clk_src",
286 .parent_data = gcc_xo_gpll0,
287 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
288 .ops = &clk_rcg2_ops,
292 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
295 .parent_map = gcc_xo_gpll0_map,
296 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
297 .clkr.hw.init = &(struct clk_init_data){
298 .name = "blsp1_qup4_i2c_apps_clk_src",
299 .parent_data = gcc_xo_gpll0,
300 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
301 .ops = &clk_rcg2_ops,
305 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
309 .parent_map = gcc_xo_gpll0_map,
310 .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src,
311 .clkr.hw.init = &(struct clk_init_data){
312 .name = "blsp1_qup4_spi_apps_clk_src",
313 .parent_data = gcc_xo_gpll0,
314 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
315 .ops = &clk_rcg2_ops,
319 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
322 .parent_map = gcc_xo_gpll0_map,
323 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
324 .clkr.hw.init = &(struct clk_init_data){
325 .name = "blsp1_qup5_i2c_apps_clk_src",
326 .parent_data = gcc_xo_gpll0,
327 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
328 .ops = &clk_rcg2_ops,
332 static struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = {
333 F(960000, P_XO, 10, 1, 2),
334 F(4800000, P_XO, 4, 0, 0),
335 F(9600000, P_XO, 2, 0, 0),
336 F(15000000, P_GPLL0, 10, 1, 4),
337 F(19200000, P_XO, 1, 0, 0),
338 F(24000000, P_GPLL0, 12.5, 1, 2),
339 F(25000000, P_GPLL0, 12, 1, 2),
340 F(40000000, P_GPLL0, 15, 0, 0),
341 F(42860000, P_GPLL0, 14, 0, 0),
345 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
349 .parent_map = gcc_xo_gpll0_map,
350 .freq_tbl = ftbl_blsp1_qup5_spi_apps_clk_src,
351 .clkr.hw.init = &(struct clk_init_data){
352 .name = "blsp1_qup5_spi_apps_clk_src",
353 .parent_data = gcc_xo_gpll0,
354 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
355 .ops = &clk_rcg2_ops,
359 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
362 .parent_map = gcc_xo_gpll0_map,
363 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
364 .clkr.hw.init = &(struct clk_init_data){
365 .name = "blsp1_qup6_i2c_apps_clk_src",
366 .parent_data = gcc_xo_gpll0,
367 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
368 .ops = &clk_rcg2_ops,
372 static struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = {
373 F(960000, P_XO, 10, 1, 2),
374 F(4800000, P_XO, 4, 0, 0),
375 F(9600000, P_XO, 2, 0, 0),
376 F(15000000, P_GPLL0, 10, 1, 4),
377 F(19200000, P_XO, 1, 0, 0),
378 F(24000000, P_GPLL0, 12.5, 1, 2),
379 F(27906976, P_GPLL0, 1, 2, 43),
380 F(41380000, P_GPLL0, 15, 0, 0),
381 F(42860000, P_GPLL0, 14, 0, 0),
385 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
389 .parent_map = gcc_xo_gpll0_map,
390 .freq_tbl = ftbl_blsp1_qup6_spi_apps_clk_src,
391 .clkr.hw.init = &(struct clk_init_data){
392 .name = "blsp1_qup6_spi_apps_clk_src",
393 .parent_data = gcc_xo_gpll0,
394 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
395 .ops = &clk_rcg2_ops,
399 static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
400 F(3686400, P_GPLL0, 1, 96, 15625),
401 F(7372800, P_GPLL0, 1, 192, 15625),
402 F(14745600, P_GPLL0, 1, 384, 15625),
403 F(16000000, P_GPLL0, 5, 2, 15),
404 F(19200000, P_XO, 1, 0, 0),
405 F(24000000, P_GPLL0, 5, 1, 5),
406 F(32000000, P_GPLL0, 1, 4, 75),
407 F(40000000, P_GPLL0, 15, 0, 0),
408 F(46400000, P_GPLL0, 1, 29, 375),
409 F(48000000, P_GPLL0, 12.5, 0, 0),
410 F(51200000, P_GPLL0, 1, 32, 375),
411 F(56000000, P_GPLL0, 1, 7, 75),
412 F(58982400, P_GPLL0, 1, 1536, 15625),
413 F(60000000, P_GPLL0, 10, 0, 0),
414 F(63160000, P_GPLL0, 9.5, 0, 0),
418 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
422 .parent_map = gcc_xo_gpll0_map,
423 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
424 .clkr.hw.init = &(struct clk_init_data){
425 .name = "blsp1_uart1_apps_clk_src",
426 .parent_data = gcc_xo_gpll0,
427 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
428 .ops = &clk_rcg2_ops,
432 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
436 .parent_map = gcc_xo_gpll0_map,
437 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
438 .clkr.hw.init = &(struct clk_init_data){
439 .name = "blsp1_uart2_apps_clk_src",
440 .parent_data = gcc_xo_gpll0,
441 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
442 .ops = &clk_rcg2_ops,
446 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
450 .parent_map = gcc_xo_gpll0_map,
451 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
452 .clkr.hw.init = &(struct clk_init_data){
453 .name = "blsp1_uart3_apps_clk_src",
454 .parent_data = gcc_xo_gpll0,
455 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
456 .ops = &clk_rcg2_ops,
460 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
464 .parent_map = gcc_xo_gpll0_map,
465 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
466 .clkr.hw.init = &(struct clk_init_data){
467 .name = "blsp1_uart4_apps_clk_src",
468 .parent_data = gcc_xo_gpll0,
469 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
470 .ops = &clk_rcg2_ops,
474 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
478 .parent_map = gcc_xo_gpll0_map,
479 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
480 .clkr.hw.init = &(struct clk_init_data){
481 .name = "blsp1_uart5_apps_clk_src",
482 .parent_data = gcc_xo_gpll0,
483 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
484 .ops = &clk_rcg2_ops,
488 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
492 .parent_map = gcc_xo_gpll0_map,
493 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
494 .clkr.hw.init = &(struct clk_init_data){
495 .name = "blsp1_uart6_apps_clk_src",
496 .parent_data = gcc_xo_gpll0,
497 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
498 .ops = &clk_rcg2_ops,
502 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
505 .parent_map = gcc_xo_gpll0_map,
506 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
507 .clkr.hw.init = &(struct clk_init_data){
508 .name = "blsp2_qup1_i2c_apps_clk_src",
509 .parent_data = gcc_xo_gpll0,
510 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
511 .ops = &clk_rcg2_ops,
515 static struct freq_tbl ftbl_blsp2_qup1_2_spi_apps_clk_src[] = {
516 F(960000, P_XO, 10, 1, 2),
517 F(4800000, P_XO, 4, 0, 0),
518 F(9600000, P_XO, 2, 0, 0),
519 F(15000000, P_GPLL0, 10, 1, 4),
520 F(19200000, P_XO, 1, 0, 0),
521 F(24000000, P_GPLL0, 12.5, 1, 2),
522 F(25000000, P_GPLL0, 12, 1, 2),
523 F(42860000, P_GPLL0, 14, 0, 0),
524 F(44440000, P_GPLL0, 13.5, 0, 0),
528 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
532 .parent_map = gcc_xo_gpll0_map,
533 .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src,
534 .clkr.hw.init = &(struct clk_init_data){
535 .name = "blsp2_qup1_spi_apps_clk_src",
536 .parent_data = gcc_xo_gpll0,
537 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
538 .ops = &clk_rcg2_ops,
542 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
545 .parent_map = gcc_xo_gpll0_map,
546 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
547 .clkr.hw.init = &(struct clk_init_data){
548 .name = "blsp2_qup2_i2c_apps_clk_src",
549 .parent_data = gcc_xo_gpll0,
550 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
551 .ops = &clk_rcg2_ops,
555 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
559 .parent_map = gcc_xo_gpll0_map,
560 .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src,
561 .clkr.hw.init = &(struct clk_init_data){
562 .name = "blsp2_qup2_spi_apps_clk_src",
563 .parent_data = gcc_xo_gpll0,
564 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
565 .ops = &clk_rcg2_ops,
569 static struct freq_tbl ftbl_blsp2_qup3_4_spi_apps_clk_src[] = {
570 F(960000, P_XO, 10, 1, 2),
571 F(4800000, P_XO, 4, 0, 0),
572 F(9600000, P_XO, 2, 0, 0),
573 F(15000000, P_GPLL0, 10, 1, 4),
574 F(19200000, P_XO, 1, 0, 0),
575 F(24000000, P_GPLL0, 12.5, 1, 2),
576 F(25000000, P_GPLL0, 12, 1, 2),
577 F(42860000, P_GPLL0, 14, 0, 0),
578 F(48000000, P_GPLL0, 12.5, 0, 0),
582 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
585 .parent_map = gcc_xo_gpll0_map,
586 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
587 .clkr.hw.init = &(struct clk_init_data){
588 .name = "blsp2_qup3_i2c_apps_clk_src",
589 .parent_data = gcc_xo_gpll0,
590 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
591 .ops = &clk_rcg2_ops,
595 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
599 .parent_map = gcc_xo_gpll0_map,
600 .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src,
601 .clkr.hw.init = &(struct clk_init_data){
602 .name = "blsp2_qup3_spi_apps_clk_src",
603 .parent_data = gcc_xo_gpll0,
604 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
605 .ops = &clk_rcg2_ops,
609 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
612 .parent_map = gcc_xo_gpll0_map,
613 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
614 .clkr.hw.init = &(struct clk_init_data){
615 .name = "blsp2_qup4_i2c_apps_clk_src",
616 .parent_data = gcc_xo_gpll0,
617 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
618 .ops = &clk_rcg2_ops,
622 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
626 .parent_map = gcc_xo_gpll0_map,
627 .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src,
628 .clkr.hw.init = &(struct clk_init_data){
629 .name = "blsp2_qup4_spi_apps_clk_src",
630 .parent_data = gcc_xo_gpll0,
631 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
632 .ops = &clk_rcg2_ops,
636 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
639 .parent_map = gcc_xo_gpll0_map,
640 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
641 .clkr.hw.init = &(struct clk_init_data){
642 .name = "blsp2_qup5_i2c_apps_clk_src",
643 .parent_data = gcc_xo_gpll0,
644 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
645 .ops = &clk_rcg2_ops,
649 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
653 .parent_map = gcc_xo_gpll0_map,
654 /* BLSP1 QUP1 and BLSP2 QUP5 use the same freqs */
655 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
656 .clkr.hw.init = &(struct clk_init_data){
657 .name = "blsp2_qup5_spi_apps_clk_src",
658 .parent_data = gcc_xo_gpll0,
659 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
660 .ops = &clk_rcg2_ops,
664 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
667 .parent_map = gcc_xo_gpll0_map,
668 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
669 .clkr.hw.init = &(struct clk_init_data){
670 .name = "blsp2_qup6_i2c_apps_clk_src",
671 .parent_data = gcc_xo_gpll0,
672 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
673 .ops = &clk_rcg2_ops,
677 static struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = {
678 F(960000, P_XO, 10, 1, 2),
679 F(4800000, P_XO, 4, 0, 0),
680 F(9600000, P_XO, 2, 0, 0),
681 F(15000000, P_GPLL0, 10, 1, 4),
682 F(19200000, P_XO, 1, 0, 0),
683 F(24000000, P_GPLL0, 12.5, 1, 2),
684 F(25000000, P_GPLL0, 12, 1, 2),
685 F(44440000, P_GPLL0, 13.5, 0, 0),
686 F(48000000, P_GPLL0, 12.5, 0, 0),
690 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
694 .parent_map = gcc_xo_gpll0_map,
695 .freq_tbl = ftbl_blsp2_qup6_spi_apps_clk_src,
696 .clkr.hw.init = &(struct clk_init_data){
697 .name = "blsp2_qup6_spi_apps_clk_src",
698 .parent_data = gcc_xo_gpll0,
699 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
700 .ops = &clk_rcg2_ops,
704 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
708 .parent_map = gcc_xo_gpll0_map,
709 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
710 .clkr.hw.init = &(struct clk_init_data){
711 .name = "blsp2_uart1_apps_clk_src",
712 .parent_data = gcc_xo_gpll0,
713 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
714 .ops = &clk_rcg2_ops,
718 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
722 .parent_map = gcc_xo_gpll0_map,
723 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
724 .clkr.hw.init = &(struct clk_init_data){
725 .name = "blsp2_uart2_apps_clk_src",
726 .parent_data = gcc_xo_gpll0,
727 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
728 .ops = &clk_rcg2_ops,
732 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
736 .parent_map = gcc_xo_gpll0_map,
737 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
738 .clkr.hw.init = &(struct clk_init_data){
739 .name = "blsp2_uart3_apps_clk_src",
740 .parent_data = gcc_xo_gpll0,
741 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
742 .ops = &clk_rcg2_ops,
746 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
750 .parent_map = gcc_xo_gpll0_map,
751 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
752 .clkr.hw.init = &(struct clk_init_data){
753 .name = "blsp2_uart4_apps_clk_src",
754 .parent_data = gcc_xo_gpll0,
755 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
756 .ops = &clk_rcg2_ops,
760 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
764 .parent_map = gcc_xo_gpll0_map,
765 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
766 .clkr.hw.init = &(struct clk_init_data){
767 .name = "blsp2_uart5_apps_clk_src",
768 .parent_data = gcc_xo_gpll0,
769 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
770 .ops = &clk_rcg2_ops,
774 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
778 .parent_map = gcc_xo_gpll0_map,
779 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
780 .clkr.hw.init = &(struct clk_init_data){
781 .name = "blsp2_uart6_apps_clk_src",
782 .parent_data = gcc_xo_gpll0,
783 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
784 .ops = &clk_rcg2_ops,
788 static struct freq_tbl ftbl_gp1_clk_src[] = {
789 F(19200000, P_XO, 1, 0, 0),
790 F(100000000, P_GPLL0, 6, 0, 0),
791 F(200000000, P_GPLL0, 3, 0, 0),
795 static struct clk_rcg2 gp1_clk_src = {
799 .parent_map = gcc_xo_gpll0_map,
800 .freq_tbl = ftbl_gp1_clk_src,
801 .clkr.hw.init = &(struct clk_init_data){
802 .name = "gp1_clk_src",
803 .parent_data = gcc_xo_gpll0,
804 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
805 .ops = &clk_rcg2_ops,
809 static struct freq_tbl ftbl_gp2_clk_src[] = {
810 F(19200000, P_XO, 1, 0, 0),
811 F(100000000, P_GPLL0, 6, 0, 0),
812 F(200000000, P_GPLL0, 3, 0, 0),
816 static struct clk_rcg2 gp2_clk_src = {
820 .parent_map = gcc_xo_gpll0_map,
821 .freq_tbl = ftbl_gp2_clk_src,
822 .clkr.hw.init = &(struct clk_init_data){
823 .name = "gp2_clk_src",
824 .parent_data = gcc_xo_gpll0,
825 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
826 .ops = &clk_rcg2_ops,
830 static struct freq_tbl ftbl_gp3_clk_src[] = {
831 F(19200000, P_XO, 1, 0, 0),
832 F(100000000, P_GPLL0, 6, 0, 0),
833 F(200000000, P_GPLL0, 3, 0, 0),
837 static struct clk_rcg2 gp3_clk_src = {
841 .parent_map = gcc_xo_gpll0_map,
842 .freq_tbl = ftbl_gp3_clk_src,
843 .clkr.hw.init = &(struct clk_init_data){
844 .name = "gp3_clk_src",
845 .parent_data = gcc_xo_gpll0,
846 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
847 .ops = &clk_rcg2_ops,
851 static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
852 F(1011000, P_XO, 1, 1, 19),
856 static struct clk_rcg2 pcie_0_aux_clk_src = {
860 .freq_tbl = ftbl_pcie_0_aux_clk_src,
861 .clkr.hw.init = &(struct clk_init_data){
862 .name = "pcie_0_aux_clk_src",
863 .parent_data = &(const struct clk_parent_data){
867 .ops = &clk_rcg2_ops,
871 static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
872 F(125000000, P_XO, 1, 0, 0),
876 static struct clk_rcg2 pcie_0_pipe_clk_src = {
879 .freq_tbl = ftbl_pcie_pipe_clk_src,
880 .clkr.hw.init = &(struct clk_init_data){
881 .name = "pcie_0_pipe_clk_src",
882 .parent_data = &(const struct clk_parent_data){
886 .ops = &clk_rcg2_ops,
890 static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
891 F(1011000, P_XO, 1, 1, 19),
895 static struct clk_rcg2 pcie_1_aux_clk_src = {
899 .freq_tbl = ftbl_pcie_1_aux_clk_src,
900 .clkr.hw.init = &(struct clk_init_data){
901 .name = "pcie_1_aux_clk_src",
902 .parent_data = &(const struct clk_parent_data){
906 .ops = &clk_rcg2_ops,
910 static struct clk_rcg2 pcie_1_pipe_clk_src = {
913 .freq_tbl = ftbl_pcie_pipe_clk_src,
914 .clkr.hw.init = &(struct clk_init_data){
915 .name = "pcie_1_pipe_clk_src",
916 .parent_data = &(const struct clk_parent_data){
920 .ops = &clk_rcg2_ops,
924 static struct freq_tbl ftbl_pdm2_clk_src[] = {
925 F(60000000, P_GPLL0, 10, 0, 0),
929 static struct clk_rcg2 pdm2_clk_src = {
932 .parent_map = gcc_xo_gpll0_map,
933 .freq_tbl = ftbl_pdm2_clk_src,
934 .clkr.hw.init = &(struct clk_init_data){
935 .name = "pdm2_clk_src",
936 .parent_data = gcc_xo_gpll0,
937 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
938 .ops = &clk_rcg2_ops,
942 static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
943 F(144000, P_XO, 16, 3, 25),
944 F(400000, P_XO, 12, 1, 4),
945 F(20000000, P_GPLL0, 15, 1, 2),
946 F(25000000, P_GPLL0, 12, 1, 2),
947 F(50000000, P_GPLL0, 12, 0, 0),
948 F(100000000, P_GPLL0, 6, 0, 0),
949 F(192000000, P_GPLL4, 2, 0, 0),
950 F(384000000, P_GPLL4, 1, 0, 0),
954 static struct freq_tbl ftbl_sdcc1_apps_clk_src_8992[] = {
955 F(144000, P_XO, 16, 3, 25),
956 F(400000, P_XO, 12, 1, 4),
957 F(20000000, P_GPLL0, 15, 1, 2),
958 F(25000000, P_GPLL0, 12, 1, 2),
959 F(50000000, P_GPLL0, 12, 0, 0),
960 F(100000000, P_GPLL0, 6, 0, 0),
961 F(172000000, P_GPLL4, 2, 0, 0),
962 F(344000000, P_GPLL4, 1, 0, 0),
966 static struct clk_rcg2 sdcc1_apps_clk_src = {
970 .parent_map = gcc_xo_gpll0_gpll4_map,
971 .freq_tbl = ftbl_sdcc1_apps_clk_src,
972 .clkr.hw.init = &(struct clk_init_data){
973 .name = "sdcc1_apps_clk_src",
974 .parent_data = gcc_xo_gpll0_gpll4,
975 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
976 .ops = &clk_rcg2_floor_ops,
980 static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
981 F(144000, P_XO, 16, 3, 25),
982 F(400000, P_XO, 12, 1, 4),
983 F(20000000, P_GPLL0, 15, 1, 2),
984 F(25000000, P_GPLL0, 12, 1, 2),
985 F(50000000, P_GPLL0, 12, 0, 0),
986 F(100000000, P_GPLL0, 6, 0, 0),
987 F(200000000, P_GPLL0, 3, 0, 0),
991 static struct clk_rcg2 sdcc2_apps_clk_src = {
995 .parent_map = gcc_xo_gpll0_map,
996 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
997 .clkr.hw.init = &(struct clk_init_data){
998 .name = "sdcc2_apps_clk_src",
999 .parent_data = gcc_xo_gpll0,
1000 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1001 .ops = &clk_rcg2_floor_ops,
1005 static struct clk_rcg2 sdcc3_apps_clk_src = {
1009 .parent_map = gcc_xo_gpll0_map,
1010 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
1011 .clkr.hw.init = &(struct clk_init_data){
1012 .name = "sdcc3_apps_clk_src",
1013 .parent_data = gcc_xo_gpll0,
1014 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1015 .ops = &clk_rcg2_floor_ops,
1019 static struct clk_rcg2 sdcc4_apps_clk_src = {
1023 .parent_map = gcc_xo_gpll0_map,
1024 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
1025 .clkr.hw.init = &(struct clk_init_data){
1026 .name = "sdcc4_apps_clk_src",
1027 .parent_data = gcc_xo_gpll0,
1028 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1029 .ops = &clk_rcg2_floor_ops,
1033 static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1034 F(105500, P_XO, 1, 1, 182),
1038 static struct clk_rcg2 tsif_ref_clk_src = {
1042 .freq_tbl = ftbl_tsif_ref_clk_src,
1043 .clkr.hw.init = &(struct clk_init_data){
1044 .name = "tsif_ref_clk_src",
1045 .parent_data = &(const struct clk_parent_data){
1049 .ops = &clk_rcg2_ops,
1053 static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
1054 F(19200000, P_XO, 1, 0, 0),
1055 F(60000000, P_GPLL0, 10, 0, 0),
1059 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1062 .parent_map = gcc_xo_gpll0_map,
1063 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1064 .clkr.hw.init = &(struct clk_init_data){
1065 .name = "usb30_mock_utmi_clk_src",
1066 .parent_data = gcc_xo_gpll0,
1067 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1068 .ops = &clk_rcg2_ops,
1072 static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
1073 F(1200000, P_XO, 16, 0, 0),
1077 static struct clk_rcg2 usb3_phy_aux_clk_src = {
1080 .freq_tbl = ftbl_usb3_phy_aux_clk_src,
1081 .clkr.hw.init = &(struct clk_init_data){
1082 .name = "usb3_phy_aux_clk_src",
1083 .parent_data = &(const struct clk_parent_data){
1087 .ops = &clk_rcg2_ops,
1091 static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1092 F(75000000, P_GPLL0, 8, 0, 0),
1096 static struct clk_rcg2 usb_hs_system_clk_src = {
1099 .parent_map = gcc_xo_gpll0_map,
1100 .freq_tbl = ftbl_usb_hs_system_clk_src,
1101 .clkr.hw.init = &(struct clk_init_data){
1102 .name = "usb_hs_system_clk_src",
1103 .parent_data = gcc_xo_gpll0,
1104 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1105 .ops = &clk_rcg2_ops,
1109 static struct clk_branch gcc_blsp1_ahb_clk = {
1111 .halt_check = BRANCH_HALT_VOTED,
1113 .enable_reg = 0x1484,
1114 .enable_mask = BIT(17),
1115 .hw.init = &(struct clk_init_data){
1116 .name = "gcc_blsp1_ahb_clk",
1117 .ops = &clk_branch2_ops,
1122 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1125 .enable_reg = 0x0648,
1126 .enable_mask = BIT(0),
1127 .hw.init = &(struct clk_init_data){
1128 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1129 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
1131 .flags = CLK_SET_RATE_PARENT,
1132 .ops = &clk_branch2_ops,
1137 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1140 .enable_reg = 0x0644,
1141 .enable_mask = BIT(0),
1142 .hw.init = &(struct clk_init_data){
1143 .name = "gcc_blsp1_qup1_spi_apps_clk",
1144 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw },
1146 .flags = CLK_SET_RATE_PARENT,
1147 .ops = &clk_branch2_ops,
1152 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1155 .enable_reg = 0x06c8,
1156 .enable_mask = BIT(0),
1157 .hw.init = &(struct clk_init_data){
1158 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1159 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
1161 .flags = CLK_SET_RATE_PARENT,
1162 .ops = &clk_branch2_ops,
1167 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1170 .enable_reg = 0x06c4,
1171 .enable_mask = BIT(0),
1172 .hw.init = &(struct clk_init_data){
1173 .name = "gcc_blsp1_qup2_spi_apps_clk",
1174 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw },
1176 .flags = CLK_SET_RATE_PARENT,
1177 .ops = &clk_branch2_ops,
1182 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1185 .enable_reg = 0x0748,
1186 .enable_mask = BIT(0),
1187 .hw.init = &(struct clk_init_data){
1188 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1189 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
1191 .flags = CLK_SET_RATE_PARENT,
1192 .ops = &clk_branch2_ops,
1197 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1200 .enable_reg = 0x0744,
1201 .enable_mask = BIT(0),
1202 .hw.init = &(struct clk_init_data){
1203 .name = "gcc_blsp1_qup3_spi_apps_clk",
1204 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw },
1206 .flags = CLK_SET_RATE_PARENT,
1207 .ops = &clk_branch2_ops,
1212 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1215 .enable_reg = 0x07c8,
1216 .enable_mask = BIT(0),
1217 .hw.init = &(struct clk_init_data){
1218 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1219 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
1221 .flags = CLK_SET_RATE_PARENT,
1222 .ops = &clk_branch2_ops,
1227 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1230 .enable_reg = 0x07c4,
1231 .enable_mask = BIT(0),
1232 .hw.init = &(struct clk_init_data){
1233 .name = "gcc_blsp1_qup4_spi_apps_clk",
1234 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw },
1236 .flags = CLK_SET_RATE_PARENT,
1237 .ops = &clk_branch2_ops,
1242 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1245 .enable_reg = 0x0848,
1246 .enable_mask = BIT(0),
1247 .hw.init = &(struct clk_init_data){
1248 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1249 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
1251 .flags = CLK_SET_RATE_PARENT,
1252 .ops = &clk_branch2_ops,
1257 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1260 .enable_reg = 0x0844,
1261 .enable_mask = BIT(0),
1262 .hw.init = &(struct clk_init_data){
1263 .name = "gcc_blsp1_qup5_spi_apps_clk",
1264 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw },
1266 .flags = CLK_SET_RATE_PARENT,
1267 .ops = &clk_branch2_ops,
1272 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1275 .enable_reg = 0x08c8,
1276 .enable_mask = BIT(0),
1277 .hw.init = &(struct clk_init_data){
1278 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1279 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
1281 .flags = CLK_SET_RATE_PARENT,
1282 .ops = &clk_branch2_ops,
1287 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1290 .enable_reg = 0x08c4,
1291 .enable_mask = BIT(0),
1292 .hw.init = &(struct clk_init_data){
1293 .name = "gcc_blsp1_qup6_spi_apps_clk",
1294 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw },
1296 .flags = CLK_SET_RATE_PARENT,
1297 .ops = &clk_branch2_ops,
1302 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1305 .enable_reg = 0x0684,
1306 .enable_mask = BIT(0),
1307 .hw.init = &(struct clk_init_data){
1308 .name = "gcc_blsp1_uart1_apps_clk",
1309 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw },
1311 .flags = CLK_SET_RATE_PARENT,
1312 .ops = &clk_branch2_ops,
1317 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1320 .enable_reg = 0x0704,
1321 .enable_mask = BIT(0),
1322 .hw.init = &(struct clk_init_data){
1323 .name = "gcc_blsp1_uart2_apps_clk",
1324 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw },
1326 .flags = CLK_SET_RATE_PARENT,
1327 .ops = &clk_branch2_ops,
1332 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1335 .enable_reg = 0x0784,
1336 .enable_mask = BIT(0),
1337 .hw.init = &(struct clk_init_data){
1338 .name = "gcc_blsp1_uart3_apps_clk",
1339 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw },
1341 .flags = CLK_SET_RATE_PARENT,
1342 .ops = &clk_branch2_ops,
1347 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1350 .enable_reg = 0x0804,
1351 .enable_mask = BIT(0),
1352 .hw.init = &(struct clk_init_data){
1353 .name = "gcc_blsp1_uart4_apps_clk",
1354 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw },
1356 .flags = CLK_SET_RATE_PARENT,
1357 .ops = &clk_branch2_ops,
1362 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1365 .enable_reg = 0x0884,
1366 .enable_mask = BIT(0),
1367 .hw.init = &(struct clk_init_data){
1368 .name = "gcc_blsp1_uart5_apps_clk",
1369 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw },
1371 .flags = CLK_SET_RATE_PARENT,
1372 .ops = &clk_branch2_ops,
1377 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1380 .enable_reg = 0x0904,
1381 .enable_mask = BIT(0),
1382 .hw.init = &(struct clk_init_data){
1383 .name = "gcc_blsp1_uart6_apps_clk",
1384 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw },
1386 .flags = CLK_SET_RATE_PARENT,
1387 .ops = &clk_branch2_ops,
1392 static struct clk_branch gcc_blsp2_ahb_clk = {
1394 .halt_check = BRANCH_HALT_VOTED,
1396 .enable_reg = 0x1484,
1397 .enable_mask = BIT(15),
1398 .hw.init = &(struct clk_init_data){
1399 .name = "gcc_blsp2_ahb_clk",
1400 .ops = &clk_branch2_ops,
1405 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1408 .enable_reg = 0x0988,
1409 .enable_mask = BIT(0),
1410 .hw.init = &(struct clk_init_data){
1411 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1412 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_i2c_apps_clk_src.clkr.hw },
1414 .flags = CLK_SET_RATE_PARENT,
1415 .ops = &clk_branch2_ops,
1420 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1423 .enable_reg = 0x0984,
1424 .enable_mask = BIT(0),
1425 .hw.init = &(struct clk_init_data){
1426 .name = "gcc_blsp2_qup1_spi_apps_clk",
1427 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_spi_apps_clk_src.clkr.hw },
1429 .flags = CLK_SET_RATE_PARENT,
1430 .ops = &clk_branch2_ops,
1435 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1438 .enable_reg = 0x0a08,
1439 .enable_mask = BIT(0),
1440 .hw.init = &(struct clk_init_data){
1441 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1442 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_i2c_apps_clk_src.clkr.hw },
1444 .flags = CLK_SET_RATE_PARENT,
1445 .ops = &clk_branch2_ops,
1450 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1453 .enable_reg = 0x0a04,
1454 .enable_mask = BIT(0),
1455 .hw.init = &(struct clk_init_data){
1456 .name = "gcc_blsp2_qup2_spi_apps_clk",
1457 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_spi_apps_clk_src.clkr.hw },
1459 .flags = CLK_SET_RATE_PARENT,
1460 .ops = &clk_branch2_ops,
1465 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1468 .enable_reg = 0x0a88,
1469 .enable_mask = BIT(0),
1470 .hw.init = &(struct clk_init_data){
1471 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1472 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_i2c_apps_clk_src.clkr.hw },
1474 .flags = CLK_SET_RATE_PARENT,
1475 .ops = &clk_branch2_ops,
1480 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1483 .enable_reg = 0x0a84,
1484 .enable_mask = BIT(0),
1485 .hw.init = &(struct clk_init_data){
1486 .name = "gcc_blsp2_qup3_spi_apps_clk",
1487 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_spi_apps_clk_src.clkr.hw },
1489 .flags = CLK_SET_RATE_PARENT,
1490 .ops = &clk_branch2_ops,
1495 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1498 .enable_reg = 0x0b08,
1499 .enable_mask = BIT(0),
1500 .hw.init = &(struct clk_init_data){
1501 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1502 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_i2c_apps_clk_src.clkr.hw },
1504 .flags = CLK_SET_RATE_PARENT,
1505 .ops = &clk_branch2_ops,
1510 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1513 .enable_reg = 0x0b04,
1514 .enable_mask = BIT(0),
1515 .hw.init = &(struct clk_init_data){
1516 .name = "gcc_blsp2_qup4_spi_apps_clk",
1517 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_spi_apps_clk_src.clkr.hw },
1519 .flags = CLK_SET_RATE_PARENT,
1520 .ops = &clk_branch2_ops,
1525 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1528 .enable_reg = 0x0b88,
1529 .enable_mask = BIT(0),
1530 .hw.init = &(struct clk_init_data){
1531 .name = "gcc_blsp2_qup5_i2c_apps_clk",
1532 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_i2c_apps_clk_src.clkr.hw },
1534 .flags = CLK_SET_RATE_PARENT,
1535 .ops = &clk_branch2_ops,
1540 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1543 .enable_reg = 0x0b84,
1544 .enable_mask = BIT(0),
1545 .hw.init = &(struct clk_init_data){
1546 .name = "gcc_blsp2_qup5_spi_apps_clk",
1547 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_spi_apps_clk_src.clkr.hw },
1549 .flags = CLK_SET_RATE_PARENT,
1550 .ops = &clk_branch2_ops,
1555 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1558 .enable_reg = 0x0c08,
1559 .enable_mask = BIT(0),
1560 .hw.init = &(struct clk_init_data){
1561 .name = "gcc_blsp2_qup6_i2c_apps_clk",
1562 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_i2c_apps_clk_src.clkr.hw },
1564 .flags = CLK_SET_RATE_PARENT,
1565 .ops = &clk_branch2_ops,
1570 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1573 .enable_reg = 0x0c04,
1574 .enable_mask = BIT(0),
1575 .hw.init = &(struct clk_init_data){
1576 .name = "gcc_blsp2_qup6_spi_apps_clk",
1577 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_spi_apps_clk_src.clkr.hw },
1579 .flags = CLK_SET_RATE_PARENT,
1580 .ops = &clk_branch2_ops,
1585 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1588 .enable_reg = 0x09c4,
1589 .enable_mask = BIT(0),
1590 .hw.init = &(struct clk_init_data){
1591 .name = "gcc_blsp2_uart1_apps_clk",
1592 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart1_apps_clk_src.clkr.hw },
1594 .flags = CLK_SET_RATE_PARENT,
1595 .ops = &clk_branch2_ops,
1600 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1603 .enable_reg = 0x0a44,
1604 .enable_mask = BIT(0),
1605 .hw.init = &(struct clk_init_data){
1606 .name = "gcc_blsp2_uart2_apps_clk",
1607 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart2_apps_clk_src.clkr.hw },
1609 .flags = CLK_SET_RATE_PARENT,
1610 .ops = &clk_branch2_ops,
1615 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1618 .enable_reg = 0x0ac4,
1619 .enable_mask = BIT(0),
1620 .hw.init = &(struct clk_init_data){
1621 .name = "gcc_blsp2_uart3_apps_clk",
1622 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart3_apps_clk_src.clkr.hw },
1624 .flags = CLK_SET_RATE_PARENT,
1625 .ops = &clk_branch2_ops,
1630 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1633 .enable_reg = 0x0b44,
1634 .enable_mask = BIT(0),
1635 .hw.init = &(struct clk_init_data){
1636 .name = "gcc_blsp2_uart4_apps_clk",
1637 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart4_apps_clk_src.clkr.hw },
1639 .flags = CLK_SET_RATE_PARENT,
1640 .ops = &clk_branch2_ops,
1645 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1648 .enable_reg = 0x0bc4,
1649 .enable_mask = BIT(0),
1650 .hw.init = &(struct clk_init_data){
1651 .name = "gcc_blsp2_uart5_apps_clk",
1652 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart5_apps_clk_src.clkr.hw },
1654 .flags = CLK_SET_RATE_PARENT,
1655 .ops = &clk_branch2_ops,
1660 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1663 .enable_reg = 0x0c44,
1664 .enable_mask = BIT(0),
1665 .hw.init = &(struct clk_init_data){
1666 .name = "gcc_blsp2_uart6_apps_clk",
1667 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart6_apps_clk_src.clkr.hw },
1669 .flags = CLK_SET_RATE_PARENT,
1670 .ops = &clk_branch2_ops,
1675 static struct clk_branch gcc_gp1_clk = {
1678 .enable_reg = 0x1900,
1679 .enable_mask = BIT(0),
1680 .hw.init = &(struct clk_init_data){
1681 .name = "gcc_gp1_clk",
1682 .parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw },
1684 .flags = CLK_SET_RATE_PARENT,
1685 .ops = &clk_branch2_ops,
1690 static struct clk_branch gcc_gp2_clk = {
1693 .enable_reg = 0x1940,
1694 .enable_mask = BIT(0),
1695 .hw.init = &(struct clk_init_data){
1696 .name = "gcc_gp2_clk",
1697 .parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw },
1699 .flags = CLK_SET_RATE_PARENT,
1700 .ops = &clk_branch2_ops,
1705 static struct clk_branch gcc_gp3_clk = {
1708 .enable_reg = 0x1980,
1709 .enable_mask = BIT(0),
1710 .hw.init = &(struct clk_init_data){
1711 .name = "gcc_gp3_clk",
1712 .parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw },
1714 .flags = CLK_SET_RATE_PARENT,
1715 .ops = &clk_branch2_ops,
1720 static struct clk_branch gcc_lpass_q6_axi_clk = {
1723 .enable_reg = 0x0280,
1724 .enable_mask = BIT(0),
1725 .hw.init = &(struct clk_init_data){
1726 .name = "gcc_lpass_q6_axi_clk",
1727 .ops = &clk_branch2_ops,
1732 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
1735 .enable_reg = 0x0284,
1736 .enable_mask = BIT(0),
1737 .hw.init = &(struct clk_init_data){
1738 .name = "gcc_mss_q6_bimc_axi_clk",
1739 .ops = &clk_branch2_ops,
1744 static struct clk_branch gcc_pcie_0_aux_clk = {
1747 .enable_reg = 0x1ad4,
1748 .enable_mask = BIT(0),
1749 .hw.init = &(struct clk_init_data){
1750 .name = "gcc_pcie_0_aux_clk",
1751 .parent_hws = (const struct clk_hw *[]){ &pcie_0_aux_clk_src.clkr.hw },
1753 .flags = CLK_SET_RATE_PARENT,
1754 .ops = &clk_branch2_ops,
1759 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1762 .enable_reg = 0x1ad0,
1763 .enable_mask = BIT(0),
1764 .hw.init = &(struct clk_init_data){
1765 .name = "gcc_pcie_0_cfg_ahb_clk",
1766 .ops = &clk_branch2_ops,
1771 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1774 .enable_reg = 0x1acc,
1775 .enable_mask = BIT(0),
1776 .hw.init = &(struct clk_init_data){
1777 .name = "gcc_pcie_0_mstr_axi_clk",
1778 .ops = &clk_branch2_ops,
1783 static struct clk_branch gcc_pcie_0_pipe_clk = {
1785 .halt_check = BRANCH_HALT_DELAY,
1787 .enable_reg = 0x1ad8,
1788 .enable_mask = BIT(0),
1789 .hw.init = &(struct clk_init_data){
1790 .name = "gcc_pcie_0_pipe_clk",
1791 .parent_hws = (const struct clk_hw *[]){ &pcie_0_pipe_clk_src.clkr.hw },
1793 .flags = CLK_SET_RATE_PARENT,
1794 .ops = &clk_branch2_ops,
1799 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1801 .halt_check = BRANCH_HALT_DELAY,
1803 .enable_reg = 0x1ac8,
1804 .enable_mask = BIT(0),
1805 .hw.init = &(struct clk_init_data){
1806 .name = "gcc_pcie_0_slv_axi_clk",
1807 .ops = &clk_branch2_ops,
1812 static struct clk_branch gcc_pcie_1_aux_clk = {
1815 .enable_reg = 0x1b54,
1816 .enable_mask = BIT(0),
1817 .hw.init = &(struct clk_init_data){
1818 .name = "gcc_pcie_1_aux_clk",
1819 .parent_hws = (const struct clk_hw *[]){ &pcie_1_aux_clk_src.clkr.hw },
1821 .flags = CLK_SET_RATE_PARENT,
1822 .ops = &clk_branch2_ops,
1827 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1830 .enable_reg = 0x1b54,
1831 .enable_mask = BIT(0),
1832 .hw.init = &(struct clk_init_data){
1833 .name = "gcc_pcie_1_cfg_ahb_clk",
1834 .ops = &clk_branch2_ops,
1839 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1842 .enable_reg = 0x1b50,
1843 .enable_mask = BIT(0),
1844 .hw.init = &(struct clk_init_data){
1845 .name = "gcc_pcie_1_mstr_axi_clk",
1846 .ops = &clk_branch2_ops,
1851 static struct clk_branch gcc_pcie_1_pipe_clk = {
1853 .halt_check = BRANCH_HALT_DELAY,
1855 .enable_reg = 0x1b58,
1856 .enable_mask = BIT(0),
1857 .hw.init = &(struct clk_init_data){
1858 .name = "gcc_pcie_1_pipe_clk",
1859 .parent_hws = (const struct clk_hw *[]){ &pcie_1_pipe_clk_src.clkr.hw },
1861 .flags = CLK_SET_RATE_PARENT,
1862 .ops = &clk_branch2_ops,
1867 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1870 .enable_reg = 0x1b48,
1871 .enable_mask = BIT(0),
1872 .hw.init = &(struct clk_init_data){
1873 .name = "gcc_pcie_1_slv_axi_clk",
1874 .ops = &clk_branch2_ops,
1879 static struct clk_branch gcc_pdm2_clk = {
1882 .enable_reg = 0x0ccc,
1883 .enable_mask = BIT(0),
1884 .hw.init = &(struct clk_init_data){
1885 .name = "gcc_pdm2_clk",
1886 .parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw },
1888 .flags = CLK_SET_RATE_PARENT,
1889 .ops = &clk_branch2_ops,
1894 static struct clk_branch gcc_pdm_ahb_clk = {
1897 .enable_reg = 0x0cc4,
1898 .enable_mask = BIT(0),
1899 .hw.init = &(struct clk_init_data){
1900 .name = "gcc_pdm_ahb_clk",
1901 .ops = &clk_branch2_ops,
1906 static struct clk_branch gcc_sdcc1_apps_clk = {
1909 .enable_reg = 0x04c4,
1910 .enable_mask = BIT(0),
1911 .hw.init = &(struct clk_init_data){
1912 .name = "gcc_sdcc1_apps_clk",
1913 .parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw },
1915 .flags = CLK_SET_RATE_PARENT,
1916 .ops = &clk_branch2_ops,
1921 static struct clk_branch gcc_sdcc1_ahb_clk = {
1924 .enable_reg = 0x04c8,
1925 .enable_mask = BIT(0),
1926 .hw.init = &(struct clk_init_data){
1927 .name = "gcc_sdcc1_ahb_clk",
1928 .ops = &clk_branch2_ops,
1933 static struct clk_branch gcc_sdcc2_ahb_clk = {
1936 .enable_reg = 0x0508,
1937 .enable_mask = BIT(0),
1938 .hw.init = &(struct clk_init_data){
1939 .name = "gcc_sdcc2_ahb_clk",
1940 .ops = &clk_branch2_ops,
1945 static struct clk_branch gcc_sdcc2_apps_clk = {
1948 .enable_reg = 0x0504,
1949 .enable_mask = BIT(0),
1950 .hw.init = &(struct clk_init_data){
1951 .name = "gcc_sdcc2_apps_clk",
1952 .parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw },
1954 .flags = CLK_SET_RATE_PARENT,
1955 .ops = &clk_branch2_ops,
1960 static struct clk_branch gcc_sdcc3_ahb_clk = {
1963 .enable_reg = 0x0548,
1964 .enable_mask = BIT(0),
1965 .hw.init = &(struct clk_init_data){
1966 .name = "gcc_sdcc3_ahb_clk",
1967 .ops = &clk_branch2_ops,
1972 static struct clk_branch gcc_sdcc3_apps_clk = {
1975 .enable_reg = 0x0544,
1976 .enable_mask = BIT(0),
1977 .hw.init = &(struct clk_init_data){
1978 .name = "gcc_sdcc3_apps_clk",
1979 .parent_hws = (const struct clk_hw *[]){ &sdcc3_apps_clk_src.clkr.hw },
1981 .flags = CLK_SET_RATE_PARENT,
1982 .ops = &clk_branch2_ops,
1987 static struct clk_branch gcc_sdcc4_ahb_clk = {
1990 .enable_reg = 0x0588,
1991 .enable_mask = BIT(0),
1992 .hw.init = &(struct clk_init_data){
1993 .name = "gcc_sdcc4_ahb_clk",
1994 .ops = &clk_branch2_ops,
1999 static struct clk_branch gcc_sdcc4_apps_clk = {
2002 .enable_reg = 0x0584,
2003 .enable_mask = BIT(0),
2004 .hw.init = &(struct clk_init_data){
2005 .name = "gcc_sdcc4_apps_clk",
2006 .parent_hws = (const struct clk_hw *[]){ &sdcc4_apps_clk_src.clkr.hw },
2008 .flags = CLK_SET_RATE_PARENT,
2009 .ops = &clk_branch2_ops,
2014 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
2017 .enable_reg = 0x1d7c,
2018 .enable_mask = BIT(0),
2019 .hw.init = &(struct clk_init_data){
2020 .name = "gcc_sys_noc_ufs_axi_clk",
2021 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2023 .flags = CLK_SET_RATE_PARENT,
2024 .ops = &clk_branch2_ops,
2029 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
2032 .enable_reg = 0x03fc,
2033 .enable_mask = BIT(0),
2034 .hw.init = &(struct clk_init_data){
2035 .name = "gcc_sys_noc_usb3_axi_clk",
2036 .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw },
2038 .flags = CLK_SET_RATE_PARENT,
2039 .ops = &clk_branch2_ops,
2044 static struct clk_branch gcc_tsif_ahb_clk = {
2047 .enable_reg = 0x0d84,
2048 .enable_mask = BIT(0),
2049 .hw.init = &(struct clk_init_data){
2050 .name = "gcc_tsif_ahb_clk",
2051 .ops = &clk_branch2_ops,
2056 static struct clk_branch gcc_tsif_ref_clk = {
2059 .enable_reg = 0x0d88,
2060 .enable_mask = BIT(0),
2061 .hw.init = &(struct clk_init_data){
2062 .name = "gcc_tsif_ref_clk",
2063 .parent_hws = (const struct clk_hw *[]){ &tsif_ref_clk_src.clkr.hw },
2065 .flags = CLK_SET_RATE_PARENT,
2066 .ops = &clk_branch2_ops,
2071 static struct clk_branch gcc_ufs_ahb_clk = {
2074 .enable_reg = 0x1d4c,
2075 .enable_mask = BIT(0),
2076 .hw.init = &(struct clk_init_data){
2077 .name = "gcc_ufs_ahb_clk",
2078 .ops = &clk_branch2_ops,
2083 static struct clk_branch gcc_ufs_axi_clk = {
2086 .enable_reg = 0x1d48,
2087 .enable_mask = BIT(0),
2088 .hw.init = &(struct clk_init_data){
2089 .name = "gcc_ufs_axi_clk",
2090 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2092 .flags = CLK_SET_RATE_PARENT,
2093 .ops = &clk_branch2_ops,
2098 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2101 .enable_reg = 0x1d54,
2102 .enable_mask = BIT(0),
2103 .hw.init = &(struct clk_init_data){
2104 .name = "gcc_ufs_rx_cfg_clk",
2105 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2107 .flags = CLK_SET_RATE_PARENT,
2108 .ops = &clk_branch2_ops,
2113 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2115 .halt_check = BRANCH_HALT_DELAY,
2117 .enable_reg = 0x1d60,
2118 .enable_mask = BIT(0),
2119 .hw.init = &(struct clk_init_data){
2120 .name = "gcc_ufs_rx_symbol_0_clk",
2121 .ops = &clk_branch2_ops,
2126 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2128 .halt_check = BRANCH_HALT_DELAY,
2130 .enable_reg = 0x1d64,
2131 .enable_mask = BIT(0),
2132 .hw.init = &(struct clk_init_data){
2133 .name = "gcc_ufs_rx_symbol_1_clk",
2134 .ops = &clk_branch2_ops,
2139 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2142 .enable_reg = 0x1d50,
2143 .enable_mask = BIT(0),
2144 .hw.init = &(struct clk_init_data){
2145 .name = "gcc_ufs_tx_cfg_clk",
2146 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2148 .flags = CLK_SET_RATE_PARENT,
2149 .ops = &clk_branch2_ops,
2154 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2156 .halt_check = BRANCH_HALT_DELAY,
2158 .enable_reg = 0x1d58,
2159 .enable_mask = BIT(0),
2160 .hw.init = &(struct clk_init_data){
2161 .name = "gcc_ufs_tx_symbol_0_clk",
2162 .ops = &clk_branch2_ops,
2167 static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
2169 .halt_check = BRANCH_HALT_DELAY,
2171 .enable_reg = 0x1d5c,
2172 .enable_mask = BIT(0),
2173 .hw.init = &(struct clk_init_data){
2174 .name = "gcc_ufs_tx_symbol_1_clk",
2175 .ops = &clk_branch2_ops,
2180 static struct clk_branch gcc_usb2_hs_phy_sleep_clk = {
2183 .enable_reg = 0x04ac,
2184 .enable_mask = BIT(0),
2185 .hw.init = &(struct clk_init_data){
2186 .name = "gcc_usb2_hs_phy_sleep_clk",
2187 .parent_data = &(const struct clk_parent_data){
2192 .ops = &clk_branch2_ops,
2197 static struct clk_branch gcc_usb30_master_clk = {
2200 .enable_reg = 0x03c8,
2201 .enable_mask = BIT(0),
2202 .hw.init = &(struct clk_init_data){
2203 .name = "gcc_usb30_master_clk",
2204 .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw },
2206 .flags = CLK_SET_RATE_PARENT,
2207 .ops = &clk_branch2_ops,
2212 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2215 .enable_reg = 0x03d0,
2216 .enable_mask = BIT(0),
2217 .hw.init = &(struct clk_init_data){
2218 .name = "gcc_usb30_mock_utmi_clk",
2219 .parent_hws = (const struct clk_hw *[]){ &usb30_mock_utmi_clk_src.clkr.hw },
2221 .flags = CLK_SET_RATE_PARENT,
2222 .ops = &clk_branch2_ops,
2227 static struct clk_branch gcc_usb30_sleep_clk = {
2230 .enable_reg = 0x03cc,
2231 .enable_mask = BIT(0),
2232 .hw.init = &(struct clk_init_data){
2233 .name = "gcc_usb30_sleep_clk",
2234 .parent_data = &(const struct clk_parent_data){
2239 .ops = &clk_branch2_ops,
2244 static struct clk_branch gcc_usb3_phy_aux_clk = {
2247 .enable_reg = 0x1408,
2248 .enable_mask = BIT(0),
2249 .hw.init = &(struct clk_init_data){
2250 .name = "gcc_usb3_phy_aux_clk",
2251 .parent_hws = (const struct clk_hw *[]){ &usb3_phy_aux_clk_src.clkr.hw },
2253 .flags = CLK_SET_RATE_PARENT,
2254 .ops = &clk_branch2_ops,
2259 static struct clk_branch gcc_usb3_phy_pipe_clk = {
2261 .halt_check = BRANCH_HALT_SKIP,
2263 .enable_reg = 0x140c,
2264 .enable_mask = BIT(0),
2265 .hw.init = &(struct clk_init_data){
2266 .name = "gcc_usb3_phy_pipe_clk",
2267 .ops = &clk_branch2_ops,
2272 static struct clk_branch gcc_usb_hs_ahb_clk = {
2275 .enable_reg = 0x0488,
2276 .enable_mask = BIT(0),
2277 .hw.init = &(struct clk_init_data){
2278 .name = "gcc_usb_hs_ahb_clk",
2279 .ops = &clk_branch2_ops,
2284 static struct clk_branch gcc_usb_hs_system_clk = {
2287 .enable_reg = 0x0484,
2288 .enable_mask = BIT(0),
2289 .hw.init = &(struct clk_init_data){
2290 .name = "gcc_usb_hs_system_clk",
2291 .parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw },
2293 .flags = CLK_SET_RATE_PARENT,
2294 .ops = &clk_branch2_ops,
2299 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2302 .enable_reg = 0x1a84,
2303 .enable_mask = BIT(0),
2304 .hw.init = &(struct clk_init_data){
2305 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2306 .ops = &clk_branch2_ops,
2311 static struct clk_branch gpll0_out_mmsscc = {
2312 .halt_check = BRANCH_HALT_DELAY,
2314 .enable_reg = 0x1484,
2315 .enable_mask = BIT(26),
2316 .hw.init = &(struct clk_init_data){
2317 .name = "gpll0_out_mmsscc",
2318 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
2320 .ops = &clk_branch2_ops,
2325 static struct clk_branch gpll0_out_msscc = {
2326 .halt_check = BRANCH_HALT_DELAY,
2328 .enable_reg = 0x1484,
2329 .enable_mask = BIT(27),
2330 .hw.init = &(struct clk_init_data){
2331 .name = "gpll0_out_msscc",
2332 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
2334 .ops = &clk_branch2_ops,
2339 static struct clk_branch pcie_0_phy_ldo = {
2341 .halt_check = BRANCH_HALT_SKIP,
2343 .enable_reg = 0x1E00,
2344 .enable_mask = BIT(0),
2345 .hw.init = &(struct clk_init_data){
2346 .name = "pcie_0_phy_ldo",
2347 .ops = &clk_branch2_ops,
2352 static struct clk_branch pcie_1_phy_ldo = {
2354 .halt_check = BRANCH_HALT_SKIP,
2356 .enable_reg = 0x1E04,
2357 .enable_mask = BIT(0),
2358 .hw.init = &(struct clk_init_data){
2359 .name = "pcie_1_phy_ldo",
2360 .ops = &clk_branch2_ops,
2365 static struct clk_branch ufs_phy_ldo = {
2367 .halt_check = BRANCH_HALT_SKIP,
2369 .enable_reg = 0x1E0C,
2370 .enable_mask = BIT(0),
2371 .hw.init = &(struct clk_init_data){
2372 .name = "ufs_phy_ldo",
2373 .ops = &clk_branch2_ops,
2378 static struct clk_branch usb_ss_phy_ldo = {
2380 .halt_check = BRANCH_HALT_SKIP,
2382 .enable_reg = 0x1E08,
2383 .enable_mask = BIT(0),
2384 .hw.init = &(struct clk_init_data){
2385 .name = "usb_ss_phy_ldo",
2386 .ops = &clk_branch2_ops,
2391 static struct clk_branch gcc_boot_rom_ahb_clk = {
2393 .halt_check = BRANCH_HALT_VOTED,
2397 .enable_reg = 0x1484,
2398 .enable_mask = BIT(10),
2399 .hw.init = &(struct clk_init_data){
2400 .name = "gcc_boot_rom_ahb_clk",
2401 .ops = &clk_branch2_ops,
2406 static struct clk_branch gcc_prng_ahb_clk = {
2408 .halt_check = BRANCH_HALT_VOTED,
2410 .enable_reg = 0x1484,
2411 .enable_mask = BIT(13),
2412 .hw.init = &(struct clk_init_data){
2413 .name = "gcc_prng_ahb_clk",
2414 .ops = &clk_branch2_ops,
2419 static struct gdsc pcie_0_gdsc = {
2424 .pwrsts = PWRSTS_OFF_ON,
2427 static struct gdsc pcie_1_gdsc = {
2432 .pwrsts = PWRSTS_OFF_ON,
2435 static struct gdsc usb30_gdsc = {
2440 .pwrsts = PWRSTS_OFF_ON,
2443 static struct gdsc ufs_gdsc = {
2448 .pwrsts = PWRSTS_OFF_ON,
2451 static struct clk_regmap *gcc_msm8994_clocks[] = {
2452 [GPLL0_EARLY] = &gpll0_early.clkr,
2453 [GPLL0] = &gpll0.clkr,
2454 [GPLL4_EARLY] = &gpll4_early.clkr,
2455 [GPLL4] = &gpll4.clkr,
2456 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2457 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2458 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2459 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2460 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2461 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2462 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2463 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2464 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2465 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2466 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2467 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2468 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2469 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2470 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2471 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2472 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2473 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2474 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2475 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2476 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2477 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2478 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2479 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2480 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2481 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2482 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2483 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2484 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2485 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2486 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2487 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2488 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2489 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2490 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2491 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2492 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2493 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2494 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2495 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2496 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2497 [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
2498 [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
2499 [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
2500 [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
2501 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2502 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2503 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2504 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2505 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2506 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2507 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2508 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2509 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2510 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2511 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2512 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2513 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2514 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2515 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2516 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2517 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2518 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2519 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2520 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2521 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2522 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2523 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2524 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2525 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2526 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2527 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2528 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2529 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2530 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2531 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2532 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2533 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2534 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2535 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2536 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2537 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2538 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2539 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2540 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2541 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2542 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2543 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2544 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2545 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2546 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2547 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2548 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2549 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2550 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2551 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
2552 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
2553 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2554 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2555 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2556 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2557 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2558 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
2559 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
2560 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
2561 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
2562 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
2563 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2564 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2565 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2566 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2567 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2568 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2569 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
2570 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2571 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2572 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2573 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
2574 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2575 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2576 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2577 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
2578 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2579 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
2580 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
2581 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
2582 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
2583 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
2584 [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr,
2585 [GCC_USB2_HS_PHY_SLEEP_CLK] = &gcc_usb2_hs_phy_sleep_clk.clkr,
2586 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2587 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2588 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2589 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2590 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2591 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
2592 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2593 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2594 [GPLL0_OUT_MMSSCC] = &gpll0_out_mmsscc.clkr,
2595 [GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr,
2596 [PCIE_0_PHY_LDO] = &pcie_0_phy_ldo.clkr,
2597 [PCIE_1_PHY_LDO] = &pcie_1_phy_ldo.clkr,
2598 [UFS_PHY_LDO] = &ufs_phy_ldo.clkr,
2599 [USB_SS_PHY_LDO] = &usb_ss_phy_ldo.clkr,
2600 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2601 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2604 * The following clocks should NOT be managed by this driver, but they once were
2605 * mistakengly added. Now they are only here to indicate that they are not defined
2606 * on purpose, even though the names will stay in the header file (for ABI sanity).
2608 [CONFIG_NOC_CLK_SRC] = NULL,
2609 [PERIPH_NOC_CLK_SRC] = NULL,
2610 [SYSTEM_NOC_CLK_SRC] = NULL,
2613 static struct gdsc *gcc_msm8994_gdscs[] = {
2614 /* This GDSC does not exist, but ABI has to remain intact */
2616 [PCIE_0_GDSC] = &pcie_0_gdsc,
2617 [PCIE_1_GDSC] = &pcie_1_gdsc,
2618 [USB30_GDSC] = &usb30_gdsc,
2619 [UFS_GDSC] = &ufs_gdsc,
2622 static const struct qcom_reset_map gcc_msm8994_resets[] = {
2623 [USB3_PHY_RESET] = { 0x1400 },
2624 [USB3PHY_PHY_RESET] = { 0x1404 },
2625 [MSS_RESET] = { 0x1680 },
2626 [PCIE_PHY_0_RESET] = { 0x1b18 },
2627 [PCIE_PHY_1_RESET] = { 0x1b98 },
2628 [QUSB2_PHY_RESET] = { 0x04b8 },
2631 static const struct regmap_config gcc_msm8994_regmap_config = {
2635 .max_register = 0x2000,
2639 static const struct qcom_cc_desc gcc_msm8994_desc = {
2640 .config = &gcc_msm8994_regmap_config,
2641 .clks = gcc_msm8994_clocks,
2642 .num_clks = ARRAY_SIZE(gcc_msm8994_clocks),
2643 .resets = gcc_msm8994_resets,
2644 .num_resets = ARRAY_SIZE(gcc_msm8994_resets),
2645 .gdscs = gcc_msm8994_gdscs,
2646 .num_gdscs = ARRAY_SIZE(gcc_msm8994_gdscs),
2649 static const struct of_device_id gcc_msm8994_match_table[] = {
2650 { .compatible = "qcom,gcc-msm8992" },
2651 { .compatible = "qcom,gcc-msm8994" }, /* V2 and V2.1 */
2654 MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
2656 static int gcc_msm8994_probe(struct platform_device *pdev)
2658 if (of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-msm8992")) {
2659 /* MSM8992 features less clocks and some have different freq tables */
2660 gcc_msm8994_desc.clks[UFS_AXI_CLK_SRC] = NULL;
2661 gcc_msm8994_desc.clks[GCC_LPASS_Q6_AXI_CLK] = NULL;
2662 gcc_msm8994_desc.clks[UFS_PHY_LDO] = NULL;
2663 gcc_msm8994_desc.clks[GCC_UFS_AHB_CLK] = NULL;
2664 gcc_msm8994_desc.clks[GCC_UFS_AXI_CLK] = NULL;
2665 gcc_msm8994_desc.clks[GCC_UFS_RX_CFG_CLK] = NULL;
2666 gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_0_CLK] = NULL;
2667 gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_1_CLK] = NULL;
2668 gcc_msm8994_desc.clks[GCC_UFS_TX_CFG_CLK] = NULL;
2669 gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_0_CLK] = NULL;
2670 gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_1_CLK] = NULL;
2672 sdcc1_apps_clk_src.freq_tbl = ftbl_sdcc1_apps_clk_src_8992;
2673 blsp1_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2674 blsp1_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2675 blsp1_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2676 blsp1_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2677 blsp1_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2678 blsp1_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2679 blsp2_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2680 blsp2_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2681 blsp2_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2682 blsp2_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2683 blsp2_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2684 blsp2_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2687 * Some 8992 boards might *possibly* use
2688 * PCIe1 clocks and controller, but it's not
2689 * standard and they should be disabled otherwise.
2691 gcc_msm8994_desc.clks[PCIE_1_AUX_CLK_SRC] = NULL;
2692 gcc_msm8994_desc.clks[PCIE_1_PIPE_CLK_SRC] = NULL;
2693 gcc_msm8994_desc.clks[PCIE_1_PHY_LDO] = NULL;
2694 gcc_msm8994_desc.clks[GCC_PCIE_1_AUX_CLK] = NULL;
2695 gcc_msm8994_desc.clks[GCC_PCIE_1_CFG_AHB_CLK] = NULL;
2696 gcc_msm8994_desc.clks[GCC_PCIE_1_MSTR_AXI_CLK] = NULL;
2697 gcc_msm8994_desc.clks[GCC_PCIE_1_PIPE_CLK] = NULL;
2698 gcc_msm8994_desc.clks[GCC_PCIE_1_SLV_AXI_CLK] = NULL;
2699 gcc_msm8994_desc.clks[GCC_SYS_NOC_UFS_AXI_CLK] = NULL;
2702 return qcom_cc_probe(pdev, &gcc_msm8994_desc);
2705 static struct platform_driver gcc_msm8994_driver = {
2706 .probe = gcc_msm8994_probe,
2708 .name = "gcc-msm8994",
2709 .of_match_table = gcc_msm8994_match_table,
2713 static int __init gcc_msm8994_init(void)
2715 return platform_driver_register(&gcc_msm8994_driver);
2717 core_initcall(gcc_msm8994_init);
2719 static void __exit gcc_msm8994_exit(void)
2721 platform_driver_unregister(&gcc_msm8994_driver);
2723 module_exit(gcc_msm8994_exit);
2725 MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver");
2726 MODULE_LICENSE("GPL v2");
2727 MODULE_ALIAS("platform:gcc-msm8994");