drivers/clk/qcom/gcc-msm8994.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
   3  */
   4
   5 #include <linux/clk-provider.h>
   6 #include <linux/kernel.h>
   7 #include <linux/init.h>
   8 #include <linux/err.h>
   9 #include <linux/ctype.h>
  10 #include <linux/io.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/module.h>
  15 #include <linux/regmap.h>
  16
  17 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
  18
  19 #include "common.h"
  20 #include "clk-regmap.h"
  21 #include "clk-alpha-pll.h"
  22 #include "clk-rcg.h"
  23 #include "clk-branch.h"
  24 #include "reset.h"
  25 #include "gdsc.h"
  26
  27 enum {
  28         P_XO,
  29         P_GPLL0,
  30         P_GPLL4,
  31 };
  32
  33 static struct clk_alpha_pll gpll0_early = {
  34         .offset = 0,
  35         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  36         .clkr = {
  37                 .enable_reg = 0x1480,
  38                 .enable_mask = BIT(0),
  39                 .hw.init = &(struct clk_init_data){
  40                         .name = "gpll0_early",
  41                         .parent_data = &(const struct clk_parent_data){
  42                                 .fw_name = "xo",
  43                         },
  44                         .num_parents = 1,
  45                         .ops = &clk_alpha_pll_ops,
  46                 },
  47         },
  48 };
  49
  50 static struct clk_alpha_pll_postdiv gpll0 = {
  51         .offset = 0,
  52         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  53         .clkr.hw.init = &(struct clk_init_data){
  54                 .name = "gpll0",
  55                 .parent_names = (const char *[]) { "gpll0_early" },
  56                 .num_parents = 1,
  57                 .ops = &clk_alpha_pll_postdiv_ops,
  58         },
  59 };
  60
  61 static struct clk_alpha_pll gpll4_early = {
  62         .offset = 0x1dc0,
  63         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  64         .clkr = {
  65                 .enable_reg = 0x1480,
  66                 .enable_mask = BIT(4),
  67                 .hw.init = &(struct clk_init_data){
  68                         .name = "gpll4_early",
  69                         .parent_data = &(const struct clk_parent_data){
  70                                 .fw_name = "xo",
  71                         },
  72                         .num_parents = 1,
  73                         .ops = &clk_alpha_pll_ops,
  74                 },
  75         },
  76 };
  77
  78 static struct clk_alpha_pll_postdiv gpll4 = {
  79         .offset = 0x1dc0,
  80         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  81         .clkr.hw.init = &(struct clk_init_data){
  82                 .name = "gpll4",
  83                 .parent_names = (const char *[]) { "gpll4_early" },
  84                 .num_parents = 1,
  85                 .ops = &clk_alpha_pll_postdiv_ops,
  86         },
  87 };
  88
  89 static const struct parent_map gcc_xo_gpll0_map[] = {
  90         { P_XO, 0 },
  91         { P_GPLL0, 1 },
  92 };
  93
  94 static const struct clk_parent_data gcc_xo_gpll0[] = {
  95         { .fw_name = "xo" },
  96         { .hw = &gpll0.clkr.hw },
  97 };
  98
  99 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
 100         { P_XO, 0 },
 101         { P_GPLL0, 1 },
 102         { P_GPLL4, 5 },
 103 };
 104
 105 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
 106         { .fw_name = "xo" },
 107         { .hw = &gpll0.clkr.hw },
 108         { .hw = &gpll4.clkr.hw },
 109 };
 110
 111 static struct clk_rcg2 system_noc_clk_src = {
 112         .cmd_rcgr = 0x0120,
 113         .hid_width = 5,
 114         .parent_map = gcc_xo_gpll0_map,
 115         .clkr.hw.init = &(struct clk_init_data){
 116                 .name = "system_noc_clk_src",
 117                 .parent_data = gcc_xo_gpll0,
 118                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 119                 .ops = &clk_rcg2_ops,
 120         },
 121 };
 122
 123 static struct clk_rcg2 config_noc_clk_src = {
 124         .cmd_rcgr = 0x0150,
 125         .hid_width = 5,
 126         .parent_map = gcc_xo_gpll0_map,
 127         .clkr.hw.init = &(struct clk_init_data){
 128                 .name = "config_noc_clk_src",
 129                 .parent_data = gcc_xo_gpll0,
 130                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 131                 .ops = &clk_rcg2_ops,
 132         },
 133 };
 134
 135 static struct clk_rcg2 periph_noc_clk_src = {
 136         .cmd_rcgr = 0x0190,
 137         .hid_width = 5,
 138         .parent_map = gcc_xo_gpll0_map,
 139         .clkr.hw.init = &(struct clk_init_data){
 140                 .name = "periph_noc_clk_src",
 141                 .parent_data = gcc_xo_gpll0,
 142                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 143                 .ops = &clk_rcg2_ops,
 144         },
 145 };
 146
 147 static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
 148         F(50000000, P_GPLL0, 12, 0, 0),
 149         F(100000000, P_GPLL0, 6, 0, 0),
 150         F(150000000, P_GPLL0, 4, 0, 0),
 151         F(171430000, P_GPLL0, 3.5, 0, 0),
 152         F(200000000, P_GPLL0, 3, 0, 0),
 153         F(240000000, P_GPLL0, 2.5, 0, 0),
 154         { }
 155 };
 156
 157 static struct clk_rcg2 ufs_axi_clk_src = {
 158         .cmd_rcgr = 0x1d68,
 159         .mnd_width = 8,
 160         .hid_width = 5,
 161         .parent_map = gcc_xo_gpll0_map,
 162         .freq_tbl = ftbl_ufs_axi_clk_src,
 163         .clkr.hw.init = &(struct clk_init_data){
 164                 .name = "ufs_axi_clk_src",
 165                 .parent_data = gcc_xo_gpll0,
 166                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 167                 .ops = &clk_rcg2_ops,
 168         },
 169 };
 170
 171 static struct freq_tbl ftbl_usb30_master_clk_src[] = {
 172         F(19200000, P_XO, 1, 0, 0),
 173         F(125000000, P_GPLL0, 1, 5, 24),
 174         { }
 175 };
 176
 177 static struct clk_rcg2 usb30_master_clk_src = {
 178         .cmd_rcgr = 0x03d4,
 179         .mnd_width = 8,
 180         .hid_width = 5,
 181         .parent_map = gcc_xo_gpll0_map,
 182         .freq_tbl = ftbl_usb30_master_clk_src,
 183         .clkr.hw.init = &(struct clk_init_data){
 184                 .name = "usb30_master_clk_src",
 185                 .parent_data = gcc_xo_gpll0,
 186                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 187                 .ops = &clk_rcg2_ops,
 188         },
 189 };
 190
 191 static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
 192         F(19200000, P_XO, 1, 0, 0),
 193         F(50000000, P_GPLL0, 12, 0, 0),
 194         { }
 195 };
 196
 197 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 198         .cmd_rcgr = 0x0660,
 199         .hid_width = 5,
 200         .parent_map = gcc_xo_gpll0_map,
 201         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 202         .clkr.hw.init = &(struct clk_init_data){
 203                 .name = "blsp1_qup1_i2c_apps_clk_src",
 204                 .parent_data = gcc_xo_gpll0,
 205                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 206                 .ops = &clk_rcg2_ops,
 207         },
 208 };
 209
 210 static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
 211         F(960000, P_XO, 10, 1, 2),
 212         F(4800000, P_XO, 4, 0, 0),
 213         F(9600000, P_XO, 2, 0, 0),
 214         F(15000000, P_GPLL0, 10, 1, 4),
 215         F(19200000, P_XO, 1, 0, 0),
 216         F(24000000, P_GPLL0, 12.5, 1, 2),
 217         F(25000000, P_GPLL0, 12, 1, 2),
 218         F(48000000, P_GPLL0, 12.5, 0, 0),
 219         F(50000000, P_GPLL0, 12, 0, 0),
 220         { }
 221 };
 222
 223 static struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src_8992[] = {
 224         F(960000, P_XO, 10, 1, 2),
 225         F(4800000, P_XO, 4, 0, 0),
 226         F(9600000, P_XO, 2, 0, 0),
 227         F(15000000, P_GPLL0, 10, 1, 4),
 228         F(19200000, P_XO, 1, 0, 0),
 229         F(25000000, P_GPLL0, 12, 1, 2),
 230         F(50000000, P_GPLL0, 12, 0, 0),
 231         { }
 232 };
 233
 234 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 235         .cmd_rcgr = 0x064c,
 236         .mnd_width = 8,
 237         .hid_width = 5,
 238         .parent_map = gcc_xo_gpll0_map,
 239         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 240         .clkr.hw.init = &(struct clk_init_data){
 241                 .name = "blsp1_qup1_spi_apps_clk_src",
 242                 .parent_data = gcc_xo_gpll0,
 243                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 244                 .ops = &clk_rcg2_ops,
 245         },
 246 };
 247
 248 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 249         .cmd_rcgr = 0x06e0,
 250         .hid_width = 5,
 251         .parent_map = gcc_xo_gpll0_map,
 252         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 253         .clkr.hw.init = &(struct clk_init_data){
 254                 .name = "blsp1_qup2_i2c_apps_clk_src",
 255                 .parent_data = gcc_xo_gpll0,
 256                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 257                 .ops = &clk_rcg2_ops,
 258         },
 259 };
 260
 261 static struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
 262         F(960000, P_XO, 10, 1, 2),
 263         F(4800000, P_XO, 4, 0, 0),
 264         F(9600000, P_XO, 2, 0, 0),
 265         F(15000000, P_GPLL0, 10, 1, 4),
 266         F(19200000, P_XO, 1, 0, 0),
 267         F(24000000, P_GPLL0, 12.5, 1, 2),
 268         F(25000000, P_GPLL0, 12, 1, 2),
 269         F(42860000, P_GPLL0, 14, 0, 0),
 270         F(46150000, P_GPLL0, 13, 0, 0),
 271         { }
 272 };
 273
 274 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 275         .cmd_rcgr = 0x06cc,
 276         .mnd_width = 8,
 277         .hid_width = 5,
 278         .parent_map = gcc_xo_gpll0_map,
 279         .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
 280         .clkr.hw.init = &(struct clk_init_data){
 281                 .name = "blsp1_qup2_spi_apps_clk_src",
 282                 .parent_data = gcc_xo_gpll0,
 283                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 284                 .ops = &clk_rcg2_ops,
 285         },
 286 };
 287
 288 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 289         .cmd_rcgr = 0x0760,
 290         .hid_width = 5,
 291         .parent_map = gcc_xo_gpll0_map,
 292         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 293         .clkr.hw.init = &(struct clk_init_data){
 294                 .name = "blsp1_qup3_i2c_apps_clk_src",
 295                 .parent_data = gcc_xo_gpll0,
 296                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 297                 .ops = &clk_rcg2_ops,
 298         },
 299 };
 300
 301 static struct freq_tbl ftbl_blsp1_qup3_4_spi_apps_clk_src[] = {
 302         F(960000, P_XO, 10, 1, 2),
 303         F(4800000, P_XO, 4, 0, 0),
 304         F(9600000, P_XO, 2, 0, 0),
 305         F(15000000, P_GPLL0, 10, 1, 4),
 306         F(19200000, P_XO, 1, 0, 0),
 307         F(24000000, P_GPLL0, 12.5, 1, 2),
 308         F(25000000, P_GPLL0, 12, 1, 2),
 309         F(42860000, P_GPLL0, 14, 0, 0),
 310         F(44440000, P_GPLL0, 13.5, 0, 0),
 311         { }
 312 };
 313
 314 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 315         .cmd_rcgr = 0x074c,
 316         .mnd_width = 8,
 317         .hid_width = 5,
 318         .parent_map = gcc_xo_gpll0_map,
 319         .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src,
 320         .clkr.hw.init = &(struct clk_init_data){
 321                 .name = "blsp1_qup3_spi_apps_clk_src",
 322                 .parent_data = gcc_xo_gpll0,
 323                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 324                 .ops = &clk_rcg2_ops,
 325         },
 326 };
 327
 328 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 329         .cmd_rcgr = 0x07e0,
 330         .hid_width = 5,
 331         .parent_map = gcc_xo_gpll0_map,
 332         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 333         .clkr.hw.init = &(struct clk_init_data){
 334                 .name = "blsp1_qup4_i2c_apps_clk_src",
 335                 .parent_data = gcc_xo_gpll0,
 336                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 337                 .ops = &clk_rcg2_ops,
 338         },
 339 };
 340
 341 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 342         .cmd_rcgr = 0x07cc,
 343         .mnd_width = 8,
 344         .hid_width = 5,
 345         .parent_map = gcc_xo_gpll0_map,
 346         .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src,
 347         .clkr.hw.init = &(struct clk_init_data){
 348                 .name = "blsp1_qup4_spi_apps_clk_src",
 349                 .parent_data = gcc_xo_gpll0,
 350                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 351                 .ops = &clk_rcg2_ops,
 352         },
 353 };
 354
 355 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 356         .cmd_rcgr = 0x0860,
 357         .hid_width = 5,
 358         .parent_map = gcc_xo_gpll0_map,
 359         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 360         .clkr.hw.init = &(struct clk_init_data){
 361                 .name = "blsp1_qup5_i2c_apps_clk_src",
 362                 .parent_data = gcc_xo_gpll0,
 363                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 364                 .ops = &clk_rcg2_ops,
 365         },
 366 };
 367
 368 static struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = {
 369         F(960000, P_XO, 10, 1, 2),
 370         F(4800000, P_XO, 4, 0, 0),
 371         F(9600000, P_XO, 2, 0, 0),
 372         F(15000000, P_GPLL0, 10, 1, 4),
 373         F(19200000, P_XO, 1, 0, 0),
 374         F(24000000, P_GPLL0, 12.5, 1, 2),
 375         F(25000000, P_GPLL0, 12, 1, 2),
 376         F(40000000, P_GPLL0, 15, 0, 0),
 377         F(42860000, P_GPLL0, 14, 0, 0),
 378         { }
 379 };
 380
 381 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 382         .cmd_rcgr = 0x084c,
 383         .mnd_width = 8,
 384         .hid_width = 5,
 385         .parent_map = gcc_xo_gpll0_map,
 386         .freq_tbl = ftbl_blsp1_qup5_spi_apps_clk_src,
 387         .clkr.hw.init = &(struct clk_init_data){
 388                 .name = "blsp1_qup5_spi_apps_clk_src",
 389                 .parent_data = gcc_xo_gpll0,
 390                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 391                 .ops = &clk_rcg2_ops,
 392         },
 393 };
 394
 395 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 396         .cmd_rcgr = 0x08e0,
 397         .hid_width = 5,
 398         .parent_map = gcc_xo_gpll0_map,
 399         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 400         .clkr.hw.init = &(struct clk_init_data){
 401                 .name = "blsp1_qup6_i2c_apps_clk_src",
 402                 .parent_data = gcc_xo_gpll0,
 403                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 404                 .ops = &clk_rcg2_ops,
 405         },
 406 };
 407
 408 static struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = {
 409         F(960000, P_XO, 10, 1, 2),
 410         F(4800000, P_XO, 4, 0, 0),
 411         F(9600000, P_XO, 2, 0, 0),
 412         F(15000000, P_GPLL0, 10, 1, 4),
 413         F(19200000, P_XO, 1, 0, 0),
 414         F(24000000, P_GPLL0, 12.5, 1, 2),
 415         F(27906976, P_GPLL0, 1, 2, 43),
 416         F(41380000, P_GPLL0, 15, 0, 0),
 417         F(42860000, P_GPLL0, 14, 0, 0),
 418         { }
 419 };
 420
 421 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 422         .cmd_rcgr = 0x08cc,
 423         .mnd_width = 8,
 424         .hid_width = 5,
 425         .parent_map = gcc_xo_gpll0_map,
 426         .freq_tbl = ftbl_blsp1_qup6_spi_apps_clk_src,
 427         .clkr.hw.init = &(struct clk_init_data){
 428                 .name = "blsp1_qup6_spi_apps_clk_src",
 429                 .parent_data = gcc_xo_gpll0,
 430                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 431                 .ops = &clk_rcg2_ops,
 432         },
 433 };
 434
 435 static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
 436         F(3686400, P_GPLL0, 1, 96, 15625),
 437         F(7372800, P_GPLL0, 1, 192, 15625),
 438         F(14745600, P_GPLL0, 1, 384, 15625),
 439         F(16000000, P_GPLL0, 5, 2, 15),
 440         F(19200000, P_XO, 1, 0, 0),
 441         F(24000000, P_GPLL0, 5, 1, 5),
 442         F(32000000, P_GPLL0, 1, 4, 75),
 443         F(40000000, P_GPLL0, 15, 0, 0),
 444         F(46400000, P_GPLL0, 1, 29, 375),
 445         F(48000000, P_GPLL0, 12.5, 0, 0),
 446         F(51200000, P_GPLL0, 1, 32, 375),
 447         F(56000000, P_GPLL0, 1, 7, 75),
 448         F(58982400, P_GPLL0, 1, 1536, 15625),
 449         F(60000000, P_GPLL0, 10, 0, 0),
 450         F(63160000, P_GPLL0, 9.5, 0, 0),
 451         { }
 452 };
 453
 454 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 455         .cmd_rcgr = 0x068c,
 456         .mnd_width = 16,
 457         .hid_width = 5,
 458         .parent_map = gcc_xo_gpll0_map,
 459         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 460         .clkr.hw.init = &(struct clk_init_data){
 461                 .name = "blsp1_uart1_apps_clk_src",
 462                 .parent_data = gcc_xo_gpll0,
 463                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 464                 .ops = &clk_rcg2_ops,
 465         },
 466 };
 467
 468 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 469         .cmd_rcgr = 0x070c,
 470         .mnd_width = 16,
 471         .hid_width = 5,
 472         .parent_map = gcc_xo_gpll0_map,
 473         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 474         .clkr.hw.init = &(struct clk_init_data){
 475                 .name = "blsp1_uart2_apps_clk_src",
 476                 .parent_data = gcc_xo_gpll0,
 477                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 478                 .ops = &clk_rcg2_ops,
 479         },
 480 };
 481
 482 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 483         .cmd_rcgr = 0x078c,
 484         .mnd_width = 16,
 485         .hid_width = 5,
 486         .parent_map = gcc_xo_gpll0_map,
 487         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 488         .clkr.hw.init = &(struct clk_init_data){
 489                 .name = "blsp1_uart3_apps_clk_src",
 490                 .parent_data = gcc_xo_gpll0,
 491                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 492                 .ops = &clk_rcg2_ops,
 493         },
 494 };
 495
 496 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 497         .cmd_rcgr = 0x080c,
 498         .mnd_width = 16,
 499         .hid_width = 5,
 500         .parent_map = gcc_xo_gpll0_map,
 501         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 502         .clkr.hw.init = &(struct clk_init_data){
 503                 .name = "blsp1_uart4_apps_clk_src",
 504                 .parent_data = gcc_xo_gpll0,
 505                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 506                 .ops = &clk_rcg2_ops,
 507         },
 508 };
 509
 510 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 511         .cmd_rcgr = 0x088c,
 512         .mnd_width = 16,
 513         .hid_width = 5,
 514         .parent_map = gcc_xo_gpll0_map,
 515         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 516         .clkr.hw.init = &(struct clk_init_data){
 517                 .name = "blsp1_uart5_apps_clk_src",
 518                 .parent_data = gcc_xo_gpll0,
 519                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 520                 .ops = &clk_rcg2_ops,
 521         },
 522 };
 523
 524 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 525         .cmd_rcgr = 0x090c,
 526         .mnd_width = 16,
 527         .hid_width = 5,
 528         .parent_map = gcc_xo_gpll0_map,
 529         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 530         .clkr.hw.init = &(struct clk_init_data){
 531                 .name = "blsp1_uart6_apps_clk_src",
 532                 .parent_data = gcc_xo_gpll0,
 533                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 534                 .ops = &clk_rcg2_ops,
 535         },
 536 };
 537
 538 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 539         .cmd_rcgr = 0x09a0,
 540         .hid_width = 5,
 541         .parent_map = gcc_xo_gpll0_map,
 542         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 543         .clkr.hw.init = &(struct clk_init_data){
 544                 .name = "blsp2_qup1_i2c_apps_clk_src",
 545                 .parent_data = gcc_xo_gpll0,
 546                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 547                 .ops = &clk_rcg2_ops,
 548         },
 549 };
 550
 551 static struct freq_tbl ftbl_blsp2_qup1_2_spi_apps_clk_src[] = {
 552         F(960000, P_XO, 10, 1, 2),
 553         F(4800000, P_XO, 4, 0, 0),
 554         F(9600000, P_XO, 2, 0, 0),
 555         F(15000000, P_GPLL0, 10, 1, 4),
 556         F(19200000, P_XO, 1, 0, 0),
 557         F(24000000, P_GPLL0, 12.5, 1, 2),
 558         F(25000000, P_GPLL0, 12, 1, 2),
 559         F(42860000, P_GPLL0, 14, 0, 0),
 560         F(44440000, P_GPLL0, 13.5, 0, 0),
 561         { }
 562 };
 563
 564 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 565         .cmd_rcgr = 0x098c,
 566         .mnd_width = 8,
 567         .hid_width = 5,
 568         .parent_map = gcc_xo_gpll0_map,
 569         .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src,
 570         .clkr.hw.init = &(struct clk_init_data){
 571                 .name = "blsp2_qup1_spi_apps_clk_src",
 572                 .parent_data = gcc_xo_gpll0,
 573                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 574                 .ops = &clk_rcg2_ops,
 575         },
 576 };
 577
 578 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 579         .cmd_rcgr = 0x0a20,
 580         .hid_width = 5,
 581         .parent_map = gcc_xo_gpll0_map,
 582         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 583         .clkr.hw.init = &(struct clk_init_data){
 584                 .name = "blsp2_qup2_i2c_apps_clk_src",
 585                 .parent_data = gcc_xo_gpll0,
 586                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 587                 .ops = &clk_rcg2_ops,
 588         },
 589 };
 590
 591 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 592         .cmd_rcgr = 0x0a0c,
 593         .mnd_width = 8,
 594         .hid_width = 5,
 595         .parent_map = gcc_xo_gpll0_map,
 596         .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src,
 597         .clkr.hw.init = &(struct clk_init_data){
 598                 .name = "blsp2_qup2_spi_apps_clk_src",
 599                 .parent_data = gcc_xo_gpll0,
 600                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 601                 .ops = &clk_rcg2_ops,
 602         },
 603 };
 604
 605 static struct freq_tbl ftbl_blsp2_qup3_4_spi_apps_clk_src[] = {
 606         F(960000, P_XO, 10, 1, 2),
 607         F(4800000, P_XO, 4, 0, 0),
 608         F(9600000, P_XO, 2, 0, 0),
 609         F(15000000, P_GPLL0, 10, 1, 4),
 610         F(19200000, P_XO, 1, 0, 0),
 611         F(24000000, P_GPLL0, 12.5, 1, 2),
 612         F(25000000, P_GPLL0, 12, 1, 2),
 613         F(42860000, P_GPLL0, 14, 0, 0),
 614         F(48000000, P_GPLL0, 12.5, 0, 0),
 615         { }
 616 };
 617
 618 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 619         .cmd_rcgr = 0x0aa0,
 620         .hid_width = 5,
 621         .parent_map = gcc_xo_gpll0_map,
 622         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 623         .clkr.hw.init = &(struct clk_init_data){
 624                 .name = "blsp2_qup3_i2c_apps_clk_src",
 625                 .parent_data = gcc_xo_gpll0,
 626                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 627                 .ops = &clk_rcg2_ops,
 628         },
 629 };
 630
 631 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 632         .cmd_rcgr = 0x0a8c,
 633         .mnd_width = 8,
 634         .hid_width = 5,
 635         .parent_map = gcc_xo_gpll0_map,
 636         .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src,
 637         .clkr.hw.init = &(struct clk_init_data){
 638                 .name = "blsp2_qup3_spi_apps_clk_src",
 639                 .parent_data = gcc_xo_gpll0,
 640                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 641                 .ops = &clk_rcg2_ops,
 642         },
 643 };
 644
 645 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 646         .cmd_rcgr = 0x0b20,
 647         .hid_width = 5,
 648         .parent_map = gcc_xo_gpll0_map,
 649         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 650         .clkr.hw.init = &(struct clk_init_data){
 651                 .name = "blsp2_qup4_i2c_apps_clk_src",
 652                 .parent_data = gcc_xo_gpll0,
 653                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 654                 .ops = &clk_rcg2_ops,
 655         },
 656 };
 657
 658 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 659         .cmd_rcgr = 0x0b0c,
 660         .mnd_width = 8,
 661         .hid_width = 5,
 662         .parent_map = gcc_xo_gpll0_map,
 663         .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src,
 664         .clkr.hw.init = &(struct clk_init_data){
 665                 .name = "blsp2_qup4_spi_apps_clk_src",
 666                 .parent_data = gcc_xo_gpll0,
 667                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 668                 .ops = &clk_rcg2_ops,
 669         },
 670 };
 671
 672 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 673         .cmd_rcgr = 0x0ba0,
 674         .hid_width = 5,
 675         .parent_map = gcc_xo_gpll0_map,
 676         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 677         .clkr.hw.init = &(struct clk_init_data){
 678                 .name = "blsp2_qup5_i2c_apps_clk_src",
 679                 .parent_data = gcc_xo_gpll0,
 680                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 681                 .ops = &clk_rcg2_ops,
 682         },
 683 };
 684
 685 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 686         .cmd_rcgr = 0x0b8c,
 687         .mnd_width = 8,
 688         .hid_width = 5,
 689         .parent_map = gcc_xo_gpll0_map,
 690         /* BLSP1 QUP1 and BLSP2 QUP5 use the same freqs */
 691         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 692         .clkr.hw.init = &(struct clk_init_data){
 693                 .name = "blsp2_qup5_spi_apps_clk_src",
 694                 .parent_data = gcc_xo_gpll0,
 695                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 696                 .ops = &clk_rcg2_ops,
 697         },
 698 };
 699
 700 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
 701         .cmd_rcgr = 0x0c20,
 702         .hid_width = 5,
 703         .parent_map = gcc_xo_gpll0_map,
 704         .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
 705         .clkr.hw.init = &(struct clk_init_data){
 706                 .name = "blsp2_qup6_i2c_apps_clk_src",
 707                 .parent_data = gcc_xo_gpll0,
 708                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 709                 .ops = &clk_rcg2_ops,
 710         },
 711 };
 712
 713 static struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = {
 714         F(960000, P_XO, 10, 1, 2),
 715         F(4800000, P_XO, 4, 0, 0),
 716         F(9600000, P_XO, 2, 0, 0),
 717         F(15000000, P_GPLL0, 10, 1, 4),
 718         F(19200000, P_XO, 1, 0, 0),
 719         F(24000000, P_GPLL0, 12.5, 1, 2),
 720         F(25000000, P_GPLL0, 12, 1, 2),
 721         F(44440000, P_GPLL0, 13.5, 0, 0),
 722         F(48000000, P_GPLL0, 12.5, 0, 0),
 723         { }
 724 };
 725
 726 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
 727         .cmd_rcgr = 0x0c0c,
 728         .mnd_width = 8,
 729         .hid_width = 5,
 730         .parent_map = gcc_xo_gpll0_map,
 731         .freq_tbl = ftbl_blsp2_qup6_spi_apps_clk_src,
 732         .clkr.hw.init = &(struct clk_init_data){
 733                 .name = "blsp2_qup6_spi_apps_clk_src",
 734                 .parent_data = gcc_xo_gpll0,
 735                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 736                 .ops = &clk_rcg2_ops,
 737         },
 738 };
 739
 740 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 741         .cmd_rcgr = 0x09cc,
 742         .mnd_width = 16,
 743         .hid_width = 5,
 744         .parent_map = gcc_xo_gpll0_map,
 745         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 746         .clkr.hw.init = &(struct clk_init_data){
 747                 .name = "blsp2_uart1_apps_clk_src",
 748                 .parent_data = gcc_xo_gpll0,
 749                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 750                 .ops = &clk_rcg2_ops,
 751         },
 752 };
 753
 754 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 755         .cmd_rcgr = 0x0a4c,
 756         .mnd_width = 16,
 757         .hid_width = 5,
 758         .parent_map = gcc_xo_gpll0_map,
 759         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 760         .clkr.hw.init = &(struct clk_init_data){
 761                 .name = "blsp2_uart2_apps_clk_src",
 762                 .parent_data = gcc_xo_gpll0,
 763                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 764                 .ops = &clk_rcg2_ops,
 765         },
 766 };
 767
 768 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 769         .cmd_rcgr = 0x0acc,
 770         .mnd_width = 16,
 771         .hid_width = 5,
 772         .parent_map = gcc_xo_gpll0_map,
 773         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 774         .clkr.hw.init = &(struct clk_init_data){
 775                 .name = "blsp2_uart3_apps_clk_src",
 776                 .parent_data = gcc_xo_gpll0,
 777                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 778                 .ops = &clk_rcg2_ops,
 779         },
 780 };
 781
 782 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
 783         .cmd_rcgr = 0x0b4c,
 784         .mnd_width = 16,
 785         .hid_width = 5,
 786         .parent_map = gcc_xo_gpll0_map,
 787         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 788         .clkr.hw.init = &(struct clk_init_data){
 789                 .name = "blsp2_uart4_apps_clk_src",
 790                 .parent_data = gcc_xo_gpll0,
 791                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 792                 .ops = &clk_rcg2_ops,
 793         },
 794 };
 795
 796 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
 797         .cmd_rcgr = 0x0bcc,
 798         .mnd_width = 16,
 799         .hid_width = 5,
 800         .parent_map = gcc_xo_gpll0_map,
 801         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 802         .clkr.hw.init = &(struct clk_init_data){
 803                 .name = "blsp2_uart5_apps_clk_src",
 804                 .parent_data = gcc_xo_gpll0,
 805                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 806                 .ops = &clk_rcg2_ops,
 807         },
 808 };
 809
 810 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
 811         .cmd_rcgr = 0x0c4c,
 812         .mnd_width = 16,
 813         .hid_width = 5,
 814         .parent_map = gcc_xo_gpll0_map,
 815         .freq_tbl = ftbl_blsp_uart_apps_clk_src,
 816         .clkr.hw.init = &(struct clk_init_data){
 817                 .name = "blsp2_uart6_apps_clk_src",
 818                 .parent_data = gcc_xo_gpll0,
 819                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 820                 .ops = &clk_rcg2_ops,
 821         },
 822 };
 823
 824 static struct freq_tbl ftbl_gp1_clk_src[] = {
 825         F(19200000, P_XO, 1, 0, 0),
 826         F(100000000, P_GPLL0, 6, 0, 0),
 827         F(200000000, P_GPLL0, 3, 0, 0),
 828         { }
 829 };
 830
 831 static struct clk_rcg2 gp1_clk_src = {
 832         .cmd_rcgr = 0x1904,
 833         .mnd_width = 8,
 834         .hid_width = 5,
 835         .parent_map = gcc_xo_gpll0_map,
 836         .freq_tbl = ftbl_gp1_clk_src,
 837         .clkr.hw.init = &(struct clk_init_data){
 838                 .name = "gp1_clk_src",
 839                 .parent_data = gcc_xo_gpll0,
 840                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 841                 .ops = &clk_rcg2_ops,
 842         },
 843 };
 844
 845 static struct freq_tbl ftbl_gp2_clk_src[] = {
 846         F(19200000, P_XO, 1, 0, 0),
 847         F(100000000, P_GPLL0, 6, 0, 0),
 848         F(200000000, P_GPLL0, 3, 0, 0),
 849         { }
 850 };
 851
 852 static struct clk_rcg2 gp2_clk_src = {
 853         .cmd_rcgr = 0x1944,
 854         .mnd_width = 8,
 855         .hid_width = 5,
 856         .parent_map = gcc_xo_gpll0_map,
 857         .freq_tbl = ftbl_gp2_clk_src,
 858         .clkr.hw.init = &(struct clk_init_data){
 859                 .name = "gp2_clk_src",
 860                 .parent_data = gcc_xo_gpll0,
 861                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 862                 .ops = &clk_rcg2_ops,
 863         },
 864 };
 865
 866 static struct freq_tbl ftbl_gp3_clk_src[] = {
 867         F(19200000, P_XO, 1, 0, 0),
 868         F(100000000, P_GPLL0, 6, 0, 0),
 869         F(200000000, P_GPLL0, 3, 0, 0),
 870         { }
 871 };
 872
 873 static struct clk_rcg2 gp3_clk_src = {
 874         .cmd_rcgr = 0x1984,
 875         .mnd_width = 8,
 876         .hid_width = 5,
 877         .parent_map = gcc_xo_gpll0_map,
 878         .freq_tbl = ftbl_gp3_clk_src,
 879         .clkr.hw.init = &(struct clk_init_data){
 880                 .name = "gp3_clk_src",
 881                 .parent_data = gcc_xo_gpll0,
 882                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 883                 .ops = &clk_rcg2_ops,
 884         },
 885 };
 886
 887 static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
 888         F(1011000, P_XO, 1, 1, 19),
 889         { }
 890 };
 891
 892 static struct clk_rcg2 pcie_0_aux_clk_src = {
 893         .cmd_rcgr = 0x1b00,
 894         .mnd_width = 8,
 895         .hid_width = 5,
 896         .freq_tbl = ftbl_pcie_0_aux_clk_src,
 897         .clkr.hw.init = &(struct clk_init_data){
 898                 .name = "pcie_0_aux_clk_src",
 899                 .parent_data = &(const struct clk_parent_data){
 900                                 .fw_name = "xo",
 901                 },
 902                 .num_parents = 1,
 903                 .ops = &clk_rcg2_ops,
 904         },
 905 };
 906
 907 static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
 908         F(125000000, P_XO, 1, 0, 0),
 909         { }
 910 };
 911
 912 static struct clk_rcg2 pcie_0_pipe_clk_src = {
 913         .cmd_rcgr = 0x1adc,
 914         .hid_width = 5,
 915         .freq_tbl = ftbl_pcie_pipe_clk_src,
 916         .clkr.hw.init = &(struct clk_init_data){
 917                 .name = "pcie_0_pipe_clk_src",
 918                 .parent_data = &(const struct clk_parent_data){
 919                                 .fw_name = "xo",
 920                 },
 921                 .num_parents = 1,
 922                 .ops = &clk_rcg2_ops,
 923         },
 924 };
 925
 926 static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
 927         F(1011000, P_XO, 1, 1, 19),
 928         { }
 929 };
 930
 931 static struct clk_rcg2 pcie_1_aux_clk_src = {
 932         .cmd_rcgr = 0x1b80,
 933         .mnd_width = 8,
 934         .hid_width = 5,
 935         .freq_tbl = ftbl_pcie_1_aux_clk_src,
 936         .clkr.hw.init = &(struct clk_init_data){
 937                 .name = "pcie_1_aux_clk_src",
 938                 .parent_data = &(const struct clk_parent_data){
 939                                 .fw_name = "xo",
 940                 },
 941                 .num_parents = 1,
 942                 .ops = &clk_rcg2_ops,
 943         },
 944 };
 945
 946 static struct clk_rcg2 pcie_1_pipe_clk_src = {
 947         .cmd_rcgr = 0x1b5c,
 948         .hid_width = 5,
 949         .freq_tbl = ftbl_pcie_pipe_clk_src,
 950         .clkr.hw.init = &(struct clk_init_data){
 951                 .name = "pcie_1_pipe_clk_src",
 952                 .parent_data = &(const struct clk_parent_data){
 953                                 .fw_name = "xo",
 954                 },
 955                 .num_parents = 1,
 956                 .ops = &clk_rcg2_ops,
 957         },
 958 };
 959
 960 static struct freq_tbl ftbl_pdm2_clk_src[] = {
 961         F(60000000, P_GPLL0, 10, 0, 0),
 962         { }
 963 };
 964
 965 static struct clk_rcg2 pdm2_clk_src = {
 966         .cmd_rcgr = 0x0cd0,
 967         .hid_width = 5,
 968         .parent_map = gcc_xo_gpll0_map,
 969         .freq_tbl = ftbl_pdm2_clk_src,
 970         .clkr.hw.init = &(struct clk_init_data){
 971                 .name = "pdm2_clk_src",
 972                 .parent_data = gcc_xo_gpll0,
 973                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 974                 .ops = &clk_rcg2_ops,
 975         },
 976 };
 977
 978 static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
 979         F(144000, P_XO, 16, 3, 25),
 980         F(400000, P_XO, 12, 1, 4),
 981         F(20000000, P_GPLL0, 15, 1, 2),
 982         F(25000000, P_GPLL0, 12, 1, 2),
 983         F(50000000, P_GPLL0, 12, 0, 0),
 984         F(100000000, P_GPLL0, 6, 0, 0),
 985         F(192000000, P_GPLL4, 2, 0, 0),
 986         F(384000000, P_GPLL4, 1, 0, 0),
 987         { }
 988 };
 989
 990 static struct freq_tbl ftbl_sdcc1_apps_clk_src_8992[] = {
 991         F(144000, P_XO, 16, 3, 25),
 992         F(400000, P_XO, 12, 1, 4),
 993         F(20000000, P_GPLL0, 15, 1, 2),
 994         F(25000000, P_GPLL0, 12, 1, 2),
 995         F(50000000, P_GPLL0, 12, 0, 0),
 996         F(100000000, P_GPLL0, 6, 0, 0),
 997         F(172000000, P_GPLL4, 2, 0, 0),
 998         F(344000000, P_GPLL4, 1, 0, 0),
 999         { }
1000 };
1001
1002 static struct clk_rcg2 sdcc1_apps_clk_src = {
1003         .cmd_rcgr = 0x04d0,
1004         .mnd_width = 8,
1005         .hid_width = 5,
1006         .parent_map = gcc_xo_gpll0_gpll4_map,
1007         .freq_tbl = ftbl_sdcc1_apps_clk_src,
1008         .clkr.hw.init = &(struct clk_init_data){
1009                 .name = "sdcc1_apps_clk_src",
1010                 .parent_data = gcc_xo_gpll0_gpll4,
1011                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1012                 .ops = &clk_rcg2_floor_ops,
1013         },
1014 };
1015
1016 static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
1017         F(144000, P_XO, 16, 3, 25),
1018         F(400000, P_XO, 12, 1, 4),
1019         F(20000000, P_GPLL0, 15, 1, 2),
1020         F(25000000, P_GPLL0, 12, 1, 2),
1021         F(50000000, P_GPLL0, 12, 0, 0),
1022         F(100000000, P_GPLL0, 6, 0, 0),
1023         F(200000000, P_GPLL0, 3, 0, 0),
1024         { }
1025 };
1026
1027 static struct clk_rcg2 sdcc2_apps_clk_src = {
1028         .cmd_rcgr = 0x0510,
1029         .mnd_width = 8,
1030         .hid_width = 5,
1031         .parent_map = gcc_xo_gpll0_map,
1032         .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
1033         .clkr.hw.init = &(struct clk_init_data){
1034                 .name = "sdcc2_apps_clk_src",
1035                 .parent_data = gcc_xo_gpll0,
1036                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1037                 .ops = &clk_rcg2_floor_ops,
1038         },
1039 };
1040
1041 static struct clk_rcg2 sdcc3_apps_clk_src = {
1042         .cmd_rcgr = 0x0550,
1043         .mnd_width = 8,
1044         .hid_width = 5,
1045         .parent_map = gcc_xo_gpll0_map,
1046         .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
1047         .clkr.hw.init = &(struct clk_init_data){
1048                 .name = "sdcc3_apps_clk_src",
1049                 .parent_data = gcc_xo_gpll0,
1050                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1051                 .ops = &clk_rcg2_floor_ops,
1052         },
1053 };
1054
1055 static struct clk_rcg2 sdcc4_apps_clk_src = {
1056         .cmd_rcgr = 0x0590,
1057         .mnd_width = 8,
1058         .hid_width = 5,
1059         .parent_map = gcc_xo_gpll0_map,
1060         .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
1061         .clkr.hw.init = &(struct clk_init_data){
1062                 .name = "sdcc4_apps_clk_src",
1063                 .parent_data = gcc_xo_gpll0,
1064                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1065                 .ops = &clk_rcg2_floor_ops,
1066         },
1067 };
1068
1069 static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1070         F(105500, P_XO, 1, 1, 182),
1071         { }
1072 };
1073
1074 static struct clk_rcg2 tsif_ref_clk_src = {
1075         .cmd_rcgr = 0x0d90,
1076         .mnd_width = 8,
1077         .hid_width = 5,
1078         .freq_tbl = ftbl_tsif_ref_clk_src,
1079         .clkr.hw.init = &(struct clk_init_data){
1080                 .name = "tsif_ref_clk_src",
1081                 .parent_data = &(const struct clk_parent_data){
1082                                 .fw_name = "xo",
1083                 },
1084                 .num_parents = 1,
1085                 .ops = &clk_rcg2_ops,
1086         },
1087 };
1088
1089 static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
1090         F(19200000, P_XO, 1, 0, 0),
1091         F(60000000, P_GPLL0, 10, 0, 0),
1092         { }
1093 };
1094
1095 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1096         .cmd_rcgr = 0x03e8,
1097         .hid_width = 5,
1098         .parent_map = gcc_xo_gpll0_map,
1099         .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1100         .clkr.hw.init = &(struct clk_init_data){
1101                 .name = "usb30_mock_utmi_clk_src",
1102                 .parent_data = gcc_xo_gpll0,
1103                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1104                 .ops = &clk_rcg2_ops,
1105         },
1106 };
1107
1108 static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
1109         F(1200000, P_XO, 16, 0, 0),
1110         { }
1111 };
1112
1113 static struct clk_rcg2 usb3_phy_aux_clk_src = {
1114         .cmd_rcgr = 0x1414,
1115         .hid_width = 5,
1116         .freq_tbl = ftbl_usb3_phy_aux_clk_src,
1117         .clkr.hw.init = &(struct clk_init_data){
1118                 .name = "usb3_phy_aux_clk_src",
1119                 .parent_data = &(const struct clk_parent_data){
1120                                 .fw_name = "xo",
1121                 },
1122                 .num_parents = 1,
1123                 .ops = &clk_rcg2_ops,
1124         },
1125 };
1126
1127 static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1128         F(75000000, P_GPLL0, 8, 0, 0),
1129         { }
1130 };
1131
1132 static struct clk_rcg2 usb_hs_system_clk_src = {
1133         .cmd_rcgr = 0x0490,
1134         .hid_width = 5,
1135         .parent_map = gcc_xo_gpll0_map,
1136         .freq_tbl = ftbl_usb_hs_system_clk_src,
1137         .clkr.hw.init = &(struct clk_init_data){
1138                 .name = "usb_hs_system_clk_src",
1139                 .parent_data = gcc_xo_gpll0,
1140                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1141                 .ops = &clk_rcg2_ops,
1142         },
1143 };
1144
1145 static struct clk_branch gcc_blsp1_ahb_clk = {
1146         .halt_reg = 0x05c4,
1147         .halt_check = BRANCH_HALT_VOTED,
1148         .clkr = {
1149                 .enable_reg = 0x1484,
1150                 .enable_mask = BIT(17),
1151                 .hw.init = &(struct clk_init_data){
1152                         .name = "gcc_blsp1_ahb_clk",
1153                         .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
1154                         .num_parents = 1,
1155                         .ops = &clk_branch2_ops,
1156                 },
1157         },
1158 };
1159
1160 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1161         .halt_reg = 0x0648,
1162         .clkr = {
1163                 .enable_reg = 0x0648,
1164                 .enable_mask = BIT(0),
1165                 .hw.init = &(struct clk_init_data){
1166                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1167                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
1168                         .num_parents = 1,
1169                         .flags = CLK_SET_RATE_PARENT,
1170                         .ops = &clk_branch2_ops,
1171                 },
1172         },
1173 };
1174
1175 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1176         .halt_reg = 0x0644,
1177         .clkr = {
1178                 .enable_reg = 0x0644,
1179                 .enable_mask = BIT(0),
1180                 .hw.init = &(struct clk_init_data){
1181                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1182                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw },
1183                         .num_parents = 1,
1184                         .flags = CLK_SET_RATE_PARENT,
1185                         .ops = &clk_branch2_ops,
1186                 },
1187         },
1188 };
1189
1190 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1191         .halt_reg = 0x06c8,
1192         .clkr = {
1193                 .enable_reg = 0x06c8,
1194                 .enable_mask = BIT(0),
1195                 .hw.init = &(struct clk_init_data){
1196                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1197                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
1198                         .num_parents = 1,
1199                         .flags = CLK_SET_RATE_PARENT,
1200                         .ops = &clk_branch2_ops,
1201                 },
1202         },
1203 };
1204
1205 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1206         .halt_reg = 0x06c4,
1207         .clkr = {
1208                 .enable_reg = 0x06c4,
1209                 .enable_mask = BIT(0),
1210                 .hw.init = &(struct clk_init_data){
1211                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1212                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw },
1213                         .num_parents = 1,
1214                         .flags = CLK_SET_RATE_PARENT,
1215                         .ops = &clk_branch2_ops,
1216                 },
1217         },
1218 };
1219
1220 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1221         .halt_reg = 0x0748,
1222         .clkr = {
1223                 .enable_reg = 0x0748,
1224                 .enable_mask = BIT(0),
1225                 .hw.init = &(struct clk_init_data){
1226                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1227                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
1228                         .num_parents = 1,
1229                         .flags = CLK_SET_RATE_PARENT,
1230                         .ops = &clk_branch2_ops,
1231                 },
1232         },
1233 };
1234
1235 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1236         .halt_reg = 0x0744,
1237         .clkr = {
1238                 .enable_reg = 0x0744,
1239                 .enable_mask = BIT(0),
1240                 .hw.init = &(struct clk_init_data){
1241                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1242                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw },
1243                         .num_parents = 1,
1244                         .flags = CLK_SET_RATE_PARENT,
1245                         .ops = &clk_branch2_ops,
1246                 },
1247         },
1248 };
1249
1250 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1251         .halt_reg = 0x07c8,
1252         .clkr = {
1253                 .enable_reg = 0x07c8,
1254                 .enable_mask = BIT(0),
1255                 .hw.init = &(struct clk_init_data){
1256                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1257                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
1258                         .num_parents = 1,
1259                         .flags = CLK_SET_RATE_PARENT,
1260                         .ops = &clk_branch2_ops,
1261                 },
1262         },
1263 };
1264
1265 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1266         .halt_reg = 0x07c4,
1267         .clkr = {
1268                 .enable_reg = 0x07c4,
1269                 .enable_mask = BIT(0),
1270                 .hw.init = &(struct clk_init_data){
1271                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1272                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw },
1273                         .num_parents = 1,
1274                         .flags = CLK_SET_RATE_PARENT,
1275                         .ops = &clk_branch2_ops,
1276                 },
1277         },
1278 };
1279
1280 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1281         .halt_reg = 0x0848,
1282         .clkr = {
1283                 .enable_reg = 0x0848,
1284                 .enable_mask = BIT(0),
1285                 .hw.init = &(struct clk_init_data){
1286                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
1287                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
1288                         .num_parents = 1,
1289                         .flags = CLK_SET_RATE_PARENT,
1290                         .ops = &clk_branch2_ops,
1291                 },
1292         },
1293 };
1294
1295 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1296         .halt_reg = 0x0844,
1297         .clkr = {
1298                 .enable_reg = 0x0844,
1299                 .enable_mask = BIT(0),
1300                 .hw.init = &(struct clk_init_data){
1301                         .name = "gcc_blsp1_qup5_spi_apps_clk",
1302                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw },
1303                         .num_parents = 1,
1304                         .flags = CLK_SET_RATE_PARENT,
1305                         .ops = &clk_branch2_ops,
1306                 },
1307         },
1308 };
1309
1310 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1311         .halt_reg = 0x08c8,
1312         .clkr = {
1313                 .enable_reg = 0x08c8,
1314                 .enable_mask = BIT(0),
1315                 .hw.init = &(struct clk_init_data){
1316                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
1317                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
1318                         .num_parents = 1,
1319                         .flags = CLK_SET_RATE_PARENT,
1320                         .ops = &clk_branch2_ops,
1321                 },
1322         },
1323 };
1324
1325 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1326         .halt_reg = 0x08c4,
1327         .clkr = {
1328                 .enable_reg = 0x08c4,
1329                 .enable_mask = BIT(0),
1330                 .hw.init = &(struct clk_init_data){
1331                         .name = "gcc_blsp1_qup6_spi_apps_clk",
1332                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw },
1333                         .num_parents = 1,
1334                         .flags = CLK_SET_RATE_PARENT,
1335                         .ops = &clk_branch2_ops,
1336                 },
1337         },
1338 };
1339
1340 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1341         .halt_reg = 0x0684,
1342         .clkr = {
1343                 .enable_reg = 0x0684,
1344                 .enable_mask = BIT(0),
1345                 .hw.init = &(struct clk_init_data){
1346                         .name = "gcc_blsp1_uart1_apps_clk",
1347                         .parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw },
1348                         .num_parents = 1,
1349                         .flags = CLK_SET_RATE_PARENT,
1350                         .ops = &clk_branch2_ops,
1351                 },
1352         },
1353 };
1354
1355 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1356         .halt_reg = 0x0704,
1357         .clkr = {
1358                 .enable_reg = 0x0704,
1359                 .enable_mask = BIT(0),
1360                 .hw.init = &(struct clk_init_data){
1361                         .name = "gcc_blsp1_uart2_apps_clk",
1362                         .parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw },
1363                         .num_parents = 1,
1364                         .flags = CLK_SET_RATE_PARENT,
1365                         .ops = &clk_branch2_ops,
1366                 },
1367         },
1368 };
1369
1370 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1371         .halt_reg = 0x0784,
1372         .clkr = {
1373                 .enable_reg = 0x0784,
1374                 .enable_mask = BIT(0),
1375                 .hw.init = &(struct clk_init_data){
1376                         .name = "gcc_blsp1_uart3_apps_clk",
1377                         .parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw },
1378                         .num_parents = 1,
1379                         .flags = CLK_SET_RATE_PARENT,
1380                         .ops = &clk_branch2_ops,
1381                 },
1382         },
1383 };
1384
1385 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1386         .halt_reg = 0x0804,
1387         .clkr = {
1388                 .enable_reg = 0x0804,
1389                 .enable_mask = BIT(0),
1390                 .hw.init = &(struct clk_init_data){
1391                         .name = "gcc_blsp1_uart4_apps_clk",
1392                         .parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw },
1393                         .num_parents = 1,
1394                         .flags = CLK_SET_RATE_PARENT,
1395                         .ops = &clk_branch2_ops,
1396                 },
1397         },
1398 };
1399
1400 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1401         .halt_reg = 0x0884,
1402         .clkr = {
1403                 .enable_reg = 0x0884,
1404                 .enable_mask = BIT(0),
1405                 .hw.init = &(struct clk_init_data){
1406                         .name = "gcc_blsp1_uart5_apps_clk",
1407                         .parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw },
1408                         .num_parents = 1,
1409                         .flags = CLK_SET_RATE_PARENT,
1410                         .ops = &clk_branch2_ops,
1411                 },
1412         },
1413 };
1414
1415 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1416         .halt_reg = 0x0904,
1417         .clkr = {
1418                 .enable_reg = 0x0904,
1419                 .enable_mask = BIT(0),
1420                 .hw.init = &(struct clk_init_data){
1421                         .name = "gcc_blsp1_uart6_apps_clk",
1422                         .parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw },
1423                         .num_parents = 1,
1424                         .flags = CLK_SET_RATE_PARENT,
1425                         .ops = &clk_branch2_ops,
1426                 },
1427         },
1428 };
1429
1430 static struct clk_branch gcc_blsp2_ahb_clk = {
1431         .halt_reg = 0x0944,
1432         .halt_check = BRANCH_HALT_VOTED,
1433         .clkr = {
1434                 .enable_reg = 0x1484,
1435                 .enable_mask = BIT(15),
1436                 .hw.init = &(struct clk_init_data){
1437                         .name = "gcc_blsp2_ahb_clk",
1438                         .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
1439                         .num_parents = 1,
1440                         .ops = &clk_branch2_ops,
1441                 },
1442         },
1443 };
1444
1445 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1446         .halt_reg = 0x0988,
1447         .clkr = {
1448                 .enable_reg = 0x0988,
1449                 .enable_mask = BIT(0),
1450                 .hw.init = &(struct clk_init_data){
1451                         .name = "gcc_blsp2_qup1_i2c_apps_clk",
1452                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_i2c_apps_clk_src.clkr.hw },
1453                         .num_parents = 1,
1454                         .flags = CLK_SET_RATE_PARENT,
1455                         .ops = &clk_branch2_ops,
1456                 },
1457         },
1458 };
1459
1460 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1461         .halt_reg = 0x0984,
1462         .clkr = {
1463                 .enable_reg = 0x0984,
1464                 .enable_mask = BIT(0),
1465                 .hw.init = &(struct clk_init_data){
1466                         .name = "gcc_blsp2_qup1_spi_apps_clk",
1467                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_spi_apps_clk_src.clkr.hw },
1468                         .num_parents = 1,
1469                         .flags = CLK_SET_RATE_PARENT,
1470                         .ops = &clk_branch2_ops,
1471                 },
1472         },
1473 };
1474
1475 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1476         .halt_reg = 0x0a08,
1477         .clkr = {
1478                 .enable_reg = 0x0a08,
1479                 .enable_mask = BIT(0),
1480                 .hw.init = &(struct clk_init_data){
1481                         .name = "gcc_blsp2_qup2_i2c_apps_clk",
1482                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_i2c_apps_clk_src.clkr.hw },
1483                         .num_parents = 1,
1484                         .flags = CLK_SET_RATE_PARENT,
1485                         .ops = &clk_branch2_ops,
1486                 },
1487         },
1488 };
1489
1490 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1491         .halt_reg = 0x0a04,
1492         .clkr = {
1493                 .enable_reg = 0x0a04,
1494                 .enable_mask = BIT(0),
1495                 .hw.init = &(struct clk_init_data){
1496                         .name = "gcc_blsp2_qup2_spi_apps_clk",
1497                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_spi_apps_clk_src.clkr.hw },
1498                         .num_parents = 1,
1499                         .flags = CLK_SET_RATE_PARENT,
1500                         .ops = &clk_branch2_ops,
1501                 },
1502         },
1503 };
1504
1505 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1506         .halt_reg = 0x0a88,
1507         .clkr = {
1508                 .enable_reg = 0x0a88,
1509                 .enable_mask = BIT(0),
1510                 .hw.init = &(struct clk_init_data){
1511                         .name = "gcc_blsp2_qup3_i2c_apps_clk",
1512                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_i2c_apps_clk_src.clkr.hw },
1513                         .num_parents = 1,
1514                         .flags = CLK_SET_RATE_PARENT,
1515                         .ops = &clk_branch2_ops,
1516                 },
1517         },
1518 };
1519
1520 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1521         .halt_reg = 0x0a84,
1522         .clkr = {
1523                 .enable_reg = 0x0a84,
1524                 .enable_mask = BIT(0),
1525                 .hw.init = &(struct clk_init_data){
1526                         .name = "gcc_blsp2_qup3_spi_apps_clk",
1527                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_spi_apps_clk_src.clkr.hw },
1528                         .num_parents = 1,
1529                         .flags = CLK_SET_RATE_PARENT,
1530                         .ops = &clk_branch2_ops,
1531                 },
1532         },
1533 };
1534
1535 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1536         .halt_reg = 0x0b08,
1537         .clkr = {
1538                 .enable_reg = 0x0b08,
1539                 .enable_mask = BIT(0),
1540                 .hw.init = &(struct clk_init_data){
1541                         .name = "gcc_blsp2_qup4_i2c_apps_clk",
1542                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_i2c_apps_clk_src.clkr.hw },
1543                         .num_parents = 1,
1544                         .flags = CLK_SET_RATE_PARENT,
1545                         .ops = &clk_branch2_ops,
1546                 },
1547         },
1548 };
1549
1550 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1551         .halt_reg = 0x0b04,
1552         .clkr = {
1553                 .enable_reg = 0x0b04,
1554                 .enable_mask = BIT(0),
1555                 .hw.init = &(struct clk_init_data){
1556                         .name = "gcc_blsp2_qup4_spi_apps_clk",
1557                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_spi_apps_clk_src.clkr.hw },
1558                         .num_parents = 1,
1559                         .flags = CLK_SET_RATE_PARENT,
1560                         .ops = &clk_branch2_ops,
1561                 },
1562         },
1563 };
1564
1565 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1566         .halt_reg = 0x0b88,
1567         .clkr = {
1568                 .enable_reg = 0x0b88,
1569                 .enable_mask = BIT(0),
1570                 .hw.init = &(struct clk_init_data){
1571                         .name = "gcc_blsp2_qup5_i2c_apps_clk",
1572                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_i2c_apps_clk_src.clkr.hw },
1573                         .num_parents = 1,
1574                         .flags = CLK_SET_RATE_PARENT,
1575                         .ops = &clk_branch2_ops,
1576                 },
1577         },
1578 };
1579
1580 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1581         .halt_reg = 0x0b84,
1582         .clkr = {
1583                 .enable_reg = 0x0b84,
1584                 .enable_mask = BIT(0),
1585                 .hw.init = &(struct clk_init_data){
1586                         .name = "gcc_blsp2_qup5_spi_apps_clk",
1587                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_spi_apps_clk_src.clkr.hw },
1588                         .num_parents = 1,
1589                         .flags = CLK_SET_RATE_PARENT,
1590                         .ops = &clk_branch2_ops,
1591                 },
1592         },
1593 };
1594
1595 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1596         .halt_reg = 0x0c08,
1597         .clkr = {
1598                 .enable_reg = 0x0c08,
1599                 .enable_mask = BIT(0),
1600                 .hw.init = &(struct clk_init_data){
1601                         .name = "gcc_blsp2_qup6_i2c_apps_clk",
1602                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_i2c_apps_clk_src.clkr.hw },
1603                         .num_parents = 1,
1604                         .flags = CLK_SET_RATE_PARENT,
1605                         .ops = &clk_branch2_ops,
1606                 },
1607         },
1608 };
1609
1610 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1611         .halt_reg = 0x0c04,
1612         .clkr = {
1613                 .enable_reg = 0x0c04,
1614                 .enable_mask = BIT(0),
1615                 .hw.init = &(struct clk_init_data){
1616                         .name = "gcc_blsp2_qup6_spi_apps_clk",
1617                         .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_spi_apps_clk_src.clkr.hw },
1618                         .num_parents = 1,
1619                         .flags = CLK_SET_RATE_PARENT,
1620                         .ops = &clk_branch2_ops,
1621                 },
1622         },
1623 };
1624
1625 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1626         .halt_reg = 0x09c4,
1627         .clkr = {
1628                 .enable_reg = 0x09c4,
1629                 .enable_mask = BIT(0),
1630                 .hw.init = &(struct clk_init_data){
1631                         .name = "gcc_blsp2_uart1_apps_clk",
1632                         .parent_hws = (const struct clk_hw *[]){ &blsp2_uart1_apps_clk_src.clkr.hw },
1633                         .num_parents = 1,
1634                         .flags = CLK_SET_RATE_PARENT,
1635                         .ops = &clk_branch2_ops,
1636                 },
1637         },
1638 };
1639
1640 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1641         .halt_reg = 0x0a44,
1642         .clkr = {
1643                 .enable_reg = 0x0a44,
1644                 .enable_mask = BIT(0),
1645                 .hw.init = &(struct clk_init_data){
1646                         .name = "gcc_blsp2_uart2_apps_clk",
1647                         .parent_hws = (const struct clk_hw *[]){ &blsp2_uart2_apps_clk_src.clkr.hw },
1648                         .num_parents = 1,
1649                         .flags = CLK_SET_RATE_PARENT,
1650                         .ops = &clk_branch2_ops,
1651                 },
1652         },
1653 };
1654
1655 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1656         .halt_reg = 0x0ac4,
1657         .clkr = {
1658                 .enable_reg = 0x0ac4,
1659                 .enable_mask = BIT(0),
1660                 .hw.init = &(struct clk_init_data){
1661                         .name = "gcc_blsp2_uart3_apps_clk",
1662                         .parent_hws = (const struct clk_hw *[]){ &blsp2_uart3_apps_clk_src.clkr.hw },
1663                         .num_parents = 1,
1664                         .flags = CLK_SET_RATE_PARENT,
1665                         .ops = &clk_branch2_ops,
1666                 },
1667         },
1668 };
1669
1670 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1671         .halt_reg = 0x0b44,
1672         .clkr = {
1673                 .enable_reg = 0x0b44,
1674                 .enable_mask = BIT(0),
1675                 .hw.init = &(struct clk_init_data){
1676                         .name = "gcc_blsp2_uart4_apps_clk",
1677                         .parent_hws = (const struct clk_hw *[]){ &blsp2_uart4_apps_clk_src.clkr.hw },
1678                         .num_parents = 1,
1679                         .flags = CLK_SET_RATE_PARENT,
1680                         .ops = &clk_branch2_ops,
1681                 },
1682         },
1683 };
1684
1685 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1686         .halt_reg = 0x0bc4,
1687         .clkr = {
1688                 .enable_reg = 0x0bc4,
1689                 .enable_mask = BIT(0),
1690                 .hw.init = &(struct clk_init_data){
1691                         .name = "gcc_blsp2_uart5_apps_clk",
1692                         .parent_hws = (const struct clk_hw *[]){ &blsp2_uart5_apps_clk_src.clkr.hw },
1693                         .num_parents = 1,
1694                         .flags = CLK_SET_RATE_PARENT,
1695                         .ops = &clk_branch2_ops,
1696                 },
1697         },
1698 };
1699
1700 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1701         .halt_reg = 0x0c44,
1702         .clkr = {
1703                 .enable_reg = 0x0c44,
1704                 .enable_mask = BIT(0),
1705                 .hw.init = &(struct clk_init_data){
1706                         .name = "gcc_blsp2_uart6_apps_clk",
1707                         .parent_hws = (const struct clk_hw *[]){ &blsp2_uart6_apps_clk_src.clkr.hw },
1708                         .num_parents = 1,
1709                         .flags = CLK_SET_RATE_PARENT,
1710                         .ops = &clk_branch2_ops,
1711                 },
1712         },
1713 };
1714
1715 static struct clk_branch gcc_gp1_clk = {
1716         .halt_reg = 0x1900,
1717         .clkr = {
1718                 .enable_reg = 0x1900,
1719                 .enable_mask = BIT(0),
1720                 .hw.init = &(struct clk_init_data){
1721                         .name = "gcc_gp1_clk",
1722                         .parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw },
1723                         .num_parents = 1,
1724                         .flags = CLK_SET_RATE_PARENT,
1725                         .ops = &clk_branch2_ops,
1726                 },
1727         },
1728 };
1729
1730 static struct clk_branch gcc_gp2_clk = {
1731         .halt_reg = 0x1940,
1732         .clkr = {
1733                 .enable_reg = 0x1940,
1734                 .enable_mask = BIT(0),
1735                 .hw.init = &(struct clk_init_data){
1736                         .name = "gcc_gp2_clk",
1737                         .parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw },
1738                         .num_parents = 1,
1739                         .flags = CLK_SET_RATE_PARENT,
1740                         .ops = &clk_branch2_ops,
1741                 },
1742         },
1743 };
1744
1745 static struct clk_branch gcc_gp3_clk = {
1746         .halt_reg = 0x1980,
1747         .clkr = {
1748                 .enable_reg = 0x1980,
1749                 .enable_mask = BIT(0),
1750                 .hw.init = &(struct clk_init_data){
1751                         .name = "gcc_gp3_clk",
1752                         .parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw },
1753                         .num_parents = 1,
1754                         .flags = CLK_SET_RATE_PARENT,
1755                         .ops = &clk_branch2_ops,
1756                 },
1757         },
1758 };
1759
1760 static struct clk_branch gcc_lpass_q6_axi_clk = {
1761         .halt_reg = 0x0280,
1762         .clkr = {
1763                 .enable_reg = 0x0280,
1764                 .enable_mask = BIT(0),
1765                 .hw.init = &(struct clk_init_data){
1766                         .name = "gcc_lpass_q6_axi_clk",
1767                         .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
1768                         .num_parents = 1,
1769                         .ops = &clk_branch2_ops,
1770                 },
1771         },
1772 };
1773
1774 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
1775         .halt_reg = 0x0284,
1776         .clkr = {
1777                 .enable_reg = 0x0284,
1778                 .enable_mask = BIT(0),
1779                 .hw.init = &(struct clk_init_data){
1780                         .name = "gcc_mss_q6_bimc_axi_clk",
1781                         .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
1782                         .num_parents = 1,
1783                         .ops = &clk_branch2_ops,
1784                 },
1785         },
1786 };
1787
1788 static struct clk_branch gcc_pcie_0_aux_clk = {
1789         .halt_reg = 0x1ad4,
1790         .clkr = {
1791                 .enable_reg = 0x1ad4,
1792                 .enable_mask = BIT(0),
1793                 .hw.init = &(struct clk_init_data){
1794                         .name = "gcc_pcie_0_aux_clk",
1795                         .parent_hws = (const struct clk_hw *[]){ &pcie_0_aux_clk_src.clkr.hw },
1796                         .num_parents = 1,
1797                         .flags = CLK_SET_RATE_PARENT,
1798                         .ops = &clk_branch2_ops,
1799                 },
1800         },
1801 };
1802
1803 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1804         .halt_reg = 0x1ad0,
1805         .clkr = {
1806                 .enable_reg = 0x1ad0,
1807                 .enable_mask = BIT(0),
1808                 .hw.init = &(struct clk_init_data){
1809                         .name = "gcc_pcie_0_cfg_ahb_clk",
1810                         .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw },
1811                         .num_parents = 1,
1812                         .flags = CLK_SET_RATE_PARENT,
1813                         .ops = &clk_branch2_ops,
1814                 },
1815         },
1816 };
1817
1818 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1819         .halt_reg = 0x1acc,
1820         .clkr = {
1821                 .enable_reg = 0x1acc,
1822                 .enable_mask = BIT(0),
1823                 .hw.init = &(struct clk_init_data){
1824                         .name = "gcc_pcie_0_mstr_axi_clk",
1825                         .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
1826                         .num_parents = 1,
1827                         .flags = CLK_SET_RATE_PARENT,
1828                         .ops = &clk_branch2_ops,
1829                 },
1830         },
1831 };
1832
1833 static struct clk_branch gcc_pcie_0_pipe_clk = {
1834         .halt_reg = 0x1ad8,
1835         .halt_check = BRANCH_HALT_DELAY,
1836         .clkr = {
1837                 .enable_reg = 0x1ad8,
1838                 .enable_mask = BIT(0),
1839                 .hw.init = &(struct clk_init_data){
1840                         .name = "gcc_pcie_0_pipe_clk",
1841                         .parent_hws = (const struct clk_hw *[]){ &pcie_0_pipe_clk_src.clkr.hw },
1842                         .num_parents = 1,
1843                         .flags = CLK_SET_RATE_PARENT,
1844                         .ops = &clk_branch2_ops,
1845                 },
1846         },
1847 };
1848
1849 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1850         .halt_reg = 0x1ac8,
1851         .halt_check = BRANCH_HALT_DELAY,
1852         .clkr = {
1853                 .enable_reg = 0x1ac8,
1854                 .enable_mask = BIT(0),
1855                 .hw.init = &(struct clk_init_data){
1856                         .name = "gcc_pcie_0_slv_axi_clk",
1857                         .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
1858                         .num_parents = 1,
1859                         .flags = CLK_SET_RATE_PARENT,
1860                         .ops = &clk_branch2_ops,
1861                 },
1862         },
1863 };
1864
1865 static struct clk_branch gcc_pcie_1_aux_clk = {
1866         .halt_reg = 0x1b54,
1867         .clkr = {
1868                 .enable_reg = 0x1b54,
1869                 .enable_mask = BIT(0),
1870                 .hw.init = &(struct clk_init_data){
1871                         .name = "gcc_pcie_1_aux_clk",
1872                         .parent_hws = (const struct clk_hw *[]){ &pcie_1_aux_clk_src.clkr.hw },
1873                         .num_parents = 1,
1874                         .flags = CLK_SET_RATE_PARENT,
1875                         .ops = &clk_branch2_ops,
1876                 },
1877         },
1878 };
1879
1880 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1881         .halt_reg = 0x1b54,
1882         .clkr = {
1883                 .enable_reg = 0x1b54,
1884                 .enable_mask = BIT(0),
1885                 .hw.init = &(struct clk_init_data){
1886                         .name = "gcc_pcie_1_cfg_ahb_clk",
1887                         .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw },
1888                         .num_parents = 1,
1889                         .flags = CLK_SET_RATE_PARENT,
1890                         .ops = &clk_branch2_ops,
1891                 },
1892         },
1893 };
1894
1895 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1896         .halt_reg = 0x1b50,
1897         .clkr = {
1898                 .enable_reg = 0x1b50,
1899                 .enable_mask = BIT(0),
1900                 .hw.init = &(struct clk_init_data){
1901                         .name = "gcc_pcie_1_mstr_axi_clk",
1902                         .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
1903                         .num_parents = 1,
1904                         .flags = CLK_SET_RATE_PARENT,
1905                         .ops = &clk_branch2_ops,
1906                 },
1907         },
1908 };
1909
1910 static struct clk_branch gcc_pcie_1_pipe_clk = {
1911         .halt_reg = 0x1b58,
1912         .halt_check = BRANCH_HALT_DELAY,
1913         .clkr = {
1914                 .enable_reg = 0x1b58,
1915                 .enable_mask = BIT(0),
1916                 .hw.init = &(struct clk_init_data){
1917                         .name = "gcc_pcie_1_pipe_clk",
1918                         .parent_hws = (const struct clk_hw *[]){ &pcie_1_pipe_clk_src.clkr.hw },
1919                         .num_parents = 1,
1920                         .flags = CLK_SET_RATE_PARENT,
1921                         .ops = &clk_branch2_ops,
1922                 },
1923         },
1924 };
1925
1926 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1927         .halt_reg = 0x1b48,
1928         .clkr = {
1929                 .enable_reg = 0x1b48,
1930                 .enable_mask = BIT(0),
1931                 .hw.init = &(struct clk_init_data){
1932                         .name = "gcc_pcie_1_slv_axi_clk",
1933                         .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
1934                         .num_parents = 1,
1935                         .flags = CLK_SET_RATE_PARENT,
1936                         .ops = &clk_branch2_ops,
1937                 },
1938         },
1939 };
1940
1941 static struct clk_branch gcc_pdm2_clk = {
1942         .halt_reg = 0x0ccc,
1943         .clkr = {
1944                 .enable_reg = 0x0ccc,
1945                 .enable_mask = BIT(0),
1946                 .hw.init = &(struct clk_init_data){
1947                         .name = "gcc_pdm2_clk",
1948                         .parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw },
1949                         .num_parents = 1,
1950                         .flags = CLK_SET_RATE_PARENT,
1951                         .ops = &clk_branch2_ops,
1952                 },
1953         },
1954 };
1955
1956 static struct clk_branch gcc_pdm_ahb_clk = {
1957         .halt_reg = 0x0cc4,
1958         .clkr = {
1959                 .enable_reg = 0x0cc4,
1960                 .enable_mask = BIT(0),
1961                 .hw.init = &(struct clk_init_data){
1962                         .name = "gcc_pdm_ahb_clk",
1963                         .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
1964                         .num_parents = 1,
1965                         .ops = &clk_branch2_ops,
1966                 },
1967         },
1968 };
1969
1970 static struct clk_branch gcc_sdcc1_apps_clk = {
1971         .halt_reg = 0x04c4,
1972         .clkr = {
1973                 .enable_reg = 0x04c4,
1974                 .enable_mask = BIT(0),
1975                 .hw.init = &(struct clk_init_data){
1976                         .name = "gcc_sdcc1_apps_clk",
1977                         .parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw },
1978                         .num_parents = 1,
1979                         .flags = CLK_SET_RATE_PARENT,
1980                         .ops = &clk_branch2_ops,
1981                 },
1982         },
1983 };
1984
1985 static struct clk_branch gcc_sdcc1_ahb_clk = {
1986         .halt_reg = 0x04c8,
1987         .clkr = {
1988                 .enable_reg = 0x04c8,
1989                 .enable_mask = BIT(0),
1990                 .hw.init = &(struct clk_init_data){
1991                         .name = "gcc_sdcc1_ahb_clk",
1992                         .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
1993                         .num_parents = 1,
1994                         .flags = CLK_SET_RATE_PARENT,
1995                         .ops = &clk_branch2_ops,
1996                 },
1997         },
1998 };
1999
2000 static struct clk_branch gcc_sdcc2_ahb_clk = {
2001         .halt_reg = 0x0508,
2002         .clkr = {
2003                 .enable_reg = 0x0508,
2004                 .enable_mask = BIT(0),
2005                 .hw.init = &(struct clk_init_data){
2006                         .name = "gcc_sdcc2_ahb_clk",
2007                         .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
2008                         .num_parents = 1,
2009                         .flags = CLK_SET_RATE_PARENT,
2010                         .ops = &clk_branch2_ops,
2011                 },
2012         },
2013 };
2014
2015 static struct clk_branch gcc_sdcc2_apps_clk = {
2016         .halt_reg = 0x0504,
2017         .clkr = {
2018                 .enable_reg = 0x0504,
2019                 .enable_mask = BIT(0),
2020                 .hw.init = &(struct clk_init_data){
2021                         .name = "gcc_sdcc2_apps_clk",
2022                         .parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw },
2023                         .num_parents = 1,
2024                         .flags = CLK_SET_RATE_PARENT,
2025                         .ops = &clk_branch2_ops,
2026                 },
2027         },
2028 };
2029
2030 static struct clk_branch gcc_sdcc3_ahb_clk = {
2031         .halt_reg = 0x0548,
2032         .clkr = {
2033                 .enable_reg = 0x0548,
2034                 .enable_mask = BIT(0),
2035                 .hw.init = &(struct clk_init_data){
2036                         .name = "gcc_sdcc3_ahb_clk",
2037                         .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
2038                         .num_parents = 1,
2039                         .flags = CLK_SET_RATE_PARENT,
2040                         .ops = &clk_branch2_ops,
2041                 },
2042         },
2043 };
2044
2045 static struct clk_branch gcc_sdcc3_apps_clk = {
2046         .halt_reg = 0x0544,
2047         .clkr = {
2048                 .enable_reg = 0x0544,
2049                 .enable_mask = BIT(0),
2050                 .hw.init = &(struct clk_init_data){
2051                         .name = "gcc_sdcc3_apps_clk",
2052                         .parent_hws = (const struct clk_hw *[]){ &sdcc3_apps_clk_src.clkr.hw },
2053                         .num_parents = 1,
2054                         .flags = CLK_SET_RATE_PARENT,
2055                         .ops = &clk_branch2_ops,
2056                 },
2057         },
2058 };
2059
2060 static struct clk_branch gcc_sdcc4_ahb_clk = {
2061         .halt_reg = 0x0588,
2062         .clkr = {
2063                 .enable_reg = 0x0588,
2064                 .enable_mask = BIT(0),
2065                 .hw.init = &(struct clk_init_data){
2066                         .name = "gcc_sdcc4_ahb_clk",
2067                         .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
2068                         .num_parents = 1,
2069                         .flags = CLK_SET_RATE_PARENT,
2070                         .ops = &clk_branch2_ops,
2071                 },
2072         },
2073 };
2074
2075 static struct clk_branch gcc_sdcc4_apps_clk = {
2076         .halt_reg = 0x0584,
2077         .clkr = {
2078                 .enable_reg = 0x0584,
2079                 .enable_mask = BIT(0),
2080                 .hw.init = &(struct clk_init_data){
2081                         .name = "gcc_sdcc4_apps_clk",
2082                         .parent_hws = (const struct clk_hw *[]){ &sdcc4_apps_clk_src.clkr.hw },
2083                         .num_parents = 1,
2084                         .flags = CLK_SET_RATE_PARENT,
2085                         .ops = &clk_branch2_ops,
2086                 },
2087         },
2088 };
2089
2090 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
2091         .halt_reg = 0x1d7c,
2092         .clkr = {
2093                 .enable_reg = 0x1d7c,
2094                 .enable_mask = BIT(0),
2095                 .hw.init = &(struct clk_init_data){
2096                         .name = "gcc_sys_noc_ufs_axi_clk",
2097                         .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2098                         .num_parents = 1,
2099                         .flags = CLK_SET_RATE_PARENT,
2100                         .ops = &clk_branch2_ops,
2101                 },
2102         },
2103 };
2104
2105 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
2106         .halt_reg = 0x03fc,
2107         .clkr = {
2108                 .enable_reg = 0x03fc,
2109                 .enable_mask = BIT(0),
2110                 .hw.init = &(struct clk_init_data){
2111                         .name = "gcc_sys_noc_usb3_axi_clk",
2112                         .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw },
2113                         .num_parents = 1,
2114                         .flags = CLK_SET_RATE_PARENT,
2115                         .ops = &clk_branch2_ops,
2116                 },
2117         },
2118 };
2119
2120 static struct clk_branch gcc_tsif_ahb_clk = {
2121         .halt_reg = 0x0d84,
2122         .clkr = {
2123                 .enable_reg = 0x0d84,
2124                 .enable_mask = BIT(0),
2125                 .hw.init = &(struct clk_init_data){
2126                         .name = "gcc_tsif_ahb_clk",
2127                         .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
2128                         .num_parents = 1,
2129                         .ops = &clk_branch2_ops,
2130                 },
2131         },
2132 };
2133
2134 static struct clk_branch gcc_tsif_ref_clk = {
2135         .halt_reg = 0x0d88,
2136         .clkr = {
2137                 .enable_reg = 0x0d88,
2138                 .enable_mask = BIT(0),
2139                 .hw.init = &(struct clk_init_data){
2140                         .name = "gcc_tsif_ref_clk",
2141                         .parent_hws = (const struct clk_hw *[]){ &tsif_ref_clk_src.clkr.hw },
2142                         .num_parents = 1,
2143                         .flags = CLK_SET_RATE_PARENT,
2144                         .ops = &clk_branch2_ops,
2145                 },
2146         },
2147 };
2148
2149 static struct clk_branch gcc_ufs_ahb_clk = {
2150         .halt_reg = 0x1d4c,
2151         .clkr = {
2152                 .enable_reg = 0x1d4c,
2153                 .enable_mask = BIT(0),
2154                 .hw.init = &(struct clk_init_data){
2155                         .name = "gcc_ufs_ahb_clk",
2156                         .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw },
2157                         .num_parents = 1,
2158                         .ops = &clk_branch2_ops,
2159                 },
2160         },
2161 };
2162
2163 static struct clk_branch gcc_ufs_axi_clk = {
2164         .halt_reg = 0x1d48,
2165         .clkr = {
2166                 .enable_reg = 0x1d48,
2167                 .enable_mask = BIT(0),
2168                 .hw.init = &(struct clk_init_data){
2169                         .name = "gcc_ufs_axi_clk",
2170                         .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2171                         .num_parents = 1,
2172                         .flags = CLK_SET_RATE_PARENT,
2173                         .ops = &clk_branch2_ops,
2174                 },
2175         },
2176 };
2177
2178 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2179         .halt_reg = 0x1d54,
2180         .clkr = {
2181                 .enable_reg = 0x1d54,
2182                 .enable_mask = BIT(0),
2183                 .hw.init = &(struct clk_init_data){
2184                         .name = "gcc_ufs_rx_cfg_clk",
2185                         .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2186                         .num_parents = 1,
2187                         .flags = CLK_SET_RATE_PARENT,
2188                         .ops = &clk_branch2_ops,
2189                 },
2190         },
2191 };
2192
2193 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2194         .halt_reg = 0x1d60,
2195         .halt_check = BRANCH_HALT_DELAY,
2196         .clkr = {
2197                 .enable_reg = 0x1d60,
2198                 .enable_mask = BIT(0),
2199                 .hw.init = &(struct clk_init_data){
2200                         .name = "gcc_ufs_rx_symbol_0_clk",
2201                         .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
2202                         .num_parents = 1,
2203                         .ops = &clk_branch2_ops,
2204                 },
2205         },
2206 };
2207
2208 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2209         .halt_reg = 0x1d64,
2210         .halt_check = BRANCH_HALT_DELAY,
2211         .clkr = {
2212                 .enable_reg = 0x1d64,
2213                 .enable_mask = BIT(0),
2214                 .hw.init = &(struct clk_init_data){
2215                         .name = "gcc_ufs_rx_symbol_1_clk",
2216                         .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
2217                         .num_parents = 1,
2218                         .ops = &clk_branch2_ops,
2219                 },
2220         },
2221 };
2222
2223 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2224         .halt_reg = 0x1d50,
2225         .clkr = {
2226                 .enable_reg = 0x1d50,
2227                 .enable_mask = BIT(0),
2228                 .hw.init = &(struct clk_init_data){
2229                         .name = "gcc_ufs_tx_cfg_clk",
2230                         .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2231                         .num_parents = 1,
2232                         .flags = CLK_SET_RATE_PARENT,
2233                         .ops = &clk_branch2_ops,
2234                 },
2235         },
2236 };
2237
2238 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2239         .halt_reg = 0x1d58,
2240         .halt_check = BRANCH_HALT_DELAY,
2241         .clkr = {
2242                 .enable_reg = 0x1d58,
2243                 .enable_mask = BIT(0),
2244                 .hw.init = &(struct clk_init_data){
2245                         .name = "gcc_ufs_tx_symbol_0_clk",
2246                         .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
2247                         .num_parents = 1,
2248                         .ops = &clk_branch2_ops,
2249                 },
2250         },
2251 };
2252
2253 static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
2254         .halt_reg = 0x1d5c,
2255         .halt_check = BRANCH_HALT_DELAY,
2256         .clkr = {
2257                 .enable_reg = 0x1d5c,
2258                 .enable_mask = BIT(0),
2259                 .hw.init = &(struct clk_init_data){
2260                         .name = "gcc_ufs_tx_symbol_1_clk",
2261                         .parent_hws = (const struct clk_hw *[]){ &system_noc_clk_src.clkr.hw },
2262                         .num_parents = 1,
2263                         .ops = &clk_branch2_ops,
2264                 },
2265         },
2266 };
2267
2268 static struct clk_branch gcc_usb2_hs_phy_sleep_clk = {
2269         .halt_reg = 0x04ac,
2270         .clkr = {
2271                 .enable_reg = 0x04ac,
2272                 .enable_mask = BIT(0),
2273                 .hw.init = &(struct clk_init_data){
2274                         .name = "gcc_usb2_hs_phy_sleep_clk",
2275                         .parent_data = &(const struct clk_parent_data){
2276                                 .fw_name = "sleep",
2277                                 .name = "sleep"
2278                         },
2279                         .num_parents = 1,
2280                         .ops = &clk_branch2_ops,
2281                 },
2282         },
2283 };
2284
2285 static struct clk_branch gcc_usb30_master_clk = {
2286         .halt_reg = 0x03c8,
2287         .clkr = {
2288                 .enable_reg = 0x03c8,
2289                 .enable_mask = BIT(0),
2290                 .hw.init = &(struct clk_init_data){
2291                         .name = "gcc_usb30_master_clk",
2292                         .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw },
2293                         .num_parents = 1,
2294                         .flags = CLK_SET_RATE_PARENT,
2295                         .ops = &clk_branch2_ops,
2296                 },
2297         },
2298 };
2299
2300 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2301         .halt_reg = 0x03d0,
2302         .clkr = {
2303                 .enable_reg = 0x03d0,
2304                 .enable_mask = BIT(0),
2305                 .hw.init = &(struct clk_init_data){
2306                         .name = "gcc_usb30_mock_utmi_clk",
2307                         .parent_hws = (const struct clk_hw *[]){ &usb30_mock_utmi_clk_src.clkr.hw },
2308                         .num_parents = 1,
2309                         .flags = CLK_SET_RATE_PARENT,
2310                         .ops = &clk_branch2_ops,
2311                 },
2312         },
2313 };
2314
2315 static struct clk_branch gcc_usb30_sleep_clk = {
2316         .halt_reg = 0x03cc,
2317         .clkr = {
2318                 .enable_reg = 0x03cc,
2319                 .enable_mask = BIT(0),
2320                 .hw.init = &(struct clk_init_data){
2321                         .name = "gcc_usb30_sleep_clk",
2322                         .parent_data = &(const struct clk_parent_data){
2323                                 .fw_name = "sleep",
2324                                 .name = "sleep"
2325                         },
2326                         .num_parents = 1,
2327                         .ops = &clk_branch2_ops,
2328                 },
2329         },
2330 };
2331
2332 static struct clk_branch gcc_usb3_phy_aux_clk = {
2333         .halt_reg = 0x1408,
2334         .clkr = {
2335                 .enable_reg = 0x1408,
2336                 .enable_mask = BIT(0),
2337                 .hw.init = &(struct clk_init_data){
2338                         .name = "gcc_usb3_phy_aux_clk",
2339                         .parent_hws = (const struct clk_hw *[]){ &usb3_phy_aux_clk_src.clkr.hw },
2340                         .num_parents = 1,
2341                         .flags = CLK_SET_RATE_PARENT,
2342                         .ops = &clk_branch2_ops,
2343                 },
2344         },
2345 };
2346
2347 static struct clk_branch gcc_usb3_phy_pipe_clk = {
2348         .halt_reg = 0x140c,
2349         .halt_check = BRANCH_HALT_SKIP,
2350         .clkr = {
2351                 .enable_reg = 0x140c,
2352                 .enable_mask = BIT(0),
2353                 .hw.init = &(struct clk_init_data){
2354                         .name = "gcc_usb3_phy_pipe_clk",
2355                         .ops = &clk_branch2_ops,
2356                 },
2357         },
2358 };
2359
2360 static struct clk_branch gcc_usb_hs_ahb_clk = {
2361         .halt_reg = 0x0488,
2362         .clkr = {
2363                 .enable_reg = 0x0488,
2364                 .enable_mask = BIT(0),
2365                 .hw.init = &(struct clk_init_data){
2366                         .name = "gcc_usb_hs_ahb_clk",
2367                         .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
2368                         .num_parents = 1,
2369                         .ops = &clk_branch2_ops,
2370                 },
2371         },
2372 };
2373
2374 static struct clk_branch gcc_usb_hs_system_clk = {
2375         .halt_reg = 0x0484,
2376         .clkr = {
2377                 .enable_reg = 0x0484,
2378                 .enable_mask = BIT(0),
2379                 .hw.init = &(struct clk_init_data){
2380                         .name = "gcc_usb_hs_system_clk",
2381                         .parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw },
2382                         .num_parents = 1,
2383                         .flags = CLK_SET_RATE_PARENT,
2384                         .ops = &clk_branch2_ops,
2385                 },
2386         },
2387 };
2388
2389 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2390         .halt_reg = 0x1a84,
2391         .clkr = {
2392                 .enable_reg = 0x1a84,
2393                 .enable_mask = BIT(0),
2394                 .hw.init = &(struct clk_init_data){
2395                         .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2396                         .ops = &clk_branch2_ops,
2397                 },
2398         },
2399 };
2400
2401 static struct clk_branch gpll0_out_mmsscc = {
2402         .halt_check = BRANCH_HALT_DELAY,
2403         .clkr = {
2404                 .enable_reg = 0x1484,
2405                 .enable_mask = BIT(26),
2406                 .hw.init = &(struct clk_init_data){
2407                         .name = "gpll0_out_mmsscc",
2408                         .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
2409                         .num_parents = 1,
2410                         .ops = &clk_branch2_ops,
2411                 },
2412         },
2413 };
2414
2415 static struct clk_branch gpll0_out_msscc = {
2416         .halt_check = BRANCH_HALT_DELAY,
2417         .clkr = {
2418                 .enable_reg = 0x1484,
2419                 .enable_mask = BIT(27),
2420                 .hw.init = &(struct clk_init_data){
2421                         .name = "gpll0_out_msscc",
2422                         .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
2423                         .num_parents = 1,
2424                         .ops = &clk_branch2_ops,
2425                 },
2426         },
2427 };
2428
2429 static struct clk_branch pcie_0_phy_ldo = {
2430         .halt_reg = 0x1e00,
2431         .halt_check = BRANCH_HALT_SKIP,
2432         .clkr = {
2433                 .enable_reg = 0x1E00,
2434                 .enable_mask = BIT(0),
2435                 .hw.init = &(struct clk_init_data){
2436                         .name = "pcie_0_phy_ldo",
2437                         .ops = &clk_branch2_ops,
2438                 },
2439         },
2440 };
2441
2442 static struct clk_branch pcie_1_phy_ldo = {
2443         .halt_reg = 0x1e04,
2444         .halt_check = BRANCH_HALT_SKIP,
2445         .clkr = {
2446                 .enable_reg = 0x1E04,
2447                 .enable_mask = BIT(0),
2448                 .hw.init = &(struct clk_init_data){
2449                         .name = "pcie_1_phy_ldo",
2450                         .ops = &clk_branch2_ops,
2451                 },
2452         },
2453 };
2454
2455 static struct clk_branch ufs_phy_ldo = {
2456         .halt_reg = 0x1e0c,
2457         .halt_check = BRANCH_HALT_SKIP,
2458         .clkr = {
2459                 .enable_reg = 0x1E0C,
2460                 .enable_mask = BIT(0),
2461                 .hw.init = &(struct clk_init_data){
2462                         .name = "ufs_phy_ldo",
2463                         .ops = &clk_branch2_ops,
2464                 },
2465         },
2466 };
2467
2468 static struct clk_branch usb_ss_phy_ldo = {
2469         .halt_reg = 0x1e08,
2470         .halt_check = BRANCH_HALT_SKIP,
2471         .clkr = {
2472                 .enable_reg = 0x1E08,
2473                 .enable_mask = BIT(0),
2474                 .hw.init = &(struct clk_init_data){
2475                         .name = "usb_ss_phy_ldo",
2476                         .ops = &clk_branch2_ops,
2477                 },
2478         },
2479 };
2480
2481 static struct clk_branch gcc_boot_rom_ahb_clk = {
2482         .halt_reg = 0x0e04,
2483         .halt_check = BRANCH_HALT_VOTED,
2484         .hwcg_reg = 0x0e04,
2485         .hwcg_bit = 1,
2486         .clkr = {
2487                 .enable_reg = 0x1484,
2488                 .enable_mask = BIT(10),
2489                 .hw.init = &(struct clk_init_data){
2490                         .name = "gcc_boot_rom_ahb_clk",
2491                         .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw },
2492                         .num_parents = 1,
2493                         .ops = &clk_branch2_ops,
2494                 },
2495         },
2496 };
2497
2498 static struct clk_branch gcc_prng_ahb_clk = {
2499         .halt_reg = 0x0d04,
2500         .halt_check = BRANCH_HALT_VOTED,
2501         .clkr = {
2502                 .enable_reg = 0x1484,
2503                 .enable_mask = BIT(13),
2504                 .hw.init = &(struct clk_init_data){
2505                         .name = "gcc_prng_ahb_clk",
2506                         .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw },
2507                         .num_parents = 1,
2508                         .ops = &clk_branch2_ops,
2509                 },
2510         },
2511 };
2512
2513 static struct gdsc pcie_0_gdsc = {
2514                 .gdscr = 0x1ac4,
2515                 .pd = {
2516                         .name = "pcie_0",
2517                 },
2518                 .pwrsts = PWRSTS_OFF_ON,
2519 };
2520
2521 static struct gdsc pcie_1_gdsc = {
2522                 .gdscr = 0x1b44,
2523                 .pd = {
2524                         .name = "pcie_1",
2525                 },
2526                 .pwrsts = PWRSTS_OFF_ON,
2527 };
2528
2529 static struct gdsc usb30_gdsc = {
2530                 .gdscr = 0x3c4,
2531                 .pd = {
2532                         .name = "usb30",
2533                 },
2534                 .pwrsts = PWRSTS_OFF_ON,
2535 };
2536
2537 static struct gdsc ufs_gdsc = {
2538                 .gdscr = 0x1d44,
2539                 .pd = {
2540                         .name = "ufs",
2541                 },
2542                 .pwrsts = PWRSTS_OFF_ON,
2543 };
2544
2545 static struct clk_regmap *gcc_msm8994_clocks[] = {
2546         [GPLL0_EARLY] = &gpll0_early.clkr,
2547         [GPLL0] = &gpll0.clkr,
2548         [GPLL4_EARLY] = &gpll4_early.clkr,
2549         [GPLL4] = &gpll4.clkr,
2550         [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
2551         [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
2552         [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
2553         [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2554         [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2555         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2556         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2557         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2558         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2559         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2560         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2561         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2562         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2563         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2564         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2565         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2566         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2567         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2568         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2569         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2570         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2571         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2572         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2573         [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2574         [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2575         [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2576         [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2577         [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2578         [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2579         [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2580         [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2581         [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2582         [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2583         [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2584         [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2585         [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2586         [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2587         [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2588         [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2589         [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2590         [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2591         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2592         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2593         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2594         [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
2595         [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
2596         [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
2597         [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
2598         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2599         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2600         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2601         [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2602         [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2603         [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2604         [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2605         [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2606         [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2607         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2608         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2609         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2610         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2611         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2612         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2613         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2614         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2615         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2616         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2617         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2618         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2619         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2620         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2621         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2622         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2623         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2624         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2625         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2626         [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2627         [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2628         [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2629         [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2630         [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2631         [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2632         [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2633         [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2634         [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2635         [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2636         [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2637         [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2638         [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2639         [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2640         [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2641         [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2642         [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2643         [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2644         [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2645         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2646         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2647         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2648         [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
2649         [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
2650         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2651         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2652         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2653         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2654         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2655         [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
2656         [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
2657         [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
2658         [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
2659         [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
2660         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2661         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2662         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2663         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2664         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2665         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2666         [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
2667         [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2668         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2669         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2670         [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
2671         [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2672         [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2673         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2674         [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
2675         [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2676         [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
2677         [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
2678         [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
2679         [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
2680         [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
2681         [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr,
2682         [GCC_USB2_HS_PHY_SLEEP_CLK] = &gcc_usb2_hs_phy_sleep_clk.clkr,
2683         [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2684         [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2685         [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2686         [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2687         [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2688         [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
2689         [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2690         [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2691         [GPLL0_OUT_MMSSCC] = &gpll0_out_mmsscc.clkr,
2692         [GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr,
2693         [PCIE_0_PHY_LDO] = &pcie_0_phy_ldo.clkr,
2694         [PCIE_1_PHY_LDO] = &pcie_1_phy_ldo.clkr,
2695         [UFS_PHY_LDO] = &ufs_phy_ldo.clkr,
2696         [USB_SS_PHY_LDO] = &usb_ss_phy_ldo.clkr,
2697         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2698         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2699 };
2700
2701 static struct gdsc *gcc_msm8994_gdscs[] = {
2702         /* This GDSC does not exist, but ABI has to remain intact */
2703         [PCIE_GDSC] = NULL,
2704         [PCIE_0_GDSC] = &pcie_0_gdsc,
2705         [PCIE_1_GDSC] = &pcie_1_gdsc,
2706         [USB30_GDSC] = &usb30_gdsc,
2707         [UFS_GDSC] = &ufs_gdsc,
2708 };
2709
2710 static const struct qcom_reset_map gcc_msm8994_resets[] = {
2711         [USB3_PHY_RESET] = { 0x1400 },
2712         [USB3PHY_PHY_RESET] = { 0x1404 },
2713         [MSS_RESET] = { 0x1680 },
2714         [PCIE_PHY_0_RESET] = { 0x1b18 },
2715         [PCIE_PHY_1_RESET] = { 0x1b98 },
2716         [QUSB2_PHY_RESET] = { 0x04b8 },
2717 };
2718
2719 static const struct regmap_config gcc_msm8994_regmap_config = {
2720         .reg_bits       = 32,
2721         .reg_stride     = 4,
2722         .val_bits       = 32,
2723         .max_register   = 0x2000,
2724         .fast_io        = true,
2725 };
2726
2727 static const struct qcom_cc_desc gcc_msm8994_desc = {
2728         .config = &gcc_msm8994_regmap_config,
2729         .clks = gcc_msm8994_clocks,
2730         .num_clks = ARRAY_SIZE(gcc_msm8994_clocks),
2731         .resets = gcc_msm8994_resets,
2732         .num_resets = ARRAY_SIZE(gcc_msm8994_resets),
2733         .gdscs = gcc_msm8994_gdscs,
2734         .num_gdscs = ARRAY_SIZE(gcc_msm8994_gdscs),
2735 };
2736
2737 static const struct of_device_id gcc_msm8994_match_table[] = {
2738         { .compatible = "qcom,gcc-msm8992" },
2739         { .compatible = "qcom,gcc-msm8994" }, /* V2 and V2.1 */
2740         {}
2741 };
2742 MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
2743
2744 static int gcc_msm8994_probe(struct platform_device *pdev)
2745 {
2746         if (of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-msm8992")) {
2747                 /* MSM8992 features less clocks and some have different freq tables */
2748                 gcc_msm8994_desc.clks[UFS_AXI_CLK_SRC] = NULL;
2749                 gcc_msm8994_desc.clks[GCC_LPASS_Q6_AXI_CLK] = NULL;
2750                 gcc_msm8994_desc.clks[UFS_PHY_LDO] = NULL;
2751                 gcc_msm8994_desc.clks[GCC_UFS_AHB_CLK] = NULL;
2752                 gcc_msm8994_desc.clks[GCC_UFS_AXI_CLK] = NULL;
2753                 gcc_msm8994_desc.clks[GCC_UFS_RX_CFG_CLK] = NULL;
2754                 gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_0_CLK] = NULL;
2755                 gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_1_CLK] = NULL;
2756                 gcc_msm8994_desc.clks[GCC_UFS_TX_CFG_CLK] = NULL;
2757                 gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_0_CLK] = NULL;
2758                 gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_1_CLK] = NULL;
2759
2760                 sdcc1_apps_clk_src.freq_tbl = ftbl_sdcc1_apps_clk_src_8992;
2761                 blsp1_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2762                 blsp1_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2763                 blsp1_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2764                 blsp1_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2765                 blsp1_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2766                 blsp1_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2767                 blsp2_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2768                 blsp2_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2769                 blsp2_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2770                 blsp2_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2771                 blsp2_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2772                 blsp2_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2773
2774                 /*
2775                  * Some 8992 boards might *possibly* use
2776                  * PCIe1 clocks and controller, but it's not
2777                  * standard and they should be disabled otherwise.
2778                  */
2779                 gcc_msm8994_desc.clks[PCIE_1_AUX_CLK_SRC] = NULL;
2780                 gcc_msm8994_desc.clks[PCIE_1_PIPE_CLK_SRC] = NULL;
2781                 gcc_msm8994_desc.clks[PCIE_1_PHY_LDO] = NULL;
2782                 gcc_msm8994_desc.clks[GCC_PCIE_1_AUX_CLK] = NULL;
2783                 gcc_msm8994_desc.clks[GCC_PCIE_1_CFG_AHB_CLK] = NULL;
2784                 gcc_msm8994_desc.clks[GCC_PCIE_1_MSTR_AXI_CLK] = NULL;
2785                 gcc_msm8994_desc.clks[GCC_PCIE_1_PIPE_CLK] = NULL;
2786                 gcc_msm8994_desc.clks[GCC_PCIE_1_SLV_AXI_CLK] = NULL;
2787                 gcc_msm8994_desc.clks[GCC_SYS_NOC_UFS_AXI_CLK] = NULL;
2788         }
2789
2790         return qcom_cc_probe(pdev, &gcc_msm8994_desc);
2791 }
2792
2793 static struct platform_driver gcc_msm8994_driver = {
2794         .probe          = gcc_msm8994_probe,
2795         .driver         = {
2796                 .name   = "gcc-msm8994",
2797                 .of_match_table = gcc_msm8994_match_table,
2798         },
2799 };
2800
2801 static int __init gcc_msm8994_init(void)
2802 {
2803         return platform_driver_register(&gcc_msm8994_driver);
2804 }
2805 core_initcall(gcc_msm8994_init);
2806
2807 static void __exit gcc_msm8994_exit(void)
2808 {
2809         platform_driver_unregister(&gcc_msm8994_driver);
2810 }
2811 module_exit(gcc_msm8994_exit);
2812
2813 MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver");
2814 MODULE_LICENSE("GPL v2");
2815 MODULE_ALIAS("platform:gcc-msm8994");