drivers/clk/qcom/gcc-msm8974.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset-controller.h>
  16
  17 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
  18 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
  19
  20 #include "common.h"
  21 #include "clk-regmap.h"
  22 #include "clk-pll.h"
  23 #include "clk-rcg.h"
  24 #include "clk-branch.h"
  25 #include "reset.h"
  26 #include "gdsc.h"
  27
  28 enum {
  29         P_XO,
  30         P_GPLL0,
  31         P_GPLL1,
  32         P_GPLL4,
  33 };
  34
  35 static const struct parent_map gcc_xo_gpll0_map[] = {
  36         { P_XO, 0 },
  37         { P_GPLL0, 1 }
  38 };
  39
  40 static const char * const gcc_xo_gpll0[] = {
  41         "xo",
  42         "gpll0_vote",
  43 };
  44
  45 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
  46         { P_XO, 0 },
  47         { P_GPLL0, 1 },
  48         { P_GPLL4, 5 }
  49 };
  50
  51 static const char * const gcc_xo_gpll0_gpll4[] = {
  52         "xo",
  53         "gpll0_vote",
  54         "gpll4_vote",
  55 };
  56
  57 static struct clk_pll gpll0 = {
  58         .l_reg = 0x0004,
  59         .m_reg = 0x0008,
  60         .n_reg = 0x000c,
  61         .config_reg = 0x0014,
  62         .mode_reg = 0x0000,
  63         .status_reg = 0x001c,
  64         .status_bit = 17,
  65         .clkr.hw.init = &(struct clk_init_data){
  66                 .name = "gpll0",
  67                 .parent_names = (const char *[]){ "xo" },
  68                 .num_parents = 1,
  69                 .ops = &clk_pll_ops,
  70         },
  71 };
  72
  73 static struct clk_regmap gpll0_vote = {
  74         .enable_reg = 0x1480,
  75         .enable_mask = BIT(0),
  76         .hw.init = &(struct clk_init_data){
  77                 .name = "gpll0_vote",
  78                 .parent_names = (const char *[]){ "gpll0" },
  79                 .num_parents = 1,
  80                 .ops = &clk_pll_vote_ops,
  81         },
  82 };
  83
  84 static struct clk_rcg2 config_noc_clk_src = {
  85         .cmd_rcgr = 0x0150,
  86         .hid_width = 5,
  87         .parent_map = gcc_xo_gpll0_map,
  88         .clkr.hw.init = &(struct clk_init_data){
  89                 .name = "config_noc_clk_src",
  90                 .parent_names = gcc_xo_gpll0,
  91                 .num_parents = 2,
  92                 .ops = &clk_rcg2_ops,
  93         },
  94 };
  95
  96 static struct clk_rcg2 periph_noc_clk_src = {
  97         .cmd_rcgr = 0x0190,
  98         .hid_width = 5,
  99         .parent_map = gcc_xo_gpll0_map,
 100         .clkr.hw.init = &(struct clk_init_data){
 101                 .name = "periph_noc_clk_src",
 102                 .parent_names = gcc_xo_gpll0,
 103                 .num_parents = 2,
 104                 .ops = &clk_rcg2_ops,
 105         },
 106 };
 107
 108 static struct clk_rcg2 system_noc_clk_src = {
 109         .cmd_rcgr = 0x0120,
 110         .hid_width = 5,
 111         .parent_map = gcc_xo_gpll0_map,
 112         .clkr.hw.init = &(struct clk_init_data){
 113                 .name = "system_noc_clk_src",
 114                 .parent_names = gcc_xo_gpll0,
 115                 .num_parents = 2,
 116                 .ops = &clk_rcg2_ops,
 117         },
 118 };
 119
 120 static struct clk_pll gpll1 = {
 121         .l_reg = 0x0044,
 122         .m_reg = 0x0048,
 123         .n_reg = 0x004c,
 124         .config_reg = 0x0054,
 125         .mode_reg = 0x0040,
 126         .status_reg = 0x005c,
 127         .status_bit = 17,
 128         .clkr.hw.init = &(struct clk_init_data){
 129                 .name = "gpll1",
 130                 .parent_names = (const char *[]){ "xo" },
 131                 .num_parents = 1,
 132                 .ops = &clk_pll_ops,
 133         },
 134 };
 135
 136 static struct clk_regmap gpll1_vote = {
 137         .enable_reg = 0x1480,
 138         .enable_mask = BIT(1),
 139         .hw.init = &(struct clk_init_data){
 140                 .name = "gpll1_vote",
 141                 .parent_names = (const char *[]){ "gpll1" },
 142                 .num_parents = 1,
 143                 .ops = &clk_pll_vote_ops,
 144         },
 145 };
 146
 147 static struct clk_pll gpll4 = {
 148         .l_reg = 0x1dc4,
 149         .m_reg = 0x1dc8,
 150         .n_reg = 0x1dcc,
 151         .config_reg = 0x1dd4,
 152         .mode_reg = 0x1dc0,
 153         .status_reg = 0x1ddc,
 154         .status_bit = 17,
 155         .clkr.hw.init = &(struct clk_init_data){
 156                 .name = "gpll4",
 157                 .parent_names = (const char *[]){ "xo" },
 158                 .num_parents = 1,
 159                 .ops = &clk_pll_ops,
 160         },
 161 };
 162
 163 static struct clk_regmap gpll4_vote = {
 164         .enable_reg = 0x1480,
 165         .enable_mask = BIT(4),
 166         .hw.init = &(struct clk_init_data){
 167                 .name = "gpll4_vote",
 168                 .parent_names = (const char *[]){ "gpll4" },
 169                 .num_parents = 1,
 170                 .ops = &clk_pll_vote_ops,
 171         },
 172 };
 173
 174 static const struct freq_tbl ftbl_gcc_usb30_master_clk[] = {
 175         F(125000000, P_GPLL0, 1, 5, 24),
 176         { }
 177 };
 178
 179 static struct clk_rcg2 usb30_master_clk_src = {
 180         .cmd_rcgr = 0x03d4,
 181         .mnd_width = 8,
 182         .hid_width = 5,
 183         .parent_map = gcc_xo_gpll0_map,
 184         .freq_tbl = ftbl_gcc_usb30_master_clk,
 185         .clkr.hw.init = &(struct clk_init_data){
 186                 .name = "usb30_master_clk_src",
 187                 .parent_names = gcc_xo_gpll0,
 188                 .num_parents = 2,
 189                 .ops = &clk_rcg2_ops,
 190         },
 191 };
 192
 193 static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk[] = {
 194         F(19200000, P_XO, 1, 0, 0),
 195         F(37500000, P_GPLL0, 16, 0, 0),
 196         F(50000000, P_GPLL0, 12, 0, 0),
 197         { }
 198 };
 199
 200 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 201         .cmd_rcgr = 0x0660,
 202         .hid_width = 5,
 203         .parent_map = gcc_xo_gpll0_map,
 204         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 205         .clkr.hw.init = &(struct clk_init_data){
 206                 .name = "blsp1_qup1_i2c_apps_clk_src",
 207                 .parent_names = gcc_xo_gpll0,
 208                 .num_parents = 2,
 209                 .ops = &clk_rcg2_ops,
 210         },
 211 };
 212
 213 static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk[] = {
 214         F(960000, P_XO, 10, 1, 2),
 215         F(4800000, P_XO, 4, 0, 0),
 216         F(9600000, P_XO, 2, 0, 0),
 217         F(15000000, P_GPLL0, 10, 1, 4),
 218         F(19200000, P_XO, 1, 0, 0),
 219         F(25000000, P_GPLL0, 12, 1, 2),
 220         F(50000000, P_GPLL0, 12, 0, 0),
 221         { }
 222 };
 223
 224 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 225         .cmd_rcgr = 0x064c,
 226         .mnd_width = 8,
 227         .hid_width = 5,
 228         .parent_map = gcc_xo_gpll0_map,
 229         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 230         .clkr.hw.init = &(struct clk_init_data){
 231                 .name = "blsp1_qup1_spi_apps_clk_src",
 232                 .parent_names = gcc_xo_gpll0,
 233                 .num_parents = 2,
 234                 .ops = &clk_rcg2_ops,
 235         },
 236 };
 237
 238 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 239         .cmd_rcgr = 0x06e0,
 240         .hid_width = 5,
 241         .parent_map = gcc_xo_gpll0_map,
 242         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 243         .clkr.hw.init = &(struct clk_init_data){
 244                 .name = "blsp1_qup2_i2c_apps_clk_src",
 245                 .parent_names = gcc_xo_gpll0,
 246                 .num_parents = 2,
 247                 .ops = &clk_rcg2_ops,
 248         },
 249 };
 250
 251 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 252         .cmd_rcgr = 0x06cc,
 253         .mnd_width = 8,
 254         .hid_width = 5,
 255         .parent_map = gcc_xo_gpll0_map,
 256         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 257         .clkr.hw.init = &(struct clk_init_data){
 258                 .name = "blsp1_qup2_spi_apps_clk_src",
 259                 .parent_names = gcc_xo_gpll0,
 260                 .num_parents = 2,
 261                 .ops = &clk_rcg2_ops,
 262         },
 263 };
 264
 265 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 266         .cmd_rcgr = 0x0760,
 267         .hid_width = 5,
 268         .parent_map = gcc_xo_gpll0_map,
 269         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 270         .clkr.hw.init = &(struct clk_init_data){
 271                 .name = "blsp1_qup3_i2c_apps_clk_src",
 272                 .parent_names = gcc_xo_gpll0,
 273                 .num_parents = 2,
 274                 .ops = &clk_rcg2_ops,
 275         },
 276 };
 277
 278 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 279         .cmd_rcgr = 0x074c,
 280         .mnd_width = 8,
 281         .hid_width = 5,
 282         .parent_map = gcc_xo_gpll0_map,
 283         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 284         .clkr.hw.init = &(struct clk_init_data){
 285                 .name = "blsp1_qup3_spi_apps_clk_src",
 286                 .parent_names = gcc_xo_gpll0,
 287                 .num_parents = 2,
 288                 .ops = &clk_rcg2_ops,
 289         },
 290 };
 291
 292 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 293         .cmd_rcgr = 0x07e0,
 294         .hid_width = 5,
 295         .parent_map = gcc_xo_gpll0_map,
 296         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 297         .clkr.hw.init = &(struct clk_init_data){
 298                 .name = "blsp1_qup4_i2c_apps_clk_src",
 299                 .parent_names = gcc_xo_gpll0,
 300                 .num_parents = 2,
 301                 .ops = &clk_rcg2_ops,
 302         },
 303 };
 304
 305 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 306         .cmd_rcgr = 0x07cc,
 307         .mnd_width = 8,
 308         .hid_width = 5,
 309         .parent_map = gcc_xo_gpll0_map,
 310         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 311         .clkr.hw.init = &(struct clk_init_data){
 312                 .name = "blsp1_qup4_spi_apps_clk_src",
 313                 .parent_names = gcc_xo_gpll0,
 314                 .num_parents = 2,
 315                 .ops = &clk_rcg2_ops,
 316         },
 317 };
 318
 319 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 320         .cmd_rcgr = 0x0860,
 321         .hid_width = 5,
 322         .parent_map = gcc_xo_gpll0_map,
 323         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 324         .clkr.hw.init = &(struct clk_init_data){
 325                 .name = "blsp1_qup5_i2c_apps_clk_src",
 326                 .parent_names = gcc_xo_gpll0,
 327                 .num_parents = 2,
 328                 .ops = &clk_rcg2_ops,
 329         },
 330 };
 331
 332 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 333         .cmd_rcgr = 0x084c,
 334         .mnd_width = 8,
 335         .hid_width = 5,
 336         .parent_map = gcc_xo_gpll0_map,
 337         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 338         .clkr.hw.init = &(struct clk_init_data){
 339                 .name = "blsp1_qup5_spi_apps_clk_src",
 340                 .parent_names = gcc_xo_gpll0,
 341                 .num_parents = 2,
 342                 .ops = &clk_rcg2_ops,
 343         },
 344 };
 345
 346 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 347         .cmd_rcgr = 0x08e0,
 348         .hid_width = 5,
 349         .parent_map = gcc_xo_gpll0_map,
 350         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 351         .clkr.hw.init = &(struct clk_init_data){
 352                 .name = "blsp1_qup6_i2c_apps_clk_src",
 353                 .parent_names = gcc_xo_gpll0,
 354                 .num_parents = 2,
 355                 .ops = &clk_rcg2_ops,
 356         },
 357 };
 358
 359 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 360         .cmd_rcgr = 0x08cc,
 361         .mnd_width = 8,
 362         .hid_width = 5,
 363         .parent_map = gcc_xo_gpll0_map,
 364         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 365         .clkr.hw.init = &(struct clk_init_data){
 366                 .name = "blsp1_qup6_spi_apps_clk_src",
 367                 .parent_names = gcc_xo_gpll0,
 368                 .num_parents = 2,
 369                 .ops = &clk_rcg2_ops,
 370         },
 371 };
 372
 373 static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = {
 374         F(3686400, P_GPLL0, 1, 96, 15625),
 375         F(7372800, P_GPLL0, 1, 192, 15625),
 376         F(14745600, P_GPLL0, 1, 384, 15625),
 377         F(16000000, P_GPLL0, 5, 2, 15),
 378         F(19200000, P_XO, 1, 0, 0),
 379         F(24000000, P_GPLL0, 5, 1, 5),
 380         F(32000000, P_GPLL0, 1, 4, 75),
 381         F(40000000, P_GPLL0, 15, 0, 0),
 382         F(46400000, P_GPLL0, 1, 29, 375),
 383         F(48000000, P_GPLL0, 12.5, 0, 0),
 384         F(51200000, P_GPLL0, 1, 32, 375),
 385         F(56000000, P_GPLL0, 1, 7, 75),
 386         F(58982400, P_GPLL0, 1, 1536, 15625),
 387         F(60000000, P_GPLL0, 10, 0, 0),
 388         F(63160000, P_GPLL0, 9.5, 0, 0),
 389         { }
 390 };
 391
 392 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 393         .cmd_rcgr = 0x068c,
 394         .mnd_width = 16,
 395         .hid_width = 5,
 396         .parent_map = gcc_xo_gpll0_map,
 397         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 398         .clkr.hw.init = &(struct clk_init_data){
 399                 .name = "blsp1_uart1_apps_clk_src",
 400                 .parent_names = gcc_xo_gpll0,
 401                 .num_parents = 2,
 402                 .ops = &clk_rcg2_ops,
 403         },
 404 };
 405
 406 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 407         .cmd_rcgr = 0x070c,
 408         .mnd_width = 16,
 409         .hid_width = 5,
 410         .parent_map = gcc_xo_gpll0_map,
 411         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 412         .clkr.hw.init = &(struct clk_init_data){
 413                 .name = "blsp1_uart2_apps_clk_src",
 414                 .parent_names = gcc_xo_gpll0,
 415                 .num_parents = 2,
 416                 .ops = &clk_rcg2_ops,
 417         },
 418 };
 419
 420 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 421         .cmd_rcgr = 0x078c,
 422         .mnd_width = 16,
 423         .hid_width = 5,
 424         .parent_map = gcc_xo_gpll0_map,
 425         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 426         .clkr.hw.init = &(struct clk_init_data){
 427                 .name = "blsp1_uart3_apps_clk_src",
 428                 .parent_names = gcc_xo_gpll0,
 429                 .num_parents = 2,
 430                 .ops = &clk_rcg2_ops,
 431         },
 432 };
 433
 434 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 435         .cmd_rcgr = 0x080c,
 436         .mnd_width = 16,
 437         .hid_width = 5,
 438         .parent_map = gcc_xo_gpll0_map,
 439         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 440         .clkr.hw.init = &(struct clk_init_data){
 441                 .name = "blsp1_uart4_apps_clk_src",
 442                 .parent_names = gcc_xo_gpll0,
 443                 .num_parents = 2,
 444                 .ops = &clk_rcg2_ops,
 445         },
 446 };
 447
 448 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 449         .cmd_rcgr = 0x088c,
 450         .mnd_width = 16,
 451         .hid_width = 5,
 452         .parent_map = gcc_xo_gpll0_map,
 453         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 454         .clkr.hw.init = &(struct clk_init_data){
 455                 .name = "blsp1_uart5_apps_clk_src",
 456                 .parent_names = gcc_xo_gpll0,
 457                 .num_parents = 2,
 458                 .ops = &clk_rcg2_ops,
 459         },
 460 };
 461
 462 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 463         .cmd_rcgr = 0x090c,
 464         .mnd_width = 16,
 465         .hid_width = 5,
 466         .parent_map = gcc_xo_gpll0_map,
 467         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 468         .clkr.hw.init = &(struct clk_init_data){
 469                 .name = "blsp1_uart6_apps_clk_src",
 470                 .parent_names = gcc_xo_gpll0,
 471                 .num_parents = 2,
 472                 .ops = &clk_rcg2_ops,
 473         },
 474 };
 475
 476 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 477         .cmd_rcgr = 0x09a0,
 478         .hid_width = 5,
 479         .parent_map = gcc_xo_gpll0_map,
 480         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 481         .clkr.hw.init = &(struct clk_init_data){
 482                 .name = "blsp2_qup1_i2c_apps_clk_src",
 483                 .parent_names = gcc_xo_gpll0,
 484                 .num_parents = 2,
 485                 .ops = &clk_rcg2_ops,
 486         },
 487 };
 488
 489 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 490         .cmd_rcgr = 0x098c,
 491         .mnd_width = 8,
 492         .hid_width = 5,
 493         .parent_map = gcc_xo_gpll0_map,
 494         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 495         .clkr.hw.init = &(struct clk_init_data){
 496                 .name = "blsp2_qup1_spi_apps_clk_src",
 497                 .parent_names = gcc_xo_gpll0,
 498                 .num_parents = 2,
 499                 .ops = &clk_rcg2_ops,
 500         },
 501 };
 502
 503 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 504         .cmd_rcgr = 0x0a20,
 505         .hid_width = 5,
 506         .parent_map = gcc_xo_gpll0_map,
 507         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 508         .clkr.hw.init = &(struct clk_init_data){
 509                 .name = "blsp2_qup2_i2c_apps_clk_src",
 510                 .parent_names = gcc_xo_gpll0,
 511                 .num_parents = 2,
 512                 .ops = &clk_rcg2_ops,
 513         },
 514 };
 515
 516 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 517         .cmd_rcgr = 0x0a0c,
 518         .mnd_width = 8,
 519         .hid_width = 5,
 520         .parent_map = gcc_xo_gpll0_map,
 521         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 522         .clkr.hw.init = &(struct clk_init_data){
 523                 .name = "blsp2_qup2_spi_apps_clk_src",
 524                 .parent_names = gcc_xo_gpll0,
 525                 .num_parents = 2,
 526                 .ops = &clk_rcg2_ops,
 527         },
 528 };
 529
 530 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 531         .cmd_rcgr = 0x0aa0,
 532         .hid_width = 5,
 533         .parent_map = gcc_xo_gpll0_map,
 534         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 535         .clkr.hw.init = &(struct clk_init_data){
 536                 .name = "blsp2_qup3_i2c_apps_clk_src",
 537                 .parent_names = gcc_xo_gpll0,
 538                 .num_parents = 2,
 539                 .ops = &clk_rcg2_ops,
 540         },
 541 };
 542
 543 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 544         .cmd_rcgr = 0x0a8c,
 545         .mnd_width = 8,
 546         .hid_width = 5,
 547         .parent_map = gcc_xo_gpll0_map,
 548         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 549         .clkr.hw.init = &(struct clk_init_data){
 550                 .name = "blsp2_qup3_spi_apps_clk_src",
 551                 .parent_names = gcc_xo_gpll0,
 552                 .num_parents = 2,
 553                 .ops = &clk_rcg2_ops,
 554         },
 555 };
 556
 557 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 558         .cmd_rcgr = 0x0b20,
 559         .hid_width = 5,
 560         .parent_map = gcc_xo_gpll0_map,
 561         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 562         .clkr.hw.init = &(struct clk_init_data){
 563                 .name = "blsp2_qup4_i2c_apps_clk_src",
 564                 .parent_names = gcc_xo_gpll0,
 565                 .num_parents = 2,
 566                 .ops = &clk_rcg2_ops,
 567         },
 568 };
 569
 570 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 571         .cmd_rcgr = 0x0b0c,
 572         .mnd_width = 8,
 573         .hid_width = 5,
 574         .parent_map = gcc_xo_gpll0_map,
 575         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 576         .clkr.hw.init = &(struct clk_init_data){
 577                 .name = "blsp2_qup4_spi_apps_clk_src",
 578                 .parent_names = gcc_xo_gpll0,
 579                 .num_parents = 2,
 580                 .ops = &clk_rcg2_ops,
 581         },
 582 };
 583
 584 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 585         .cmd_rcgr = 0x0ba0,
 586         .hid_width = 5,
 587         .parent_map = gcc_xo_gpll0_map,
 588         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 589         .clkr.hw.init = &(struct clk_init_data){
 590                 .name = "blsp2_qup5_i2c_apps_clk_src",
 591                 .parent_names = gcc_xo_gpll0,
 592                 .num_parents = 2,
 593                 .ops = &clk_rcg2_ops,
 594         },
 595 };
 596
 597 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 598         .cmd_rcgr = 0x0b8c,
 599         .mnd_width = 8,
 600         .hid_width = 5,
 601         .parent_map = gcc_xo_gpll0_map,
 602         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 603         .clkr.hw.init = &(struct clk_init_data){
 604                 .name = "blsp2_qup5_spi_apps_clk_src",
 605                 .parent_names = gcc_xo_gpll0,
 606                 .num_parents = 2,
 607                 .ops = &clk_rcg2_ops,
 608         },
 609 };
 610
 611 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
 612         .cmd_rcgr = 0x0c20,
 613         .hid_width = 5,
 614         .parent_map = gcc_xo_gpll0_map,
 615         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk,
 616         .clkr.hw.init = &(struct clk_init_data){
 617                 .name = "blsp2_qup6_i2c_apps_clk_src",
 618                 .parent_names = gcc_xo_gpll0,
 619                 .num_parents = 2,
 620                 .ops = &clk_rcg2_ops,
 621         },
 622 };
 623
 624 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
 625         .cmd_rcgr = 0x0c0c,
 626         .mnd_width = 8,
 627         .hid_width = 5,
 628         .parent_map = gcc_xo_gpll0_map,
 629         .freq_tbl = ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk,
 630         .clkr.hw.init = &(struct clk_init_data){
 631                 .name = "blsp2_qup6_spi_apps_clk_src",
 632                 .parent_names = gcc_xo_gpll0,
 633                 .num_parents = 2,
 634                 .ops = &clk_rcg2_ops,
 635         },
 636 };
 637
 638 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 639         .cmd_rcgr = 0x09cc,
 640         .mnd_width = 16,
 641         .hid_width = 5,
 642         .parent_map = gcc_xo_gpll0_map,
 643         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 644         .clkr.hw.init = &(struct clk_init_data){
 645                 .name = "blsp2_uart1_apps_clk_src",
 646                 .parent_names = gcc_xo_gpll0,
 647                 .num_parents = 2,
 648                 .ops = &clk_rcg2_ops,
 649         },
 650 };
 651
 652 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 653         .cmd_rcgr = 0x0a4c,
 654         .mnd_width = 16,
 655         .hid_width = 5,
 656         .parent_map = gcc_xo_gpll0_map,
 657         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 658         .clkr.hw.init = &(struct clk_init_data){
 659                 .name = "blsp2_uart2_apps_clk_src",
 660                 .parent_names = gcc_xo_gpll0,
 661                 .num_parents = 2,
 662                 .ops = &clk_rcg2_ops,
 663         },
 664 };
 665
 666 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 667         .cmd_rcgr = 0x0acc,
 668         .mnd_width = 16,
 669         .hid_width = 5,
 670         .parent_map = gcc_xo_gpll0_map,
 671         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 672         .clkr.hw.init = &(struct clk_init_data){
 673                 .name = "blsp2_uart3_apps_clk_src",
 674                 .parent_names = gcc_xo_gpll0,
 675                 .num_parents = 2,
 676                 .ops = &clk_rcg2_ops,
 677         },
 678 };
 679
 680 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
 681         .cmd_rcgr = 0x0b4c,
 682         .mnd_width = 16,
 683         .hid_width = 5,
 684         .parent_map = gcc_xo_gpll0_map,
 685         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 686         .clkr.hw.init = &(struct clk_init_data){
 687                 .name = "blsp2_uart4_apps_clk_src",
 688                 .parent_names = gcc_xo_gpll0,
 689                 .num_parents = 2,
 690                 .ops = &clk_rcg2_ops,
 691         },
 692 };
 693
 694 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
 695         .cmd_rcgr = 0x0bcc,
 696         .mnd_width = 16,
 697         .hid_width = 5,
 698         .parent_map = gcc_xo_gpll0_map,
 699         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 700         .clkr.hw.init = &(struct clk_init_data){
 701                 .name = "blsp2_uart5_apps_clk_src",
 702                 .parent_names = gcc_xo_gpll0,
 703                 .num_parents = 2,
 704                 .ops = &clk_rcg2_ops,
 705         },
 706 };
 707
 708 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
 709         .cmd_rcgr = 0x0c4c,
 710         .mnd_width = 16,
 711         .hid_width = 5,
 712         .parent_map = gcc_xo_gpll0_map,
 713         .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
 714         .clkr.hw.init = &(struct clk_init_data){
 715                 .name = "blsp2_uart6_apps_clk_src",
 716                 .parent_names = gcc_xo_gpll0,
 717                 .num_parents = 2,
 718                 .ops = &clk_rcg2_ops,
 719         },
 720 };
 721
 722 static const struct freq_tbl ftbl_gcc_ce1_clk_msm8226[] = {
 723         F(50000000, P_GPLL0, 12, 0, 0),
 724         F(100000000, P_GPLL0, 6, 0, 0),
 725         { }
 726 };
 727
 728 static const struct freq_tbl ftbl_gcc_ce1_clk[] = {
 729         F(50000000, P_GPLL0, 12, 0, 0),
 730         F(75000000, P_GPLL0, 8, 0, 0),
 731         F(100000000, P_GPLL0, 6, 0, 0),
 732         F(150000000, P_GPLL0, 4, 0, 0),
 733         { }
 734 };
 735
 736 static struct clk_rcg2 ce1_clk_src = {
 737         .cmd_rcgr = 0x1050,
 738         .hid_width = 5,
 739         .parent_map = gcc_xo_gpll0_map,
 740         .freq_tbl = ftbl_gcc_ce1_clk,
 741         .clkr.hw.init = &(struct clk_init_data){
 742                 .name = "ce1_clk_src",
 743                 .parent_names = gcc_xo_gpll0,
 744                 .num_parents = 2,
 745                 .ops = &clk_rcg2_ops,
 746         },
 747 };
 748
 749 static const struct freq_tbl ftbl_gcc_ce2_clk[] = {
 750         F(50000000, P_GPLL0, 12, 0, 0),
 751         F(75000000, P_GPLL0, 8, 0, 0),
 752         F(100000000, P_GPLL0, 6, 0, 0),
 753         F(150000000, P_GPLL0, 4, 0, 0),
 754         { }
 755 };
 756
 757 static struct clk_rcg2 ce2_clk_src = {
 758         .cmd_rcgr = 0x1090,
 759         .hid_width = 5,
 760         .parent_map = gcc_xo_gpll0_map,
 761         .freq_tbl = ftbl_gcc_ce2_clk,
 762         .clkr.hw.init = &(struct clk_init_data){
 763                 .name = "ce2_clk_src",
 764                 .parent_names = gcc_xo_gpll0,
 765                 .num_parents = 2,
 766                 .ops = &clk_rcg2_ops,
 767         },
 768 };
 769
 770 static const struct freq_tbl ftbl_gcc_gp_clk_msm8226[] = {
 771         F(19200000, P_XO, 1, 0, 0),
 772         { }
 773 };
 774
 775 static const struct freq_tbl ftbl_gcc_gp_clk[] = {
 776         F(4800000, P_XO, 4, 0, 0),
 777         F(6000000, P_GPLL0, 10, 1, 10),
 778         F(6750000, P_GPLL0, 1, 1, 89),
 779         F(8000000, P_GPLL0, 15, 1, 5),
 780         F(9600000, P_XO, 2, 0, 0),
 781         F(16000000, P_GPLL0, 1, 2, 75),
 782         F(19200000, P_XO, 1, 0, 0),
 783         F(24000000, P_GPLL0, 5, 1, 5),
 784         { }
 785 };
 786
 787
 788 static struct clk_rcg2 gp1_clk_src = {
 789         .cmd_rcgr = 0x1904,
 790         .mnd_width = 8,
 791         .hid_width = 5,
 792         .parent_map = gcc_xo_gpll0_map,
 793         .freq_tbl = ftbl_gcc_gp_clk,
 794         .clkr.hw.init = &(struct clk_init_data){
 795                 .name = "gp1_clk_src",
 796                 .parent_names = gcc_xo_gpll0,
 797                 .num_parents = 2,
 798                 .ops = &clk_rcg2_ops,
 799         },
 800 };
 801
 802 static struct clk_rcg2 gp2_clk_src = {
 803         .cmd_rcgr = 0x1944,
 804         .mnd_width = 8,
 805         .hid_width = 5,
 806         .parent_map = gcc_xo_gpll0_map,
 807         .freq_tbl = ftbl_gcc_gp_clk,
 808         .clkr.hw.init = &(struct clk_init_data){
 809                 .name = "gp2_clk_src",
 810                 .parent_names = gcc_xo_gpll0,
 811                 .num_parents = 2,
 812                 .ops = &clk_rcg2_ops,
 813         },
 814 };
 815
 816 static struct clk_rcg2 gp3_clk_src = {
 817         .cmd_rcgr = 0x1984,
 818         .mnd_width = 8,
 819         .hid_width = 5,
 820         .parent_map = gcc_xo_gpll0_map,
 821         .freq_tbl = ftbl_gcc_gp_clk,
 822         .clkr.hw.init = &(struct clk_init_data){
 823                 .name = "gp3_clk_src",
 824                 .parent_names = gcc_xo_gpll0,
 825                 .num_parents = 2,
 826                 .ops = &clk_rcg2_ops,
 827         },
 828 };
 829
 830 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
 831         F(60000000, P_GPLL0, 10, 0, 0),
 832         { }
 833 };
 834
 835 static struct clk_rcg2 pdm2_clk_src = {
 836         .cmd_rcgr = 0x0cd0,
 837         .hid_width = 5,
 838         .parent_map = gcc_xo_gpll0_map,
 839         .freq_tbl = ftbl_gcc_pdm2_clk,
 840         .clkr.hw.init = &(struct clk_init_data){
 841                 .name = "pdm2_clk_src",
 842                 .parent_names = gcc_xo_gpll0,
 843                 .num_parents = 2,
 844                 .ops = &clk_rcg2_ops,
 845         },
 846 };
 847
 848 static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] = {
 849         F(144000, P_XO, 16, 3, 25),
 850         F(400000, P_XO, 12, 1, 4),
 851         F(20000000, P_GPLL0, 15, 1, 2),
 852         F(25000000, P_GPLL0, 12, 1, 2),
 853         F(50000000, P_GPLL0, 12, 0, 0),
 854         F(100000000, P_GPLL0, 6, 0, 0),
 855         F(200000000, P_GPLL0, 3, 0, 0),
 856         { }
 857 };
 858
 859 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_pro[] = {
 860         F(144000, P_XO, 16, 3, 25),
 861         F(400000, P_XO, 12, 1, 4),
 862         F(20000000, P_GPLL0, 15, 1, 2),
 863         F(25000000, P_GPLL0, 12, 1, 2),
 864         F(50000000, P_GPLL0, 12, 0, 0),
 865         F(100000000, P_GPLL0, 6, 0, 0),
 866         F(192000000, P_GPLL4, 4, 0, 0),
 867         F(200000000, P_GPLL0, 3, 0, 0),
 868         F(384000000, P_GPLL4, 2, 0, 0),
 869         { }
 870 };
 871
 872 static struct clk_init_data sdcc1_apps_clk_src_init = {
 873         .name = "sdcc1_apps_clk_src",
 874         .parent_names = gcc_xo_gpll0,
 875         .num_parents = 2,
 876         .ops = &clk_rcg2_floor_ops,
 877 };
 878
 879 static struct clk_rcg2 sdcc1_apps_clk_src = {
 880         .cmd_rcgr = 0x04d0,
 881         .mnd_width = 8,
 882         .hid_width = 5,
 883         .parent_map = gcc_xo_gpll0_map,
 884         .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
 885         .clkr.hw.init = &sdcc1_apps_clk_src_init,
 886 };
 887
 888 static struct clk_rcg2 sdcc2_apps_clk_src = {
 889         .cmd_rcgr = 0x0510,
 890         .mnd_width = 8,
 891         .hid_width = 5,
 892         .parent_map = gcc_xo_gpll0_map,
 893         .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
 894         .clkr.hw.init = &(struct clk_init_data){
 895                 .name = "sdcc2_apps_clk_src",
 896                 .parent_names = gcc_xo_gpll0,
 897                 .num_parents = 2,
 898                 .ops = &clk_rcg2_floor_ops,
 899         },
 900 };
 901
 902 static struct clk_rcg2 sdcc3_apps_clk_src = {
 903         .cmd_rcgr = 0x0550,
 904         .mnd_width = 8,
 905         .hid_width = 5,
 906         .parent_map = gcc_xo_gpll0_map,
 907         .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
 908         .clkr.hw.init = &(struct clk_init_data){
 909                 .name = "sdcc3_apps_clk_src",
 910                 .parent_names = gcc_xo_gpll0,
 911                 .num_parents = 2,
 912                 .ops = &clk_rcg2_floor_ops,
 913         },
 914 };
 915
 916 static struct clk_rcg2 sdcc4_apps_clk_src = {
 917         .cmd_rcgr = 0x0590,
 918         .mnd_width = 8,
 919         .hid_width = 5,
 920         .parent_map = gcc_xo_gpll0_map,
 921         .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
 922         .clkr.hw.init = &(struct clk_init_data){
 923                 .name = "sdcc4_apps_clk_src",
 924                 .parent_names = gcc_xo_gpll0,
 925                 .num_parents = 2,
 926                 .ops = &clk_rcg2_floor_ops,
 927         },
 928 };
 929
 930 static const struct freq_tbl ftbl_gcc_tsif_ref_clk[] = {
 931         F(105000, P_XO, 2, 1, 91),
 932         { }
 933 };
 934
 935 static struct clk_rcg2 tsif_ref_clk_src = {
 936         .cmd_rcgr = 0x0d90,
 937         .mnd_width = 8,
 938         .hid_width = 5,
 939         .parent_map = gcc_xo_gpll0_map,
 940         .freq_tbl = ftbl_gcc_tsif_ref_clk,
 941         .clkr.hw.init = &(struct clk_init_data){
 942                 .name = "tsif_ref_clk_src",
 943                 .parent_names = gcc_xo_gpll0,
 944                 .num_parents = 2,
 945                 .ops = &clk_rcg2_ops,
 946         },
 947 };
 948
 949 static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk[] = {
 950         F(60000000, P_GPLL0, 10, 0, 0),
 951         { }
 952 };
 953
 954 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
 955         .cmd_rcgr = 0x03e8,
 956         .hid_width = 5,
 957         .parent_map = gcc_xo_gpll0_map,
 958         .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk,
 959         .clkr.hw.init = &(struct clk_init_data){
 960                 .name = "usb30_mock_utmi_clk_src",
 961                 .parent_names = gcc_xo_gpll0,
 962                 .num_parents = 2,
 963                 .ops = &clk_rcg2_ops,
 964         },
 965 };
 966
 967 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
 968         F(60000000, P_GPLL0, 10, 0, 0),
 969         F(75000000, P_GPLL0, 8, 0, 0),
 970         { }
 971 };
 972
 973 static struct clk_rcg2 usb_hs_system_clk_src = {
 974         .cmd_rcgr = 0x0490,
 975         .hid_width = 5,
 976         .parent_map = gcc_xo_gpll0_map,
 977         .freq_tbl = ftbl_gcc_usb_hs_system_clk,
 978         .clkr.hw.init = &(struct clk_init_data){
 979                 .name = "usb_hs_system_clk_src",
 980                 .parent_names = gcc_xo_gpll0,
 981                 .num_parents = 2,
 982                 .ops = &clk_rcg2_ops,
 983         },
 984 };
 985
 986 static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
 987         F(480000000, P_GPLL1, 1, 0, 0),
 988         { }
 989 };
 990
 991 static const struct parent_map usb_hsic_clk_src_map[] = {
 992         { P_XO, 0 },
 993         { P_GPLL1, 4 }
 994 };
 995
 996 static struct clk_rcg2 usb_hsic_clk_src = {
 997         .cmd_rcgr = 0x0440,
 998         .hid_width = 5,
 999         .parent_map = usb_hsic_clk_src_map,
1000         .freq_tbl = ftbl_gcc_usb_hsic_clk,
1001         .clkr.hw.init = &(struct clk_init_data){
1002                 .name = "usb_hsic_clk_src",
1003                 .parent_names = (const char *[]){
1004                         "xo",
1005                         "gpll1_vote",
1006                 },
1007                 .num_parents = 2,
1008                 .ops = &clk_rcg2_ops,
1009         },
1010 };
1011
1012 static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = {
1013         F(9600000, P_XO, 2, 0, 0),
1014         { }
1015 };
1016
1017 static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
1018         .cmd_rcgr = 0x0458,
1019         .hid_width = 5,
1020         .parent_map = gcc_xo_gpll0_map,
1021         .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk,
1022         .clkr.hw.init = &(struct clk_init_data){
1023                 .name = "usb_hsic_io_cal_clk_src",
1024                 .parent_names = gcc_xo_gpll0,
1025                 .num_parents = 1,
1026                 .ops = &clk_rcg2_ops,
1027         },
1028 };
1029
1030 static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk[] = {
1031         F(60000000, P_GPLL0, 10, 0, 0),
1032         F(75000000, P_GPLL0, 8, 0, 0),
1033         { }
1034 };
1035
1036 static struct clk_rcg2 usb_hsic_system_clk_src = {
1037         .cmd_rcgr = 0x041c,
1038         .hid_width = 5,
1039         .parent_map = gcc_xo_gpll0_map,
1040         .freq_tbl = ftbl_gcc_usb_hsic_system_clk,
1041         .clkr.hw.init = &(struct clk_init_data){
1042                 .name = "usb_hsic_system_clk_src",
1043                 .parent_names = gcc_xo_gpll0,
1044                 .num_parents = 2,
1045                 .ops = &clk_rcg2_ops,
1046         },
1047 };
1048
1049 static struct clk_regmap gcc_mmss_gpll0_clk_src = {
1050         .enable_reg = 0x1484,
1051         .enable_mask = BIT(26),
1052         .hw.init = &(struct clk_init_data){
1053                 .name = "mmss_gpll0_vote",
1054                 .parent_names = (const char *[]){
1055                         "gpll0_vote",
1056                 },
1057                 .num_parents = 1,
1058                 .ops = &clk_branch_simple_ops,
1059         },
1060 };
1061
1062 static struct clk_branch gcc_bam_dma_ahb_clk = {
1063         .halt_reg = 0x0d44,
1064         .halt_check = BRANCH_HALT_VOTED,
1065         .clkr = {
1066                 .enable_reg = 0x1484,
1067                 .enable_mask = BIT(12),
1068                 .hw.init = &(struct clk_init_data){
1069                         .name = "gcc_bam_dma_ahb_clk",
1070                         .parent_names = (const char *[]){
1071                                 "periph_noc_clk_src",
1072                         },
1073                         .num_parents = 1,
1074                         .ops = &clk_branch2_ops,
1075                 },
1076         },
1077 };
1078
1079 static struct clk_branch gcc_blsp1_ahb_clk = {
1080         .halt_reg = 0x05c4,
1081         .halt_check = BRANCH_HALT_VOTED,
1082         .clkr = {
1083                 .enable_reg = 0x1484,
1084                 .enable_mask = BIT(17),
1085                 .hw.init = &(struct clk_init_data){
1086                         .name = "gcc_blsp1_ahb_clk",
1087                         .parent_names = (const char *[]){
1088                                 "periph_noc_clk_src",
1089                         },
1090                         .num_parents = 1,
1091                         .ops = &clk_branch2_ops,
1092                 },
1093         },
1094 };
1095
1096 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1097         .halt_reg = 0x0648,
1098         .clkr = {
1099                 .enable_reg = 0x0648,
1100                 .enable_mask = BIT(0),
1101                 .hw.init = &(struct clk_init_data){
1102                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1103                         .parent_names = (const char *[]){
1104                                 "blsp1_qup1_i2c_apps_clk_src",
1105                         },
1106                         .num_parents = 1,
1107                         .flags = CLK_SET_RATE_PARENT,
1108                         .ops = &clk_branch2_ops,
1109                 },
1110         },
1111 };
1112
1113 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1114         .halt_reg = 0x0644,
1115         .clkr = {
1116                 .enable_reg = 0x0644,
1117                 .enable_mask = BIT(0),
1118                 .hw.init = &(struct clk_init_data){
1119                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1120                         .parent_names = (const char *[]){
1121                                 "blsp1_qup1_spi_apps_clk_src",
1122                         },
1123                         .num_parents = 1,
1124                         .flags = CLK_SET_RATE_PARENT,
1125                         .ops = &clk_branch2_ops,
1126                 },
1127         },
1128 };
1129
1130 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1131         .halt_reg = 0x06c8,
1132         .clkr = {
1133                 .enable_reg = 0x06c8,
1134                 .enable_mask = BIT(0),
1135                 .hw.init = &(struct clk_init_data){
1136                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1137                         .parent_names = (const char *[]){
1138                                 "blsp1_qup2_i2c_apps_clk_src",
1139                         },
1140                         .num_parents = 1,
1141                         .flags = CLK_SET_RATE_PARENT,
1142                         .ops = &clk_branch2_ops,
1143                 },
1144         },
1145 };
1146
1147 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1148         .halt_reg = 0x06c4,
1149         .clkr = {
1150                 .enable_reg = 0x06c4,
1151                 .enable_mask = BIT(0),
1152                 .hw.init = &(struct clk_init_data){
1153                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1154                         .parent_names = (const char *[]){
1155                                 "blsp1_qup2_spi_apps_clk_src",
1156                         },
1157                         .num_parents = 1,
1158                         .flags = CLK_SET_RATE_PARENT,
1159                         .ops = &clk_branch2_ops,
1160                 },
1161         },
1162 };
1163
1164 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1165         .halt_reg = 0x0748,
1166         .clkr = {
1167                 .enable_reg = 0x0748,
1168                 .enable_mask = BIT(0),
1169                 .hw.init = &(struct clk_init_data){
1170                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1171                         .parent_names = (const char *[]){
1172                                 "blsp1_qup3_i2c_apps_clk_src",
1173                         },
1174                         .num_parents = 1,
1175                         .flags = CLK_SET_RATE_PARENT,
1176                         .ops = &clk_branch2_ops,
1177                 },
1178         },
1179 };
1180
1181 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1182         .halt_reg = 0x0744,
1183         .clkr = {
1184                 .enable_reg = 0x0744,
1185                 .enable_mask = BIT(0),
1186                 .hw.init = &(struct clk_init_data){
1187                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1188                         .parent_names = (const char *[]){
1189                                 "blsp1_qup3_spi_apps_clk_src",
1190                         },
1191                         .num_parents = 1,
1192                         .flags = CLK_SET_RATE_PARENT,
1193                         .ops = &clk_branch2_ops,
1194                 },
1195         },
1196 };
1197
1198 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1199         .halt_reg = 0x07c8,
1200         .clkr = {
1201                 .enable_reg = 0x07c8,
1202                 .enable_mask = BIT(0),
1203                 .hw.init = &(struct clk_init_data){
1204                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1205                         .parent_names = (const char *[]){
1206                                 "blsp1_qup4_i2c_apps_clk_src",
1207                         },
1208                         .num_parents = 1,
1209                         .flags = CLK_SET_RATE_PARENT,
1210                         .ops = &clk_branch2_ops,
1211                 },
1212         },
1213 };
1214
1215 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1216         .halt_reg = 0x07c4,
1217         .clkr = {
1218                 .enable_reg = 0x07c4,
1219                 .enable_mask = BIT(0),
1220                 .hw.init = &(struct clk_init_data){
1221                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1222                         .parent_names = (const char *[]){
1223                                 "blsp1_qup4_spi_apps_clk_src",
1224                         },
1225                         .num_parents = 1,
1226                         .flags = CLK_SET_RATE_PARENT,
1227                         .ops = &clk_branch2_ops,
1228                 },
1229         },
1230 };
1231
1232 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1233         .halt_reg = 0x0848,
1234         .clkr = {
1235                 .enable_reg = 0x0848,
1236                 .enable_mask = BIT(0),
1237                 .hw.init = &(struct clk_init_data){
1238                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
1239                         .parent_names = (const char *[]){
1240                                 "blsp1_qup5_i2c_apps_clk_src",
1241                         },
1242                         .num_parents = 1,
1243                         .flags = CLK_SET_RATE_PARENT,
1244                         .ops = &clk_branch2_ops,
1245                 },
1246         },
1247 };
1248
1249 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1250         .halt_reg = 0x0844,
1251         .clkr = {
1252                 .enable_reg = 0x0844,
1253                 .enable_mask = BIT(0),
1254                 .hw.init = &(struct clk_init_data){
1255                         .name = "gcc_blsp1_qup5_spi_apps_clk",
1256                         .parent_names = (const char *[]){
1257                                 "blsp1_qup5_spi_apps_clk_src",
1258                         },
1259                         .num_parents = 1,
1260                         .flags = CLK_SET_RATE_PARENT,
1261                         .ops = &clk_branch2_ops,
1262                 },
1263         },
1264 };
1265
1266 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1267         .halt_reg = 0x08c8,
1268         .clkr = {
1269                 .enable_reg = 0x08c8,
1270                 .enable_mask = BIT(0),
1271                 .hw.init = &(struct clk_init_data){
1272                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
1273                         .parent_names = (const char *[]){
1274                                 "blsp1_qup6_i2c_apps_clk_src",
1275                         },
1276                         .num_parents = 1,
1277                         .flags = CLK_SET_RATE_PARENT,
1278                         .ops = &clk_branch2_ops,
1279                 },
1280         },
1281 };
1282
1283 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1284         .halt_reg = 0x08c4,
1285         .clkr = {
1286                 .enable_reg = 0x08c4,
1287                 .enable_mask = BIT(0),
1288                 .hw.init = &(struct clk_init_data){
1289                         .name = "gcc_blsp1_qup6_spi_apps_clk",
1290                         .parent_names = (const char *[]){
1291                                 "blsp1_qup6_spi_apps_clk_src",
1292                         },
1293                         .num_parents = 1,
1294                         .flags = CLK_SET_RATE_PARENT,
1295                         .ops = &clk_branch2_ops,
1296                 },
1297         },
1298 };
1299
1300 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1301         .halt_reg = 0x0684,
1302         .clkr = {
1303                 .enable_reg = 0x0684,
1304                 .enable_mask = BIT(0),
1305                 .hw.init = &(struct clk_init_data){
1306                         .name = "gcc_blsp1_uart1_apps_clk",
1307                         .parent_names = (const char *[]){
1308                                 "blsp1_uart1_apps_clk_src",
1309                         },
1310                         .num_parents = 1,
1311                         .flags = CLK_SET_RATE_PARENT,
1312                         .ops = &clk_branch2_ops,
1313                 },
1314         },
1315 };
1316
1317 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1318         .halt_reg = 0x0704,
1319         .clkr = {
1320                 .enable_reg = 0x0704,
1321                 .enable_mask = BIT(0),
1322                 .hw.init = &(struct clk_init_data){
1323                         .name = "gcc_blsp1_uart2_apps_clk",
1324                         .parent_names = (const char *[]){
1325                                 "blsp1_uart2_apps_clk_src",
1326                         },
1327                         .num_parents = 1,
1328                         .flags = CLK_SET_RATE_PARENT,
1329                         .ops = &clk_branch2_ops,
1330                 },
1331         },
1332 };
1333
1334 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1335         .halt_reg = 0x0784,
1336         .clkr = {
1337                 .enable_reg = 0x0784,
1338                 .enable_mask = BIT(0),
1339                 .hw.init = &(struct clk_init_data){
1340                         .name = "gcc_blsp1_uart3_apps_clk",
1341                         .parent_names = (const char *[]){
1342                                 "blsp1_uart3_apps_clk_src",
1343                         },
1344                         .num_parents = 1,
1345                         .flags = CLK_SET_RATE_PARENT,
1346                         .ops = &clk_branch2_ops,
1347                 },
1348         },
1349 };
1350
1351 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1352         .halt_reg = 0x0804,
1353         .clkr = {
1354                 .enable_reg = 0x0804,
1355                 .enable_mask = BIT(0),
1356                 .hw.init = &(struct clk_init_data){
1357                         .name = "gcc_blsp1_uart4_apps_clk",
1358                         .parent_names = (const char *[]){
1359                                 "blsp1_uart4_apps_clk_src",
1360                         },
1361                         .num_parents = 1,
1362                         .flags = CLK_SET_RATE_PARENT,
1363                         .ops = &clk_branch2_ops,
1364                 },
1365         },
1366 };
1367
1368 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1369         .halt_reg = 0x0884,
1370         .clkr = {
1371                 .enable_reg = 0x0884,
1372                 .enable_mask = BIT(0),
1373                 .hw.init = &(struct clk_init_data){
1374                         .name = "gcc_blsp1_uart5_apps_clk",
1375                         .parent_names = (const char *[]){
1376                                 "blsp1_uart5_apps_clk_src",
1377                         },
1378                         .num_parents = 1,
1379                         .flags = CLK_SET_RATE_PARENT,
1380                         .ops = &clk_branch2_ops,
1381                 },
1382         },
1383 };
1384
1385 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1386         .halt_reg = 0x0904,
1387         .clkr = {
1388                 .enable_reg = 0x0904,
1389                 .enable_mask = BIT(0),
1390                 .hw.init = &(struct clk_init_data){
1391                         .name = "gcc_blsp1_uart6_apps_clk",
1392                         .parent_names = (const char *[]){
1393                                 "blsp1_uart6_apps_clk_src",
1394                         },
1395                         .num_parents = 1,
1396                         .flags = CLK_SET_RATE_PARENT,
1397                         .ops = &clk_branch2_ops,
1398                 },
1399         },
1400 };
1401
1402 static struct clk_branch gcc_blsp2_ahb_clk = {
1403         .halt_reg = 0x0944,
1404         .halt_check = BRANCH_HALT_VOTED,
1405         .clkr = {
1406                 .enable_reg = 0x1484,
1407                 .enable_mask = BIT(15),
1408                 .hw.init = &(struct clk_init_data){
1409                         .name = "gcc_blsp2_ahb_clk",
1410                         .parent_names = (const char *[]){
1411                                 "periph_noc_clk_src",
1412                         },
1413                         .num_parents = 1,
1414                         .ops = &clk_branch2_ops,
1415                 },
1416         },
1417 };
1418
1419 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1420         .halt_reg = 0x0988,
1421         .clkr = {
1422                 .enable_reg = 0x0988,
1423                 .enable_mask = BIT(0),
1424                 .hw.init = &(struct clk_init_data){
1425                         .name = "gcc_blsp2_qup1_i2c_apps_clk",
1426                         .parent_names = (const char *[]){
1427                                 "blsp2_qup1_i2c_apps_clk_src",
1428                         },
1429                         .num_parents = 1,
1430                         .flags = CLK_SET_RATE_PARENT,
1431                         .ops = &clk_branch2_ops,
1432                 },
1433         },
1434 };
1435
1436 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1437         .halt_reg = 0x0984,
1438         .clkr = {
1439                 .enable_reg = 0x0984,
1440                 .enable_mask = BIT(0),
1441                 .hw.init = &(struct clk_init_data){
1442                         .name = "gcc_blsp2_qup1_spi_apps_clk",
1443                         .parent_names = (const char *[]){
1444                                 "blsp2_qup1_spi_apps_clk_src",
1445                         },
1446                         .num_parents = 1,
1447                         .flags = CLK_SET_RATE_PARENT,
1448                         .ops = &clk_branch2_ops,
1449                 },
1450         },
1451 };
1452
1453 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1454         .halt_reg = 0x0a08,
1455         .clkr = {
1456                 .enable_reg = 0x0a08,
1457                 .enable_mask = BIT(0),
1458                 .hw.init = &(struct clk_init_data){
1459                         .name = "gcc_blsp2_qup2_i2c_apps_clk",
1460                         .parent_names = (const char *[]){
1461                                 "blsp2_qup2_i2c_apps_clk_src",
1462                         },
1463                         .num_parents = 1,
1464                         .flags = CLK_SET_RATE_PARENT,
1465                         .ops = &clk_branch2_ops,
1466                 },
1467         },
1468 };
1469
1470 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1471         .halt_reg = 0x0a04,
1472         .clkr = {
1473                 .enable_reg = 0x0a04,
1474                 .enable_mask = BIT(0),
1475                 .hw.init = &(struct clk_init_data){
1476                         .name = "gcc_blsp2_qup2_spi_apps_clk",
1477                         .parent_names = (const char *[]){
1478                                 "blsp2_qup2_spi_apps_clk_src",
1479                         },
1480                         .num_parents = 1,
1481                         .flags = CLK_SET_RATE_PARENT,
1482                         .ops = &clk_branch2_ops,
1483                 },
1484         },
1485 };
1486
1487 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1488         .halt_reg = 0x0a88,
1489         .clkr = {
1490                 .enable_reg = 0x0a88,
1491                 .enable_mask = BIT(0),
1492                 .hw.init = &(struct clk_init_data){
1493                         .name = "gcc_blsp2_qup3_i2c_apps_clk",
1494                         .parent_names = (const char *[]){
1495                                 "blsp2_qup3_i2c_apps_clk_src",
1496                         },
1497                         .num_parents = 1,
1498                         .flags = CLK_SET_RATE_PARENT,
1499                         .ops = &clk_branch2_ops,
1500                 },
1501         },
1502 };
1503
1504 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1505         .halt_reg = 0x0a84,
1506         .clkr = {
1507                 .enable_reg = 0x0a84,
1508                 .enable_mask = BIT(0),
1509                 .hw.init = &(struct clk_init_data){
1510                         .name = "gcc_blsp2_qup3_spi_apps_clk",
1511                         .parent_names = (const char *[]){
1512                                 "blsp2_qup3_spi_apps_clk_src",
1513                         },
1514                         .num_parents = 1,
1515                         .flags = CLK_SET_RATE_PARENT,
1516                         .ops = &clk_branch2_ops,
1517                 },
1518         },
1519 };
1520
1521 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1522         .halt_reg = 0x0b08,
1523         .clkr = {
1524                 .enable_reg = 0x0b08,
1525                 .enable_mask = BIT(0),
1526                 .hw.init = &(struct clk_init_data){
1527                         .name = "gcc_blsp2_qup4_i2c_apps_clk",
1528                         .parent_names = (const char *[]){
1529                                 "blsp2_qup4_i2c_apps_clk_src",
1530                         },
1531                         .num_parents = 1,
1532                         .flags = CLK_SET_RATE_PARENT,
1533                         .ops = &clk_branch2_ops,
1534                 },
1535         },
1536 };
1537
1538 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1539         .halt_reg = 0x0b04,
1540         .clkr = {
1541                 .enable_reg = 0x0b04,
1542                 .enable_mask = BIT(0),
1543                 .hw.init = &(struct clk_init_data){
1544                         .name = "gcc_blsp2_qup4_spi_apps_clk",
1545                         .parent_names = (const char *[]){
1546                                 "blsp2_qup4_spi_apps_clk_src",
1547                         },
1548                         .num_parents = 1,
1549                         .flags = CLK_SET_RATE_PARENT,
1550                         .ops = &clk_branch2_ops,
1551                 },
1552         },
1553 };
1554
1555 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1556         .halt_reg = 0x0b88,
1557         .clkr = {
1558                 .enable_reg = 0x0b88,
1559                 .enable_mask = BIT(0),
1560                 .hw.init = &(struct clk_init_data){
1561                         .name = "gcc_blsp2_qup5_i2c_apps_clk",
1562                         .parent_names = (const char *[]){
1563                                 "blsp2_qup5_i2c_apps_clk_src",
1564                         },
1565                         .num_parents = 1,
1566                         .flags = CLK_SET_RATE_PARENT,
1567                         .ops = &clk_branch2_ops,
1568                 },
1569         },
1570 };
1571
1572 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1573         .halt_reg = 0x0b84,
1574         .clkr = {
1575                 .enable_reg = 0x0b84,
1576                 .enable_mask = BIT(0),
1577                 .hw.init = &(struct clk_init_data){
1578                         .name = "gcc_blsp2_qup5_spi_apps_clk",
1579                         .parent_names = (const char *[]){
1580                                 "blsp2_qup5_spi_apps_clk_src",
1581                         },
1582                         .num_parents = 1,
1583                         .flags = CLK_SET_RATE_PARENT,
1584                         .ops = &clk_branch2_ops,
1585                 },
1586         },
1587 };
1588
1589 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1590         .halt_reg = 0x0c08,
1591         .clkr = {
1592                 .enable_reg = 0x0c08,
1593                 .enable_mask = BIT(0),
1594                 .hw.init = &(struct clk_init_data){
1595                         .name = "gcc_blsp2_qup6_i2c_apps_clk",
1596                         .parent_names = (const char *[]){
1597                                 "blsp2_qup6_i2c_apps_clk_src",
1598                         },
1599                         .num_parents = 1,
1600                         .flags = CLK_SET_RATE_PARENT,
1601                         .ops = &clk_branch2_ops,
1602                 },
1603         },
1604 };
1605
1606 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1607         .halt_reg = 0x0c04,
1608         .clkr = {
1609                 .enable_reg = 0x0c04,
1610                 .enable_mask = BIT(0),
1611                 .hw.init = &(struct clk_init_data){
1612                         .name = "gcc_blsp2_qup6_spi_apps_clk",
1613                         .parent_names = (const char *[]){
1614                                 "blsp2_qup6_spi_apps_clk_src",
1615                         },
1616                         .num_parents = 1,
1617                         .flags = CLK_SET_RATE_PARENT,
1618                         .ops = &clk_branch2_ops,
1619                 },
1620         },
1621 };
1622
1623 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1624         .halt_reg = 0x09c4,
1625         .clkr = {
1626                 .enable_reg = 0x09c4,
1627                 .enable_mask = BIT(0),
1628                 .hw.init = &(struct clk_init_data){
1629                         .name = "gcc_blsp2_uart1_apps_clk",
1630                         .parent_names = (const char *[]){
1631                                 "blsp2_uart1_apps_clk_src",
1632                         },
1633                         .num_parents = 1,
1634                         .flags = CLK_SET_RATE_PARENT,
1635                         .ops = &clk_branch2_ops,
1636                 },
1637         },
1638 };
1639
1640 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1641         .halt_reg = 0x0a44,
1642         .clkr = {
1643                 .enable_reg = 0x0a44,
1644                 .enable_mask = BIT(0),
1645                 .hw.init = &(struct clk_init_data){
1646                         .name = "gcc_blsp2_uart2_apps_clk",
1647                         .parent_names = (const char *[]){
1648                                 "blsp2_uart2_apps_clk_src",
1649                         },
1650                         .num_parents = 1,
1651                         .flags = CLK_SET_RATE_PARENT,
1652                         .ops = &clk_branch2_ops,
1653                 },
1654         },
1655 };
1656
1657 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1658         .halt_reg = 0x0ac4,
1659         .clkr = {
1660                 .enable_reg = 0x0ac4,
1661                 .enable_mask = BIT(0),
1662                 .hw.init = &(struct clk_init_data){
1663                         .name = "gcc_blsp2_uart3_apps_clk",
1664                         .parent_names = (const char *[]){
1665                                 "blsp2_uart3_apps_clk_src",
1666                         },
1667                         .num_parents = 1,
1668                         .flags = CLK_SET_RATE_PARENT,
1669                         .ops = &clk_branch2_ops,
1670                 },
1671         },
1672 };
1673
1674 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1675         .halt_reg = 0x0b44,
1676         .clkr = {
1677                 .enable_reg = 0x0b44,
1678                 .enable_mask = BIT(0),
1679                 .hw.init = &(struct clk_init_data){
1680                         .name = "gcc_blsp2_uart4_apps_clk",
1681                         .parent_names = (const char *[]){
1682                                 "blsp2_uart4_apps_clk_src",
1683                         },
1684                         .num_parents = 1,
1685                         .flags = CLK_SET_RATE_PARENT,
1686                         .ops = &clk_branch2_ops,
1687                 },
1688         },
1689 };
1690
1691 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1692         .halt_reg = 0x0bc4,
1693         .clkr = {
1694                 .enable_reg = 0x0bc4,
1695                 .enable_mask = BIT(0),
1696                 .hw.init = &(struct clk_init_data){
1697                         .name = "gcc_blsp2_uart5_apps_clk",
1698                         .parent_names = (const char *[]){
1699                                 "blsp2_uart5_apps_clk_src",
1700                         },
1701                         .num_parents = 1,
1702                         .flags = CLK_SET_RATE_PARENT,
1703                         .ops = &clk_branch2_ops,
1704                 },
1705         },
1706 };
1707
1708 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1709         .halt_reg = 0x0c44,
1710         .clkr = {
1711                 .enable_reg = 0x0c44,
1712                 .enable_mask = BIT(0),
1713                 .hw.init = &(struct clk_init_data){
1714                         .name = "gcc_blsp2_uart6_apps_clk",
1715                         .parent_names = (const char *[]){
1716                                 "blsp2_uart6_apps_clk_src",
1717                         },
1718                         .num_parents = 1,
1719                         .flags = CLK_SET_RATE_PARENT,
1720                         .ops = &clk_branch2_ops,
1721                 },
1722         },
1723 };
1724
1725 static struct clk_branch gcc_boot_rom_ahb_clk = {
1726         .halt_reg = 0x0e04,
1727         .halt_check = BRANCH_HALT_VOTED,
1728         .clkr = {
1729                 .enable_reg = 0x1484,
1730                 .enable_mask = BIT(10),
1731                 .hw.init = &(struct clk_init_data){
1732                         .name = "gcc_boot_rom_ahb_clk",
1733                         .parent_names = (const char *[]){
1734                                 "config_noc_clk_src",
1735                         },
1736                         .num_parents = 1,
1737                         .ops = &clk_branch2_ops,
1738                 },
1739         },
1740 };
1741
1742 static struct clk_branch gcc_ce1_ahb_clk = {
1743         .halt_reg = 0x104c,
1744         .halt_check = BRANCH_HALT_VOTED,
1745         .clkr = {
1746                 .enable_reg = 0x1484,
1747                 .enable_mask = BIT(3),
1748                 .hw.init = &(struct clk_init_data){
1749                         .name = "gcc_ce1_ahb_clk",
1750                         .parent_names = (const char *[]){
1751                                 "config_noc_clk_src",
1752                         },
1753                         .num_parents = 1,
1754                         .ops = &clk_branch2_ops,
1755                 },
1756         },
1757 };
1758
1759 static struct clk_branch gcc_ce1_axi_clk = {
1760         .halt_reg = 0x1048,
1761         .halt_check = BRANCH_HALT_VOTED,
1762         .clkr = {
1763                 .enable_reg = 0x1484,
1764                 .enable_mask = BIT(4),
1765                 .hw.init = &(struct clk_init_data){
1766                         .name = "gcc_ce1_axi_clk",
1767                         .parent_names = (const char *[]){
1768                                 "system_noc_clk_src",
1769                         },
1770                         .num_parents = 1,
1771                         .ops = &clk_branch2_ops,
1772                 },
1773         },
1774 };
1775
1776 static struct clk_branch gcc_ce1_clk = {
1777         .halt_reg = 0x1050,
1778         .halt_check = BRANCH_HALT_VOTED,
1779         .clkr = {
1780                 .enable_reg = 0x1484,
1781                 .enable_mask = BIT(5),
1782                 .hw.init = &(struct clk_init_data){
1783                         .name = "gcc_ce1_clk",
1784                         .parent_names = (const char *[]){
1785                                 "ce1_clk_src",
1786                         },
1787                         .num_parents = 1,
1788                         .flags = CLK_SET_RATE_PARENT,
1789                         .ops = &clk_branch2_ops,
1790                 },
1791         },
1792 };
1793
1794 static struct clk_branch gcc_ce2_ahb_clk = {
1795         .halt_reg = 0x108c,
1796         .halt_check = BRANCH_HALT_VOTED,
1797         .clkr = {
1798                 .enable_reg = 0x1484,
1799                 .enable_mask = BIT(0),
1800                 .hw.init = &(struct clk_init_data){
1801                         .name = "gcc_ce2_ahb_clk",
1802                         .parent_names = (const char *[]){
1803                                 "config_noc_clk_src",
1804                         },
1805                         .num_parents = 1,
1806                         .ops = &clk_branch2_ops,
1807                 },
1808         },
1809 };
1810
1811 static struct clk_branch gcc_ce2_axi_clk = {
1812         .halt_reg = 0x1088,
1813         .halt_check = BRANCH_HALT_VOTED,
1814         .clkr = {
1815                 .enable_reg = 0x1484,
1816                 .enable_mask = BIT(1),
1817                 .hw.init = &(struct clk_init_data){
1818                         .name = "gcc_ce2_axi_clk",
1819                         .parent_names = (const char *[]){
1820                                 "system_noc_clk_src",
1821                         },
1822                         .num_parents = 1,
1823                         .ops = &clk_branch2_ops,
1824                 },
1825         },
1826 };
1827
1828 static struct clk_branch gcc_ce2_clk = {
1829         .halt_reg = 0x1090,
1830         .halt_check = BRANCH_HALT_VOTED,
1831         .clkr = {
1832                 .enable_reg = 0x1484,
1833                 .enable_mask = BIT(2),
1834                 .hw.init = &(struct clk_init_data){
1835                         .name = "gcc_ce2_clk",
1836                         .parent_names = (const char *[]){
1837                                 "ce2_clk_src",
1838                         },
1839                         .num_parents = 1,
1840                         .flags = CLK_SET_RATE_PARENT,
1841                         .ops = &clk_branch2_ops,
1842                 },
1843         },
1844 };
1845
1846 static struct clk_branch gcc_gp1_clk = {
1847         .halt_reg = 0x1900,
1848         .clkr = {
1849                 .enable_reg = 0x1900,
1850                 .enable_mask = BIT(0),
1851                 .hw.init = &(struct clk_init_data){
1852                         .name = "gcc_gp1_clk",
1853                         .parent_names = (const char *[]){
1854                                 "gp1_clk_src",
1855                         },
1856                         .num_parents = 1,
1857                         .flags = CLK_SET_RATE_PARENT,
1858                         .ops = &clk_branch2_ops,
1859                 },
1860         },
1861 };
1862
1863 static struct clk_branch gcc_gp2_clk = {
1864         .halt_reg = 0x1940,
1865         .clkr = {
1866                 .enable_reg = 0x1940,
1867                 .enable_mask = BIT(0),
1868                 .hw.init = &(struct clk_init_data){
1869                         .name = "gcc_gp2_clk",
1870                         .parent_names = (const char *[]){
1871                                 "gp2_clk_src",
1872                         },
1873                         .num_parents = 1,
1874                         .flags = CLK_SET_RATE_PARENT,
1875                         .ops = &clk_branch2_ops,
1876                 },
1877         },
1878 };
1879
1880 static struct clk_branch gcc_gp3_clk = {
1881         .halt_reg = 0x1980,
1882         .clkr = {
1883                 .enable_reg = 0x1980,
1884                 .enable_mask = BIT(0),
1885                 .hw.init = &(struct clk_init_data){
1886                         .name = "gcc_gp3_clk",
1887                         .parent_names = (const char *[]){
1888                                 "gp3_clk_src",
1889                         },
1890                         .num_parents = 1,
1891                         .flags = CLK_SET_RATE_PARENT,
1892                         .ops = &clk_branch2_ops,
1893                 },
1894         },
1895 };
1896
1897 static struct clk_branch gcc_lpass_q6_axi_clk = {
1898         .halt_reg = 0x11c0,
1899         .clkr = {
1900                 .enable_reg = 0x11c0,
1901                 .enable_mask = BIT(0),
1902                 .hw.init = &(struct clk_init_data){
1903                         .name = "gcc_lpass_q6_axi_clk",
1904                         .parent_names = (const char *[]){
1905                                 "system_noc_clk_src",
1906                         },
1907                         .num_parents = 1,
1908                         .ops = &clk_branch2_ops,
1909                 },
1910         },
1911 };
1912
1913 static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
1914         .halt_reg = 0x024c,
1915         .clkr = {
1916                 .enable_reg = 0x024c,
1917                 .enable_mask = BIT(0),
1918                 .hw.init = &(struct clk_init_data){
1919                         .name = "gcc_mmss_noc_cfg_ahb_clk",
1920                         .parent_names = (const char *[]){
1921                                 "config_noc_clk_src",
1922                         },
1923                         .num_parents = 1,
1924                         .ops = &clk_branch2_ops,
1925                         .flags = CLK_IGNORE_UNUSED,
1926                 },
1927         },
1928 };
1929
1930 static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk = {
1931         .halt_reg = 0x0248,
1932         .clkr = {
1933                 .enable_reg = 0x0248,
1934                 .enable_mask = BIT(0),
1935                 .hw.init = &(struct clk_init_data){
1936                         .name = "gcc_ocmem_noc_cfg_ahb_clk",
1937                         .parent_names = (const char *[]){
1938                                 "config_noc_clk_src",
1939                         },
1940                         .num_parents = 1,
1941                         .ops = &clk_branch2_ops,
1942                 },
1943         },
1944 };
1945
1946 static struct clk_branch gcc_mss_cfg_ahb_clk = {
1947         .halt_reg = 0x0280,
1948         .clkr = {
1949                 .enable_reg = 0x0280,
1950                 .enable_mask = BIT(0),
1951                 .hw.init = &(struct clk_init_data){
1952                         .name = "gcc_mss_cfg_ahb_clk",
1953                         .parent_names = (const char *[]){
1954                                 "config_noc_clk_src",
1955                         },
1956                         .num_parents = 1,
1957                         .ops = &clk_branch2_ops,
1958                 },
1959         },
1960 };
1961
1962 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
1963         .halt_reg = 0x0284,
1964         .clkr = {
1965                 .enable_reg = 0x0284,
1966                 .enable_mask = BIT(0),
1967                 .hw.init = &(struct clk_init_data){
1968                         .name = "gcc_mss_q6_bimc_axi_clk",
1969                         .parent_names = (const char *[]){
1970                                 "system_noc_clk_src",
1971                         },
1972                         .num_parents = 1,
1973                         .ops = &clk_branch2_ops,
1974                 },
1975         },
1976 };
1977
1978 static struct clk_branch gcc_pdm2_clk = {
1979         .halt_reg = 0x0ccc,
1980         .clkr = {
1981                 .enable_reg = 0x0ccc,
1982                 .enable_mask = BIT(0),
1983                 .hw.init = &(struct clk_init_data){
1984                         .name = "gcc_pdm2_clk",
1985                         .parent_names = (const char *[]){
1986                                 "pdm2_clk_src",
1987                         },
1988                         .num_parents = 1,
1989                         .flags = CLK_SET_RATE_PARENT,
1990                         .ops = &clk_branch2_ops,
1991                 },
1992         },
1993 };
1994
1995 static struct clk_branch gcc_pdm_ahb_clk = {
1996         .halt_reg = 0x0cc4,
1997         .clkr = {
1998                 .enable_reg = 0x0cc4,
1999                 .enable_mask = BIT(0),
2000                 .hw.init = &(struct clk_init_data){
2001                         .name = "gcc_pdm_ahb_clk",
2002                         .parent_names = (const char *[]){
2003                                 "periph_noc_clk_src",
2004                         },
2005                         .num_parents = 1,
2006                         .ops = &clk_branch2_ops,
2007                 },
2008         },
2009 };
2010
2011 static struct clk_branch gcc_pdm_xo4_clk = {
2012         .halt_reg = 0x0cc8,
2013         .clkr = {
2014                 .enable_reg = 0x0cc8,
2015                 .enable_mask = BIT(0),
2016                 .hw.init = &(struct clk_init_data){
2017                         .name = "gcc_pdm_xo4_clk",
2018                         .parent_names = (const char *[]){ "xo" },
2019                         .num_parents = 1,
2020                         .ops = &clk_branch2_ops,
2021                 },
2022         },
2023 };
2024
2025 static struct clk_branch gcc_prng_ahb_clk = {
2026         .halt_reg = 0x0d04,
2027         .halt_check = BRANCH_HALT_VOTED,
2028         .clkr = {
2029                 .enable_reg = 0x1484,
2030                 .enable_mask = BIT(13),
2031                 .hw.init = &(struct clk_init_data){
2032                         .name = "gcc_prng_ahb_clk",
2033                         .parent_names = (const char *[]){
2034                                 "periph_noc_clk_src",
2035                         },
2036                         .num_parents = 1,
2037                         .ops = &clk_branch2_ops,
2038                 },
2039         },
2040 };
2041
2042 static struct clk_branch gcc_sdcc1_ahb_clk = {
2043         .halt_reg = 0x04c8,
2044         .clkr = {
2045                 .enable_reg = 0x04c8,
2046                 .enable_mask = BIT(0),
2047                 .hw.init = &(struct clk_init_data){
2048                         .name = "gcc_sdcc1_ahb_clk",
2049                         .parent_names = (const char *[]){
2050                                 "periph_noc_clk_src",
2051                         },
2052                         .num_parents = 1,
2053                         .ops = &clk_branch2_ops,
2054                 },
2055         },
2056 };
2057
2058 static struct clk_branch gcc_sdcc1_apps_clk = {
2059         .halt_reg = 0x04c4,
2060         .clkr = {
2061                 .enable_reg = 0x04c4,
2062                 .enable_mask = BIT(0),
2063                 .hw.init = &(struct clk_init_data){
2064                         .name = "gcc_sdcc1_apps_clk",
2065                         .parent_names = (const char *[]){
2066                                 "sdcc1_apps_clk_src",
2067                         },
2068                         .num_parents = 1,
2069                         .flags = CLK_SET_RATE_PARENT,
2070                         .ops = &clk_branch2_ops,
2071                 },
2072         },
2073 };
2074
2075 static struct clk_branch gcc_sdcc1_cdccal_ff_clk = {
2076         .halt_reg = 0x04e8,
2077         .clkr = {
2078                 .enable_reg = 0x04e8,
2079                 .enable_mask = BIT(0),
2080                 .hw.init = &(struct clk_init_data){
2081                         .name = "gcc_sdcc1_cdccal_ff_clk",
2082                         .parent_names = (const char *[]){
2083                                 "xo"
2084                         },
2085                         .num_parents = 1,
2086                         .ops = &clk_branch2_ops,
2087                 },
2088         },
2089 };
2090
2091 static struct clk_branch gcc_sdcc1_cdccal_sleep_clk = {
2092         .halt_reg = 0x04e4,
2093         .clkr = {
2094                 .enable_reg = 0x04e4,
2095                 .enable_mask = BIT(0),
2096                 .hw.init = &(struct clk_init_data){
2097                         .name = "gcc_sdcc1_cdccal_sleep_clk",
2098                         .parent_names = (const char *[]){
2099                                 "sleep_clk_src"
2100                         },
2101                         .num_parents = 1,
2102                         .ops = &clk_branch2_ops,
2103                 },
2104         },
2105 };
2106
2107 static struct clk_branch gcc_sdcc2_ahb_clk = {
2108         .halt_reg = 0x0508,
2109         .clkr = {
2110                 .enable_reg = 0x0508,
2111                 .enable_mask = BIT(0),
2112                 .hw.init = &(struct clk_init_data){
2113                         .name = "gcc_sdcc2_ahb_clk",
2114                         .parent_names = (const char *[]){
2115                                 "periph_noc_clk_src",
2116                         },
2117                         .num_parents = 1,
2118                         .ops = &clk_branch2_ops,
2119                 },
2120         },
2121 };
2122
2123 static struct clk_branch gcc_sdcc2_apps_clk = {
2124         .halt_reg = 0x0504,
2125         .clkr = {
2126                 .enable_reg = 0x0504,
2127                 .enable_mask = BIT(0),
2128                 .hw.init = &(struct clk_init_data){
2129                         .name = "gcc_sdcc2_apps_clk",
2130                         .parent_names = (const char *[]){
2131                                 "sdcc2_apps_clk_src",
2132                         },
2133                         .num_parents = 1,
2134                         .flags = CLK_SET_RATE_PARENT,
2135                         .ops = &clk_branch2_ops,
2136                 },
2137         },
2138 };
2139
2140 static struct clk_branch gcc_sdcc3_ahb_clk = {
2141         .halt_reg = 0x0548,
2142         .clkr = {
2143                 .enable_reg = 0x0548,
2144                 .enable_mask = BIT(0),
2145                 .hw.init = &(struct clk_init_data){
2146                         .name = "gcc_sdcc3_ahb_clk",
2147                         .parent_names = (const char *[]){
2148                                 "periph_noc_clk_src",
2149                         },
2150                         .num_parents = 1,
2151                         .ops = &clk_branch2_ops,
2152                 },
2153         },
2154 };
2155
2156 static struct clk_branch gcc_sdcc3_apps_clk = {
2157         .halt_reg = 0x0544,
2158         .clkr = {
2159                 .enable_reg = 0x0544,
2160                 .enable_mask = BIT(0),
2161                 .hw.init = &(struct clk_init_data){
2162                         .name = "gcc_sdcc3_apps_clk",
2163                         .parent_names = (const char *[]){
2164                                 "sdcc3_apps_clk_src",
2165                         },
2166                         .num_parents = 1,
2167                         .flags = CLK_SET_RATE_PARENT,
2168                         .ops = &clk_branch2_ops,
2169                 },
2170         },
2171 };
2172
2173 static struct clk_branch gcc_sdcc4_ahb_clk = {
2174         .halt_reg = 0x0588,
2175         .clkr = {
2176                 .enable_reg = 0x0588,
2177                 .enable_mask = BIT(0),
2178                 .hw.init = &(struct clk_init_data){
2179                         .name = "gcc_sdcc4_ahb_clk",
2180                         .parent_names = (const char *[]){
2181                                 "periph_noc_clk_src",
2182                         },
2183                         .num_parents = 1,
2184                         .ops = &clk_branch2_ops,
2185                 },
2186         },
2187 };
2188
2189 static struct clk_branch gcc_sdcc4_apps_clk = {
2190         .halt_reg = 0x0584,
2191         .clkr = {
2192                 .enable_reg = 0x0584,
2193                 .enable_mask = BIT(0),
2194                 .hw.init = &(struct clk_init_data){
2195                         .name = "gcc_sdcc4_apps_clk",
2196                         .parent_names = (const char *[]){
2197                                 "sdcc4_apps_clk_src",
2198                         },
2199                         .num_parents = 1,
2200                         .flags = CLK_SET_RATE_PARENT,
2201                         .ops = &clk_branch2_ops,
2202                 },
2203         },
2204 };
2205
2206 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
2207         .halt_reg = 0x0108,
2208         .clkr = {
2209                 .enable_reg = 0x0108,
2210                 .enable_mask = BIT(0),
2211                 .hw.init = &(struct clk_init_data){
2212                         .name = "gcc_sys_noc_usb3_axi_clk",
2213                         .parent_names = (const char *[]){
2214                                 "usb30_master_clk_src",
2215                         },
2216                         .num_parents = 1,
2217                         .flags = CLK_SET_RATE_PARENT,
2218                         .ops = &clk_branch2_ops,
2219                 },
2220         },
2221 };
2222
2223 static struct clk_branch gcc_tsif_ahb_clk = {
2224         .halt_reg = 0x0d84,
2225         .clkr = {
2226                 .enable_reg = 0x0d84,
2227                 .enable_mask = BIT(0),
2228                 .hw.init = &(struct clk_init_data){
2229                         .name = "gcc_tsif_ahb_clk",
2230                         .parent_names = (const char *[]){
2231                                 "periph_noc_clk_src",
2232                         },
2233                         .num_parents = 1,
2234                         .ops = &clk_branch2_ops,
2235                 },
2236         },
2237 };
2238
2239 static struct clk_branch gcc_tsif_ref_clk = {
2240         .halt_reg = 0x0d88,
2241         .clkr = {
2242                 .enable_reg = 0x0d88,
2243                 .enable_mask = BIT(0),
2244                 .hw.init = &(struct clk_init_data){
2245                         .name = "gcc_tsif_ref_clk",
2246                         .parent_names = (const char *[]){
2247                                 "tsif_ref_clk_src",
2248                         },
2249                         .num_parents = 1,
2250                         .flags = CLK_SET_RATE_PARENT,
2251                         .ops = &clk_branch2_ops,
2252                 },
2253         },
2254 };
2255
2256 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2257         .halt_reg = 0x04ac,
2258         .clkr = {
2259                 .enable_reg = 0x04ac,
2260                 .enable_mask = BIT(0),
2261                 .hw.init = &(struct clk_init_data){
2262                         .name = "gcc_usb2a_phy_sleep_clk",
2263                         .parent_names = (const char *[]){
2264                                 "sleep_clk_src",
2265                         },
2266                         .num_parents = 1,
2267                         .ops = &clk_branch2_ops,
2268                 },
2269         },
2270 };
2271
2272 static struct clk_branch gcc_usb2b_phy_sleep_clk = {
2273         .halt_reg = 0x04b4,
2274         .clkr = {
2275                 .enable_reg = 0x04b4,
2276                 .enable_mask = BIT(0),
2277                 .hw.init = &(struct clk_init_data){
2278                         .name = "gcc_usb2b_phy_sleep_clk",
2279                         .parent_names = (const char *[]){
2280                                 "sleep_clk_src",
2281                         },
2282                         .num_parents = 1,
2283                         .ops = &clk_branch2_ops,
2284                 },
2285         },
2286 };
2287
2288 static struct clk_branch gcc_usb30_master_clk = {
2289         .halt_reg = 0x03c8,
2290         .clkr = {
2291                 .enable_reg = 0x03c8,
2292                 .enable_mask = BIT(0),
2293                 .hw.init = &(struct clk_init_data){
2294                         .name = "gcc_usb30_master_clk",
2295                         .parent_names = (const char *[]){
2296                                 "usb30_master_clk_src",
2297                         },
2298                         .num_parents = 1,
2299                         .flags = CLK_SET_RATE_PARENT,
2300                         .ops = &clk_branch2_ops,
2301                 },
2302         },
2303 };
2304
2305 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2306         .halt_reg = 0x03d0,
2307         .clkr = {
2308                 .enable_reg = 0x03d0,
2309                 .enable_mask = BIT(0),
2310                 .hw.init = &(struct clk_init_data){
2311                         .name = "gcc_usb30_mock_utmi_clk",
2312                         .parent_names = (const char *[]){
2313                                 "usb30_mock_utmi_clk_src",
2314                         },
2315                         .num_parents = 1,
2316                         .flags = CLK_SET_RATE_PARENT,
2317                         .ops = &clk_branch2_ops,
2318                 },
2319         },
2320 };
2321
2322 static struct clk_branch gcc_usb30_sleep_clk = {
2323         .halt_reg = 0x03cc,
2324         .clkr = {
2325                 .enable_reg = 0x03cc,
2326                 .enable_mask = BIT(0),
2327                 .hw.init = &(struct clk_init_data){
2328                         .name = "gcc_usb30_sleep_clk",
2329                         .parent_names = (const char *[]){
2330                                 "sleep_clk_src",
2331                         },
2332                         .num_parents = 1,
2333                         .ops = &clk_branch2_ops,
2334                 },
2335         },
2336 };
2337
2338 static struct clk_branch gcc_usb_hs_ahb_clk = {
2339         .halt_reg = 0x0488,
2340         .clkr = {
2341                 .enable_reg = 0x0488,
2342                 .enable_mask = BIT(0),
2343                 .hw.init = &(struct clk_init_data){
2344                         .name = "gcc_usb_hs_ahb_clk",
2345                         .parent_names = (const char *[]){
2346                                 "periph_noc_clk_src",
2347                         },
2348                         .num_parents = 1,
2349                         .ops = &clk_branch2_ops,
2350                 },
2351         },
2352 };
2353
2354 static struct clk_branch gcc_usb_hs_system_clk = {
2355         .halt_reg = 0x0484,
2356         .clkr = {
2357                 .enable_reg = 0x0484,
2358                 .enable_mask = BIT(0),
2359                 .hw.init = &(struct clk_init_data){
2360                         .name = "gcc_usb_hs_system_clk",
2361                         .parent_names = (const char *[]){
2362                                 "usb_hs_system_clk_src",
2363                         },
2364                         .num_parents = 1,
2365                         .flags = CLK_SET_RATE_PARENT,
2366                         .ops = &clk_branch2_ops,
2367                 },
2368         },
2369 };
2370
2371 static struct clk_branch gcc_usb_hsic_ahb_clk = {
2372         .halt_reg = 0x0408,
2373         .clkr = {
2374                 .enable_reg = 0x0408,
2375                 .enable_mask = BIT(0),
2376                 .hw.init = &(struct clk_init_data){
2377                         .name = "gcc_usb_hsic_ahb_clk",
2378                         .parent_names = (const char *[]){
2379                                 "periph_noc_clk_src",
2380                         },
2381                         .num_parents = 1,
2382                         .ops = &clk_branch2_ops,
2383                 },
2384         },
2385 };
2386
2387 static struct clk_branch gcc_usb_hsic_clk = {
2388         .halt_reg = 0x0410,
2389         .clkr = {
2390                 .enable_reg = 0x0410,
2391                 .enable_mask = BIT(0),
2392                 .hw.init = &(struct clk_init_data){
2393                         .name = "gcc_usb_hsic_clk",
2394                         .parent_names = (const char *[]){
2395                                 "usb_hsic_clk_src",
2396                         },
2397                         .num_parents = 1,
2398                         .flags = CLK_SET_RATE_PARENT,
2399                         .ops = &clk_branch2_ops,
2400                 },
2401         },
2402 };
2403
2404 static struct clk_branch gcc_usb_hsic_io_cal_clk = {
2405         .halt_reg = 0x0414,
2406         .clkr = {
2407                 .enable_reg = 0x0414,
2408                 .enable_mask = BIT(0),
2409                 .hw.init = &(struct clk_init_data){
2410                         .name = "gcc_usb_hsic_io_cal_clk",
2411                         .parent_names = (const char *[]){
2412                                 "usb_hsic_io_cal_clk_src",
2413                         },
2414                         .num_parents = 1,
2415                         .flags = CLK_SET_RATE_PARENT,
2416                         .ops = &clk_branch2_ops,
2417                 },
2418         },
2419 };
2420
2421 static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk = {
2422         .halt_reg = 0x0418,
2423         .clkr = {
2424                 .enable_reg = 0x0418,
2425                 .enable_mask = BIT(0),
2426                 .hw.init = &(struct clk_init_data){
2427                         .name = "gcc_usb_hsic_io_cal_sleep_clk",
2428                         .parent_names = (const char *[]){
2429                                 "sleep_clk_src",
2430                         },
2431                         .num_parents = 1,
2432                         .ops = &clk_branch2_ops,
2433                 },
2434         },
2435 };
2436
2437 static struct clk_branch gcc_usb_hsic_system_clk = {
2438         .halt_reg = 0x040c,
2439         .clkr = {
2440                 .enable_reg = 0x040c,
2441                 .enable_mask = BIT(0),
2442                 .hw.init = &(struct clk_init_data){
2443                         .name = "gcc_usb_hsic_system_clk",
2444                         .parent_names = (const char *[]){
2445                                 "usb_hsic_system_clk_src",
2446                         },
2447                         .num_parents = 1,
2448                         .flags = CLK_SET_RATE_PARENT,
2449                         .ops = &clk_branch2_ops,
2450                 },
2451         },
2452 };
2453
2454 static struct gdsc usb_hs_hsic_gdsc = {
2455         .gdscr = 0x404,
2456         .pd = {
2457                 .name = "usb_hs_hsic",
2458         },
2459         .pwrsts = PWRSTS_OFF_ON,
2460 };
2461
2462 static struct clk_regmap *gcc_msm8226_clocks[] = {
2463         [GPLL0] = &gpll0.clkr,
2464         [GPLL0_VOTE] = &gpll0_vote,
2465         [GPLL1] = &gpll1.clkr,
2466         [GPLL1_VOTE] = &gpll1_vote,
2467         [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
2468         [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
2469         [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
2470         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2471         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2472         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2473         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2474         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2475         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2476         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2477         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2478         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2479         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2480         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2481         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2482         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2483         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2484         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2485         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2486         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2487         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2488         [CE1_CLK_SRC] = &ce1_clk_src.clkr,
2489         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2490         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2491         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2492         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2493         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2494         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2495         [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2496         [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2497         [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
2498         [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
2499         [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
2500         [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
2501         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2502         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2503         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2504         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2505         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2506         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2507         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2508         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2509         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2510         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2511         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2512         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2513         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2514         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2515         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2516         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2517         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2518         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2519         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2520         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2521         [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
2522         [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
2523         [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
2524         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2525         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2526         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2527         [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
2528         [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2529         [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
2530         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2531         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2532         [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
2533         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2534         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2535         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2536         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2537         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2538         [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
2539         [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2540         [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
2541         [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
2542         [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2543         [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
2544         [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
2545         [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
2546         [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
2547 };
2548
2549 static const struct qcom_reset_map gcc_msm8226_resets[] = {
2550         [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
2551         [GCC_USB_HS_BCR] = { 0x0480 },
2552         [GCC_USB2A_PHY_BCR] = { 0x04a8 },
2553 };
2554
2555 static struct gdsc *gcc_msm8226_gdscs[] = {
2556         [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc,
2557 };
2558
2559 static const struct regmap_config gcc_msm8226_regmap_config = {
2560         .reg_bits       = 32,
2561         .reg_stride     = 4,
2562         .val_bits       = 32,
2563         .max_register   = 0x1a80,
2564         .fast_io        = true,
2565 };
2566
2567 static const struct qcom_cc_desc gcc_msm8226_desc = {
2568         .config = &gcc_msm8226_regmap_config,
2569         .clks = gcc_msm8226_clocks,
2570         .num_clks = ARRAY_SIZE(gcc_msm8226_clocks),
2571         .resets = gcc_msm8226_resets,
2572         .num_resets = ARRAY_SIZE(gcc_msm8226_resets),
2573         .gdscs = gcc_msm8226_gdscs,
2574         .num_gdscs = ARRAY_SIZE(gcc_msm8226_gdscs),
2575 };
2576
2577 static struct clk_regmap *gcc_msm8974_clocks[] = {
2578         [GPLL0] = &gpll0.clkr,
2579         [GPLL0_VOTE] = &gpll0_vote,
2580         [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,
2581         [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,
2582         [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,
2583         [GPLL1] = &gpll1.clkr,
2584         [GPLL1_VOTE] = &gpll1_vote,
2585         [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2586         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2587         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2588         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2589         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2590         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2591         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2592         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2593         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2594         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2595         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2596         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2597         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2598         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2599         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2600         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2601         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2602         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2603         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2604         [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2605         [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2606         [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2607         [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2608         [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2609         [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2610         [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2611         [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2612         [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2613         [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2614         [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2615         [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2616         [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2617         [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2618         [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2619         [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2620         [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2621         [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2622         [CE1_CLK_SRC] = &ce1_clk_src.clkr,
2623         [CE2_CLK_SRC] = &ce2_clk_src.clkr,
2624         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2625         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2626         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2627         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2628         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2629         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2630         [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2631         [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2632         [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2633         [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2634         [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2635         [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
2636         [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
2637         [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
2638         [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr,
2639         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2640         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2641         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2642         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2643         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2644         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2645         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2646         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2647         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2648         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2649         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2650         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2651         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2652         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2653         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2654         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2655         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2656         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2657         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2658         [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2659         [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2660         [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2661         [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2662         [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2663         [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2664         [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2665         [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2666         [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2667         [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2668         [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2669         [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2670         [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2671         [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2672         [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2673         [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2674         [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2675         [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2676         [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2677         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2678         [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr,
2679         [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr,
2680         [GCC_CE1_CLK] = &gcc_ce1_clk.clkr,
2681         [GCC_CE2_AHB_CLK] = &gcc_ce2_ahb_clk.clkr,
2682         [GCC_CE2_AXI_CLK] = &gcc_ce2_axi_clk.clkr,
2683         [GCC_CE2_CLK] = &gcc_ce2_clk.clkr,
2684         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2685         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2686         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2687         [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
2688         [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
2689         [GCC_OCMEM_NOC_CFG_AHB_CLK] = &gcc_ocmem_noc_cfg_ahb_clk.clkr,
2690         [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
2691         [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
2692         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2693         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2694         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2695         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2696         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2697         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2698         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2699         [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
2700         [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2701         [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2702         [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2703         [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2704         [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2705         [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2706         [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
2707         [GCC_USB2B_PHY_SLEEP_CLK] = &gcc_usb2b_phy_sleep_clk.clkr,
2708         [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2709         [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2710         [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2711         [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
2712         [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2713         [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr,
2714         [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr,
2715         [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr,
2716         [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr,
2717         [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr,
2718         [GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src,
2719         [GPLL4] = NULL,
2720         [GPLL4_VOTE] = NULL,
2721         [GCC_SDCC1_CDCCAL_SLEEP_CLK] = NULL,
2722         [GCC_SDCC1_CDCCAL_FF_CLK] = NULL,
2723 };
2724
2725 static const struct qcom_reset_map gcc_msm8974_resets[] = {
2726         [GCC_SYSTEM_NOC_BCR] = { 0x0100 },
2727         [GCC_CONFIG_NOC_BCR] = { 0x0140 },
2728         [GCC_PERIPH_NOC_BCR] = { 0x0180 },
2729         [GCC_IMEM_BCR] = { 0x0200 },
2730         [GCC_MMSS_BCR] = { 0x0240 },
2731         [GCC_QDSS_BCR] = { 0x0300 },
2732         [GCC_USB_30_BCR] = { 0x03c0 },
2733         [GCC_USB3_PHY_BCR] = { 0x03fc },
2734         [GCC_USB_HS_HSIC_BCR] = { 0x0400 },
2735         [GCC_USB_HS_BCR] = { 0x0480 },
2736         [GCC_USB2A_PHY_BCR] = { 0x04a8 },
2737         [GCC_USB2B_PHY_BCR] = { 0x04b0 },
2738         [GCC_SDCC1_BCR] = { 0x04c0 },
2739         [GCC_SDCC2_BCR] = { 0x0500 },
2740         [GCC_SDCC3_BCR] = { 0x0540 },
2741         [GCC_SDCC4_BCR] = { 0x0580 },
2742         [GCC_BLSP1_BCR] = { 0x05c0 },
2743         [GCC_BLSP1_QUP1_BCR] = { 0x0640 },
2744         [GCC_BLSP1_UART1_BCR] = { 0x0680 },
2745         [GCC_BLSP1_QUP2_BCR] = { 0x06c0 },
2746         [GCC_BLSP1_UART2_BCR] = { 0x0700 },
2747         [GCC_BLSP1_QUP3_BCR] = { 0x0740 },
2748         [GCC_BLSP1_UART3_BCR] = { 0x0780 },
2749         [GCC_BLSP1_QUP4_BCR] = { 0x07c0 },
2750         [GCC_BLSP1_UART4_BCR] = { 0x0800 },
2751         [GCC_BLSP1_QUP5_BCR] = { 0x0840 },
2752         [GCC_BLSP1_UART5_BCR] = { 0x0880 },
2753         [GCC_BLSP1_QUP6_BCR] = { 0x08c0 },
2754         [GCC_BLSP1_UART6_BCR] = { 0x0900 },
2755         [GCC_BLSP2_BCR] = { 0x0940 },
2756         [GCC_BLSP2_QUP1_BCR] = { 0x0980 },
2757         [GCC_BLSP2_UART1_BCR] = { 0x09c0 },
2758         [GCC_BLSP2_QUP2_BCR] = { 0x0a00 },
2759         [GCC_BLSP2_UART2_BCR] = { 0x0a40 },
2760         [GCC_BLSP2_QUP3_BCR] = { 0x0a80 },
2761         [GCC_BLSP2_UART3_BCR] = { 0x0ac0 },
2762         [GCC_BLSP2_QUP4_BCR] = { 0x0b00 },
2763         [GCC_BLSP2_UART4_BCR] = { 0x0b40 },
2764         [GCC_BLSP2_QUP5_BCR] = { 0x0b80 },
2765         [GCC_BLSP2_UART5_BCR] = { 0x0bc0 },
2766         [GCC_BLSP2_QUP6_BCR] = { 0x0c00 },
2767         [GCC_BLSP2_UART6_BCR] = { 0x0c40 },
2768         [GCC_PDM_BCR] = { 0x0cc0 },
2769         [GCC_BAM_DMA_BCR] = { 0x0d40 },
2770         [GCC_TSIF_BCR] = { 0x0d80 },
2771         [GCC_TCSR_BCR] = { 0x0dc0 },
2772         [GCC_BOOT_ROM_BCR] = { 0x0e00 },
2773         [GCC_MSG_RAM_BCR] = { 0x0e40 },
2774         [GCC_TLMM_BCR] = { 0x0e80 },
2775         [GCC_MPM_BCR] = { 0x0ec0 },
2776         [GCC_SEC_CTRL_BCR] = { 0x0f40 },
2777         [GCC_SPMI_BCR] = { 0x0fc0 },
2778         [GCC_SPDM_BCR] = { 0x1000 },
2779         [GCC_CE1_BCR] = { 0x1040 },
2780         [GCC_CE2_BCR] = { 0x1080 },
2781         [GCC_BIMC_BCR] = { 0x1100 },
2782         [GCC_MPM_NON_AHB_RESET] = { 0x0ec4, 2 },
2783         [GCC_MPM_AHB_RESET] = { 0x0ec4, 1 },
2784         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x1240 },
2785         [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x1248 },
2786         [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x1280 },
2787         [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x1288 },
2788         [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x1290 },
2789         [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x1298 },
2790         [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x12a0 },
2791         [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x12c0 },
2792         [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x12c8 },
2793         [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x12d0 },
2794         [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x12d8 },
2795         [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x12e0 },
2796         [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x12e8 },
2797         [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x12f0 },
2798         [GCC_DEHR_BCR] = { 0x1300 },
2799         [GCC_RBCPR_BCR] = { 0x1380 },
2800         [GCC_MSS_RESTART] = { 0x1680 },
2801         [GCC_LPASS_RESTART] = { 0x16c0 },
2802         [GCC_WCSS_RESTART] = { 0x1700 },
2803         [GCC_VENUS_RESTART] = { 0x1740 },
2804 };
2805
2806 static struct gdsc *gcc_msm8974_gdscs[] = {
2807         [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc,
2808 };
2809
2810 static const struct regmap_config gcc_msm8974_regmap_config = {
2811         .reg_bits       = 32,
2812         .reg_stride     = 4,
2813         .val_bits       = 32,
2814         .max_register   = 0x1fc0,
2815         .fast_io        = true,
2816 };
2817
2818 static const struct qcom_cc_desc gcc_msm8974_desc = {
2819         .config = &gcc_msm8974_regmap_config,
2820         .clks = gcc_msm8974_clocks,
2821         .num_clks = ARRAY_SIZE(gcc_msm8974_clocks),
2822         .resets = gcc_msm8974_resets,
2823         .num_resets = ARRAY_SIZE(gcc_msm8974_resets),
2824         .gdscs = gcc_msm8974_gdscs,
2825         .num_gdscs = ARRAY_SIZE(gcc_msm8974_gdscs),
2826 };
2827
2828 static const struct of_device_id gcc_msm8974_match_table[] = {
2829         { .compatible = "qcom,gcc-msm8226", .data = &gcc_msm8226_desc },
2830         { .compatible = "qcom,gcc-msm8974", .data = &gcc_msm8974_desc },
2831         { .compatible = "qcom,gcc-msm8974pro", .data = &gcc_msm8974_desc },
2832         { .compatible = "qcom,gcc-msm8974pro-ac", .data = &gcc_msm8974_desc },
2833         { }
2834 };
2835 MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table);
2836
2837 static void msm8226_clock_override(void)
2838 {
2839         ce1_clk_src.freq_tbl = ftbl_gcc_ce1_clk_msm8226;
2840         gp1_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226;
2841         gp2_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226;
2842         gp3_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226;
2843 }
2844
2845 static void msm8974_pro_clock_override(void)
2846 {
2847         sdcc1_apps_clk_src_init.parent_names = gcc_xo_gpll0_gpll4;
2848         sdcc1_apps_clk_src_init.num_parents = 3;
2849         sdcc1_apps_clk_src.freq_tbl = ftbl_gcc_sdcc1_apps_clk_pro;
2850         sdcc1_apps_clk_src.parent_map = gcc_xo_gpll0_gpll4_map;
2851
2852         gcc_msm8974_clocks[GPLL4] = &gpll4.clkr;
2853         gcc_msm8974_clocks[GPLL4_VOTE] = &gpll4_vote;
2854         gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_SLEEP_CLK] =
2855                 &gcc_sdcc1_cdccal_sleep_clk.clkr;
2856         gcc_msm8974_clocks[GCC_SDCC1_CDCCAL_FF_CLK] =
2857                 &gcc_sdcc1_cdccal_ff_clk.clkr;
2858 }
2859
2860 static int gcc_msm8974_probe(struct platform_device *pdev)
2861 {
2862         int ret;
2863         struct device *dev = &pdev->dev;
2864         const struct of_device_id *id;
2865
2866         id = of_match_device(gcc_msm8974_match_table, dev);
2867         if (!id)
2868                 return -ENODEV;
2869
2870         if (!of_device_is_compatible(dev->of_node, "qcom,gcc-msm8974")) {
2871                 if (id->data == &gcc_msm8226_desc)
2872                         msm8226_clock_override();
2873                 else
2874                         msm8974_pro_clock_override();
2875         }
2876
2877         ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000);
2878         if (ret)
2879                 return ret;
2880
2881         ret = qcom_cc_register_sleep_clk(dev);
2882         if (ret)
2883                 return ret;
2884
2885         return qcom_cc_probe(pdev, &gcc_msm8974_desc);
2886 }
2887
2888 static struct platform_driver gcc_msm8974_driver = {
2889         .probe          = gcc_msm8974_probe,
2890         .driver         = {
2891                 .name   = "gcc-msm8974",
2892                 .of_match_table = gcc_msm8974_match_table,
2893         },
2894 };
2895
2896 static int __init gcc_msm8974_init(void)
2897 {
2898         return platform_driver_register(&gcc_msm8974_driver);
2899 }
2900 core_initcall(gcc_msm8974_init);
2901
2902 static void __exit gcc_msm8974_exit(void)
2903 {
2904         platform_driver_unregister(&gcc_msm8974_driver);
2905 }
2906 module_exit(gcc_msm8974_exit);
2907
2908 MODULE_DESCRIPTION("QCOM GCC MSM8974 Driver");
2909 MODULE_LICENSE("GPL v2");
2910 MODULE_ALIAS("platform:gcc-msm8974");