2 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
26 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
29 #include "clk-regmap.h"
32 #include "clk-branch.h"
35 static struct clk_pll pll3 = {
43 .clkr.hw.init = &(struct clk_init_data){
45 .parent_names = (const char *[]){ "pxo" },
51 static struct clk_regmap pll4_vote = {
53 .enable_mask = BIT(4),
54 .hw.init = &(struct clk_init_data){
56 .parent_names = (const char *[]){ "pll4" },
58 .ops = &clk_pll_vote_ops,
62 static struct clk_pll pll8 = {
70 .clkr.hw.init = &(struct clk_init_data){
72 .parent_names = (const char *[]){ "pxo" },
78 static struct clk_regmap pll8_vote = {
80 .enable_mask = BIT(8),
81 .hw.init = &(struct clk_init_data){
83 .parent_names = (const char *[]){ "pll8" },
85 .ops = &clk_pll_vote_ops,
89 static struct clk_pll pll14 = {
97 .clkr.hw.init = &(struct clk_init_data){
99 .parent_names = (const char *[]){ "pxo" },
105 static struct clk_regmap pll14_vote = {
106 .enable_reg = 0x34c0,
107 .enable_mask = BIT(14),
108 .hw.init = &(struct clk_init_data){
109 .name = "pll14_vote",
110 .parent_names = (const char *[]){ "pll14" },
112 .ops = &clk_pll_vote_ops,
123 static const struct parent_map gcc_pxo_pll8_map[] = {
128 static const char * const gcc_pxo_pll8[] = {
133 static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
139 static const char * const gcc_pxo_pll8_cxo[] = {
145 static const struct parent_map gcc_pxo_pll8_pll3_map[] = {
151 static const char * const gcc_pxo_pll8_pll3[] = {
157 static struct freq_tbl clk_tbl_gsbi_uart[] = {
158 { 1843200, P_PLL8, 2, 6, 625 },
159 { 3686400, P_PLL8, 2, 12, 625 },
160 { 7372800, P_PLL8, 2, 24, 625 },
161 { 14745600, P_PLL8, 2, 48, 625 },
162 { 16000000, P_PLL8, 4, 1, 6 },
163 { 24000000, P_PLL8, 4, 1, 4 },
164 { 32000000, P_PLL8, 4, 1, 3 },
165 { 40000000, P_PLL8, 1, 5, 48 },
166 { 46400000, P_PLL8, 1, 29, 240 },
167 { 48000000, P_PLL8, 4, 1, 2 },
168 { 51200000, P_PLL8, 1, 2, 15 },
169 { 56000000, P_PLL8, 1, 7, 48 },
170 { 58982400, P_PLL8, 1, 96, 625 },
171 { 64000000, P_PLL8, 2, 1, 3 },
175 static struct clk_rcg gsbi1_uart_src = {
180 .mnctr_reset_bit = 7,
181 .mnctr_mode_shift = 5,
192 .parent_map = gcc_pxo_pll8_map,
194 .freq_tbl = clk_tbl_gsbi_uart,
196 .enable_reg = 0x29d4,
197 .enable_mask = BIT(11),
198 .hw.init = &(struct clk_init_data){
199 .name = "gsbi1_uart_src",
200 .parent_names = gcc_pxo_pll8,
203 .flags = CLK_SET_PARENT_GATE,
208 static struct clk_branch gsbi1_uart_clk = {
212 .enable_reg = 0x29d4,
213 .enable_mask = BIT(9),
214 .hw.init = &(struct clk_init_data){
215 .name = "gsbi1_uart_clk",
216 .parent_names = (const char *[]){
220 .ops = &clk_branch_ops,
221 .flags = CLK_SET_RATE_PARENT,
226 static struct clk_rcg gsbi2_uart_src = {
231 .mnctr_reset_bit = 7,
232 .mnctr_mode_shift = 5,
243 .parent_map = gcc_pxo_pll8_map,
245 .freq_tbl = clk_tbl_gsbi_uart,
247 .enable_reg = 0x29f4,
248 .enable_mask = BIT(11),
249 .hw.init = &(struct clk_init_data){
250 .name = "gsbi2_uart_src",
251 .parent_names = gcc_pxo_pll8,
254 .flags = CLK_SET_PARENT_GATE,
259 static struct clk_branch gsbi2_uart_clk = {
263 .enable_reg = 0x29f4,
264 .enable_mask = BIT(9),
265 .hw.init = &(struct clk_init_data){
266 .name = "gsbi2_uart_clk",
267 .parent_names = (const char *[]){
271 .ops = &clk_branch_ops,
272 .flags = CLK_SET_RATE_PARENT,
277 static struct clk_rcg gsbi3_uart_src = {
282 .mnctr_reset_bit = 7,
283 .mnctr_mode_shift = 5,
294 .parent_map = gcc_pxo_pll8_map,
296 .freq_tbl = clk_tbl_gsbi_uart,
298 .enable_reg = 0x2a14,
299 .enable_mask = BIT(11),
300 .hw.init = &(struct clk_init_data){
301 .name = "gsbi3_uart_src",
302 .parent_names = gcc_pxo_pll8,
305 .flags = CLK_SET_PARENT_GATE,
310 static struct clk_branch gsbi3_uart_clk = {
314 .enable_reg = 0x2a14,
315 .enable_mask = BIT(9),
316 .hw.init = &(struct clk_init_data){
317 .name = "gsbi3_uart_clk",
318 .parent_names = (const char *[]){
322 .ops = &clk_branch_ops,
323 .flags = CLK_SET_RATE_PARENT,
328 static struct clk_rcg gsbi4_uart_src = {
333 .mnctr_reset_bit = 7,
334 .mnctr_mode_shift = 5,
345 .parent_map = gcc_pxo_pll8_map,
347 .freq_tbl = clk_tbl_gsbi_uart,
349 .enable_reg = 0x2a34,
350 .enable_mask = BIT(11),
351 .hw.init = &(struct clk_init_data){
352 .name = "gsbi4_uart_src",
353 .parent_names = gcc_pxo_pll8,
356 .flags = CLK_SET_PARENT_GATE,
361 static struct clk_branch gsbi4_uart_clk = {
365 .enable_reg = 0x2a34,
366 .enable_mask = BIT(9),
367 .hw.init = &(struct clk_init_data){
368 .name = "gsbi4_uart_clk",
369 .parent_names = (const char *[]){
373 .ops = &clk_branch_ops,
374 .flags = CLK_SET_RATE_PARENT,
379 static struct clk_rcg gsbi5_uart_src = {
384 .mnctr_reset_bit = 7,
385 .mnctr_mode_shift = 5,
396 .parent_map = gcc_pxo_pll8_map,
398 .freq_tbl = clk_tbl_gsbi_uart,
400 .enable_reg = 0x2a54,
401 .enable_mask = BIT(11),
402 .hw.init = &(struct clk_init_data){
403 .name = "gsbi5_uart_src",
404 .parent_names = gcc_pxo_pll8,
407 .flags = CLK_SET_PARENT_GATE,
412 static struct clk_branch gsbi5_uart_clk = {
416 .enable_reg = 0x2a54,
417 .enable_mask = BIT(9),
418 .hw.init = &(struct clk_init_data){
419 .name = "gsbi5_uart_clk",
420 .parent_names = (const char *[]){
424 .ops = &clk_branch_ops,
425 .flags = CLK_SET_RATE_PARENT,
430 static struct clk_rcg gsbi6_uart_src = {
435 .mnctr_reset_bit = 7,
436 .mnctr_mode_shift = 5,
447 .parent_map = gcc_pxo_pll8_map,
449 .freq_tbl = clk_tbl_gsbi_uart,
451 .enable_reg = 0x2a74,
452 .enable_mask = BIT(11),
453 .hw.init = &(struct clk_init_data){
454 .name = "gsbi6_uart_src",
455 .parent_names = gcc_pxo_pll8,
458 .flags = CLK_SET_PARENT_GATE,
463 static struct clk_branch gsbi6_uart_clk = {
467 .enable_reg = 0x2a74,
468 .enable_mask = BIT(9),
469 .hw.init = &(struct clk_init_data){
470 .name = "gsbi6_uart_clk",
471 .parent_names = (const char *[]){
475 .ops = &clk_branch_ops,
476 .flags = CLK_SET_RATE_PARENT,
481 static struct clk_rcg gsbi7_uart_src = {
486 .mnctr_reset_bit = 7,
487 .mnctr_mode_shift = 5,
498 .parent_map = gcc_pxo_pll8_map,
500 .freq_tbl = clk_tbl_gsbi_uart,
502 .enable_reg = 0x2a94,
503 .enable_mask = BIT(11),
504 .hw.init = &(struct clk_init_data){
505 .name = "gsbi7_uart_src",
506 .parent_names = gcc_pxo_pll8,
509 .flags = CLK_SET_PARENT_GATE,
514 static struct clk_branch gsbi7_uart_clk = {
518 .enable_reg = 0x2a94,
519 .enable_mask = BIT(9),
520 .hw.init = &(struct clk_init_data){
521 .name = "gsbi7_uart_clk",
522 .parent_names = (const char *[]){
526 .ops = &clk_branch_ops,
527 .flags = CLK_SET_RATE_PARENT,
532 static struct clk_rcg gsbi8_uart_src = {
537 .mnctr_reset_bit = 7,
538 .mnctr_mode_shift = 5,
549 .parent_map = gcc_pxo_pll8_map,
551 .freq_tbl = clk_tbl_gsbi_uart,
553 .enable_reg = 0x2ab4,
554 .enable_mask = BIT(11),
555 .hw.init = &(struct clk_init_data){
556 .name = "gsbi8_uart_src",
557 .parent_names = gcc_pxo_pll8,
560 .flags = CLK_SET_PARENT_GATE,
565 static struct clk_branch gsbi8_uart_clk = {
569 .enable_reg = 0x2ab4,
570 .enable_mask = BIT(9),
571 .hw.init = &(struct clk_init_data){
572 .name = "gsbi8_uart_clk",
573 .parent_names = (const char *[]){ "gsbi8_uart_src" },
575 .ops = &clk_branch_ops,
576 .flags = CLK_SET_RATE_PARENT,
581 static struct clk_rcg gsbi9_uart_src = {
586 .mnctr_reset_bit = 7,
587 .mnctr_mode_shift = 5,
598 .parent_map = gcc_pxo_pll8_map,
600 .freq_tbl = clk_tbl_gsbi_uart,
602 .enable_reg = 0x2ad4,
603 .enable_mask = BIT(11),
604 .hw.init = &(struct clk_init_data){
605 .name = "gsbi9_uart_src",
606 .parent_names = gcc_pxo_pll8,
609 .flags = CLK_SET_PARENT_GATE,
614 static struct clk_branch gsbi9_uart_clk = {
618 .enable_reg = 0x2ad4,
619 .enable_mask = BIT(9),
620 .hw.init = &(struct clk_init_data){
621 .name = "gsbi9_uart_clk",
622 .parent_names = (const char *[]){ "gsbi9_uart_src" },
624 .ops = &clk_branch_ops,
625 .flags = CLK_SET_RATE_PARENT,
630 static struct clk_rcg gsbi10_uart_src = {
635 .mnctr_reset_bit = 7,
636 .mnctr_mode_shift = 5,
647 .parent_map = gcc_pxo_pll8_map,
649 .freq_tbl = clk_tbl_gsbi_uart,
651 .enable_reg = 0x2af4,
652 .enable_mask = BIT(11),
653 .hw.init = &(struct clk_init_data){
654 .name = "gsbi10_uart_src",
655 .parent_names = gcc_pxo_pll8,
658 .flags = CLK_SET_PARENT_GATE,
663 static struct clk_branch gsbi10_uart_clk = {
667 .enable_reg = 0x2af4,
668 .enable_mask = BIT(9),
669 .hw.init = &(struct clk_init_data){
670 .name = "gsbi10_uart_clk",
671 .parent_names = (const char *[]){ "gsbi10_uart_src" },
673 .ops = &clk_branch_ops,
674 .flags = CLK_SET_RATE_PARENT,
679 static struct clk_rcg gsbi11_uart_src = {
684 .mnctr_reset_bit = 7,
685 .mnctr_mode_shift = 5,
696 .parent_map = gcc_pxo_pll8_map,
698 .freq_tbl = clk_tbl_gsbi_uart,
700 .enable_reg = 0x2b14,
701 .enable_mask = BIT(11),
702 .hw.init = &(struct clk_init_data){
703 .name = "gsbi11_uart_src",
704 .parent_names = gcc_pxo_pll8,
707 .flags = CLK_SET_PARENT_GATE,
712 static struct clk_branch gsbi11_uart_clk = {
716 .enable_reg = 0x2b14,
717 .enable_mask = BIT(9),
718 .hw.init = &(struct clk_init_data){
719 .name = "gsbi11_uart_clk",
720 .parent_names = (const char *[]){ "gsbi11_uart_src" },
722 .ops = &clk_branch_ops,
723 .flags = CLK_SET_RATE_PARENT,
728 static struct clk_rcg gsbi12_uart_src = {
733 .mnctr_reset_bit = 7,
734 .mnctr_mode_shift = 5,
745 .parent_map = gcc_pxo_pll8_map,
747 .freq_tbl = clk_tbl_gsbi_uart,
749 .enable_reg = 0x2b34,
750 .enable_mask = BIT(11),
751 .hw.init = &(struct clk_init_data){
752 .name = "gsbi12_uart_src",
753 .parent_names = gcc_pxo_pll8,
756 .flags = CLK_SET_PARENT_GATE,
761 static struct clk_branch gsbi12_uart_clk = {
765 .enable_reg = 0x2b34,
766 .enable_mask = BIT(9),
767 .hw.init = &(struct clk_init_data){
768 .name = "gsbi12_uart_clk",
769 .parent_names = (const char *[]){ "gsbi12_uart_src" },
771 .ops = &clk_branch_ops,
772 .flags = CLK_SET_RATE_PARENT,
777 static struct freq_tbl clk_tbl_gsbi_qup[] = {
778 { 1100000, P_PXO, 1, 2, 49 },
779 { 5400000, P_PXO, 1, 1, 5 },
780 { 10800000, P_PXO, 1, 2, 5 },
781 { 15060000, P_PLL8, 1, 2, 51 },
782 { 24000000, P_PLL8, 4, 1, 4 },
783 { 25600000, P_PLL8, 1, 1, 15 },
784 { 27000000, P_PXO, 1, 0, 0 },
785 { 48000000, P_PLL8, 4, 1, 2 },
786 { 51200000, P_PLL8, 1, 2, 15 },
790 static struct clk_rcg gsbi1_qup_src = {
795 .mnctr_reset_bit = 7,
796 .mnctr_mode_shift = 5,
807 .parent_map = gcc_pxo_pll8_map,
809 .freq_tbl = clk_tbl_gsbi_qup,
811 .enable_reg = 0x29cc,
812 .enable_mask = BIT(11),
813 .hw.init = &(struct clk_init_data){
814 .name = "gsbi1_qup_src",
815 .parent_names = gcc_pxo_pll8,
818 .flags = CLK_SET_PARENT_GATE,
823 static struct clk_branch gsbi1_qup_clk = {
827 .enable_reg = 0x29cc,
828 .enable_mask = BIT(9),
829 .hw.init = &(struct clk_init_data){
830 .name = "gsbi1_qup_clk",
831 .parent_names = (const char *[]){ "gsbi1_qup_src" },
833 .ops = &clk_branch_ops,
834 .flags = CLK_SET_RATE_PARENT,
839 static struct clk_rcg gsbi2_qup_src = {
844 .mnctr_reset_bit = 7,
845 .mnctr_mode_shift = 5,
856 .parent_map = gcc_pxo_pll8_map,
858 .freq_tbl = clk_tbl_gsbi_qup,
860 .enable_reg = 0x29ec,
861 .enable_mask = BIT(11),
862 .hw.init = &(struct clk_init_data){
863 .name = "gsbi2_qup_src",
864 .parent_names = gcc_pxo_pll8,
867 .flags = CLK_SET_PARENT_GATE,
872 static struct clk_branch gsbi2_qup_clk = {
876 .enable_reg = 0x29ec,
877 .enable_mask = BIT(9),
878 .hw.init = &(struct clk_init_data){
879 .name = "gsbi2_qup_clk",
880 .parent_names = (const char *[]){ "gsbi2_qup_src" },
882 .ops = &clk_branch_ops,
883 .flags = CLK_SET_RATE_PARENT,
888 static struct clk_rcg gsbi3_qup_src = {
893 .mnctr_reset_bit = 7,
894 .mnctr_mode_shift = 5,
905 .parent_map = gcc_pxo_pll8_map,
907 .freq_tbl = clk_tbl_gsbi_qup,
909 .enable_reg = 0x2a0c,
910 .enable_mask = BIT(11),
911 .hw.init = &(struct clk_init_data){
912 .name = "gsbi3_qup_src",
913 .parent_names = gcc_pxo_pll8,
916 .flags = CLK_SET_PARENT_GATE,
921 static struct clk_branch gsbi3_qup_clk = {
925 .enable_reg = 0x2a0c,
926 .enable_mask = BIT(9),
927 .hw.init = &(struct clk_init_data){
928 .name = "gsbi3_qup_clk",
929 .parent_names = (const char *[]){ "gsbi3_qup_src" },
931 .ops = &clk_branch_ops,
932 .flags = CLK_SET_RATE_PARENT,
937 static struct clk_rcg gsbi4_qup_src = {
942 .mnctr_reset_bit = 7,
943 .mnctr_mode_shift = 5,
954 .parent_map = gcc_pxo_pll8_map,
956 .freq_tbl = clk_tbl_gsbi_qup,
958 .enable_reg = 0x2a2c,
959 .enable_mask = BIT(11),
960 .hw.init = &(struct clk_init_data){
961 .name = "gsbi4_qup_src",
962 .parent_names = gcc_pxo_pll8,
965 .flags = CLK_SET_PARENT_GATE,
970 static struct clk_branch gsbi4_qup_clk = {
974 .enable_reg = 0x2a2c,
975 .enable_mask = BIT(9),
976 .hw.init = &(struct clk_init_data){
977 .name = "gsbi4_qup_clk",
978 .parent_names = (const char *[]){ "gsbi4_qup_src" },
980 .ops = &clk_branch_ops,
981 .flags = CLK_SET_RATE_PARENT,
986 static struct clk_rcg gsbi5_qup_src = {
991 .mnctr_reset_bit = 7,
992 .mnctr_mode_shift = 5,
1003 .parent_map = gcc_pxo_pll8_map,
1005 .freq_tbl = clk_tbl_gsbi_qup,
1007 .enable_reg = 0x2a4c,
1008 .enable_mask = BIT(11),
1009 .hw.init = &(struct clk_init_data){
1010 .name = "gsbi5_qup_src",
1011 .parent_names = gcc_pxo_pll8,
1013 .ops = &clk_rcg_ops,
1014 .flags = CLK_SET_PARENT_GATE,
1019 static struct clk_branch gsbi5_qup_clk = {
1023 .enable_reg = 0x2a4c,
1024 .enable_mask = BIT(9),
1025 .hw.init = &(struct clk_init_data){
1026 .name = "gsbi5_qup_clk",
1027 .parent_names = (const char *[]){ "gsbi5_qup_src" },
1029 .ops = &clk_branch_ops,
1030 .flags = CLK_SET_RATE_PARENT,
1035 static struct clk_rcg gsbi6_qup_src = {
1040 .mnctr_reset_bit = 7,
1041 .mnctr_mode_shift = 5,
1052 .parent_map = gcc_pxo_pll8_map,
1054 .freq_tbl = clk_tbl_gsbi_qup,
1056 .enable_reg = 0x2a6c,
1057 .enable_mask = BIT(11),
1058 .hw.init = &(struct clk_init_data){
1059 .name = "gsbi6_qup_src",
1060 .parent_names = gcc_pxo_pll8,
1062 .ops = &clk_rcg_ops,
1063 .flags = CLK_SET_PARENT_GATE,
1068 static struct clk_branch gsbi6_qup_clk = {
1072 .enable_reg = 0x2a6c,
1073 .enable_mask = BIT(9),
1074 .hw.init = &(struct clk_init_data){
1075 .name = "gsbi6_qup_clk",
1076 .parent_names = (const char *[]){ "gsbi6_qup_src" },
1078 .ops = &clk_branch_ops,
1079 .flags = CLK_SET_RATE_PARENT,
1084 static struct clk_rcg gsbi7_qup_src = {
1089 .mnctr_reset_bit = 7,
1090 .mnctr_mode_shift = 5,
1101 .parent_map = gcc_pxo_pll8_map,
1103 .freq_tbl = clk_tbl_gsbi_qup,
1105 .enable_reg = 0x2a8c,
1106 .enable_mask = BIT(11),
1107 .hw.init = &(struct clk_init_data){
1108 .name = "gsbi7_qup_src",
1109 .parent_names = gcc_pxo_pll8,
1111 .ops = &clk_rcg_ops,
1112 .flags = CLK_SET_PARENT_GATE,
1117 static struct clk_branch gsbi7_qup_clk = {
1121 .enable_reg = 0x2a8c,
1122 .enable_mask = BIT(9),
1123 .hw.init = &(struct clk_init_data){
1124 .name = "gsbi7_qup_clk",
1125 .parent_names = (const char *[]){ "gsbi7_qup_src" },
1127 .ops = &clk_branch_ops,
1128 .flags = CLK_SET_RATE_PARENT,
1133 static struct clk_rcg gsbi8_qup_src = {
1138 .mnctr_reset_bit = 7,
1139 .mnctr_mode_shift = 5,
1150 .parent_map = gcc_pxo_pll8_map,
1152 .freq_tbl = clk_tbl_gsbi_qup,
1154 .enable_reg = 0x2aac,
1155 .enable_mask = BIT(11),
1156 .hw.init = &(struct clk_init_data){
1157 .name = "gsbi8_qup_src",
1158 .parent_names = gcc_pxo_pll8,
1160 .ops = &clk_rcg_ops,
1161 .flags = CLK_SET_PARENT_GATE,
1166 static struct clk_branch gsbi8_qup_clk = {
1170 .enable_reg = 0x2aac,
1171 .enable_mask = BIT(9),
1172 .hw.init = &(struct clk_init_data){
1173 .name = "gsbi8_qup_clk",
1174 .parent_names = (const char *[]){ "gsbi8_qup_src" },
1176 .ops = &clk_branch_ops,
1177 .flags = CLK_SET_RATE_PARENT,
1182 static struct clk_rcg gsbi9_qup_src = {
1187 .mnctr_reset_bit = 7,
1188 .mnctr_mode_shift = 5,
1199 .parent_map = gcc_pxo_pll8_map,
1201 .freq_tbl = clk_tbl_gsbi_qup,
1203 .enable_reg = 0x2acc,
1204 .enable_mask = BIT(11),
1205 .hw.init = &(struct clk_init_data){
1206 .name = "gsbi9_qup_src",
1207 .parent_names = gcc_pxo_pll8,
1209 .ops = &clk_rcg_ops,
1210 .flags = CLK_SET_PARENT_GATE,
1215 static struct clk_branch gsbi9_qup_clk = {
1219 .enable_reg = 0x2acc,
1220 .enable_mask = BIT(9),
1221 .hw.init = &(struct clk_init_data){
1222 .name = "gsbi9_qup_clk",
1223 .parent_names = (const char *[]){ "gsbi9_qup_src" },
1225 .ops = &clk_branch_ops,
1226 .flags = CLK_SET_RATE_PARENT,
1231 static struct clk_rcg gsbi10_qup_src = {
1236 .mnctr_reset_bit = 7,
1237 .mnctr_mode_shift = 5,
1248 .parent_map = gcc_pxo_pll8_map,
1250 .freq_tbl = clk_tbl_gsbi_qup,
1252 .enable_reg = 0x2aec,
1253 .enable_mask = BIT(11),
1254 .hw.init = &(struct clk_init_data){
1255 .name = "gsbi10_qup_src",
1256 .parent_names = gcc_pxo_pll8,
1258 .ops = &clk_rcg_ops,
1259 .flags = CLK_SET_PARENT_GATE,
1264 static struct clk_branch gsbi10_qup_clk = {
1268 .enable_reg = 0x2aec,
1269 .enable_mask = BIT(9),
1270 .hw.init = &(struct clk_init_data){
1271 .name = "gsbi10_qup_clk",
1272 .parent_names = (const char *[]){ "gsbi10_qup_src" },
1274 .ops = &clk_branch_ops,
1275 .flags = CLK_SET_RATE_PARENT,
1280 static struct clk_rcg gsbi11_qup_src = {
1285 .mnctr_reset_bit = 7,
1286 .mnctr_mode_shift = 5,
1297 .parent_map = gcc_pxo_pll8_map,
1299 .freq_tbl = clk_tbl_gsbi_qup,
1301 .enable_reg = 0x2b0c,
1302 .enable_mask = BIT(11),
1303 .hw.init = &(struct clk_init_data){
1304 .name = "gsbi11_qup_src",
1305 .parent_names = gcc_pxo_pll8,
1307 .ops = &clk_rcg_ops,
1308 .flags = CLK_SET_PARENT_GATE,
1313 static struct clk_branch gsbi11_qup_clk = {
1317 .enable_reg = 0x2b0c,
1318 .enable_mask = BIT(9),
1319 .hw.init = &(struct clk_init_data){
1320 .name = "gsbi11_qup_clk",
1321 .parent_names = (const char *[]){ "gsbi11_qup_src" },
1323 .ops = &clk_branch_ops,
1324 .flags = CLK_SET_RATE_PARENT,
1329 static struct clk_rcg gsbi12_qup_src = {
1334 .mnctr_reset_bit = 7,
1335 .mnctr_mode_shift = 5,
1346 .parent_map = gcc_pxo_pll8_map,
1348 .freq_tbl = clk_tbl_gsbi_qup,
1350 .enable_reg = 0x2b2c,
1351 .enable_mask = BIT(11),
1352 .hw.init = &(struct clk_init_data){
1353 .name = "gsbi12_qup_src",
1354 .parent_names = gcc_pxo_pll8,
1356 .ops = &clk_rcg_ops,
1357 .flags = CLK_SET_PARENT_GATE,
1362 static struct clk_branch gsbi12_qup_clk = {
1366 .enable_reg = 0x2b2c,
1367 .enable_mask = BIT(9),
1368 .hw.init = &(struct clk_init_data){
1369 .name = "gsbi12_qup_clk",
1370 .parent_names = (const char *[]){ "gsbi12_qup_src" },
1372 .ops = &clk_branch_ops,
1373 .flags = CLK_SET_RATE_PARENT,
1378 static const struct freq_tbl clk_tbl_gp[] = {
1379 { 9600000, P_CXO, 2, 0, 0 },
1380 { 13500000, P_PXO, 2, 0, 0 },
1381 { 19200000, P_CXO, 1, 0, 0 },
1382 { 27000000, P_PXO, 1, 0, 0 },
1383 { 64000000, P_PLL8, 2, 1, 3 },
1384 { 76800000, P_PLL8, 1, 1, 5 },
1385 { 96000000, P_PLL8, 4, 0, 0 },
1386 { 128000000, P_PLL8, 3, 0, 0 },
1387 { 192000000, P_PLL8, 2, 0, 0 },
1391 static struct clk_rcg gp0_src = {
1396 .mnctr_reset_bit = 7,
1397 .mnctr_mode_shift = 5,
1408 .parent_map = gcc_pxo_pll8_cxo_map,
1410 .freq_tbl = clk_tbl_gp,
1412 .enable_reg = 0x2d24,
1413 .enable_mask = BIT(11),
1414 .hw.init = &(struct clk_init_data){
1416 .parent_names = gcc_pxo_pll8_cxo,
1418 .ops = &clk_rcg_ops,
1419 .flags = CLK_SET_PARENT_GATE,
1424 static struct clk_branch gp0_clk = {
1428 .enable_reg = 0x2d24,
1429 .enable_mask = BIT(9),
1430 .hw.init = &(struct clk_init_data){
1432 .parent_names = (const char *[]){ "gp0_src" },
1434 .ops = &clk_branch_ops,
1435 .flags = CLK_SET_RATE_PARENT,
1440 static struct clk_rcg gp1_src = {
1445 .mnctr_reset_bit = 7,
1446 .mnctr_mode_shift = 5,
1457 .parent_map = gcc_pxo_pll8_cxo_map,
1459 .freq_tbl = clk_tbl_gp,
1461 .enable_reg = 0x2d44,
1462 .enable_mask = BIT(11),
1463 .hw.init = &(struct clk_init_data){
1465 .parent_names = gcc_pxo_pll8_cxo,
1467 .ops = &clk_rcg_ops,
1468 .flags = CLK_SET_RATE_GATE,
1473 static struct clk_branch gp1_clk = {
1477 .enable_reg = 0x2d44,
1478 .enable_mask = BIT(9),
1479 .hw.init = &(struct clk_init_data){
1481 .parent_names = (const char *[]){ "gp1_src" },
1483 .ops = &clk_branch_ops,
1484 .flags = CLK_SET_RATE_PARENT,
1489 static struct clk_rcg gp2_src = {
1494 .mnctr_reset_bit = 7,
1495 .mnctr_mode_shift = 5,
1506 .parent_map = gcc_pxo_pll8_cxo_map,
1508 .freq_tbl = clk_tbl_gp,
1510 .enable_reg = 0x2d64,
1511 .enable_mask = BIT(11),
1512 .hw.init = &(struct clk_init_data){
1514 .parent_names = gcc_pxo_pll8_cxo,
1516 .ops = &clk_rcg_ops,
1517 .flags = CLK_SET_RATE_GATE,
1522 static struct clk_branch gp2_clk = {
1526 .enable_reg = 0x2d64,
1527 .enable_mask = BIT(9),
1528 .hw.init = &(struct clk_init_data){
1530 .parent_names = (const char *[]){ "gp2_src" },
1532 .ops = &clk_branch_ops,
1533 .flags = CLK_SET_RATE_PARENT,
1538 static struct clk_branch pmem_clk = {
1544 .enable_reg = 0x25a0,
1545 .enable_mask = BIT(4),
1546 .hw.init = &(struct clk_init_data){
1548 .ops = &clk_branch_ops,
1549 .flags = CLK_IS_ROOT,
1554 static struct clk_rcg prng_src = {
1562 .parent_map = gcc_pxo_pll8_map,
1565 .hw.init = &(struct clk_init_data){
1567 .parent_names = gcc_pxo_pll8,
1569 .ops = &clk_rcg_ops,
1574 static struct clk_branch prng_clk = {
1576 .halt_check = BRANCH_HALT_VOTED,
1579 .enable_reg = 0x3080,
1580 .enable_mask = BIT(10),
1581 .hw.init = &(struct clk_init_data){
1583 .parent_names = (const char *[]){ "prng_src" },
1585 .ops = &clk_branch_ops,
1590 static const struct freq_tbl clk_tbl_sdc[] = {
1591 { 144000, P_PXO, 3, 2, 125 },
1592 { 400000, P_PLL8, 4, 1, 240 },
1593 { 16000000, P_PLL8, 4, 1, 6 },
1594 { 17070000, P_PLL8, 1, 2, 45 },
1595 { 20210000, P_PLL8, 1, 1, 19 },
1596 { 24000000, P_PLL8, 4, 1, 4 },
1597 { 48000000, P_PLL8, 4, 1, 2 },
1598 { 64000000, P_PLL8, 3, 1, 2 },
1599 { 96000000, P_PLL8, 4, 0, 0 },
1600 { 192000000, P_PLL8, 2, 0, 0 },
1604 static struct clk_rcg sdc1_src = {
1609 .mnctr_reset_bit = 7,
1610 .mnctr_mode_shift = 5,
1621 .parent_map = gcc_pxo_pll8_map,
1623 .freq_tbl = clk_tbl_sdc,
1625 .enable_reg = 0x282c,
1626 .enable_mask = BIT(11),
1627 .hw.init = &(struct clk_init_data){
1629 .parent_names = gcc_pxo_pll8,
1631 .ops = &clk_rcg_ops,
1632 .flags = CLK_SET_RATE_GATE,
1637 static struct clk_branch sdc1_clk = {
1641 .enable_reg = 0x282c,
1642 .enable_mask = BIT(9),
1643 .hw.init = &(struct clk_init_data){
1645 .parent_names = (const char *[]){ "sdc1_src" },
1647 .ops = &clk_branch_ops,
1648 .flags = CLK_SET_RATE_PARENT,
1653 static struct clk_rcg sdc2_src = {
1658 .mnctr_reset_bit = 7,
1659 .mnctr_mode_shift = 5,
1670 .parent_map = gcc_pxo_pll8_map,
1672 .freq_tbl = clk_tbl_sdc,
1674 .enable_reg = 0x284c,
1675 .enable_mask = BIT(11),
1676 .hw.init = &(struct clk_init_data){
1678 .parent_names = gcc_pxo_pll8,
1680 .ops = &clk_rcg_ops,
1681 .flags = CLK_SET_RATE_GATE,
1686 static struct clk_branch sdc2_clk = {
1690 .enable_reg = 0x284c,
1691 .enable_mask = BIT(9),
1692 .hw.init = &(struct clk_init_data){
1694 .parent_names = (const char *[]){ "sdc2_src" },
1696 .ops = &clk_branch_ops,
1697 .flags = CLK_SET_RATE_PARENT,
1702 static struct clk_rcg sdc3_src = {
1707 .mnctr_reset_bit = 7,
1708 .mnctr_mode_shift = 5,
1719 .parent_map = gcc_pxo_pll8_map,
1721 .freq_tbl = clk_tbl_sdc,
1723 .enable_reg = 0x286c,
1724 .enable_mask = BIT(11),
1725 .hw.init = &(struct clk_init_data){
1727 .parent_names = gcc_pxo_pll8,
1729 .ops = &clk_rcg_ops,
1730 .flags = CLK_SET_RATE_GATE,
1735 static struct clk_branch sdc3_clk = {
1739 .enable_reg = 0x286c,
1740 .enable_mask = BIT(9),
1741 .hw.init = &(struct clk_init_data){
1743 .parent_names = (const char *[]){ "sdc3_src" },
1745 .ops = &clk_branch_ops,
1746 .flags = CLK_SET_RATE_PARENT,
1751 static struct clk_rcg sdc4_src = {
1756 .mnctr_reset_bit = 7,
1757 .mnctr_mode_shift = 5,
1768 .parent_map = gcc_pxo_pll8_map,
1770 .freq_tbl = clk_tbl_sdc,
1772 .enable_reg = 0x288c,
1773 .enable_mask = BIT(11),
1774 .hw.init = &(struct clk_init_data){
1776 .parent_names = gcc_pxo_pll8,
1778 .ops = &clk_rcg_ops,
1779 .flags = CLK_SET_RATE_GATE,
1784 static struct clk_branch sdc4_clk = {
1788 .enable_reg = 0x288c,
1789 .enable_mask = BIT(9),
1790 .hw.init = &(struct clk_init_data){
1792 .parent_names = (const char *[]){ "sdc4_src" },
1794 .ops = &clk_branch_ops,
1795 .flags = CLK_SET_RATE_PARENT,
1800 static struct clk_rcg sdc5_src = {
1805 .mnctr_reset_bit = 7,
1806 .mnctr_mode_shift = 5,
1817 .parent_map = gcc_pxo_pll8_map,
1819 .freq_tbl = clk_tbl_sdc,
1821 .enable_reg = 0x28ac,
1822 .enable_mask = BIT(11),
1823 .hw.init = &(struct clk_init_data){
1825 .parent_names = gcc_pxo_pll8,
1827 .ops = &clk_rcg_ops,
1828 .flags = CLK_SET_RATE_GATE,
1833 static struct clk_branch sdc5_clk = {
1837 .enable_reg = 0x28ac,
1838 .enable_mask = BIT(9),
1839 .hw.init = &(struct clk_init_data){
1841 .parent_names = (const char *[]){ "sdc5_src" },
1843 .ops = &clk_branch_ops,
1844 .flags = CLK_SET_RATE_PARENT,
1849 static const struct freq_tbl clk_tbl_tsif_ref[] = {
1850 { 105000, P_PXO, 1, 1, 256 },
1854 static struct clk_rcg tsif_ref_src = {
1859 .mnctr_reset_bit = 7,
1860 .mnctr_mode_shift = 5,
1871 .parent_map = gcc_pxo_pll8_map,
1873 .freq_tbl = clk_tbl_tsif_ref,
1875 .enable_reg = 0x2710,
1876 .enable_mask = BIT(11),
1877 .hw.init = &(struct clk_init_data){
1878 .name = "tsif_ref_src",
1879 .parent_names = gcc_pxo_pll8,
1881 .ops = &clk_rcg_ops,
1882 .flags = CLK_SET_RATE_GATE,
1887 static struct clk_branch tsif_ref_clk = {
1891 .enable_reg = 0x2710,
1892 .enable_mask = BIT(9),
1893 .hw.init = &(struct clk_init_data){
1894 .name = "tsif_ref_clk",
1895 .parent_names = (const char *[]){ "tsif_ref_src" },
1897 .ops = &clk_branch_ops,
1898 .flags = CLK_SET_RATE_PARENT,
1903 static const struct freq_tbl clk_tbl_usb[] = {
1904 { 60000000, P_PLL8, 1, 5, 32 },
1908 static struct clk_rcg usb_hs1_xcvr_src = {
1913 .mnctr_reset_bit = 7,
1914 .mnctr_mode_shift = 5,
1925 .parent_map = gcc_pxo_pll8_map,
1927 .freq_tbl = clk_tbl_usb,
1929 .enable_reg = 0x290c,
1930 .enable_mask = BIT(11),
1931 .hw.init = &(struct clk_init_data){
1932 .name = "usb_hs1_xcvr_src",
1933 .parent_names = gcc_pxo_pll8,
1935 .ops = &clk_rcg_ops,
1936 .flags = CLK_SET_RATE_GATE,
1941 static struct clk_branch usb_hs1_xcvr_clk = {
1945 .enable_reg = 0x290c,
1946 .enable_mask = BIT(9),
1947 .hw.init = &(struct clk_init_data){
1948 .name = "usb_hs1_xcvr_clk",
1949 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
1951 .ops = &clk_branch_ops,
1952 .flags = CLK_SET_RATE_PARENT,
1957 static struct clk_rcg usb_hs3_xcvr_src = {
1962 .mnctr_reset_bit = 7,
1963 .mnctr_mode_shift = 5,
1974 .parent_map = gcc_pxo_pll8_map,
1976 .freq_tbl = clk_tbl_usb,
1978 .enable_reg = 0x370c,
1979 .enable_mask = BIT(11),
1980 .hw.init = &(struct clk_init_data){
1981 .name = "usb_hs3_xcvr_src",
1982 .parent_names = gcc_pxo_pll8,
1984 .ops = &clk_rcg_ops,
1985 .flags = CLK_SET_RATE_GATE,
1990 static struct clk_branch usb_hs3_xcvr_clk = {
1994 .enable_reg = 0x370c,
1995 .enable_mask = BIT(9),
1996 .hw.init = &(struct clk_init_data){
1997 .name = "usb_hs3_xcvr_clk",
1998 .parent_names = (const char *[]){ "usb_hs3_xcvr_src" },
2000 .ops = &clk_branch_ops,
2001 .flags = CLK_SET_RATE_PARENT,
2006 static struct clk_rcg usb_hs4_xcvr_src = {
2011 .mnctr_reset_bit = 7,
2012 .mnctr_mode_shift = 5,
2023 .parent_map = gcc_pxo_pll8_map,
2025 .freq_tbl = clk_tbl_usb,
2027 .enable_reg = 0x372c,
2028 .enable_mask = BIT(11),
2029 .hw.init = &(struct clk_init_data){
2030 .name = "usb_hs4_xcvr_src",
2031 .parent_names = gcc_pxo_pll8,
2033 .ops = &clk_rcg_ops,
2034 .flags = CLK_SET_RATE_GATE,
2039 static struct clk_branch usb_hs4_xcvr_clk = {
2043 .enable_reg = 0x372c,
2044 .enable_mask = BIT(9),
2045 .hw.init = &(struct clk_init_data){
2046 .name = "usb_hs4_xcvr_clk",
2047 .parent_names = (const char *[]){ "usb_hs4_xcvr_src" },
2049 .ops = &clk_branch_ops,
2050 .flags = CLK_SET_RATE_PARENT,
2055 static struct clk_rcg usb_hsic_xcvr_fs_src = {
2060 .mnctr_reset_bit = 7,
2061 .mnctr_mode_shift = 5,
2072 .parent_map = gcc_pxo_pll8_map,
2074 .freq_tbl = clk_tbl_usb,
2076 .enable_reg = 0x2928,
2077 .enable_mask = BIT(11),
2078 .hw.init = &(struct clk_init_data){
2079 .name = "usb_hsic_xcvr_fs_src",
2080 .parent_names = gcc_pxo_pll8,
2082 .ops = &clk_rcg_ops,
2083 .flags = CLK_SET_RATE_GATE,
2088 static const char * const usb_hsic_xcvr_fs_src_p[] = { "usb_hsic_xcvr_fs_src" };
2090 static struct clk_branch usb_hsic_xcvr_fs_clk = {
2094 .enable_reg = 0x2928,
2095 .enable_mask = BIT(9),
2096 .hw.init = &(struct clk_init_data){
2097 .name = "usb_hsic_xcvr_fs_clk",
2098 .parent_names = usb_hsic_xcvr_fs_src_p,
2100 .ops = &clk_branch_ops,
2101 .flags = CLK_SET_RATE_PARENT,
2106 static struct clk_branch usb_hsic_system_clk = {
2110 .enable_reg = 0x292c,
2111 .enable_mask = BIT(4),
2112 .hw.init = &(struct clk_init_data){
2113 .parent_names = usb_hsic_xcvr_fs_src_p,
2115 .name = "usb_hsic_system_clk",
2116 .ops = &clk_branch_ops,
2117 .flags = CLK_SET_RATE_PARENT,
2122 static struct clk_branch usb_hsic_hsic_clk = {
2126 .enable_reg = 0x2b44,
2127 .enable_mask = BIT(0),
2128 .hw.init = &(struct clk_init_data){
2129 .parent_names = (const char *[]){ "pll14_vote" },
2131 .name = "usb_hsic_hsic_clk",
2132 .ops = &clk_branch_ops,
2137 static struct clk_branch usb_hsic_hsio_cal_clk = {
2141 .enable_reg = 0x2b48,
2142 .enable_mask = BIT(0),
2143 .hw.init = &(struct clk_init_data){
2144 .name = "usb_hsic_hsio_cal_clk",
2145 .ops = &clk_branch_ops,
2146 .flags = CLK_IS_ROOT,
2151 static struct clk_rcg usb_fs1_xcvr_fs_src = {
2156 .mnctr_reset_bit = 7,
2157 .mnctr_mode_shift = 5,
2168 .parent_map = gcc_pxo_pll8_map,
2170 .freq_tbl = clk_tbl_usb,
2172 .enable_reg = 0x2968,
2173 .enable_mask = BIT(11),
2174 .hw.init = &(struct clk_init_data){
2175 .name = "usb_fs1_xcvr_fs_src",
2176 .parent_names = gcc_pxo_pll8,
2178 .ops = &clk_rcg_ops,
2179 .flags = CLK_SET_RATE_GATE,
2184 static const char * const usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" };
2186 static struct clk_branch usb_fs1_xcvr_fs_clk = {
2190 .enable_reg = 0x2968,
2191 .enable_mask = BIT(9),
2192 .hw.init = &(struct clk_init_data){
2193 .name = "usb_fs1_xcvr_fs_clk",
2194 .parent_names = usb_fs1_xcvr_fs_src_p,
2196 .ops = &clk_branch_ops,
2197 .flags = CLK_SET_RATE_PARENT,
2202 static struct clk_branch usb_fs1_system_clk = {
2206 .enable_reg = 0x296c,
2207 .enable_mask = BIT(4),
2208 .hw.init = &(struct clk_init_data){
2209 .parent_names = usb_fs1_xcvr_fs_src_p,
2211 .name = "usb_fs1_system_clk",
2212 .ops = &clk_branch_ops,
2213 .flags = CLK_SET_RATE_PARENT,
2218 static struct clk_rcg usb_fs2_xcvr_fs_src = {
2223 .mnctr_reset_bit = 7,
2224 .mnctr_mode_shift = 5,
2235 .parent_map = gcc_pxo_pll8_map,
2237 .freq_tbl = clk_tbl_usb,
2239 .enable_reg = 0x2988,
2240 .enable_mask = BIT(11),
2241 .hw.init = &(struct clk_init_data){
2242 .name = "usb_fs2_xcvr_fs_src",
2243 .parent_names = gcc_pxo_pll8,
2245 .ops = &clk_rcg_ops,
2246 .flags = CLK_SET_RATE_GATE,
2251 static const char * const usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" };
2253 static struct clk_branch usb_fs2_xcvr_fs_clk = {
2257 .enable_reg = 0x2988,
2258 .enable_mask = BIT(9),
2259 .hw.init = &(struct clk_init_data){
2260 .name = "usb_fs2_xcvr_fs_clk",
2261 .parent_names = usb_fs2_xcvr_fs_src_p,
2263 .ops = &clk_branch_ops,
2264 .flags = CLK_SET_RATE_PARENT,
2269 static struct clk_branch usb_fs2_system_clk = {
2273 .enable_reg = 0x298c,
2274 .enable_mask = BIT(4),
2275 .hw.init = &(struct clk_init_data){
2276 .name = "usb_fs2_system_clk",
2277 .parent_names = usb_fs2_xcvr_fs_src_p,
2279 .ops = &clk_branch_ops,
2280 .flags = CLK_SET_RATE_PARENT,
2285 static struct clk_branch ce1_core_clk = {
2291 .enable_reg = 0x2724,
2292 .enable_mask = BIT(4),
2293 .hw.init = &(struct clk_init_data){
2294 .name = "ce1_core_clk",
2295 .ops = &clk_branch_ops,
2296 .flags = CLK_IS_ROOT,
2301 static struct clk_branch ce1_h_clk = {
2305 .enable_reg = 0x2720,
2306 .enable_mask = BIT(4),
2307 .hw.init = &(struct clk_init_data){
2308 .name = "ce1_h_clk",
2309 .ops = &clk_branch_ops,
2310 .flags = CLK_IS_ROOT,
2315 static struct clk_branch dma_bam_h_clk = {
2321 .enable_reg = 0x25c0,
2322 .enable_mask = BIT(4),
2323 .hw.init = &(struct clk_init_data){
2324 .name = "dma_bam_h_clk",
2325 .ops = &clk_branch_ops,
2326 .flags = CLK_IS_ROOT,
2331 static struct clk_branch gsbi1_h_clk = {
2337 .enable_reg = 0x29c0,
2338 .enable_mask = BIT(4),
2339 .hw.init = &(struct clk_init_data){
2340 .name = "gsbi1_h_clk",
2341 .ops = &clk_branch_ops,
2342 .flags = CLK_IS_ROOT,
2347 static struct clk_branch gsbi2_h_clk = {
2353 .enable_reg = 0x29e0,
2354 .enable_mask = BIT(4),
2355 .hw.init = &(struct clk_init_data){
2356 .name = "gsbi2_h_clk",
2357 .ops = &clk_branch_ops,
2358 .flags = CLK_IS_ROOT,
2363 static struct clk_branch gsbi3_h_clk = {
2369 .enable_reg = 0x2a00,
2370 .enable_mask = BIT(4),
2371 .hw.init = &(struct clk_init_data){
2372 .name = "gsbi3_h_clk",
2373 .ops = &clk_branch_ops,
2374 .flags = CLK_IS_ROOT,
2379 static struct clk_branch gsbi4_h_clk = {
2385 .enable_reg = 0x2a20,
2386 .enable_mask = BIT(4),
2387 .hw.init = &(struct clk_init_data){
2388 .name = "gsbi4_h_clk",
2389 .ops = &clk_branch_ops,
2390 .flags = CLK_IS_ROOT,
2395 static struct clk_branch gsbi5_h_clk = {
2401 .enable_reg = 0x2a40,
2402 .enable_mask = BIT(4),
2403 .hw.init = &(struct clk_init_data){
2404 .name = "gsbi5_h_clk",
2405 .ops = &clk_branch_ops,
2406 .flags = CLK_IS_ROOT,
2411 static struct clk_branch gsbi6_h_clk = {
2417 .enable_reg = 0x2a60,
2418 .enable_mask = BIT(4),
2419 .hw.init = &(struct clk_init_data){
2420 .name = "gsbi6_h_clk",
2421 .ops = &clk_branch_ops,
2422 .flags = CLK_IS_ROOT,
2427 static struct clk_branch gsbi7_h_clk = {
2433 .enable_reg = 0x2a80,
2434 .enable_mask = BIT(4),
2435 .hw.init = &(struct clk_init_data){
2436 .name = "gsbi7_h_clk",
2437 .ops = &clk_branch_ops,
2438 .flags = CLK_IS_ROOT,
2443 static struct clk_branch gsbi8_h_clk = {
2449 .enable_reg = 0x2aa0,
2450 .enable_mask = BIT(4),
2451 .hw.init = &(struct clk_init_data){
2452 .name = "gsbi8_h_clk",
2453 .ops = &clk_branch_ops,
2454 .flags = CLK_IS_ROOT,
2459 static struct clk_branch gsbi9_h_clk = {
2465 .enable_reg = 0x2ac0,
2466 .enable_mask = BIT(4),
2467 .hw.init = &(struct clk_init_data){
2468 .name = "gsbi9_h_clk",
2469 .ops = &clk_branch_ops,
2470 .flags = CLK_IS_ROOT,
2475 static struct clk_branch gsbi10_h_clk = {
2481 .enable_reg = 0x2ae0,
2482 .enable_mask = BIT(4),
2483 .hw.init = &(struct clk_init_data){
2484 .name = "gsbi10_h_clk",
2485 .ops = &clk_branch_ops,
2486 .flags = CLK_IS_ROOT,
2491 static struct clk_branch gsbi11_h_clk = {
2497 .enable_reg = 0x2b00,
2498 .enable_mask = BIT(4),
2499 .hw.init = &(struct clk_init_data){
2500 .name = "gsbi11_h_clk",
2501 .ops = &clk_branch_ops,
2502 .flags = CLK_IS_ROOT,
2507 static struct clk_branch gsbi12_h_clk = {
2513 .enable_reg = 0x2b20,
2514 .enable_mask = BIT(4),
2515 .hw.init = &(struct clk_init_data){
2516 .name = "gsbi12_h_clk",
2517 .ops = &clk_branch_ops,
2518 .flags = CLK_IS_ROOT,
2523 static struct clk_branch tsif_h_clk = {
2529 .enable_reg = 0x2700,
2530 .enable_mask = BIT(4),
2531 .hw.init = &(struct clk_init_data){
2532 .name = "tsif_h_clk",
2533 .ops = &clk_branch_ops,
2534 .flags = CLK_IS_ROOT,
2539 static struct clk_branch usb_fs1_h_clk = {
2543 .enable_reg = 0x2960,
2544 .enable_mask = BIT(4),
2545 .hw.init = &(struct clk_init_data){
2546 .name = "usb_fs1_h_clk",
2547 .ops = &clk_branch_ops,
2548 .flags = CLK_IS_ROOT,
2553 static struct clk_branch usb_fs2_h_clk = {
2557 .enable_reg = 0x2980,
2558 .enable_mask = BIT(4),
2559 .hw.init = &(struct clk_init_data){
2560 .name = "usb_fs2_h_clk",
2561 .ops = &clk_branch_ops,
2562 .flags = CLK_IS_ROOT,
2567 static struct clk_branch usb_hs1_h_clk = {
2573 .enable_reg = 0x2900,
2574 .enable_mask = BIT(4),
2575 .hw.init = &(struct clk_init_data){
2576 .name = "usb_hs1_h_clk",
2577 .ops = &clk_branch_ops,
2578 .flags = CLK_IS_ROOT,
2583 static struct clk_branch usb_hs3_h_clk = {
2587 .enable_reg = 0x3700,
2588 .enable_mask = BIT(4),
2589 .hw.init = &(struct clk_init_data){
2590 .name = "usb_hs3_h_clk",
2591 .ops = &clk_branch_ops,
2592 .flags = CLK_IS_ROOT,
2597 static struct clk_branch usb_hs4_h_clk = {
2601 .enable_reg = 0x3720,
2602 .enable_mask = BIT(4),
2603 .hw.init = &(struct clk_init_data){
2604 .name = "usb_hs4_h_clk",
2605 .ops = &clk_branch_ops,
2606 .flags = CLK_IS_ROOT,
2611 static struct clk_branch usb_hsic_h_clk = {
2615 .enable_reg = 0x2920,
2616 .enable_mask = BIT(4),
2617 .hw.init = &(struct clk_init_data){
2618 .name = "usb_hsic_h_clk",
2619 .ops = &clk_branch_ops,
2620 .flags = CLK_IS_ROOT,
2625 static struct clk_branch sdc1_h_clk = {
2631 .enable_reg = 0x2820,
2632 .enable_mask = BIT(4),
2633 .hw.init = &(struct clk_init_data){
2634 .name = "sdc1_h_clk",
2635 .ops = &clk_branch_ops,
2636 .flags = CLK_IS_ROOT,
2641 static struct clk_branch sdc2_h_clk = {
2647 .enable_reg = 0x2840,
2648 .enable_mask = BIT(4),
2649 .hw.init = &(struct clk_init_data){
2650 .name = "sdc2_h_clk",
2651 .ops = &clk_branch_ops,
2652 .flags = CLK_IS_ROOT,
2657 static struct clk_branch sdc3_h_clk = {
2663 .enable_reg = 0x2860,
2664 .enable_mask = BIT(4),
2665 .hw.init = &(struct clk_init_data){
2666 .name = "sdc3_h_clk",
2667 .ops = &clk_branch_ops,
2668 .flags = CLK_IS_ROOT,
2673 static struct clk_branch sdc4_h_clk = {
2679 .enable_reg = 0x2880,
2680 .enable_mask = BIT(4),
2681 .hw.init = &(struct clk_init_data){
2682 .name = "sdc4_h_clk",
2683 .ops = &clk_branch_ops,
2684 .flags = CLK_IS_ROOT,
2689 static struct clk_branch sdc5_h_clk = {
2695 .enable_reg = 0x28a0,
2696 .enable_mask = BIT(4),
2697 .hw.init = &(struct clk_init_data){
2698 .name = "sdc5_h_clk",
2699 .ops = &clk_branch_ops,
2700 .flags = CLK_IS_ROOT,
2705 static struct clk_branch adm0_clk = {
2707 .halt_check = BRANCH_HALT_VOTED,
2710 .enable_reg = 0x3080,
2711 .enable_mask = BIT(2),
2712 .hw.init = &(struct clk_init_data){
2714 .ops = &clk_branch_ops,
2715 .flags = CLK_IS_ROOT,
2720 static struct clk_branch adm0_pbus_clk = {
2724 .halt_check = BRANCH_HALT_VOTED,
2727 .enable_reg = 0x3080,
2728 .enable_mask = BIT(3),
2729 .hw.init = &(struct clk_init_data){
2730 .name = "adm0_pbus_clk",
2731 .ops = &clk_branch_ops,
2732 .flags = CLK_IS_ROOT,
2737 static struct freq_tbl clk_tbl_ce3[] = {
2738 { 48000000, P_PLL8, 8 },
2739 { 100000000, P_PLL3, 12 },
2740 { 120000000, P_PLL3, 10 },
2744 static struct clk_rcg ce3_src = {
2752 .parent_map = gcc_pxo_pll8_pll3_map,
2754 .freq_tbl = clk_tbl_ce3,
2756 .enable_reg = 0x2c08,
2757 .enable_mask = BIT(7),
2758 .hw.init = &(struct clk_init_data){
2760 .parent_names = gcc_pxo_pll8_pll3,
2762 .ops = &clk_rcg_ops,
2763 .flags = CLK_SET_RATE_GATE,
2768 static struct clk_branch ce3_core_clk = {
2772 .enable_reg = 0x36c4,
2773 .enable_mask = BIT(4),
2774 .hw.init = &(struct clk_init_data){
2775 .name = "ce3_core_clk",
2776 .parent_names = (const char *[]){ "ce3_src" },
2778 .ops = &clk_branch_ops,
2779 .flags = CLK_SET_RATE_PARENT,
2784 static struct clk_branch ce3_h_clk = {
2788 .enable_reg = 0x36c4,
2789 .enable_mask = BIT(4),
2790 .hw.init = &(struct clk_init_data){
2791 .name = "ce3_h_clk",
2792 .parent_names = (const char *[]){ "ce3_src" },
2794 .ops = &clk_branch_ops,
2795 .flags = CLK_SET_RATE_PARENT,
2800 static const struct freq_tbl clk_tbl_sata_ref[] = {
2801 { 48000000, P_PLL8, 8, 0, 0 },
2802 { 100000000, P_PLL3, 12, 0, 0 },
2806 static struct clk_rcg sata_clk_src = {
2814 .parent_map = gcc_pxo_pll8_pll3_map,
2816 .freq_tbl = clk_tbl_sata_ref,
2818 .enable_reg = 0x2c08,
2819 .enable_mask = BIT(7),
2820 .hw.init = &(struct clk_init_data){
2821 .name = "sata_clk_src",
2822 .parent_names = gcc_pxo_pll8_pll3,
2824 .ops = &clk_rcg_ops,
2825 .flags = CLK_SET_RATE_GATE,
2830 static struct clk_branch sata_rxoob_clk = {
2834 .enable_reg = 0x2c0c,
2835 .enable_mask = BIT(4),
2836 .hw.init = &(struct clk_init_data){
2837 .name = "sata_rxoob_clk",
2838 .parent_names = (const char *[]){ "sata_clk_src" },
2840 .ops = &clk_branch_ops,
2841 .flags = CLK_SET_RATE_PARENT,
2846 static struct clk_branch sata_pmalive_clk = {
2850 .enable_reg = 0x2c10,
2851 .enable_mask = BIT(4),
2852 .hw.init = &(struct clk_init_data){
2853 .name = "sata_pmalive_clk",
2854 .parent_names = (const char *[]){ "sata_clk_src" },
2856 .ops = &clk_branch_ops,
2857 .flags = CLK_SET_RATE_PARENT,
2862 static struct clk_branch sata_phy_ref_clk = {
2866 .enable_reg = 0x2c14,
2867 .enable_mask = BIT(4),
2868 .hw.init = &(struct clk_init_data){
2869 .name = "sata_phy_ref_clk",
2870 .parent_names = (const char *[]){ "pxo" },
2872 .ops = &clk_branch_ops,
2877 static struct clk_branch sata_a_clk = {
2881 .enable_reg = 0x2c20,
2882 .enable_mask = BIT(4),
2883 .hw.init = &(struct clk_init_data){
2884 .name = "sata_a_clk",
2885 .ops = &clk_branch_ops,
2886 .flags = CLK_IS_ROOT,
2891 static struct clk_branch sata_h_clk = {
2895 .enable_reg = 0x2c00,
2896 .enable_mask = BIT(4),
2897 .hw.init = &(struct clk_init_data){
2898 .name = "sata_h_clk",
2899 .ops = &clk_branch_ops,
2900 .flags = CLK_IS_ROOT,
2905 static struct clk_branch sfab_sata_s_h_clk = {
2909 .enable_reg = 0x2480,
2910 .enable_mask = BIT(4),
2911 .hw.init = &(struct clk_init_data){
2912 .name = "sfab_sata_s_h_clk",
2913 .ops = &clk_branch_ops,
2914 .flags = CLK_IS_ROOT,
2919 static struct clk_branch sata_phy_cfg_clk = {
2923 .enable_reg = 0x2c40,
2924 .enable_mask = BIT(4),
2925 .hw.init = &(struct clk_init_data){
2926 .name = "sata_phy_cfg_clk",
2927 .ops = &clk_branch_ops,
2928 .flags = CLK_IS_ROOT,
2933 static struct clk_branch pcie_phy_ref_clk = {
2937 .enable_reg = 0x22d0,
2938 .enable_mask = BIT(4),
2939 .hw.init = &(struct clk_init_data){
2940 .name = "pcie_phy_ref_clk",
2941 .ops = &clk_branch_ops,
2942 .flags = CLK_IS_ROOT,
2947 static struct clk_branch pcie_h_clk = {
2951 .enable_reg = 0x22cc,
2952 .enable_mask = BIT(4),
2953 .hw.init = &(struct clk_init_data){
2954 .name = "pcie_h_clk",
2955 .ops = &clk_branch_ops,
2956 .flags = CLK_IS_ROOT,
2961 static struct clk_branch pcie_a_clk = {
2965 .enable_reg = 0x22c0,
2966 .enable_mask = BIT(4),
2967 .hw.init = &(struct clk_init_data){
2968 .name = "pcie_a_clk",
2969 .ops = &clk_branch_ops,
2970 .flags = CLK_IS_ROOT,
2975 static struct clk_branch pmic_arb0_h_clk = {
2977 .halt_check = BRANCH_HALT_VOTED,
2980 .enable_reg = 0x3080,
2981 .enable_mask = BIT(8),
2982 .hw.init = &(struct clk_init_data){
2983 .name = "pmic_arb0_h_clk",
2984 .ops = &clk_branch_ops,
2985 .flags = CLK_IS_ROOT,
2990 static struct clk_branch pmic_arb1_h_clk = {
2992 .halt_check = BRANCH_HALT_VOTED,
2995 .enable_reg = 0x3080,
2996 .enable_mask = BIT(9),
2997 .hw.init = &(struct clk_init_data){
2998 .name = "pmic_arb1_h_clk",
2999 .ops = &clk_branch_ops,
3000 .flags = CLK_IS_ROOT,
3005 static struct clk_branch pmic_ssbi2_clk = {
3007 .halt_check = BRANCH_HALT_VOTED,
3010 .enable_reg = 0x3080,
3011 .enable_mask = BIT(7),
3012 .hw.init = &(struct clk_init_data){
3013 .name = "pmic_ssbi2_clk",
3014 .ops = &clk_branch_ops,
3015 .flags = CLK_IS_ROOT,
3020 static struct clk_branch rpm_msg_ram_h_clk = {
3024 .halt_check = BRANCH_HALT_VOTED,
3027 .enable_reg = 0x3080,
3028 .enable_mask = BIT(6),
3029 .hw.init = &(struct clk_init_data){
3030 .name = "rpm_msg_ram_h_clk",
3031 .ops = &clk_branch_ops,
3032 .flags = CLK_IS_ROOT,
3037 static struct clk_regmap *gcc_msm8960_clks[] = {
3038 [PLL3] = &pll3.clkr,
3039 [PLL4_VOTE] = &pll4_vote,
3040 [PLL8] = &pll8.clkr,
3041 [PLL8_VOTE] = &pll8_vote,
3042 [PLL14] = &pll14.clkr,
3043 [PLL14_VOTE] = &pll14_vote,
3044 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3045 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3046 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3047 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3048 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3049 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3050 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3051 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3052 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3053 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3054 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3055 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3056 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3057 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3058 [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
3059 [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
3060 [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
3061 [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
3062 [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
3063 [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
3064 [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
3065 [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
3066 [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
3067 [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
3068 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3069 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3070 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3071 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3072 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3073 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3074 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3075 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3076 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3077 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3078 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3079 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3080 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3081 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3082 [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
3083 [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
3084 [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
3085 [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
3086 [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
3087 [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
3088 [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
3089 [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
3090 [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
3091 [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
3092 [GP0_SRC] = &gp0_src.clkr,
3093 [GP0_CLK] = &gp0_clk.clkr,
3094 [GP1_SRC] = &gp1_src.clkr,
3095 [GP1_CLK] = &gp1_clk.clkr,
3096 [GP2_SRC] = &gp2_src.clkr,
3097 [GP2_CLK] = &gp2_clk.clkr,
3098 [PMEM_A_CLK] = &pmem_clk.clkr,
3099 [PRNG_SRC] = &prng_src.clkr,
3100 [PRNG_CLK] = &prng_clk.clkr,
3101 [SDC1_SRC] = &sdc1_src.clkr,
3102 [SDC1_CLK] = &sdc1_clk.clkr,
3103 [SDC2_SRC] = &sdc2_src.clkr,
3104 [SDC2_CLK] = &sdc2_clk.clkr,
3105 [SDC3_SRC] = &sdc3_src.clkr,
3106 [SDC3_CLK] = &sdc3_clk.clkr,
3107 [SDC4_SRC] = &sdc4_src.clkr,
3108 [SDC4_CLK] = &sdc4_clk.clkr,
3109 [SDC5_SRC] = &sdc5_src.clkr,
3110 [SDC5_CLK] = &sdc5_clk.clkr,
3111 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3112 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3113 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3114 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3115 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3116 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3117 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3118 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3119 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3120 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3121 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3122 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3123 [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
3124 [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
3125 [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
3126 [CE1_CORE_CLK] = &ce1_core_clk.clkr,
3127 [CE1_H_CLK] = &ce1_h_clk.clkr,
3128 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3129 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3130 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3131 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3132 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3133 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3134 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3135 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3136 [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
3137 [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
3138 [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
3139 [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
3140 [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
3141 [TSIF_H_CLK] = &tsif_h_clk.clkr,
3142 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3143 [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
3144 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3145 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3146 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3147 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3148 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3149 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3150 [SDC5_H_CLK] = &sdc5_h_clk.clkr,
3151 [ADM0_CLK] = &adm0_clk.clkr,
3152 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3153 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3154 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3155 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3156 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3159 static const struct qcom_reset_map gcc_msm8960_resets[] = {
3160 [SFAB_MSS_Q6_SW_RESET] = { 0x2040, 7 },
3161 [SFAB_MSS_Q6_FW_RESET] = { 0x2044, 7 },
3162 [QDSS_STM_RESET] = { 0x2060, 6 },
3163 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3164 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3165 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3166 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3167 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3168 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3169 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3170 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3171 [ADM0_C2_RESET] = { 0x220c, 4},
3172 [ADM0_C1_RESET] = { 0x220c, 3},
3173 [ADM0_C0_RESET] = { 0x220c, 2},
3174 [ADM0_PBUS_RESET] = { 0x220c, 1 },
3175 [ADM0_RESET] = { 0x220c },
3176 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3177 [QDSS_POR_RESET] = { 0x2260, 4 },
3178 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3179 [QDSS_HRESET_RESET] = { 0x2260, 2 },
3180 [QDSS_AXI_RESET] = { 0x2260, 1 },
3181 [QDSS_DBG_RESET] = { 0x2260 },
3182 [PCIE_A_RESET] = { 0x22c0, 7 },
3183 [PCIE_AUX_RESET] = { 0x22c8, 7 },
3184 [PCIE_H_RESET] = { 0x22d0, 7 },
3185 [SFAB_PCIE_M_RESET] = { 0x22d4, 1 },
3186 [SFAB_PCIE_S_RESET] = { 0x22d4 },
3187 [SFAB_MSS_M_RESET] = { 0x2340, 7 },
3188 [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3189 [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3190 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3191 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3192 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3193 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3194 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3195 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3196 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3197 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3198 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3199 [DFAB_ARB0_RESET] = { 0x2560, 7 },
3200 [DFAB_ARB1_RESET] = { 0x2564, 7 },
3201 [PPSS_PROC_RESET] = { 0x2594, 1 },
3202 [PPSS_RESET] = { 0x2594},
3203 [DMA_BAM_RESET] = { 0x25c0, 7 },
3204 [SPS_TIC_H_RESET] = { 0x2600, 7 },
3205 [SLIMBUS_H_RESET] = { 0x2620, 7 },
3206 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3207 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3208 [TSIF_H_RESET] = { 0x2700, 7 },
3209 [CE1_H_RESET] = { 0x2720, 7 },
3210 [CE1_CORE_RESET] = { 0x2724, 7 },
3211 [CE1_SLEEP_RESET] = { 0x2728, 7 },
3212 [CE2_H_RESET] = { 0x2740, 7 },
3213 [CE2_CORE_RESET] = { 0x2744, 7 },
3214 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3215 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3216 [RPM_PROC_RESET] = { 0x27c0, 7 },
3217 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3218 [SDC1_RESET] = { 0x2830 },
3219 [SDC2_RESET] = { 0x2850 },
3220 [SDC3_RESET] = { 0x2870 },
3221 [SDC4_RESET] = { 0x2890 },
3222 [SDC5_RESET] = { 0x28b0 },
3223 [DFAB_A2_RESET] = { 0x28c0, 7 },
3224 [USB_HS1_RESET] = { 0x2910 },
3225 [USB_HSIC_RESET] = { 0x2934 },
3226 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3227 [USB_FS1_RESET] = { 0x2974 },
3228 [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
3229 [USB_FS2_RESET] = { 0x2994 },
3230 [GSBI1_RESET] = { 0x29dc },
3231 [GSBI2_RESET] = { 0x29fc },
3232 [GSBI3_RESET] = { 0x2a1c },
3233 [GSBI4_RESET] = { 0x2a3c },
3234 [GSBI5_RESET] = { 0x2a5c },
3235 [GSBI6_RESET] = { 0x2a7c },
3236 [GSBI7_RESET] = { 0x2a9c },
3237 [GSBI8_RESET] = { 0x2abc },
3238 [GSBI9_RESET] = { 0x2adc },
3239 [GSBI10_RESET] = { 0x2afc },
3240 [GSBI11_RESET] = { 0x2b1c },
3241 [GSBI12_RESET] = { 0x2b3c },
3242 [SPDM_RESET] = { 0x2b6c },
3243 [TLMM_H_RESET] = { 0x2ba0, 7 },
3244 [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
3245 [MSS_SLP_RESET] = { 0x2c60, 7 },
3246 [MSS_Q6SW_JTAG_RESET] = { 0x2c68, 7 },
3247 [MSS_Q6FW_JTAG_RESET] = { 0x2c6c, 7 },
3248 [MSS_RESET] = { 0x2c64 },
3249 [SATA_H_RESET] = { 0x2c80, 7 },
3250 [SATA_RXOOB_RESE] = { 0x2c8c, 7 },
3251 [SATA_PMALIVE_RESET] = { 0x2c90, 7 },
3252 [SATA_SFAB_M_RESET] = { 0x2c98, 7 },
3253 [TSSC_RESET] = { 0x2ca0, 7 },
3254 [PDM_RESET] = { 0x2cc0, 12 },
3255 [MPM_H_RESET] = { 0x2da0, 7 },
3256 [MPM_RESET] = { 0x2da4 },
3257 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3258 [PRNG_RESET] = { 0x2e80, 12 },
3259 [RIVA_RESET] = { 0x35e0 },
3262 static struct clk_regmap *gcc_apq8064_clks[] = {
3263 [PLL3] = &pll3.clkr,
3264 [PLL4_VOTE] = &pll4_vote,
3265 [PLL8] = &pll8.clkr,
3266 [PLL8_VOTE] = &pll8_vote,
3267 [PLL14] = &pll14.clkr,
3268 [PLL14_VOTE] = &pll14_vote,
3269 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3270 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3271 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3272 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3273 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3274 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3275 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3276 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3277 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3278 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3279 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3280 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3281 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3282 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3283 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3284 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3285 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3286 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3287 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3288 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3289 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3290 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3291 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3292 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3293 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3294 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3295 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3296 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3297 [GP0_SRC] = &gp0_src.clkr,
3298 [GP0_CLK] = &gp0_clk.clkr,
3299 [GP1_SRC] = &gp1_src.clkr,
3300 [GP1_CLK] = &gp1_clk.clkr,
3301 [GP2_SRC] = &gp2_src.clkr,
3302 [GP2_CLK] = &gp2_clk.clkr,
3303 [PMEM_A_CLK] = &pmem_clk.clkr,
3304 [PRNG_SRC] = &prng_src.clkr,
3305 [PRNG_CLK] = &prng_clk.clkr,
3306 [SDC1_SRC] = &sdc1_src.clkr,
3307 [SDC1_CLK] = &sdc1_clk.clkr,
3308 [SDC2_SRC] = &sdc2_src.clkr,
3309 [SDC2_CLK] = &sdc2_clk.clkr,
3310 [SDC3_SRC] = &sdc3_src.clkr,
3311 [SDC3_CLK] = &sdc3_clk.clkr,
3312 [SDC4_SRC] = &sdc4_src.clkr,
3313 [SDC4_CLK] = &sdc4_clk.clkr,
3314 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3315 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3316 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3317 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3318 [USB_HS3_XCVR_SRC] = &usb_hs3_xcvr_src.clkr,
3319 [USB_HS3_XCVR_CLK] = &usb_hs3_xcvr_clk.clkr,
3320 [USB_HS4_XCVR_SRC] = &usb_hs4_xcvr_src.clkr,
3321 [USB_HS4_XCVR_CLK] = &usb_hs4_xcvr_clk.clkr,
3322 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3323 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3324 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3325 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3326 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3327 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3328 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3329 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3330 [SATA_H_CLK] = &sata_h_clk.clkr,
3331 [SATA_CLK_SRC] = &sata_clk_src.clkr,
3332 [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
3333 [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
3334 [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
3335 [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
3336 [SATA_A_CLK] = &sata_a_clk.clkr,
3337 [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
3338 [CE3_SRC] = &ce3_src.clkr,
3339 [CE3_CORE_CLK] = &ce3_core_clk.clkr,
3340 [CE3_H_CLK] = &ce3_h_clk.clkr,
3341 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3342 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3343 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3344 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3345 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3346 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3347 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3348 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3349 [TSIF_H_CLK] = &tsif_h_clk.clkr,
3350 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3351 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3352 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3353 [USB_HS3_H_CLK] = &usb_hs3_h_clk.clkr,
3354 [USB_HS4_H_CLK] = &usb_hs4_h_clk.clkr,
3355 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3356 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3357 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3358 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3359 [ADM0_CLK] = &adm0_clk.clkr,
3360 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3361 [PCIE_A_CLK] = &pcie_a_clk.clkr,
3362 [PCIE_PHY_REF_CLK] = &pcie_phy_ref_clk.clkr,
3363 [PCIE_H_CLK] = &pcie_h_clk.clkr,
3364 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3365 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3366 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3367 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3370 static const struct qcom_reset_map gcc_apq8064_resets[] = {
3371 [QDSS_STM_RESET] = { 0x2060, 6 },
3372 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3373 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3374 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3375 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3376 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3377 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3378 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3379 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3380 [ADM0_C2_RESET] = { 0x220c, 4},
3381 [ADM0_C1_RESET] = { 0x220c, 3},
3382 [ADM0_C0_RESET] = { 0x220c, 2},
3383 [ADM0_PBUS_RESET] = { 0x220c, 1 },
3384 [ADM0_RESET] = { 0x220c },
3385 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3386 [QDSS_POR_RESET] = { 0x2260, 4 },
3387 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3388 [QDSS_HRESET_RESET] = { 0x2260, 2 },
3389 [QDSS_AXI_RESET] = { 0x2260, 1 },
3390 [QDSS_DBG_RESET] = { 0x2260 },
3391 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
3392 [SFAB_PCIE_S_RESET] = { 0x22d8 },
3393 [PCIE_EXT_PCI_RESET] = { 0x22dc, 6 },
3394 [PCIE_PHY_RESET] = { 0x22dc, 5 },
3395 [PCIE_PCI_RESET] = { 0x22dc, 4 },
3396 [PCIE_POR_RESET] = { 0x22dc, 3 },
3397 [PCIE_HCLK_RESET] = { 0x22dc, 2 },
3398 [PCIE_ACLK_RESET] = { 0x22dc },
3399 [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3400 [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3401 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3402 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3403 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3404 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3405 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3406 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3407 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3408 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3409 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3410 [DFAB_ARB0_RESET] = { 0x2560, 7 },
3411 [DFAB_ARB1_RESET] = { 0x2564, 7 },
3412 [PPSS_PROC_RESET] = { 0x2594, 1 },
3413 [PPSS_RESET] = { 0x2594},
3414 [DMA_BAM_RESET] = { 0x25c0, 7 },
3415 [SPS_TIC_H_RESET] = { 0x2600, 7 },
3416 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3417 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3418 [TSIF_H_RESET] = { 0x2700, 7 },
3419 [CE1_H_RESET] = { 0x2720, 7 },
3420 [CE1_CORE_RESET] = { 0x2724, 7 },
3421 [CE1_SLEEP_RESET] = { 0x2728, 7 },
3422 [CE2_H_RESET] = { 0x2740, 7 },
3423 [CE2_CORE_RESET] = { 0x2744, 7 },
3424 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3425 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3426 [RPM_PROC_RESET] = { 0x27c0, 7 },
3427 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3428 [SDC1_RESET] = { 0x2830 },
3429 [SDC2_RESET] = { 0x2850 },
3430 [SDC3_RESET] = { 0x2870 },
3431 [SDC4_RESET] = { 0x2890 },
3432 [USB_HS1_RESET] = { 0x2910 },
3433 [USB_HSIC_RESET] = { 0x2934 },
3434 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3435 [USB_FS1_RESET] = { 0x2974 },
3436 [GSBI1_RESET] = { 0x29dc },
3437 [GSBI2_RESET] = { 0x29fc },
3438 [GSBI3_RESET] = { 0x2a1c },
3439 [GSBI4_RESET] = { 0x2a3c },
3440 [GSBI5_RESET] = { 0x2a5c },
3441 [GSBI6_RESET] = { 0x2a7c },
3442 [GSBI7_RESET] = { 0x2a9c },
3443 [SPDM_RESET] = { 0x2b6c },
3444 [TLMM_H_RESET] = { 0x2ba0, 7 },
3445 [SATA_SFAB_M_RESET] = { 0x2c18 },
3446 [SATA_RESET] = { 0x2c1c },
3447 [GSS_SLP_RESET] = { 0x2c60, 7 },
3448 [GSS_RESET] = { 0x2c64 },
3449 [TSSC_RESET] = { 0x2ca0, 7 },
3450 [PDM_RESET] = { 0x2cc0, 12 },
3451 [MPM_H_RESET] = { 0x2da0, 7 },
3452 [MPM_RESET] = { 0x2da4 },
3453 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3454 [PRNG_RESET] = { 0x2e80, 12 },
3455 [RIVA_RESET] = { 0x35e0 },
3456 [CE3_H_RESET] = { 0x36c4, 7 },
3457 [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
3458 [SFAB_CE3_S_RESET] = { 0x36c8 },
3459 [CE3_RESET] = { 0x36cc, 7 },
3460 [CE3_SLEEP_RESET] = { 0x36d0, 7 },
3461 [USB_HS3_RESET] = { 0x3710 },
3462 [USB_HS4_RESET] = { 0x3730 },
3465 static const struct regmap_config gcc_msm8960_regmap_config = {
3469 .max_register = 0x3660,
3473 static const struct regmap_config gcc_apq8064_regmap_config = {
3477 .max_register = 0x3880,
3481 static const struct qcom_cc_desc gcc_msm8960_desc = {
3482 .config = &gcc_msm8960_regmap_config,
3483 .clks = gcc_msm8960_clks,
3484 .num_clks = ARRAY_SIZE(gcc_msm8960_clks),
3485 .resets = gcc_msm8960_resets,
3486 .num_resets = ARRAY_SIZE(gcc_msm8960_resets),
3489 static const struct qcom_cc_desc gcc_apq8064_desc = {
3490 .config = &gcc_apq8064_regmap_config,
3491 .clks = gcc_apq8064_clks,
3492 .num_clks = ARRAY_SIZE(gcc_apq8064_clks),
3493 .resets = gcc_apq8064_resets,
3494 .num_resets = ARRAY_SIZE(gcc_apq8064_resets),
3497 static const struct of_device_id gcc_msm8960_match_table[] = {
3498 { .compatible = "qcom,gcc-msm8960", .data = &gcc_msm8960_desc },
3499 { .compatible = "qcom,gcc-apq8064", .data = &gcc_apq8064_desc },
3502 MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table);
3504 static int gcc_msm8960_probe(struct platform_device *pdev)
3506 struct device *dev = &pdev->dev;
3507 const struct of_device_id *match;
3508 struct platform_device *tsens;
3511 match = of_match_device(gcc_msm8960_match_table, &pdev->dev);
3515 ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000);
3519 ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000);
3523 ret = qcom_cc_probe(pdev, match->data);
3527 tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1,
3530 return PTR_ERR(tsens);
3532 platform_set_drvdata(pdev, tsens);
3537 static int gcc_msm8960_remove(struct platform_device *pdev)
3539 struct platform_device *tsens = platform_get_drvdata(pdev);
3541 platform_device_unregister(tsens);
3546 static struct platform_driver gcc_msm8960_driver = {
3547 .probe = gcc_msm8960_probe,
3548 .remove = gcc_msm8960_remove,
3550 .name = "gcc-msm8960",
3551 .of_match_table = gcc_msm8960_match_table,
3555 static int __init gcc_msm8960_init(void)
3557 return platform_driver_register(&gcc_msm8960_driver);
3559 core_initcall(gcc_msm8960_init);
3561 static void __exit gcc_msm8960_exit(void)
3563 platform_driver_unregister(&gcc_msm8960_driver);
3565 module_exit(gcc_msm8960_exit);
3567 MODULE_DESCRIPTION("QCOM GCC MSM8960 Driver");
3568 MODULE_LICENSE("GPL v2");
3569 MODULE_ALIAS("platform:gcc-msm8960");