drivers/clk/qcom/gcc-msm8960.c

   1 /*
   2  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset-controller.h>
  24
  25 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
  26 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
  27
  28 #include "common.h"
  29 #include "clk-regmap.h"
  30 #include "clk-pll.h"
  31 #include "clk-rcg.h"
  32 #include "clk-branch.h"
  33 #include "clk-hfpll.h"
  34 #include "reset.h"
  35
  36 static struct clk_pll pll3 = {
  37         .l_reg = 0x3164,
  38         .m_reg = 0x3168,
  39         .n_reg = 0x316c,
  40         .config_reg = 0x3174,
  41         .mode_reg = 0x3160,
  42         .status_reg = 0x3178,
  43         .status_bit = 16,
  44         .clkr.hw.init = &(struct clk_init_data){
  45                 .name = "pll3",
  46                 .parent_names = (const char *[]){ "pxo" },
  47                 .num_parents = 1,
  48                 .ops = &clk_pll_ops,
  49         },
  50 };
  51
  52 static struct clk_regmap pll4_vote = {
  53         .enable_reg = 0x34c0,
  54         .enable_mask = BIT(4),
  55         .hw.init = &(struct clk_init_data){
  56                 .name = "pll4_vote",
  57                 .parent_names = (const char *[]){ "pll4" },
  58                 .num_parents = 1,
  59                 .ops = &clk_pll_vote_ops,
  60         },
  61 };
  62
  63 static struct clk_pll pll8 = {
  64         .l_reg = 0x3144,
  65         .m_reg = 0x3148,
  66         .n_reg = 0x314c,
  67         .config_reg = 0x3154,
  68         .mode_reg = 0x3140,
  69         .status_reg = 0x3158,
  70         .status_bit = 16,
  71         .clkr.hw.init = &(struct clk_init_data){
  72                 .name = "pll8",
  73                 .parent_names = (const char *[]){ "pxo" },
  74                 .num_parents = 1,
  75                 .ops = &clk_pll_ops,
  76         },
  77 };
  78
  79 static struct clk_regmap pll8_vote = {
  80         .enable_reg = 0x34c0,
  81         .enable_mask = BIT(8),
  82         .hw.init = &(struct clk_init_data){
  83                 .name = "pll8_vote",
  84                 .parent_names = (const char *[]){ "pll8" },
  85                 .num_parents = 1,
  86                 .ops = &clk_pll_vote_ops,
  87         },
  88 };
  89
  90 static struct hfpll_data hfpll0_data = {
  91         .mode_reg = 0x3200,
  92         .l_reg = 0x3208,
  93         .m_reg = 0x320c,
  94         .n_reg = 0x3210,
  95         .config_reg = 0x3204,
  96         .status_reg = 0x321c,
  97         .config_val = 0x7845c665,
  98         .droop_reg = 0x3214,
  99         .droop_val = 0x0108c000,
 100         .min_rate = 600000000UL,
 101         .max_rate = 1800000000UL,
 102 };
 103
 104 static struct clk_hfpll hfpll0 = {
 105         .d = &hfpll0_data,
 106         .clkr.hw.init = &(struct clk_init_data){
 107                 .parent_names = (const char *[]){ "pxo" },
 108                 .num_parents = 1,
 109                 .name = "hfpll0",
 110                 .ops = &clk_ops_hfpll,
 111                 .flags = CLK_IGNORE_UNUSED,
 112         },
 113         .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
 114 };
 115
 116 static struct hfpll_data hfpll1_8064_data = {
 117         .mode_reg = 0x3240,
 118         .l_reg = 0x3248,
 119         .m_reg = 0x324c,
 120         .n_reg = 0x3250,
 121         .config_reg = 0x3244,
 122         .status_reg = 0x325c,
 123         .config_val = 0x7845c665,
 124         .droop_reg = 0x3254,
 125         .droop_val = 0x0108c000,
 126         .min_rate = 600000000UL,
 127         .max_rate = 1800000000UL,
 128 };
 129
 130 static struct hfpll_data hfpll1_data = {
 131         .mode_reg = 0x3300,
 132         .l_reg = 0x3308,
 133         .m_reg = 0x330c,
 134         .n_reg = 0x3310,
 135         .config_reg = 0x3304,
 136         .status_reg = 0x331c,
 137         .config_val = 0x7845c665,
 138         .droop_reg = 0x3314,
 139         .droop_val = 0x0108c000,
 140         .min_rate = 600000000UL,
 141         .max_rate = 1800000000UL,
 142 };
 143
 144 static struct clk_hfpll hfpll1 = {
 145         .d = &hfpll1_data,
 146         .clkr.hw.init = &(struct clk_init_data){
 147                 .parent_names = (const char *[]){ "pxo" },
 148                 .num_parents = 1,
 149                 .name = "hfpll1",
 150                 .ops = &clk_ops_hfpll,
 151                 .flags = CLK_IGNORE_UNUSED,
 152         },
 153         .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
 154 };
 155
 156 static struct hfpll_data hfpll2_data = {
 157         .mode_reg = 0x3280,
 158         .l_reg = 0x3288,
 159         .m_reg = 0x328c,
 160         .n_reg = 0x3290,
 161         .config_reg = 0x3284,
 162         .status_reg = 0x329c,
 163         .config_val = 0x7845c665,
 164         .droop_reg = 0x3294,
 165         .droop_val = 0x0108c000,
 166         .min_rate = 600000000UL,
 167         .max_rate = 1800000000UL,
 168 };
 169
 170 static struct clk_hfpll hfpll2 = {
 171         .d = &hfpll2_data,
 172         .clkr.hw.init = &(struct clk_init_data){
 173                 .parent_names = (const char *[]){ "pxo" },
 174                 .num_parents = 1,
 175                 .name = "hfpll2",
 176                 .ops = &clk_ops_hfpll,
 177                 .flags = CLK_IGNORE_UNUSED,
 178         },
 179         .lock = __SPIN_LOCK_UNLOCKED(hfpll2.lock),
 180 };
 181
 182 static struct hfpll_data hfpll3_data = {
 183         .mode_reg = 0x32c0,
 184         .l_reg = 0x32c8,
 185         .m_reg = 0x32cc,
 186         .n_reg = 0x32d0,
 187         .config_reg = 0x32c4,
 188         .status_reg = 0x32dc,
 189         .config_val = 0x7845c665,
 190         .droop_reg = 0x32d4,
 191         .droop_val = 0x0108c000,
 192         .min_rate = 600000000UL,
 193         .max_rate = 1800000000UL,
 194 };
 195
 196 static struct clk_hfpll hfpll3 = {
 197         .d = &hfpll3_data,
 198         .clkr.hw.init = &(struct clk_init_data){
 199                 .parent_names = (const char *[]){ "pxo" },
 200                 .num_parents = 1,
 201                 .name = "hfpll3",
 202                 .ops = &clk_ops_hfpll,
 203                 .flags = CLK_IGNORE_UNUSED,
 204         },
 205         .lock = __SPIN_LOCK_UNLOCKED(hfpll3.lock),
 206 };
 207
 208 static struct hfpll_data hfpll_l2_8064_data = {
 209         .mode_reg = 0x3300,
 210         .l_reg = 0x3308,
 211         .m_reg = 0x330c,
 212         .n_reg = 0x3310,
 213         .config_reg = 0x3304,
 214         .status_reg = 0x331c,
 215         .config_val = 0x7845c665,
 216         .droop_reg = 0x3314,
 217         .droop_val = 0x0108c000,
 218         .min_rate = 600000000UL,
 219         .max_rate = 1800000000UL,
 220 };
 221
 222 static struct hfpll_data hfpll_l2_data = {
 223         .mode_reg = 0x3400,
 224         .l_reg = 0x3408,
 225         .m_reg = 0x340c,
 226         .n_reg = 0x3410,
 227         .config_reg = 0x3404,
 228         .status_reg = 0x341c,
 229         .config_val = 0x7845c665,
 230         .droop_reg = 0x3414,
 231         .droop_val = 0x0108c000,
 232         .min_rate = 600000000UL,
 233         .max_rate = 1800000000UL,
 234 };
 235
 236 static struct clk_hfpll hfpll_l2 = {
 237         .d = &hfpll_l2_data,
 238         .clkr.hw.init = &(struct clk_init_data){
 239                 .parent_names = (const char *[]){ "pxo" },
 240                 .num_parents = 1,
 241                 .name = "hfpll_l2",
 242                 .ops = &clk_ops_hfpll,
 243                 .flags = CLK_IGNORE_UNUSED,
 244         },
 245         .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
 246 };
 247
 248 static struct clk_pll pll14 = {
 249         .l_reg = 0x31c4,
 250         .m_reg = 0x31c8,
 251         .n_reg = 0x31cc,
 252         .config_reg = 0x31d4,
 253         .mode_reg = 0x31c0,
 254         .status_reg = 0x31d8,
 255         .status_bit = 16,
 256         .clkr.hw.init = &(struct clk_init_data){
 257                 .name = "pll14",
 258                 .parent_names = (const char *[]){ "pxo" },
 259                 .num_parents = 1,
 260                 .ops = &clk_pll_ops,
 261         },
 262 };
 263
 264 static struct clk_regmap pll14_vote = {
 265         .enable_reg = 0x34c0,
 266         .enable_mask = BIT(14),
 267         .hw.init = &(struct clk_init_data){
 268                 .name = "pll14_vote",
 269                 .parent_names = (const char *[]){ "pll14" },
 270                 .num_parents = 1,
 271                 .ops = &clk_pll_vote_ops,
 272         },
 273 };
 274
 275 enum {
 276         P_PXO,
 277         P_PLL8,
 278         P_PLL3,
 279         P_CXO,
 280 };
 281
 282 static const struct parent_map gcc_pxo_pll8_map[] = {
 283         { P_PXO, 0 },
 284         { P_PLL8, 3 }
 285 };
 286
 287 static const char * const gcc_pxo_pll8[] = {
 288         "pxo",
 289         "pll8_vote",
 290 };
 291
 292 static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
 293         { P_PXO, 0 },
 294         { P_PLL8, 3 },
 295         { P_CXO, 5 }
 296 };
 297
 298 static const char * const gcc_pxo_pll8_cxo[] = {
 299         "pxo",
 300         "pll8_vote",
 301         "cxo",
 302 };
 303
 304 static const struct parent_map gcc_pxo_pll8_pll3_map[] = {
 305         { P_PXO, 0 },
 306         { P_PLL8, 3 },
 307         { P_PLL3, 6 }
 308 };
 309
 310 static const char * const gcc_pxo_pll8_pll3[] = {
 311         "pxo",
 312         "pll8_vote",
 313         "pll3",
 314 };
 315
 316 static struct freq_tbl clk_tbl_gsbi_uart[] = {
 317         {  1843200, P_PLL8, 2,  6, 625 },
 318         {  3686400, P_PLL8, 2, 12, 625 },
 319         {  7372800, P_PLL8, 2, 24, 625 },
 320         { 14745600, P_PLL8, 2, 48, 625 },
 321         { 16000000, P_PLL8, 4,  1,   6 },
 322         { 24000000, P_PLL8, 4,  1,   4 },
 323         { 32000000, P_PLL8, 4,  1,   3 },
 324         { 40000000, P_PLL8, 1,  5,  48 },
 325         { 46400000, P_PLL8, 1, 29, 240 },
 326         { 48000000, P_PLL8, 4,  1,   2 },
 327         { 51200000, P_PLL8, 1,  2,  15 },
 328         { 56000000, P_PLL8, 1,  7,  48 },
 329         { 58982400, P_PLL8, 1, 96, 625 },
 330         { 64000000, P_PLL8, 2,  1,   3 },
 331         { }
 332 };
 333
 334 static struct clk_rcg gsbi1_uart_src = {
 335         .ns_reg = 0x29d4,
 336         .md_reg = 0x29d0,
 337         .mn = {
 338                 .mnctr_en_bit = 8,
 339                 .mnctr_reset_bit = 7,
 340                 .mnctr_mode_shift = 5,
 341                 .n_val_shift = 16,
 342                 .m_val_shift = 16,
 343                 .width = 16,
 344         },
 345         .p = {
 346                 .pre_div_shift = 3,
 347                 .pre_div_width = 2,
 348         },
 349         .s = {
 350                 .src_sel_shift = 0,
 351                 .parent_map = gcc_pxo_pll8_map,
 352         },
 353         .freq_tbl = clk_tbl_gsbi_uart,
 354         .clkr = {
 355                 .enable_reg = 0x29d4,
 356                 .enable_mask = BIT(11),
 357                 .hw.init = &(struct clk_init_data){
 358                         .name = "gsbi1_uart_src",
 359                         .parent_names = gcc_pxo_pll8,
 360                         .num_parents = 2,
 361                         .ops = &clk_rcg_ops,
 362                         .flags = CLK_SET_PARENT_GATE,
 363                 },
 364         },
 365 };
 366
 367 static struct clk_branch gsbi1_uart_clk = {
 368         .halt_reg = 0x2fcc,
 369         .halt_bit = 10,
 370         .clkr = {
 371                 .enable_reg = 0x29d4,
 372                 .enable_mask = BIT(9),
 373                 .hw.init = &(struct clk_init_data){
 374                         .name = "gsbi1_uart_clk",
 375                         .parent_names = (const char *[]){
 376                                 "gsbi1_uart_src",
 377                         },
 378                         .num_parents = 1,
 379                         .ops = &clk_branch_ops,
 380                         .flags = CLK_SET_RATE_PARENT,
 381                 },
 382         },
 383 };
 384
 385 static struct clk_rcg gsbi2_uart_src = {
 386         .ns_reg = 0x29f4,
 387         .md_reg = 0x29f0,
 388         .mn = {
 389                 .mnctr_en_bit = 8,
 390                 .mnctr_reset_bit = 7,
 391                 .mnctr_mode_shift = 5,
 392                 .n_val_shift = 16,
 393                 .m_val_shift = 16,
 394                 .width = 16,
 395         },
 396         .p = {
 397                 .pre_div_shift = 3,
 398                 .pre_div_width = 2,
 399         },
 400         .s = {
 401                 .src_sel_shift = 0,
 402                 .parent_map = gcc_pxo_pll8_map,
 403         },
 404         .freq_tbl = clk_tbl_gsbi_uart,
 405         .clkr = {
 406                 .enable_reg = 0x29f4,
 407                 .enable_mask = BIT(11),
 408                 .hw.init = &(struct clk_init_data){
 409                         .name = "gsbi2_uart_src",
 410                         .parent_names = gcc_pxo_pll8,
 411                         .num_parents = 2,
 412                         .ops = &clk_rcg_ops,
 413                         .flags = CLK_SET_PARENT_GATE,
 414                 },
 415         },
 416 };
 417
 418 static struct clk_branch gsbi2_uart_clk = {
 419         .halt_reg = 0x2fcc,
 420         .halt_bit = 6,
 421         .clkr = {
 422                 .enable_reg = 0x29f4,
 423                 .enable_mask = BIT(9),
 424                 .hw.init = &(struct clk_init_data){
 425                         .name = "gsbi2_uart_clk",
 426                         .parent_names = (const char *[]){
 427                                 "gsbi2_uart_src",
 428                         },
 429                         .num_parents = 1,
 430                         .ops = &clk_branch_ops,
 431                         .flags = CLK_SET_RATE_PARENT,
 432                 },
 433         },
 434 };
 435
 436 static struct clk_rcg gsbi3_uart_src = {
 437         .ns_reg = 0x2a14,
 438         .md_reg = 0x2a10,
 439         .mn = {
 440                 .mnctr_en_bit = 8,
 441                 .mnctr_reset_bit = 7,
 442                 .mnctr_mode_shift = 5,
 443                 .n_val_shift = 16,
 444                 .m_val_shift = 16,
 445                 .width = 16,
 446         },
 447         .p = {
 448                 .pre_div_shift = 3,
 449                 .pre_div_width = 2,
 450         },
 451         .s = {
 452                 .src_sel_shift = 0,
 453                 .parent_map = gcc_pxo_pll8_map,
 454         },
 455         .freq_tbl = clk_tbl_gsbi_uart,
 456         .clkr = {
 457                 .enable_reg = 0x2a14,
 458                 .enable_mask = BIT(11),
 459                 .hw.init = &(struct clk_init_data){
 460                         .name = "gsbi3_uart_src",
 461                         .parent_names = gcc_pxo_pll8,
 462                         .num_parents = 2,
 463                         .ops = &clk_rcg_ops,
 464                         .flags = CLK_SET_PARENT_GATE,
 465                 },
 466         },
 467 };
 468
 469 static struct clk_branch gsbi3_uart_clk = {
 470         .halt_reg = 0x2fcc,
 471         .halt_bit = 2,
 472         .clkr = {
 473                 .enable_reg = 0x2a14,
 474                 .enable_mask = BIT(9),
 475                 .hw.init = &(struct clk_init_data){
 476                         .name = "gsbi3_uart_clk",
 477                         .parent_names = (const char *[]){
 478                                 "gsbi3_uart_src",
 479                         },
 480                         .num_parents = 1,
 481                         .ops = &clk_branch_ops,
 482                         .flags = CLK_SET_RATE_PARENT,
 483                 },
 484         },
 485 };
 486
 487 static struct clk_rcg gsbi4_uart_src = {
 488         .ns_reg = 0x2a34,
 489         .md_reg = 0x2a30,
 490         .mn = {
 491                 .mnctr_en_bit = 8,
 492                 .mnctr_reset_bit = 7,
 493                 .mnctr_mode_shift = 5,
 494                 .n_val_shift = 16,
 495                 .m_val_shift = 16,
 496                 .width = 16,
 497         },
 498         .p = {
 499                 .pre_div_shift = 3,
 500                 .pre_div_width = 2,
 501         },
 502         .s = {
 503                 .src_sel_shift = 0,
 504                 .parent_map = gcc_pxo_pll8_map,
 505         },
 506         .freq_tbl = clk_tbl_gsbi_uart,
 507         .clkr = {
 508                 .enable_reg = 0x2a34,
 509                 .enable_mask = BIT(11),
 510                 .hw.init = &(struct clk_init_data){
 511                         .name = "gsbi4_uart_src",
 512                         .parent_names = gcc_pxo_pll8,
 513                         .num_parents = 2,
 514                         .ops = &clk_rcg_ops,
 515                         .flags = CLK_SET_PARENT_GATE,
 516                 },
 517         },
 518 };
 519
 520 static struct clk_branch gsbi4_uart_clk = {
 521         .halt_reg = 0x2fd0,
 522         .halt_bit = 26,
 523         .clkr = {
 524                 .enable_reg = 0x2a34,
 525                 .enable_mask = BIT(9),
 526                 .hw.init = &(struct clk_init_data){
 527                         .name = "gsbi4_uart_clk",
 528                         .parent_names = (const char *[]){
 529                                 "gsbi4_uart_src",
 530                         },
 531                         .num_parents = 1,
 532                         .ops = &clk_branch_ops,
 533                         .flags = CLK_SET_RATE_PARENT,
 534                 },
 535         },
 536 };
 537
 538 static struct clk_rcg gsbi5_uart_src = {
 539         .ns_reg = 0x2a54,
 540         .md_reg = 0x2a50,
 541         .mn = {
 542                 .mnctr_en_bit = 8,
 543                 .mnctr_reset_bit = 7,
 544                 .mnctr_mode_shift = 5,
 545                 .n_val_shift = 16,
 546                 .m_val_shift = 16,
 547                 .width = 16,
 548         },
 549         .p = {
 550                 .pre_div_shift = 3,
 551                 .pre_div_width = 2,
 552         },
 553         .s = {
 554                 .src_sel_shift = 0,
 555                 .parent_map = gcc_pxo_pll8_map,
 556         },
 557         .freq_tbl = clk_tbl_gsbi_uart,
 558         .clkr = {
 559                 .enable_reg = 0x2a54,
 560                 .enable_mask = BIT(11),
 561                 .hw.init = &(struct clk_init_data){
 562                         .name = "gsbi5_uart_src",
 563                         .parent_names = gcc_pxo_pll8,
 564                         .num_parents = 2,
 565                         .ops = &clk_rcg_ops,
 566                         .flags = CLK_SET_PARENT_GATE,
 567                 },
 568         },
 569 };
 570
 571 static struct clk_branch gsbi5_uart_clk = {
 572         .halt_reg = 0x2fd0,
 573         .halt_bit = 22,
 574         .clkr = {
 575                 .enable_reg = 0x2a54,
 576                 .enable_mask = BIT(9),
 577                 .hw.init = &(struct clk_init_data){
 578                         .name = "gsbi5_uart_clk",
 579                         .parent_names = (const char *[]){
 580                                 "gsbi5_uart_src",
 581                         },
 582                         .num_parents = 1,
 583                         .ops = &clk_branch_ops,
 584                         .flags = CLK_SET_RATE_PARENT,
 585                 },
 586         },
 587 };
 588
 589 static struct clk_rcg gsbi6_uart_src = {
 590         .ns_reg = 0x2a74,
 591         .md_reg = 0x2a70,
 592         .mn = {
 593                 .mnctr_en_bit = 8,
 594                 .mnctr_reset_bit = 7,
 595                 .mnctr_mode_shift = 5,
 596                 .n_val_shift = 16,
 597                 .m_val_shift = 16,
 598                 .width = 16,
 599         },
 600         .p = {
 601                 .pre_div_shift = 3,
 602                 .pre_div_width = 2,
 603         },
 604         .s = {
 605                 .src_sel_shift = 0,
 606                 .parent_map = gcc_pxo_pll8_map,
 607         },
 608         .freq_tbl = clk_tbl_gsbi_uart,
 609         .clkr = {
 610                 .enable_reg = 0x2a74,
 611                 .enable_mask = BIT(11),
 612                 .hw.init = &(struct clk_init_data){
 613                         .name = "gsbi6_uart_src",
 614                         .parent_names = gcc_pxo_pll8,
 615                         .num_parents = 2,
 616                         .ops = &clk_rcg_ops,
 617                         .flags = CLK_SET_PARENT_GATE,
 618                 },
 619         },
 620 };
 621
 622 static struct clk_branch gsbi6_uart_clk = {
 623         .halt_reg = 0x2fd0,
 624         .halt_bit = 18,
 625         .clkr = {
 626                 .enable_reg = 0x2a74,
 627                 .enable_mask = BIT(9),
 628                 .hw.init = &(struct clk_init_data){
 629                         .name = "gsbi6_uart_clk",
 630                         .parent_names = (const char *[]){
 631                                 "gsbi6_uart_src",
 632                         },
 633                         .num_parents = 1,
 634                         .ops = &clk_branch_ops,
 635                         .flags = CLK_SET_RATE_PARENT,
 636                 },
 637         },
 638 };
 639
 640 static struct clk_rcg gsbi7_uart_src = {
 641         .ns_reg = 0x2a94,
 642         .md_reg = 0x2a90,
 643         .mn = {
 644                 .mnctr_en_bit = 8,
 645                 .mnctr_reset_bit = 7,
 646                 .mnctr_mode_shift = 5,
 647                 .n_val_shift = 16,
 648                 .m_val_shift = 16,
 649                 .width = 16,
 650         },
 651         .p = {
 652                 .pre_div_shift = 3,
 653                 .pre_div_width = 2,
 654         },
 655         .s = {
 656                 .src_sel_shift = 0,
 657                 .parent_map = gcc_pxo_pll8_map,
 658         },
 659         .freq_tbl = clk_tbl_gsbi_uart,
 660         .clkr = {
 661                 .enable_reg = 0x2a94,
 662                 .enable_mask = BIT(11),
 663                 .hw.init = &(struct clk_init_data){
 664                         .name = "gsbi7_uart_src",
 665                         .parent_names = gcc_pxo_pll8,
 666                         .num_parents = 2,
 667                         .ops = &clk_rcg_ops,
 668                         .flags = CLK_SET_PARENT_GATE,
 669                 },
 670         },
 671 };
 672
 673 static struct clk_branch gsbi7_uart_clk = {
 674         .halt_reg = 0x2fd0,
 675         .halt_bit = 14,
 676         .clkr = {
 677                 .enable_reg = 0x2a94,
 678                 .enable_mask = BIT(9),
 679                 .hw.init = &(struct clk_init_data){
 680                         .name = "gsbi7_uart_clk",
 681                         .parent_names = (const char *[]){
 682                                 "gsbi7_uart_src",
 683                         },
 684                         .num_parents = 1,
 685                         .ops = &clk_branch_ops,
 686                         .flags = CLK_SET_RATE_PARENT,
 687                 },
 688         },
 689 };
 690
 691 static struct clk_rcg gsbi8_uart_src = {
 692         .ns_reg = 0x2ab4,
 693         .md_reg = 0x2ab0,
 694         .mn = {
 695                 .mnctr_en_bit = 8,
 696                 .mnctr_reset_bit = 7,
 697                 .mnctr_mode_shift = 5,
 698                 .n_val_shift = 16,
 699                 .m_val_shift = 16,
 700                 .width = 16,
 701         },
 702         .p = {
 703                 .pre_div_shift = 3,
 704                 .pre_div_width = 2,
 705         },
 706         .s = {
 707                 .src_sel_shift = 0,
 708                 .parent_map = gcc_pxo_pll8_map,
 709         },
 710         .freq_tbl = clk_tbl_gsbi_uart,
 711         .clkr = {
 712                 .enable_reg = 0x2ab4,
 713                 .enable_mask = BIT(11),
 714                 .hw.init = &(struct clk_init_data){
 715                         .name = "gsbi8_uart_src",
 716                         .parent_names = gcc_pxo_pll8,
 717                         .num_parents = 2,
 718                         .ops = &clk_rcg_ops,
 719                         .flags = CLK_SET_PARENT_GATE,
 720                 },
 721         },
 722 };
 723
 724 static struct clk_branch gsbi8_uart_clk = {
 725         .halt_reg = 0x2fd0,
 726         .halt_bit = 10,
 727         .clkr = {
 728                 .enable_reg = 0x2ab4,
 729                 .enable_mask = BIT(9),
 730                 .hw.init = &(struct clk_init_data){
 731                         .name = "gsbi8_uart_clk",
 732                         .parent_names = (const char *[]){ "gsbi8_uart_src" },
 733                         .num_parents = 1,
 734                         .ops = &clk_branch_ops,
 735                         .flags = CLK_SET_RATE_PARENT,
 736                 },
 737         },
 738 };
 739
 740 static struct clk_rcg gsbi9_uart_src = {
 741         .ns_reg = 0x2ad4,
 742         .md_reg = 0x2ad0,
 743         .mn = {
 744                 .mnctr_en_bit = 8,
 745                 .mnctr_reset_bit = 7,
 746                 .mnctr_mode_shift = 5,
 747                 .n_val_shift = 16,
 748                 .m_val_shift = 16,
 749                 .width = 16,
 750         },
 751         .p = {
 752                 .pre_div_shift = 3,
 753                 .pre_div_width = 2,
 754         },
 755         .s = {
 756                 .src_sel_shift = 0,
 757                 .parent_map = gcc_pxo_pll8_map,
 758         },
 759         .freq_tbl = clk_tbl_gsbi_uart,
 760         .clkr = {
 761                 .enable_reg = 0x2ad4,
 762                 .enable_mask = BIT(11),
 763                 .hw.init = &(struct clk_init_data){
 764                         .name = "gsbi9_uart_src",
 765                         .parent_names = gcc_pxo_pll8,
 766                         .num_parents = 2,
 767                         .ops = &clk_rcg_ops,
 768                         .flags = CLK_SET_PARENT_GATE,
 769                 },
 770         },
 771 };
 772
 773 static struct clk_branch gsbi9_uart_clk = {
 774         .halt_reg = 0x2fd0,
 775         .halt_bit = 6,
 776         .clkr = {
 777                 .enable_reg = 0x2ad4,
 778                 .enable_mask = BIT(9),
 779                 .hw.init = &(struct clk_init_data){
 780                         .name = "gsbi9_uart_clk",
 781                         .parent_names = (const char *[]){ "gsbi9_uart_src" },
 782                         .num_parents = 1,
 783                         .ops = &clk_branch_ops,
 784                         .flags = CLK_SET_RATE_PARENT,
 785                 },
 786         },
 787 };
 788
 789 static struct clk_rcg gsbi10_uart_src = {
 790         .ns_reg = 0x2af4,
 791         .md_reg = 0x2af0,
 792         .mn = {
 793                 .mnctr_en_bit = 8,
 794                 .mnctr_reset_bit = 7,
 795                 .mnctr_mode_shift = 5,
 796                 .n_val_shift = 16,
 797                 .m_val_shift = 16,
 798                 .width = 16,
 799         },
 800         .p = {
 801                 .pre_div_shift = 3,
 802                 .pre_div_width = 2,
 803         },
 804         .s = {
 805                 .src_sel_shift = 0,
 806                 .parent_map = gcc_pxo_pll8_map,
 807         },
 808         .freq_tbl = clk_tbl_gsbi_uart,
 809         .clkr = {
 810                 .enable_reg = 0x2af4,
 811                 .enable_mask = BIT(11),
 812                 .hw.init = &(struct clk_init_data){
 813                         .name = "gsbi10_uart_src",
 814                         .parent_names = gcc_pxo_pll8,
 815                         .num_parents = 2,
 816                         .ops = &clk_rcg_ops,
 817                         .flags = CLK_SET_PARENT_GATE,
 818                 },
 819         },
 820 };
 821
 822 static struct clk_branch gsbi10_uart_clk = {
 823         .halt_reg = 0x2fd0,
 824         .halt_bit = 2,
 825         .clkr = {
 826                 .enable_reg = 0x2af4,
 827                 .enable_mask = BIT(9),
 828                 .hw.init = &(struct clk_init_data){
 829                         .name = "gsbi10_uart_clk",
 830                         .parent_names = (const char *[]){ "gsbi10_uart_src" },
 831                         .num_parents = 1,
 832                         .ops = &clk_branch_ops,
 833                         .flags = CLK_SET_RATE_PARENT,
 834                 },
 835         },
 836 };
 837
 838 static struct clk_rcg gsbi11_uart_src = {
 839         .ns_reg = 0x2b14,
 840         .md_reg = 0x2b10,
 841         .mn = {
 842                 .mnctr_en_bit = 8,
 843                 .mnctr_reset_bit = 7,
 844                 .mnctr_mode_shift = 5,
 845                 .n_val_shift = 16,
 846                 .m_val_shift = 16,
 847                 .width = 16,
 848         },
 849         .p = {
 850                 .pre_div_shift = 3,
 851                 .pre_div_width = 2,
 852         },
 853         .s = {
 854                 .src_sel_shift = 0,
 855                 .parent_map = gcc_pxo_pll8_map,
 856         },
 857         .freq_tbl = clk_tbl_gsbi_uart,
 858         .clkr = {
 859                 .enable_reg = 0x2b14,
 860                 .enable_mask = BIT(11),
 861                 .hw.init = &(struct clk_init_data){
 862                         .name = "gsbi11_uart_src",
 863                         .parent_names = gcc_pxo_pll8,
 864                         .num_parents = 2,
 865                         .ops = &clk_rcg_ops,
 866                         .flags = CLK_SET_PARENT_GATE,
 867                 },
 868         },
 869 };
 870
 871 static struct clk_branch gsbi11_uart_clk = {
 872         .halt_reg = 0x2fd4,
 873         .halt_bit = 17,
 874         .clkr = {
 875                 .enable_reg = 0x2b14,
 876                 .enable_mask = BIT(9),
 877                 .hw.init = &(struct clk_init_data){
 878                         .name = "gsbi11_uart_clk",
 879                         .parent_names = (const char *[]){ "gsbi11_uart_src" },
 880                         .num_parents = 1,
 881                         .ops = &clk_branch_ops,
 882                         .flags = CLK_SET_RATE_PARENT,
 883                 },
 884         },
 885 };
 886
 887 static struct clk_rcg gsbi12_uart_src = {
 888         .ns_reg = 0x2b34,
 889         .md_reg = 0x2b30,
 890         .mn = {
 891                 .mnctr_en_bit = 8,
 892                 .mnctr_reset_bit = 7,
 893                 .mnctr_mode_shift = 5,
 894                 .n_val_shift = 16,
 895                 .m_val_shift = 16,
 896                 .width = 16,
 897         },
 898         .p = {
 899                 .pre_div_shift = 3,
 900                 .pre_div_width = 2,
 901         },
 902         .s = {
 903                 .src_sel_shift = 0,
 904                 .parent_map = gcc_pxo_pll8_map,
 905         },
 906         .freq_tbl = clk_tbl_gsbi_uart,
 907         .clkr = {
 908                 .enable_reg = 0x2b34,
 909                 .enable_mask = BIT(11),
 910                 .hw.init = &(struct clk_init_data){
 911                         .name = "gsbi12_uart_src",
 912                         .parent_names = gcc_pxo_pll8,
 913                         .num_parents = 2,
 914                         .ops = &clk_rcg_ops,
 915                         .flags = CLK_SET_PARENT_GATE,
 916                 },
 917         },
 918 };
 919
 920 static struct clk_branch gsbi12_uart_clk = {
 921         .halt_reg = 0x2fd4,
 922         .halt_bit = 13,
 923         .clkr = {
 924                 .enable_reg = 0x2b34,
 925                 .enable_mask = BIT(9),
 926                 .hw.init = &(struct clk_init_data){
 927                         .name = "gsbi12_uart_clk",
 928                         .parent_names = (const char *[]){ "gsbi12_uart_src" },
 929                         .num_parents = 1,
 930                         .ops = &clk_branch_ops,
 931                         .flags = CLK_SET_RATE_PARENT,
 932                 },
 933         },
 934 };
 935
 936 static struct freq_tbl clk_tbl_gsbi_qup[] = {
 937         {  1100000, P_PXO,  1, 2, 49 },
 938         {  5400000, P_PXO,  1, 1,  5 },
 939         { 10800000, P_PXO,  1, 2,  5 },
 940         { 15060000, P_PLL8, 1, 2, 51 },
 941         { 24000000, P_PLL8, 4, 1,  4 },
 942         { 25600000, P_PLL8, 1, 1, 15 },
 943         { 27000000, P_PXO,  1, 0,  0 },
 944         { 48000000, P_PLL8, 4, 1,  2 },
 945         { 51200000, P_PLL8, 1, 2, 15 },
 946         { }
 947 };
 948
 949 static struct clk_rcg gsbi1_qup_src = {
 950         .ns_reg = 0x29cc,
 951         .md_reg = 0x29c8,
 952         .mn = {
 953                 .mnctr_en_bit = 8,
 954                 .mnctr_reset_bit = 7,
 955                 .mnctr_mode_shift = 5,
 956                 .n_val_shift = 16,
 957                 .m_val_shift = 16,
 958                 .width = 8,
 959         },
 960         .p = {
 961                 .pre_div_shift = 3,
 962                 .pre_div_width = 2,
 963         },
 964         .s = {
 965                 .src_sel_shift = 0,
 966                 .parent_map = gcc_pxo_pll8_map,
 967         },
 968         .freq_tbl = clk_tbl_gsbi_qup,
 969         .clkr = {
 970                 .enable_reg = 0x29cc,
 971                 .enable_mask = BIT(11),
 972                 .hw.init = &(struct clk_init_data){
 973                         .name = "gsbi1_qup_src",
 974                         .parent_names = gcc_pxo_pll8,
 975                         .num_parents = 2,
 976                         .ops = &clk_rcg_ops,
 977                         .flags = CLK_SET_PARENT_GATE,
 978                 },
 979         },
 980 };
 981
 982 static struct clk_branch gsbi1_qup_clk = {
 983         .halt_reg = 0x2fcc,
 984         .halt_bit = 9,
 985         .clkr = {
 986                 .enable_reg = 0x29cc,
 987                 .enable_mask = BIT(9),
 988                 .hw.init = &(struct clk_init_data){
 989                         .name = "gsbi1_qup_clk",
 990                         .parent_names = (const char *[]){ "gsbi1_qup_src" },
 991                         .num_parents = 1,
 992                         .ops = &clk_branch_ops,
 993                         .flags = CLK_SET_RATE_PARENT,
 994                 },
 995         },
 996 };
 997
 998 static struct clk_rcg gsbi2_qup_src = {
 999         .ns_reg = 0x29ec,
1000         .md_reg = 0x29e8,
1001         .mn = {
1002                 .mnctr_en_bit = 8,
1003                 .mnctr_reset_bit = 7,
1004                 .mnctr_mode_shift = 5,
1005                 .n_val_shift = 16,
1006                 .m_val_shift = 16,
1007                 .width = 8,
1008         },
1009         .p = {
1010                 .pre_div_shift = 3,
1011                 .pre_div_width = 2,
1012         },
1013         .s = {
1014                 .src_sel_shift = 0,
1015                 .parent_map = gcc_pxo_pll8_map,
1016         },
1017         .freq_tbl = clk_tbl_gsbi_qup,
1018         .clkr = {
1019                 .enable_reg = 0x29ec,
1020                 .enable_mask = BIT(11),
1021                 .hw.init = &(struct clk_init_data){
1022                         .name = "gsbi2_qup_src",
1023                         .parent_names = gcc_pxo_pll8,
1024                         .num_parents = 2,
1025                         .ops = &clk_rcg_ops,
1026                         .flags = CLK_SET_PARENT_GATE,
1027                 },
1028         },
1029 };
1030
1031 static struct clk_branch gsbi2_qup_clk = {
1032         .halt_reg = 0x2fcc,
1033         .halt_bit = 4,
1034         .clkr = {
1035                 .enable_reg = 0x29ec,
1036                 .enable_mask = BIT(9),
1037                 .hw.init = &(struct clk_init_data){
1038                         .name = "gsbi2_qup_clk",
1039                         .parent_names = (const char *[]){ "gsbi2_qup_src" },
1040                         .num_parents = 1,
1041                         .ops = &clk_branch_ops,
1042                         .flags = CLK_SET_RATE_PARENT,
1043                 },
1044         },
1045 };
1046
1047 static struct clk_rcg gsbi3_qup_src = {
1048         .ns_reg = 0x2a0c,
1049         .md_reg = 0x2a08,
1050         .mn = {
1051                 .mnctr_en_bit = 8,
1052                 .mnctr_reset_bit = 7,
1053                 .mnctr_mode_shift = 5,
1054                 .n_val_shift = 16,
1055                 .m_val_shift = 16,
1056                 .width = 8,
1057         },
1058         .p = {
1059                 .pre_div_shift = 3,
1060                 .pre_div_width = 2,
1061         },
1062         .s = {
1063                 .src_sel_shift = 0,
1064                 .parent_map = gcc_pxo_pll8_map,
1065         },
1066         .freq_tbl = clk_tbl_gsbi_qup,
1067         .clkr = {
1068                 .enable_reg = 0x2a0c,
1069                 .enable_mask = BIT(11),
1070                 .hw.init = &(struct clk_init_data){
1071                         .name = "gsbi3_qup_src",
1072                         .parent_names = gcc_pxo_pll8,
1073                         .num_parents = 2,
1074                         .ops = &clk_rcg_ops,
1075                         .flags = CLK_SET_PARENT_GATE,
1076                 },
1077         },
1078 };
1079
1080 static struct clk_branch gsbi3_qup_clk = {
1081         .halt_reg = 0x2fcc,
1082         .halt_bit = 0,
1083         .clkr = {
1084                 .enable_reg = 0x2a0c,
1085                 .enable_mask = BIT(9),
1086                 .hw.init = &(struct clk_init_data){
1087                         .name = "gsbi3_qup_clk",
1088                         .parent_names = (const char *[]){ "gsbi3_qup_src" },
1089                         .num_parents = 1,
1090                         .ops = &clk_branch_ops,
1091                         .flags = CLK_SET_RATE_PARENT,
1092                 },
1093         },
1094 };
1095
1096 static struct clk_rcg gsbi4_qup_src = {
1097         .ns_reg = 0x2a2c,
1098         .md_reg = 0x2a28,
1099         .mn = {
1100                 .mnctr_en_bit = 8,
1101                 .mnctr_reset_bit = 7,
1102                 .mnctr_mode_shift = 5,
1103                 .n_val_shift = 16,
1104                 .m_val_shift = 16,
1105                 .width = 8,
1106         },
1107         .p = {
1108                 .pre_div_shift = 3,
1109                 .pre_div_width = 2,
1110         },
1111         .s = {
1112                 .src_sel_shift = 0,
1113                 .parent_map = gcc_pxo_pll8_map,
1114         },
1115         .freq_tbl = clk_tbl_gsbi_qup,
1116         .clkr = {
1117                 .enable_reg = 0x2a2c,
1118                 .enable_mask = BIT(11),
1119                 .hw.init = &(struct clk_init_data){
1120                         .name = "gsbi4_qup_src",
1121                         .parent_names = gcc_pxo_pll8,
1122                         .num_parents = 2,
1123                         .ops = &clk_rcg_ops,
1124                         .flags = CLK_SET_PARENT_GATE,
1125                 },
1126         },
1127 };
1128
1129 static struct clk_branch gsbi4_qup_clk = {
1130         .halt_reg = 0x2fd0,
1131         .halt_bit = 24,
1132         .clkr = {
1133                 .enable_reg = 0x2a2c,
1134                 .enable_mask = BIT(9),
1135                 .hw.init = &(struct clk_init_data){
1136                         .name = "gsbi4_qup_clk",
1137                         .parent_names = (const char *[]){ "gsbi4_qup_src" },
1138                         .num_parents = 1,
1139                         .ops = &clk_branch_ops,
1140                         .flags = CLK_SET_RATE_PARENT,
1141                 },
1142         },
1143 };
1144
1145 static struct clk_rcg gsbi5_qup_src = {
1146         .ns_reg = 0x2a4c,
1147         .md_reg = 0x2a48,
1148         .mn = {
1149                 .mnctr_en_bit = 8,
1150                 .mnctr_reset_bit = 7,
1151                 .mnctr_mode_shift = 5,
1152                 .n_val_shift = 16,
1153                 .m_val_shift = 16,
1154                 .width = 8,
1155         },
1156         .p = {
1157                 .pre_div_shift = 3,
1158                 .pre_div_width = 2,
1159         },
1160         .s = {
1161                 .src_sel_shift = 0,
1162                 .parent_map = gcc_pxo_pll8_map,
1163         },
1164         .freq_tbl = clk_tbl_gsbi_qup,
1165         .clkr = {
1166                 .enable_reg = 0x2a4c,
1167                 .enable_mask = BIT(11),
1168                 .hw.init = &(struct clk_init_data){
1169                         .name = "gsbi5_qup_src",
1170                         .parent_names = gcc_pxo_pll8,
1171                         .num_parents = 2,
1172                         .ops = &clk_rcg_ops,
1173                         .flags = CLK_SET_PARENT_GATE,
1174                 },
1175         },
1176 };
1177
1178 static struct clk_branch gsbi5_qup_clk = {
1179         .halt_reg = 0x2fd0,
1180         .halt_bit = 20,
1181         .clkr = {
1182                 .enable_reg = 0x2a4c,
1183                 .enable_mask = BIT(9),
1184                 .hw.init = &(struct clk_init_data){
1185                         .name = "gsbi5_qup_clk",
1186                         .parent_names = (const char *[]){ "gsbi5_qup_src" },
1187                         .num_parents = 1,
1188                         .ops = &clk_branch_ops,
1189                         .flags = CLK_SET_RATE_PARENT,
1190                 },
1191         },
1192 };
1193
1194 static struct clk_rcg gsbi6_qup_src = {
1195         .ns_reg = 0x2a6c,
1196         .md_reg = 0x2a68,
1197         .mn = {
1198                 .mnctr_en_bit = 8,
1199                 .mnctr_reset_bit = 7,
1200                 .mnctr_mode_shift = 5,
1201                 .n_val_shift = 16,
1202                 .m_val_shift = 16,
1203                 .width = 8,
1204         },
1205         .p = {
1206                 .pre_div_shift = 3,
1207                 .pre_div_width = 2,
1208         },
1209         .s = {
1210                 .src_sel_shift = 0,
1211                 .parent_map = gcc_pxo_pll8_map,
1212         },
1213         .freq_tbl = clk_tbl_gsbi_qup,
1214         .clkr = {
1215                 .enable_reg = 0x2a6c,
1216                 .enable_mask = BIT(11),
1217                 .hw.init = &(struct clk_init_data){
1218                         .name = "gsbi6_qup_src",
1219                         .parent_names = gcc_pxo_pll8,
1220                         .num_parents = 2,
1221                         .ops = &clk_rcg_ops,
1222                         .flags = CLK_SET_PARENT_GATE,
1223                 },
1224         },
1225 };
1226
1227 static struct clk_branch gsbi6_qup_clk = {
1228         .halt_reg = 0x2fd0,
1229         .halt_bit = 16,
1230         .clkr = {
1231                 .enable_reg = 0x2a6c,
1232                 .enable_mask = BIT(9),
1233                 .hw.init = &(struct clk_init_data){
1234                         .name = "gsbi6_qup_clk",
1235                         .parent_names = (const char *[]){ "gsbi6_qup_src" },
1236                         .num_parents = 1,
1237                         .ops = &clk_branch_ops,
1238                         .flags = CLK_SET_RATE_PARENT,
1239                 },
1240         },
1241 };
1242
1243 static struct clk_rcg gsbi7_qup_src = {
1244         .ns_reg = 0x2a8c,
1245         .md_reg = 0x2a88,
1246         .mn = {
1247                 .mnctr_en_bit = 8,
1248                 .mnctr_reset_bit = 7,
1249                 .mnctr_mode_shift = 5,
1250                 .n_val_shift = 16,
1251                 .m_val_shift = 16,
1252                 .width = 8,
1253         },
1254         .p = {
1255                 .pre_div_shift = 3,
1256                 .pre_div_width = 2,
1257         },
1258         .s = {
1259                 .src_sel_shift = 0,
1260                 .parent_map = gcc_pxo_pll8_map,
1261         },
1262         .freq_tbl = clk_tbl_gsbi_qup,
1263         .clkr = {
1264                 .enable_reg = 0x2a8c,
1265                 .enable_mask = BIT(11),
1266                 .hw.init = &(struct clk_init_data){
1267                         .name = "gsbi7_qup_src",
1268                         .parent_names = gcc_pxo_pll8,
1269                         .num_parents = 2,
1270                         .ops = &clk_rcg_ops,
1271                         .flags = CLK_SET_PARENT_GATE,
1272                 },
1273         },
1274 };
1275
1276 static struct clk_branch gsbi7_qup_clk = {
1277         .halt_reg = 0x2fd0,
1278         .halt_bit = 12,
1279         .clkr = {
1280                 .enable_reg = 0x2a8c,
1281                 .enable_mask = BIT(9),
1282                 .hw.init = &(struct clk_init_data){
1283                         .name = "gsbi7_qup_clk",
1284                         .parent_names = (const char *[]){ "gsbi7_qup_src" },
1285                         .num_parents = 1,
1286                         .ops = &clk_branch_ops,
1287                         .flags = CLK_SET_RATE_PARENT,
1288                 },
1289         },
1290 };
1291
1292 static struct clk_rcg gsbi8_qup_src = {
1293         .ns_reg = 0x2aac,
1294         .md_reg = 0x2aa8,
1295         .mn = {
1296                 .mnctr_en_bit = 8,
1297                 .mnctr_reset_bit = 7,
1298                 .mnctr_mode_shift = 5,
1299                 .n_val_shift = 16,
1300                 .m_val_shift = 16,
1301                 .width = 8,
1302         },
1303         .p = {
1304                 .pre_div_shift = 3,
1305                 .pre_div_width = 2,
1306         },
1307         .s = {
1308                 .src_sel_shift = 0,
1309                 .parent_map = gcc_pxo_pll8_map,
1310         },
1311         .freq_tbl = clk_tbl_gsbi_qup,
1312         .clkr = {
1313                 .enable_reg = 0x2aac,
1314                 .enable_mask = BIT(11),
1315                 .hw.init = &(struct clk_init_data){
1316                         .name = "gsbi8_qup_src",
1317                         .parent_names = gcc_pxo_pll8,
1318                         .num_parents = 2,
1319                         .ops = &clk_rcg_ops,
1320                         .flags = CLK_SET_PARENT_GATE,
1321                 },
1322         },
1323 };
1324
1325 static struct clk_branch gsbi8_qup_clk = {
1326         .halt_reg = 0x2fd0,
1327         .halt_bit = 8,
1328         .clkr = {
1329                 .enable_reg = 0x2aac,
1330                 .enable_mask = BIT(9),
1331                 .hw.init = &(struct clk_init_data){
1332                         .name = "gsbi8_qup_clk",
1333                         .parent_names = (const char *[]){ "gsbi8_qup_src" },
1334                         .num_parents = 1,
1335                         .ops = &clk_branch_ops,
1336                         .flags = CLK_SET_RATE_PARENT,
1337                 },
1338         },
1339 };
1340
1341 static struct clk_rcg gsbi9_qup_src = {
1342         .ns_reg = 0x2acc,
1343         .md_reg = 0x2ac8,
1344         .mn = {
1345                 .mnctr_en_bit = 8,
1346                 .mnctr_reset_bit = 7,
1347                 .mnctr_mode_shift = 5,
1348                 .n_val_shift = 16,
1349                 .m_val_shift = 16,
1350                 .width = 8,
1351         },
1352         .p = {
1353                 .pre_div_shift = 3,
1354                 .pre_div_width = 2,
1355         },
1356         .s = {
1357                 .src_sel_shift = 0,
1358                 .parent_map = gcc_pxo_pll8_map,
1359         },
1360         .freq_tbl = clk_tbl_gsbi_qup,
1361         .clkr = {
1362                 .enable_reg = 0x2acc,
1363                 .enable_mask = BIT(11),
1364                 .hw.init = &(struct clk_init_data){
1365                         .name = "gsbi9_qup_src",
1366                         .parent_names = gcc_pxo_pll8,
1367                         .num_parents = 2,
1368                         .ops = &clk_rcg_ops,
1369                         .flags = CLK_SET_PARENT_GATE,
1370                 },
1371         },
1372 };
1373
1374 static struct clk_branch gsbi9_qup_clk = {
1375         .halt_reg = 0x2fd0,
1376         .halt_bit = 4,
1377         .clkr = {
1378                 .enable_reg = 0x2acc,
1379                 .enable_mask = BIT(9),
1380                 .hw.init = &(struct clk_init_data){
1381                         .name = "gsbi9_qup_clk",
1382                         .parent_names = (const char *[]){ "gsbi9_qup_src" },
1383                         .num_parents = 1,
1384                         .ops = &clk_branch_ops,
1385                         .flags = CLK_SET_RATE_PARENT,
1386                 },
1387         },
1388 };
1389
1390 static struct clk_rcg gsbi10_qup_src = {
1391         .ns_reg = 0x2aec,
1392         .md_reg = 0x2ae8,
1393         .mn = {
1394                 .mnctr_en_bit = 8,
1395                 .mnctr_reset_bit = 7,
1396                 .mnctr_mode_shift = 5,
1397                 .n_val_shift = 16,
1398                 .m_val_shift = 16,
1399                 .width = 8,
1400         },
1401         .p = {
1402                 .pre_div_shift = 3,
1403                 .pre_div_width = 2,
1404         },
1405         .s = {
1406                 .src_sel_shift = 0,
1407                 .parent_map = gcc_pxo_pll8_map,
1408         },
1409         .freq_tbl = clk_tbl_gsbi_qup,
1410         .clkr = {
1411                 .enable_reg = 0x2aec,
1412                 .enable_mask = BIT(11),
1413                 .hw.init = &(struct clk_init_data){
1414                         .name = "gsbi10_qup_src",
1415                         .parent_names = gcc_pxo_pll8,
1416                         .num_parents = 2,
1417                         .ops = &clk_rcg_ops,
1418                         .flags = CLK_SET_PARENT_GATE,
1419                 },
1420         },
1421 };
1422
1423 static struct clk_branch gsbi10_qup_clk = {
1424         .halt_reg = 0x2fd0,
1425         .halt_bit = 0,
1426         .clkr = {
1427                 .enable_reg = 0x2aec,
1428                 .enable_mask = BIT(9),
1429                 .hw.init = &(struct clk_init_data){
1430                         .name = "gsbi10_qup_clk",
1431                         .parent_names = (const char *[]){ "gsbi10_qup_src" },
1432                         .num_parents = 1,
1433                         .ops = &clk_branch_ops,
1434                         .flags = CLK_SET_RATE_PARENT,
1435                 },
1436         },
1437 };
1438
1439 static struct clk_rcg gsbi11_qup_src = {
1440         .ns_reg = 0x2b0c,
1441         .md_reg = 0x2b08,
1442         .mn = {
1443                 .mnctr_en_bit = 8,
1444                 .mnctr_reset_bit = 7,
1445                 .mnctr_mode_shift = 5,
1446                 .n_val_shift = 16,
1447                 .m_val_shift = 16,
1448                 .width = 8,
1449         },
1450         .p = {
1451                 .pre_div_shift = 3,
1452                 .pre_div_width = 2,
1453         },
1454         .s = {
1455                 .src_sel_shift = 0,
1456                 .parent_map = gcc_pxo_pll8_map,
1457         },
1458         .freq_tbl = clk_tbl_gsbi_qup,
1459         .clkr = {
1460                 .enable_reg = 0x2b0c,
1461                 .enable_mask = BIT(11),
1462                 .hw.init = &(struct clk_init_data){
1463                         .name = "gsbi11_qup_src",
1464                         .parent_names = gcc_pxo_pll8,
1465                         .num_parents = 2,
1466                         .ops = &clk_rcg_ops,
1467                         .flags = CLK_SET_PARENT_GATE,
1468                 },
1469         },
1470 };
1471
1472 static struct clk_branch gsbi11_qup_clk = {
1473         .halt_reg = 0x2fd4,
1474         .halt_bit = 15,
1475         .clkr = {
1476                 .enable_reg = 0x2b0c,
1477                 .enable_mask = BIT(9),
1478                 .hw.init = &(struct clk_init_data){
1479                         .name = "gsbi11_qup_clk",
1480                         .parent_names = (const char *[]){ "gsbi11_qup_src" },
1481                         .num_parents = 1,
1482                         .ops = &clk_branch_ops,
1483                         .flags = CLK_SET_RATE_PARENT,
1484                 },
1485         },
1486 };
1487
1488 static struct clk_rcg gsbi12_qup_src = {
1489         .ns_reg = 0x2b2c,
1490         .md_reg = 0x2b28,
1491         .mn = {
1492                 .mnctr_en_bit = 8,
1493                 .mnctr_reset_bit = 7,
1494                 .mnctr_mode_shift = 5,
1495                 .n_val_shift = 16,
1496                 .m_val_shift = 16,
1497                 .width = 8,
1498         },
1499         .p = {
1500                 .pre_div_shift = 3,
1501                 .pre_div_width = 2,
1502         },
1503         .s = {
1504                 .src_sel_shift = 0,
1505                 .parent_map = gcc_pxo_pll8_map,
1506         },
1507         .freq_tbl = clk_tbl_gsbi_qup,
1508         .clkr = {
1509                 .enable_reg = 0x2b2c,
1510                 .enable_mask = BIT(11),
1511                 .hw.init = &(struct clk_init_data){
1512                         .name = "gsbi12_qup_src",
1513                         .parent_names = gcc_pxo_pll8,
1514                         .num_parents = 2,
1515                         .ops = &clk_rcg_ops,
1516                         .flags = CLK_SET_PARENT_GATE,
1517                 },
1518         },
1519 };
1520
1521 static struct clk_branch gsbi12_qup_clk = {
1522         .halt_reg = 0x2fd4,
1523         .halt_bit = 11,
1524         .clkr = {
1525                 .enable_reg = 0x2b2c,
1526                 .enable_mask = BIT(9),
1527                 .hw.init = &(struct clk_init_data){
1528                         .name = "gsbi12_qup_clk",
1529                         .parent_names = (const char *[]){ "gsbi12_qup_src" },
1530                         .num_parents = 1,
1531                         .ops = &clk_branch_ops,
1532                         .flags = CLK_SET_RATE_PARENT,
1533                 },
1534         },
1535 };
1536
1537 static const struct freq_tbl clk_tbl_gp[] = {
1538         { 9600000, P_CXO,  2, 0, 0 },
1539         { 13500000, P_PXO,  2, 0, 0 },
1540         { 19200000, P_CXO,  1, 0, 0 },
1541         { 27000000, P_PXO,  1, 0, 0 },
1542         { 64000000, P_PLL8, 2, 1, 3 },
1543         { 76800000, P_PLL8, 1, 1, 5 },
1544         { 96000000, P_PLL8, 4, 0, 0 },
1545         { 128000000, P_PLL8, 3, 0, 0 },
1546         { 192000000, P_PLL8, 2, 0, 0 },
1547         { }
1548 };
1549
1550 static struct clk_rcg gp0_src = {
1551         .ns_reg = 0x2d24,
1552         .md_reg = 0x2d00,
1553         .mn = {
1554                 .mnctr_en_bit = 8,
1555                 .mnctr_reset_bit = 7,
1556                 .mnctr_mode_shift = 5,
1557                 .n_val_shift = 16,
1558                 .m_val_shift = 16,
1559                 .width = 8,
1560         },
1561         .p = {
1562                 .pre_div_shift = 3,
1563                 .pre_div_width = 2,
1564         },
1565         .s = {
1566                 .src_sel_shift = 0,
1567                 .parent_map = gcc_pxo_pll8_cxo_map,
1568         },
1569         .freq_tbl = clk_tbl_gp,
1570         .clkr = {
1571                 .enable_reg = 0x2d24,
1572                 .enable_mask = BIT(11),
1573                 .hw.init = &(struct clk_init_data){
1574                         .name = "gp0_src",
1575                         .parent_names = gcc_pxo_pll8_cxo,
1576                         .num_parents = 3,
1577                         .ops = &clk_rcg_ops,
1578                         .flags = CLK_SET_PARENT_GATE,
1579                 },
1580         }
1581 };
1582
1583 static struct clk_branch gp0_clk = {
1584         .halt_reg = 0x2fd8,
1585         .halt_bit = 7,
1586         .clkr = {
1587                 .enable_reg = 0x2d24,
1588                 .enable_mask = BIT(9),
1589                 .hw.init = &(struct clk_init_data){
1590                         .name = "gp0_clk",
1591                         .parent_names = (const char *[]){ "gp0_src" },
1592                         .num_parents = 1,
1593                         .ops = &clk_branch_ops,
1594                         .flags = CLK_SET_RATE_PARENT,
1595                 },
1596         },
1597 };
1598
1599 static struct clk_rcg gp1_src = {
1600         .ns_reg = 0x2d44,
1601         .md_reg = 0x2d40,
1602         .mn = {
1603                 .mnctr_en_bit = 8,
1604                 .mnctr_reset_bit = 7,
1605                 .mnctr_mode_shift = 5,
1606                 .n_val_shift = 16,
1607                 .m_val_shift = 16,
1608                 .width = 8,
1609         },
1610         .p = {
1611                 .pre_div_shift = 3,
1612                 .pre_div_width = 2,
1613         },
1614         .s = {
1615                 .src_sel_shift = 0,
1616                 .parent_map = gcc_pxo_pll8_cxo_map,
1617         },
1618         .freq_tbl = clk_tbl_gp,
1619         .clkr = {
1620                 .enable_reg = 0x2d44,
1621                 .enable_mask = BIT(11),
1622                 .hw.init = &(struct clk_init_data){
1623                         .name = "gp1_src",
1624                         .parent_names = gcc_pxo_pll8_cxo,
1625                         .num_parents = 3,
1626                         .ops = &clk_rcg_ops,
1627                         .flags = CLK_SET_RATE_GATE,
1628                 },
1629         }
1630 };
1631
1632 static struct clk_branch gp1_clk = {
1633         .halt_reg = 0x2fd8,
1634         .halt_bit = 6,
1635         .clkr = {
1636                 .enable_reg = 0x2d44,
1637                 .enable_mask = BIT(9),
1638                 .hw.init = &(struct clk_init_data){
1639                         .name = "gp1_clk",
1640                         .parent_names = (const char *[]){ "gp1_src" },
1641                         .num_parents = 1,
1642                         .ops = &clk_branch_ops,
1643                         .flags = CLK_SET_RATE_PARENT,
1644                 },
1645         },
1646 };
1647
1648 static struct clk_rcg gp2_src = {
1649         .ns_reg = 0x2d64,
1650         .md_reg = 0x2d60,
1651         .mn = {
1652                 .mnctr_en_bit = 8,
1653                 .mnctr_reset_bit = 7,
1654                 .mnctr_mode_shift = 5,
1655                 .n_val_shift = 16,
1656                 .m_val_shift = 16,
1657                 .width = 8,
1658         },
1659         .p = {
1660                 .pre_div_shift = 3,
1661                 .pre_div_width = 2,
1662         },
1663         .s = {
1664                 .src_sel_shift = 0,
1665                 .parent_map = gcc_pxo_pll8_cxo_map,
1666         },
1667         .freq_tbl = clk_tbl_gp,
1668         .clkr = {
1669                 .enable_reg = 0x2d64,
1670                 .enable_mask = BIT(11),
1671                 .hw.init = &(struct clk_init_data){
1672                         .name = "gp2_src",
1673                         .parent_names = gcc_pxo_pll8_cxo,
1674                         .num_parents = 3,
1675                         .ops = &clk_rcg_ops,
1676                         .flags = CLK_SET_RATE_GATE,
1677                 },
1678         }
1679 };
1680
1681 static struct clk_branch gp2_clk = {
1682         .halt_reg = 0x2fd8,
1683         .halt_bit = 5,
1684         .clkr = {
1685                 .enable_reg = 0x2d64,
1686                 .enable_mask = BIT(9),
1687                 .hw.init = &(struct clk_init_data){
1688                         .name = "gp2_clk",
1689                         .parent_names = (const char *[]){ "gp2_src" },
1690                         .num_parents = 1,
1691                         .ops = &clk_branch_ops,
1692                         .flags = CLK_SET_RATE_PARENT,
1693                 },
1694         },
1695 };
1696
1697 static struct clk_branch pmem_clk = {
1698         .hwcg_reg = 0x25a0,
1699         .hwcg_bit = 6,
1700         .halt_reg = 0x2fc8,
1701         .halt_bit = 20,
1702         .clkr = {
1703                 .enable_reg = 0x25a0,
1704                 .enable_mask = BIT(4),
1705                 .hw.init = &(struct clk_init_data){
1706                         .name = "pmem_clk",
1707                         .ops = &clk_branch_ops,
1708                 },
1709         },
1710 };
1711
1712 static struct clk_rcg prng_src = {
1713         .ns_reg = 0x2e80,
1714         .p = {
1715                 .pre_div_shift = 3,
1716                 .pre_div_width = 4,
1717         },
1718         .s = {
1719                 .src_sel_shift = 0,
1720                 .parent_map = gcc_pxo_pll8_map,
1721         },
1722         .clkr = {
1723                 .hw.init = &(struct clk_init_data){
1724                         .name = "prng_src",
1725                         .parent_names = gcc_pxo_pll8,
1726                         .num_parents = 2,
1727                         .ops = &clk_rcg_ops,
1728                 },
1729         },
1730 };
1731
1732 static struct clk_branch prng_clk = {
1733         .halt_reg = 0x2fd8,
1734         .halt_check = BRANCH_HALT_VOTED,
1735         .halt_bit = 10,
1736         .clkr = {
1737                 .enable_reg = 0x3080,
1738                 .enable_mask = BIT(10),
1739                 .hw.init = &(struct clk_init_data){
1740                         .name = "prng_clk",
1741                         .parent_names = (const char *[]){ "prng_src" },
1742                         .num_parents = 1,
1743                         .ops = &clk_branch_ops,
1744                 },
1745         },
1746 };
1747
1748 static const struct freq_tbl clk_tbl_sdc[] = {
1749         {    144000, P_PXO,   3, 2, 125 },
1750         {    400000, P_PLL8,  4, 1, 240 },
1751         {  16000000, P_PLL8,  4, 1,   6 },
1752         {  17070000, P_PLL8,  1, 2,  45 },
1753         {  20210000, P_PLL8,  1, 1,  19 },
1754         {  24000000, P_PLL8,  4, 1,   4 },
1755         {  48000000, P_PLL8,  4, 1,   2 },
1756         {  64000000, P_PLL8,  3, 1,   2 },
1757         {  96000000, P_PLL8,  4, 0,   0 },
1758         { 192000000, P_PLL8,  2, 0,   0 },
1759         { }
1760 };
1761
1762 static struct clk_rcg sdc1_src = {
1763         .ns_reg = 0x282c,
1764         .md_reg = 0x2828,
1765         .mn = {
1766                 .mnctr_en_bit = 8,
1767                 .mnctr_reset_bit = 7,
1768                 .mnctr_mode_shift = 5,
1769                 .n_val_shift = 16,
1770                 .m_val_shift = 16,
1771                 .width = 8,
1772         },
1773         .p = {
1774                 .pre_div_shift = 3,
1775                 .pre_div_width = 2,
1776         },
1777         .s = {
1778                 .src_sel_shift = 0,
1779                 .parent_map = gcc_pxo_pll8_map,
1780         },
1781         .freq_tbl = clk_tbl_sdc,
1782         .clkr = {
1783                 .enable_reg = 0x282c,
1784                 .enable_mask = BIT(11),
1785                 .hw.init = &(struct clk_init_data){
1786                         .name = "sdc1_src",
1787                         .parent_names = gcc_pxo_pll8,
1788                         .num_parents = 2,
1789                         .ops = &clk_rcg_ops,
1790                 },
1791         }
1792 };
1793
1794 static struct clk_branch sdc1_clk = {
1795         .halt_reg = 0x2fc8,
1796         .halt_bit = 6,
1797         .clkr = {
1798                 .enable_reg = 0x282c,
1799                 .enable_mask = BIT(9),
1800                 .hw.init = &(struct clk_init_data){
1801                         .name = "sdc1_clk",
1802                         .parent_names = (const char *[]){ "sdc1_src" },
1803                         .num_parents = 1,
1804                         .ops = &clk_branch_ops,
1805                         .flags = CLK_SET_RATE_PARENT,
1806                 },
1807         },
1808 };
1809
1810 static struct clk_rcg sdc2_src = {
1811         .ns_reg = 0x284c,
1812         .md_reg = 0x2848,
1813         .mn = {
1814                 .mnctr_en_bit = 8,
1815                 .mnctr_reset_bit = 7,
1816                 .mnctr_mode_shift = 5,
1817                 .n_val_shift = 16,
1818                 .m_val_shift = 16,
1819                 .width = 8,
1820         },
1821         .p = {
1822                 .pre_div_shift = 3,
1823                 .pre_div_width = 2,
1824         },
1825         .s = {
1826                 .src_sel_shift = 0,
1827                 .parent_map = gcc_pxo_pll8_map,
1828         },
1829         .freq_tbl = clk_tbl_sdc,
1830         .clkr = {
1831                 .enable_reg = 0x284c,
1832                 .enable_mask = BIT(11),
1833                 .hw.init = &(struct clk_init_data){
1834                         .name = "sdc2_src",
1835                         .parent_names = gcc_pxo_pll8,
1836                         .num_parents = 2,
1837                         .ops = &clk_rcg_ops,
1838                 },
1839         }
1840 };
1841
1842 static struct clk_branch sdc2_clk = {
1843         .halt_reg = 0x2fc8,
1844         .halt_bit = 5,
1845         .clkr = {
1846                 .enable_reg = 0x284c,
1847                 .enable_mask = BIT(9),
1848                 .hw.init = &(struct clk_init_data){
1849                         .name = "sdc2_clk",
1850                         .parent_names = (const char *[]){ "sdc2_src" },
1851                         .num_parents = 1,
1852                         .ops = &clk_branch_ops,
1853                         .flags = CLK_SET_RATE_PARENT,
1854                 },
1855         },
1856 };
1857
1858 static struct clk_rcg sdc3_src = {
1859         .ns_reg = 0x286c,
1860         .md_reg = 0x2868,
1861         .mn = {
1862                 .mnctr_en_bit = 8,
1863                 .mnctr_reset_bit = 7,
1864                 .mnctr_mode_shift = 5,
1865                 .n_val_shift = 16,
1866                 .m_val_shift = 16,
1867                 .width = 8,
1868         },
1869         .p = {
1870                 .pre_div_shift = 3,
1871                 .pre_div_width = 2,
1872         },
1873         .s = {
1874                 .src_sel_shift = 0,
1875                 .parent_map = gcc_pxo_pll8_map,
1876         },
1877         .freq_tbl = clk_tbl_sdc,
1878         .clkr = {
1879                 .enable_reg = 0x286c,
1880                 .enable_mask = BIT(11),
1881                 .hw.init = &(struct clk_init_data){
1882                         .name = "sdc3_src",
1883                         .parent_names = gcc_pxo_pll8,
1884                         .num_parents = 2,
1885                         .ops = &clk_rcg_ops,
1886                 },
1887         }
1888 };
1889
1890 static struct clk_branch sdc3_clk = {
1891         .halt_reg = 0x2fc8,
1892         .halt_bit = 4,
1893         .clkr = {
1894                 .enable_reg = 0x286c,
1895                 .enable_mask = BIT(9),
1896                 .hw.init = &(struct clk_init_data){
1897                         .name = "sdc3_clk",
1898                         .parent_names = (const char *[]){ "sdc3_src" },
1899                         .num_parents = 1,
1900                         .ops = &clk_branch_ops,
1901                         .flags = CLK_SET_RATE_PARENT,
1902                 },
1903         },
1904 };
1905
1906 static struct clk_rcg sdc4_src = {
1907         .ns_reg = 0x288c,
1908         .md_reg = 0x2888,
1909         .mn = {
1910                 .mnctr_en_bit = 8,
1911                 .mnctr_reset_bit = 7,
1912                 .mnctr_mode_shift = 5,
1913                 .n_val_shift = 16,
1914                 .m_val_shift = 16,
1915                 .width = 8,
1916         },
1917         .p = {
1918                 .pre_div_shift = 3,
1919                 .pre_div_width = 2,
1920         },
1921         .s = {
1922                 .src_sel_shift = 0,
1923                 .parent_map = gcc_pxo_pll8_map,
1924         },
1925         .freq_tbl = clk_tbl_sdc,
1926         .clkr = {
1927                 .enable_reg = 0x288c,
1928                 .enable_mask = BIT(11),
1929                 .hw.init = &(struct clk_init_data){
1930                         .name = "sdc4_src",
1931                         .parent_names = gcc_pxo_pll8,
1932                         .num_parents = 2,
1933                         .ops = &clk_rcg_ops,
1934                 },
1935         }
1936 };
1937
1938 static struct clk_branch sdc4_clk = {
1939         .halt_reg = 0x2fc8,
1940         .halt_bit = 3,
1941         .clkr = {
1942                 .enable_reg = 0x288c,
1943                 .enable_mask = BIT(9),
1944                 .hw.init = &(struct clk_init_data){
1945                         .name = "sdc4_clk",
1946                         .parent_names = (const char *[]){ "sdc4_src" },
1947                         .num_parents = 1,
1948                         .ops = &clk_branch_ops,
1949                         .flags = CLK_SET_RATE_PARENT,
1950                 },
1951         },
1952 };
1953
1954 static struct clk_rcg sdc5_src = {
1955         .ns_reg = 0x28ac,
1956         .md_reg = 0x28a8,
1957         .mn = {
1958                 .mnctr_en_bit = 8,
1959                 .mnctr_reset_bit = 7,
1960                 .mnctr_mode_shift = 5,
1961                 .n_val_shift = 16,
1962                 .m_val_shift = 16,
1963                 .width = 8,
1964         },
1965         .p = {
1966                 .pre_div_shift = 3,
1967                 .pre_div_width = 2,
1968         },
1969         .s = {
1970                 .src_sel_shift = 0,
1971                 .parent_map = gcc_pxo_pll8_map,
1972         },
1973         .freq_tbl = clk_tbl_sdc,
1974         .clkr = {
1975                 .enable_reg = 0x28ac,
1976                 .enable_mask = BIT(11),
1977                 .hw.init = &(struct clk_init_data){
1978                         .name = "sdc5_src",
1979                         .parent_names = gcc_pxo_pll8,
1980                         .num_parents = 2,
1981                         .ops = &clk_rcg_ops,
1982                 },
1983         }
1984 };
1985
1986 static struct clk_branch sdc5_clk = {
1987         .halt_reg = 0x2fc8,
1988         .halt_bit = 2,
1989         .clkr = {
1990                 .enable_reg = 0x28ac,
1991                 .enable_mask = BIT(9),
1992                 .hw.init = &(struct clk_init_data){
1993                         .name = "sdc5_clk",
1994                         .parent_names = (const char *[]){ "sdc5_src" },
1995                         .num_parents = 1,
1996                         .ops = &clk_branch_ops,
1997                         .flags = CLK_SET_RATE_PARENT,
1998                 },
1999         },
2000 };
2001
2002 static const struct freq_tbl clk_tbl_tsif_ref[] = {
2003         { 105000, P_PXO,  1, 1, 256 },
2004         { }
2005 };
2006
2007 static struct clk_rcg tsif_ref_src = {
2008         .ns_reg = 0x2710,
2009         .md_reg = 0x270c,
2010         .mn = {
2011                 .mnctr_en_bit = 8,
2012                 .mnctr_reset_bit = 7,
2013                 .mnctr_mode_shift = 5,
2014                 .n_val_shift = 16,
2015                 .m_val_shift = 16,
2016                 .width = 16,
2017         },
2018         .p = {
2019                 .pre_div_shift = 3,
2020                 .pre_div_width = 2,
2021         },
2022         .s = {
2023                 .src_sel_shift = 0,
2024                 .parent_map = gcc_pxo_pll8_map,
2025         },
2026         .freq_tbl = clk_tbl_tsif_ref,
2027         .clkr = {
2028                 .enable_reg = 0x2710,
2029                 .enable_mask = BIT(11),
2030                 .hw.init = &(struct clk_init_data){
2031                         .name = "tsif_ref_src",
2032                         .parent_names = gcc_pxo_pll8,
2033                         .num_parents = 2,
2034                         .ops = &clk_rcg_ops,
2035                         .flags = CLK_SET_RATE_GATE,
2036                 },
2037         }
2038 };
2039
2040 static struct clk_branch tsif_ref_clk = {
2041         .halt_reg = 0x2fd4,
2042         .halt_bit = 5,
2043         .clkr = {
2044                 .enable_reg = 0x2710,
2045                 .enable_mask = BIT(9),
2046                 .hw.init = &(struct clk_init_data){
2047                         .name = "tsif_ref_clk",
2048                         .parent_names = (const char *[]){ "tsif_ref_src" },
2049                         .num_parents = 1,
2050                         .ops = &clk_branch_ops,
2051                         .flags = CLK_SET_RATE_PARENT,
2052                 },
2053         },
2054 };
2055
2056 static const struct freq_tbl clk_tbl_usb[] = {
2057         { 60000000, P_PLL8, 1, 5, 32 },
2058         { }
2059 };
2060
2061 static struct clk_rcg usb_hs1_xcvr_src = {
2062         .ns_reg = 0x290c,
2063         .md_reg = 0x2908,
2064         .mn = {
2065                 .mnctr_en_bit = 8,
2066                 .mnctr_reset_bit = 7,
2067                 .mnctr_mode_shift = 5,
2068                 .n_val_shift = 16,
2069                 .m_val_shift = 16,
2070                 .width = 8,
2071         },
2072         .p = {
2073                 .pre_div_shift = 3,
2074                 .pre_div_width = 2,
2075         },
2076         .s = {
2077                 .src_sel_shift = 0,
2078                 .parent_map = gcc_pxo_pll8_map,
2079         },
2080         .freq_tbl = clk_tbl_usb,
2081         .clkr = {
2082                 .enable_reg = 0x290c,
2083                 .enable_mask = BIT(11),
2084                 .hw.init = &(struct clk_init_data){
2085                         .name = "usb_hs1_xcvr_src",
2086                         .parent_names = gcc_pxo_pll8,
2087                         .num_parents = 2,
2088                         .ops = &clk_rcg_ops,
2089                         .flags = CLK_SET_RATE_GATE,
2090                 },
2091         }
2092 };
2093
2094 static struct clk_branch usb_hs1_xcvr_clk = {
2095         .halt_reg = 0x2fc8,
2096         .halt_bit = 0,
2097         .clkr = {
2098                 .enable_reg = 0x290c,
2099                 .enable_mask = BIT(9),
2100                 .hw.init = &(struct clk_init_data){
2101                         .name = "usb_hs1_xcvr_clk",
2102                         .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
2103                         .num_parents = 1,
2104                         .ops = &clk_branch_ops,
2105                         .flags = CLK_SET_RATE_PARENT,
2106                 },
2107         },
2108 };
2109
2110 static struct clk_rcg usb_hs3_xcvr_src = {
2111         .ns_reg = 0x370c,
2112         .md_reg = 0x3708,
2113         .mn = {
2114                 .mnctr_en_bit = 8,
2115                 .mnctr_reset_bit = 7,
2116                 .mnctr_mode_shift = 5,
2117                 .n_val_shift = 16,
2118                 .m_val_shift = 16,
2119                 .width = 8,
2120         },
2121         .p = {
2122                 .pre_div_shift = 3,
2123                 .pre_div_width = 2,
2124         },
2125         .s = {
2126                 .src_sel_shift = 0,
2127                 .parent_map = gcc_pxo_pll8_map,
2128         },
2129         .freq_tbl = clk_tbl_usb,
2130         .clkr = {
2131                 .enable_reg = 0x370c,
2132                 .enable_mask = BIT(11),
2133                 .hw.init = &(struct clk_init_data){
2134                         .name = "usb_hs3_xcvr_src",
2135                         .parent_names = gcc_pxo_pll8,
2136                         .num_parents = 2,
2137                         .ops = &clk_rcg_ops,
2138                         .flags = CLK_SET_RATE_GATE,
2139                 },
2140         }
2141 };
2142
2143 static struct clk_branch usb_hs3_xcvr_clk = {
2144         .halt_reg = 0x2fc8,
2145         .halt_bit = 30,
2146         .clkr = {
2147                 .enable_reg = 0x370c,
2148                 .enable_mask = BIT(9),
2149                 .hw.init = &(struct clk_init_data){
2150                         .name = "usb_hs3_xcvr_clk",
2151                         .parent_names = (const char *[]){ "usb_hs3_xcvr_src" },
2152                         .num_parents = 1,
2153                         .ops = &clk_branch_ops,
2154                         .flags = CLK_SET_RATE_PARENT,
2155                 },
2156         },
2157 };
2158
2159 static struct clk_rcg usb_hs4_xcvr_src = {
2160         .ns_reg = 0x372c,
2161         .md_reg = 0x3728,
2162         .mn = {
2163                 .mnctr_en_bit = 8,
2164                 .mnctr_reset_bit = 7,
2165                 .mnctr_mode_shift = 5,
2166                 .n_val_shift = 16,
2167                 .m_val_shift = 16,
2168                 .width = 8,
2169         },
2170         .p = {
2171                 .pre_div_shift = 3,
2172                 .pre_div_width = 2,
2173         },
2174         .s = {
2175                 .src_sel_shift = 0,
2176                 .parent_map = gcc_pxo_pll8_map,
2177         },
2178         .freq_tbl = clk_tbl_usb,
2179         .clkr = {
2180                 .enable_reg = 0x372c,
2181                 .enable_mask = BIT(11),
2182                 .hw.init = &(struct clk_init_data){
2183                         .name = "usb_hs4_xcvr_src",
2184                         .parent_names = gcc_pxo_pll8,
2185                         .num_parents = 2,
2186                         .ops = &clk_rcg_ops,
2187                         .flags = CLK_SET_RATE_GATE,
2188                 },
2189         }
2190 };
2191
2192 static struct clk_branch usb_hs4_xcvr_clk = {
2193         .halt_reg = 0x2fc8,
2194         .halt_bit = 2,
2195         .clkr = {
2196                 .enable_reg = 0x372c,
2197                 .enable_mask = BIT(9),
2198                 .hw.init = &(struct clk_init_data){
2199                         .name = "usb_hs4_xcvr_clk",
2200                         .parent_names = (const char *[]){ "usb_hs4_xcvr_src" },
2201                         .num_parents = 1,
2202                         .ops = &clk_branch_ops,
2203                         .flags = CLK_SET_RATE_PARENT,
2204                 },
2205         },
2206 };
2207
2208 static struct clk_rcg usb_hsic_xcvr_fs_src = {
2209         .ns_reg = 0x2928,
2210         .md_reg = 0x2924,
2211         .mn = {
2212                 .mnctr_en_bit = 8,
2213                 .mnctr_reset_bit = 7,
2214                 .mnctr_mode_shift = 5,
2215                 .n_val_shift = 16,
2216                 .m_val_shift = 16,
2217                 .width = 8,
2218         },
2219         .p = {
2220                 .pre_div_shift = 3,
2221                 .pre_div_width = 2,
2222         },
2223         .s = {
2224                 .src_sel_shift = 0,
2225                 .parent_map = gcc_pxo_pll8_map,
2226         },
2227         .freq_tbl = clk_tbl_usb,
2228         .clkr = {
2229                 .enable_reg = 0x2928,
2230                 .enable_mask = BIT(11),
2231                 .hw.init = &(struct clk_init_data){
2232                         .name = "usb_hsic_xcvr_fs_src",
2233                         .parent_names = gcc_pxo_pll8,
2234                         .num_parents = 2,
2235                         .ops = &clk_rcg_ops,
2236                         .flags = CLK_SET_RATE_GATE,
2237                 },
2238         }
2239 };
2240
2241 static const char * const usb_hsic_xcvr_fs_src_p[] = { "usb_hsic_xcvr_fs_src" };
2242
2243 static struct clk_branch usb_hsic_xcvr_fs_clk = {
2244         .halt_reg = 0x2fc8,
2245         .halt_bit = 2,
2246         .clkr = {
2247                 .enable_reg = 0x2928,
2248                 .enable_mask = BIT(9),
2249                 .hw.init = &(struct clk_init_data){
2250                         .name = "usb_hsic_xcvr_fs_clk",
2251                         .parent_names = usb_hsic_xcvr_fs_src_p,
2252                         .num_parents = 1,
2253                         .ops = &clk_branch_ops,
2254                         .flags = CLK_SET_RATE_PARENT,
2255                 },
2256         },
2257 };
2258
2259 static struct clk_branch usb_hsic_system_clk = {
2260         .halt_reg = 0x2fcc,
2261         .halt_bit = 24,
2262         .clkr = {
2263                 .enable_reg = 0x292c,
2264                 .enable_mask = BIT(4),
2265                 .hw.init = &(struct clk_init_data){
2266                         .parent_names = usb_hsic_xcvr_fs_src_p,
2267                         .num_parents = 1,
2268                         .name = "usb_hsic_system_clk",
2269                         .ops = &clk_branch_ops,
2270                         .flags = CLK_SET_RATE_PARENT,
2271                 },
2272         },
2273 };
2274
2275 static struct clk_branch usb_hsic_hsic_clk = {
2276         .halt_reg = 0x2fcc,
2277         .halt_bit = 19,
2278         .clkr = {
2279                 .enable_reg = 0x2b44,
2280                 .enable_mask = BIT(0),
2281                 .hw.init = &(struct clk_init_data){
2282                         .parent_names = (const char *[]){ "pll14_vote" },
2283                         .num_parents = 1,
2284                         .name = "usb_hsic_hsic_clk",
2285                         .ops = &clk_branch_ops,
2286                 },
2287         },
2288 };
2289
2290 static struct clk_branch usb_hsic_hsio_cal_clk = {
2291         .halt_reg = 0x2fcc,
2292         .halt_bit = 23,
2293         .clkr = {
2294                 .enable_reg = 0x2b48,
2295                 .enable_mask = BIT(0),
2296                 .hw.init = &(struct clk_init_data){
2297                         .name = "usb_hsic_hsio_cal_clk",
2298                         .ops = &clk_branch_ops,
2299                 },
2300         },
2301 };
2302
2303 static struct clk_rcg usb_fs1_xcvr_fs_src = {
2304         .ns_reg = 0x2968,
2305         .md_reg = 0x2964,
2306         .mn = {
2307                 .mnctr_en_bit = 8,
2308                 .mnctr_reset_bit = 7,
2309                 .mnctr_mode_shift = 5,
2310                 .n_val_shift = 16,
2311                 .m_val_shift = 16,
2312                 .width = 8,
2313         },
2314         .p = {
2315                 .pre_div_shift = 3,
2316                 .pre_div_width = 2,
2317         },
2318         .s = {
2319                 .src_sel_shift = 0,
2320                 .parent_map = gcc_pxo_pll8_map,
2321         },
2322         .freq_tbl = clk_tbl_usb,
2323         .clkr = {
2324                 .enable_reg = 0x2968,
2325                 .enable_mask = BIT(11),
2326                 .hw.init = &(struct clk_init_data){
2327                         .name = "usb_fs1_xcvr_fs_src",
2328                         .parent_names = gcc_pxo_pll8,
2329                         .num_parents = 2,
2330                         .ops = &clk_rcg_ops,
2331                         .flags = CLK_SET_RATE_GATE,
2332                 },
2333         }
2334 };
2335
2336 static const char * const usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" };
2337
2338 static struct clk_branch usb_fs1_xcvr_fs_clk = {
2339         .halt_reg = 0x2fcc,
2340         .halt_bit = 15,
2341         .clkr = {
2342                 .enable_reg = 0x2968,
2343                 .enable_mask = BIT(9),
2344                 .hw.init = &(struct clk_init_data){
2345                         .name = "usb_fs1_xcvr_fs_clk",
2346                         .parent_names = usb_fs1_xcvr_fs_src_p,
2347                         .num_parents = 1,
2348                         .ops = &clk_branch_ops,
2349                         .flags = CLK_SET_RATE_PARENT,
2350                 },
2351         },
2352 };
2353
2354 static struct clk_branch usb_fs1_system_clk = {
2355         .halt_reg = 0x2fcc,
2356         .halt_bit = 16,
2357         .clkr = {
2358                 .enable_reg = 0x296c,
2359                 .enable_mask = BIT(4),
2360                 .hw.init = &(struct clk_init_data){
2361                         .parent_names = usb_fs1_xcvr_fs_src_p,
2362                         .num_parents = 1,
2363                         .name = "usb_fs1_system_clk",
2364                         .ops = &clk_branch_ops,
2365                         .flags = CLK_SET_RATE_PARENT,
2366                 },
2367         },
2368 };
2369
2370 static struct clk_rcg usb_fs2_xcvr_fs_src = {
2371         .ns_reg = 0x2988,
2372         .md_reg = 0x2984,
2373         .mn = {
2374                 .mnctr_en_bit = 8,
2375                 .mnctr_reset_bit = 7,
2376                 .mnctr_mode_shift = 5,
2377                 .n_val_shift = 16,
2378                 .m_val_shift = 16,
2379                 .width = 8,
2380         },
2381         .p = {
2382                 .pre_div_shift = 3,
2383                 .pre_div_width = 2,
2384         },
2385         .s = {
2386                 .src_sel_shift = 0,
2387                 .parent_map = gcc_pxo_pll8_map,
2388         },
2389         .freq_tbl = clk_tbl_usb,
2390         .clkr = {
2391                 .enable_reg = 0x2988,
2392                 .enable_mask = BIT(11),
2393                 .hw.init = &(struct clk_init_data){
2394                         .name = "usb_fs2_xcvr_fs_src",
2395                         .parent_names = gcc_pxo_pll8,
2396                         .num_parents = 2,
2397                         .ops = &clk_rcg_ops,
2398                         .flags = CLK_SET_RATE_GATE,
2399                 },
2400         }
2401 };
2402
2403 static const char * const usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" };
2404
2405 static struct clk_branch usb_fs2_xcvr_fs_clk = {
2406         .halt_reg = 0x2fcc,
2407         .halt_bit = 12,
2408         .clkr = {
2409                 .enable_reg = 0x2988,
2410                 .enable_mask = BIT(9),
2411                 .hw.init = &(struct clk_init_data){
2412                         .name = "usb_fs2_xcvr_fs_clk",
2413                         .parent_names = usb_fs2_xcvr_fs_src_p,
2414                         .num_parents = 1,
2415                         .ops = &clk_branch_ops,
2416                         .flags = CLK_SET_RATE_PARENT,
2417                 },
2418         },
2419 };
2420
2421 static struct clk_branch usb_fs2_system_clk = {
2422         .halt_reg = 0x2fcc,
2423         .halt_bit = 13,
2424         .clkr = {
2425                 .enable_reg = 0x298c,
2426                 .enable_mask = BIT(4),
2427                 .hw.init = &(struct clk_init_data){
2428                         .name = "usb_fs2_system_clk",
2429                         .parent_names = usb_fs2_xcvr_fs_src_p,
2430                         .num_parents = 1,
2431                         .ops = &clk_branch_ops,
2432                         .flags = CLK_SET_RATE_PARENT,
2433                 },
2434         },
2435 };
2436
2437 static struct clk_branch ce1_core_clk = {
2438         .hwcg_reg = 0x2724,
2439         .hwcg_bit = 6,
2440         .halt_reg = 0x2fd4,
2441         .halt_bit = 27,
2442         .clkr = {
2443                 .enable_reg = 0x2724,
2444                 .enable_mask = BIT(4),
2445                 .hw.init = &(struct clk_init_data){
2446                         .name = "ce1_core_clk",
2447                         .ops = &clk_branch_ops,
2448                 },
2449         },
2450 };
2451
2452 static struct clk_branch ce1_h_clk = {
2453         .halt_reg = 0x2fd4,
2454         .halt_bit = 1,
2455         .clkr = {
2456                 .enable_reg = 0x2720,
2457                 .enable_mask = BIT(4),
2458                 .hw.init = &(struct clk_init_data){
2459                         .name = "ce1_h_clk",
2460                         .ops = &clk_branch_ops,
2461                 },
2462         },
2463 };
2464
2465 static struct clk_branch dma_bam_h_clk = {
2466         .hwcg_reg = 0x25c0,
2467         .hwcg_bit = 6,
2468         .halt_reg = 0x2fc8,
2469         .halt_bit = 12,
2470         .clkr = {
2471                 .enable_reg = 0x25c0,
2472                 .enable_mask = BIT(4),
2473                 .hw.init = &(struct clk_init_data){
2474                         .name = "dma_bam_h_clk",
2475                         .ops = &clk_branch_ops,
2476                 },
2477         },
2478 };
2479
2480 static struct clk_branch gsbi1_h_clk = {
2481         .hwcg_reg = 0x29c0,
2482         .hwcg_bit = 6,
2483         .halt_reg = 0x2fcc,
2484         .halt_bit = 11,
2485         .clkr = {
2486                 .enable_reg = 0x29c0,
2487                 .enable_mask = BIT(4),
2488                 .hw.init = &(struct clk_init_data){
2489                         .name = "gsbi1_h_clk",
2490                         .ops = &clk_branch_ops,
2491                 },
2492         },
2493 };
2494
2495 static struct clk_branch gsbi2_h_clk = {
2496         .hwcg_reg = 0x29e0,
2497         .hwcg_bit = 6,
2498         .halt_reg = 0x2fcc,
2499         .halt_bit = 7,
2500         .clkr = {
2501                 .enable_reg = 0x29e0,
2502                 .enable_mask = BIT(4),
2503                 .hw.init = &(struct clk_init_data){
2504                         .name = "gsbi2_h_clk",
2505                         .ops = &clk_branch_ops,
2506                 },
2507         },
2508 };
2509
2510 static struct clk_branch gsbi3_h_clk = {
2511         .hwcg_reg = 0x2a00,
2512         .hwcg_bit = 6,
2513         .halt_reg = 0x2fcc,
2514         .halt_bit = 3,
2515         .clkr = {
2516                 .enable_reg = 0x2a00,
2517                 .enable_mask = BIT(4),
2518                 .hw.init = &(struct clk_init_data){
2519                         .name = "gsbi3_h_clk",
2520                         .ops = &clk_branch_ops,
2521                 },
2522         },
2523 };
2524
2525 static struct clk_branch gsbi4_h_clk = {
2526         .hwcg_reg = 0x2a20,
2527         .hwcg_bit = 6,
2528         .halt_reg = 0x2fd0,
2529         .halt_bit = 27,
2530         .clkr = {
2531                 .enable_reg = 0x2a20,
2532                 .enable_mask = BIT(4),
2533                 .hw.init = &(struct clk_init_data){
2534                         .name = "gsbi4_h_clk",
2535                         .ops = &clk_branch_ops,
2536                 },
2537         },
2538 };
2539
2540 static struct clk_branch gsbi5_h_clk = {
2541         .hwcg_reg = 0x2a40,
2542         .hwcg_bit = 6,
2543         .halt_reg = 0x2fd0,
2544         .halt_bit = 23,
2545         .clkr = {
2546                 .enable_reg = 0x2a40,
2547                 .enable_mask = BIT(4),
2548                 .hw.init = &(struct clk_init_data){
2549                         .name = "gsbi5_h_clk",
2550                         .ops = &clk_branch_ops,
2551                 },
2552         },
2553 };
2554
2555 static struct clk_branch gsbi6_h_clk = {
2556         .hwcg_reg = 0x2a60,
2557         .hwcg_bit = 6,
2558         .halt_reg = 0x2fd0,
2559         .halt_bit = 19,
2560         .clkr = {
2561                 .enable_reg = 0x2a60,
2562                 .enable_mask = BIT(4),
2563                 .hw.init = &(struct clk_init_data){
2564                         .name = "gsbi6_h_clk",
2565                         .ops = &clk_branch_ops,
2566                 },
2567         },
2568 };
2569
2570 static struct clk_branch gsbi7_h_clk = {
2571         .hwcg_reg = 0x2a80,
2572         .hwcg_bit = 6,
2573         .halt_reg = 0x2fd0,
2574         .halt_bit = 15,
2575         .clkr = {
2576                 .enable_reg = 0x2a80,
2577                 .enable_mask = BIT(4),
2578                 .hw.init = &(struct clk_init_data){
2579                         .name = "gsbi7_h_clk",
2580                         .ops = &clk_branch_ops,
2581                 },
2582         },
2583 };
2584
2585 static struct clk_branch gsbi8_h_clk = {
2586         .hwcg_reg = 0x2aa0,
2587         .hwcg_bit = 6,
2588         .halt_reg = 0x2fd0,
2589         .halt_bit = 11,
2590         .clkr = {
2591                 .enable_reg = 0x2aa0,
2592                 .enable_mask = BIT(4),
2593                 .hw.init = &(struct clk_init_data){
2594                         .name = "gsbi8_h_clk",
2595                         .ops = &clk_branch_ops,
2596                 },
2597         },
2598 };
2599
2600 static struct clk_branch gsbi9_h_clk = {
2601         .hwcg_reg = 0x2ac0,
2602         .hwcg_bit = 6,
2603         .halt_reg = 0x2fd0,
2604         .halt_bit = 7,
2605         .clkr = {
2606                 .enable_reg = 0x2ac0,
2607                 .enable_mask = BIT(4),
2608                 .hw.init = &(struct clk_init_data){
2609                         .name = "gsbi9_h_clk",
2610                         .ops = &clk_branch_ops,
2611                 },
2612         },
2613 };
2614
2615 static struct clk_branch gsbi10_h_clk = {
2616         .hwcg_reg = 0x2ae0,
2617         .hwcg_bit = 6,
2618         .halt_reg = 0x2fd0,
2619         .halt_bit = 3,
2620         .clkr = {
2621                 .enable_reg = 0x2ae0,
2622                 .enable_mask = BIT(4),
2623                 .hw.init = &(struct clk_init_data){
2624                         .name = "gsbi10_h_clk",
2625                         .ops = &clk_branch_ops,
2626                 },
2627         },
2628 };
2629
2630 static struct clk_branch gsbi11_h_clk = {
2631         .hwcg_reg = 0x2b00,
2632         .hwcg_bit = 6,
2633         .halt_reg = 0x2fd4,
2634         .halt_bit = 18,
2635         .clkr = {
2636                 .enable_reg = 0x2b00,
2637                 .enable_mask = BIT(4),
2638                 .hw.init = &(struct clk_init_data){
2639                         .name = "gsbi11_h_clk",
2640                         .ops = &clk_branch_ops,
2641                 },
2642         },
2643 };
2644
2645 static struct clk_branch gsbi12_h_clk = {
2646         .hwcg_reg = 0x2b20,
2647         .hwcg_bit = 6,
2648         .halt_reg = 0x2fd4,
2649         .halt_bit = 14,
2650         .clkr = {
2651                 .enable_reg = 0x2b20,
2652                 .enable_mask = BIT(4),
2653                 .hw.init = &(struct clk_init_data){
2654                         .name = "gsbi12_h_clk",
2655                         .ops = &clk_branch_ops,
2656                 },
2657         },
2658 };
2659
2660 static struct clk_branch tsif_h_clk = {
2661         .hwcg_reg = 0x2700,
2662         .hwcg_bit = 6,
2663         .halt_reg = 0x2fd4,
2664         .halt_bit = 7,
2665         .clkr = {
2666                 .enable_reg = 0x2700,
2667                 .enable_mask = BIT(4),
2668                 .hw.init = &(struct clk_init_data){
2669                         .name = "tsif_h_clk",
2670                         .ops = &clk_branch_ops,
2671                 },
2672         },
2673 };
2674
2675 static struct clk_branch usb_fs1_h_clk = {
2676         .halt_reg = 0x2fcc,
2677         .halt_bit = 17,
2678         .clkr = {
2679                 .enable_reg = 0x2960,
2680                 .enable_mask = BIT(4),
2681                 .hw.init = &(struct clk_init_data){
2682                         .name = "usb_fs1_h_clk",
2683                         .ops = &clk_branch_ops,
2684                 },
2685         },
2686 };
2687
2688 static struct clk_branch usb_fs2_h_clk = {
2689         .halt_reg = 0x2fcc,
2690         .halt_bit = 14,
2691         .clkr = {
2692                 .enable_reg = 0x2980,
2693                 .enable_mask = BIT(4),
2694                 .hw.init = &(struct clk_init_data){
2695                         .name = "usb_fs2_h_clk",
2696                         .ops = &clk_branch_ops,
2697                 },
2698         },
2699 };
2700
2701 static struct clk_branch usb_hs1_h_clk = {
2702         .hwcg_reg = 0x2900,
2703         .hwcg_bit = 6,
2704         .halt_reg = 0x2fc8,
2705         .halt_bit = 1,
2706         .clkr = {
2707                 .enable_reg = 0x2900,
2708                 .enable_mask = BIT(4),
2709                 .hw.init = &(struct clk_init_data){
2710                         .name = "usb_hs1_h_clk",
2711                         .ops = &clk_branch_ops,
2712                 },
2713         },
2714 };
2715
2716 static struct clk_branch usb_hs3_h_clk = {
2717         .halt_reg = 0x2fc8,
2718         .halt_bit = 31,
2719         .clkr = {
2720                 .enable_reg = 0x3700,
2721                 .enable_mask = BIT(4),
2722                 .hw.init = &(struct clk_init_data){
2723                         .name = "usb_hs3_h_clk",
2724                         .ops = &clk_branch_ops,
2725                 },
2726         },
2727 };
2728
2729 static struct clk_branch usb_hs4_h_clk = {
2730         .halt_reg = 0x2fc8,
2731         .halt_bit = 7,
2732         .clkr = {
2733                 .enable_reg = 0x3720,
2734                 .enable_mask = BIT(4),
2735                 .hw.init = &(struct clk_init_data){
2736                         .name = "usb_hs4_h_clk",
2737                         .ops = &clk_branch_ops,
2738                 },
2739         },
2740 };
2741
2742 static struct clk_branch usb_hsic_h_clk = {
2743         .halt_reg = 0x2fcc,
2744         .halt_bit = 28,
2745         .clkr = {
2746                 .enable_reg = 0x2920,
2747                 .enable_mask = BIT(4),
2748                 .hw.init = &(struct clk_init_data){
2749                         .name = "usb_hsic_h_clk",
2750                         .ops = &clk_branch_ops,
2751                 },
2752         },
2753 };
2754
2755 static struct clk_branch sdc1_h_clk = {
2756         .hwcg_reg = 0x2820,
2757         .hwcg_bit = 6,
2758         .halt_reg = 0x2fc8,
2759         .halt_bit = 11,
2760         .clkr = {
2761                 .enable_reg = 0x2820,
2762                 .enable_mask = BIT(4),
2763                 .hw.init = &(struct clk_init_data){
2764                         .name = "sdc1_h_clk",
2765                         .ops = &clk_branch_ops,
2766                 },
2767         },
2768 };
2769
2770 static struct clk_branch sdc2_h_clk = {
2771         .hwcg_reg = 0x2840,
2772         .hwcg_bit = 6,
2773         .halt_reg = 0x2fc8,
2774         .halt_bit = 10,
2775         .clkr = {
2776                 .enable_reg = 0x2840,
2777                 .enable_mask = BIT(4),
2778                 .hw.init = &(struct clk_init_data){
2779                         .name = "sdc2_h_clk",
2780                         .ops = &clk_branch_ops,
2781                 },
2782         },
2783 };
2784
2785 static struct clk_branch sdc3_h_clk = {
2786         .hwcg_reg = 0x2860,
2787         .hwcg_bit = 6,
2788         .halt_reg = 0x2fc8,
2789         .halt_bit = 9,
2790         .clkr = {
2791                 .enable_reg = 0x2860,
2792                 .enable_mask = BIT(4),
2793                 .hw.init = &(struct clk_init_data){
2794                         .name = "sdc3_h_clk",
2795                         .ops = &clk_branch_ops,
2796                 },
2797         },
2798 };
2799
2800 static struct clk_branch sdc4_h_clk = {
2801         .hwcg_reg = 0x2880,
2802         .hwcg_bit = 6,
2803         .halt_reg = 0x2fc8,
2804         .halt_bit = 8,
2805         .clkr = {
2806                 .enable_reg = 0x2880,
2807                 .enable_mask = BIT(4),
2808                 .hw.init = &(struct clk_init_data){
2809                         .name = "sdc4_h_clk",
2810                         .ops = &clk_branch_ops,
2811                 },
2812         },
2813 };
2814
2815 static struct clk_branch sdc5_h_clk = {
2816         .hwcg_reg = 0x28a0,
2817         .hwcg_bit = 6,
2818         .halt_reg = 0x2fc8,
2819         .halt_bit = 7,
2820         .clkr = {
2821                 .enable_reg = 0x28a0,
2822                 .enable_mask = BIT(4),
2823                 .hw.init = &(struct clk_init_data){
2824                         .name = "sdc5_h_clk",
2825                         .ops = &clk_branch_ops,
2826                 },
2827         },
2828 };
2829
2830 static struct clk_branch adm0_clk = {
2831         .halt_reg = 0x2fdc,
2832         .halt_check = BRANCH_HALT_VOTED,
2833         .halt_bit = 14,
2834         .clkr = {
2835                 .enable_reg = 0x3080,
2836                 .enable_mask = BIT(2),
2837                 .hw.init = &(struct clk_init_data){
2838                         .name = "adm0_clk",
2839                         .ops = &clk_branch_ops,
2840                 },
2841         },
2842 };
2843
2844 static struct clk_branch adm0_pbus_clk = {
2845         .hwcg_reg = 0x2208,
2846         .hwcg_bit = 6,
2847         .halt_reg = 0x2fdc,
2848         .halt_check = BRANCH_HALT_VOTED,
2849         .halt_bit = 13,
2850         .clkr = {
2851                 .enable_reg = 0x3080,
2852                 .enable_mask = BIT(3),
2853                 .hw.init = &(struct clk_init_data){
2854                         .name = "adm0_pbus_clk",
2855                         .ops = &clk_branch_ops,
2856                 },
2857         },
2858 };
2859
2860 static struct freq_tbl clk_tbl_ce3[] = {
2861         { 48000000, P_PLL8, 8 },
2862         { 100000000, P_PLL3, 12 },
2863         { 120000000, P_PLL3, 10 },
2864         { }
2865 };
2866
2867 static struct clk_rcg ce3_src = {
2868         .ns_reg = 0x36c0,
2869         .p = {
2870                 .pre_div_shift = 3,
2871                 .pre_div_width = 4,
2872         },
2873         .s = {
2874                 .src_sel_shift = 0,
2875                 .parent_map = gcc_pxo_pll8_pll3_map,
2876         },
2877         .freq_tbl = clk_tbl_ce3,
2878         .clkr = {
2879                 .enable_reg = 0x36c0,
2880                 .enable_mask = BIT(7),
2881                 .hw.init = &(struct clk_init_data){
2882                         .name = "ce3_src",
2883                         .parent_names = gcc_pxo_pll8_pll3,
2884                         .num_parents = 3,
2885                         .ops = &clk_rcg_ops,
2886                         .flags = CLK_SET_RATE_GATE,
2887                 },
2888         },
2889 };
2890
2891 static struct clk_branch ce3_core_clk = {
2892         .halt_reg = 0x2fdc,
2893         .halt_bit = 5,
2894         .clkr = {
2895                 .enable_reg = 0x36cc,
2896                 .enable_mask = BIT(4),
2897                 .hw.init = &(struct clk_init_data){
2898                         .name = "ce3_core_clk",
2899                         .parent_names = (const char *[]){ "ce3_src" },
2900                         .num_parents = 1,
2901                         .ops = &clk_branch_ops,
2902                         .flags = CLK_SET_RATE_PARENT,
2903                 },
2904         },
2905 };
2906
2907 static struct clk_branch ce3_h_clk = {
2908         .halt_reg = 0x2fc4,
2909         .halt_bit = 16,
2910         .clkr = {
2911                 .enable_reg = 0x36c4,
2912                 .enable_mask = BIT(4),
2913                 .hw.init = &(struct clk_init_data){
2914                         .name = "ce3_h_clk",
2915                         .parent_names = (const char *[]){ "ce3_src" },
2916                         .num_parents = 1,
2917                         .ops = &clk_branch_ops,
2918                         .flags = CLK_SET_RATE_PARENT,
2919                 },
2920         },
2921 };
2922
2923 static const struct freq_tbl clk_tbl_sata_ref[] = {
2924         { 48000000, P_PLL8, 8, 0, 0 },
2925         { 100000000, P_PLL3, 12, 0, 0 },
2926         { }
2927 };
2928
2929 static struct clk_rcg sata_clk_src = {
2930         .ns_reg = 0x2c08,
2931         .p = {
2932                 .pre_div_shift = 3,
2933                 .pre_div_width = 4,
2934         },
2935         .s = {
2936                 .src_sel_shift = 0,
2937                 .parent_map = gcc_pxo_pll8_pll3_map,
2938         },
2939         .freq_tbl = clk_tbl_sata_ref,
2940         .clkr = {
2941                 .enable_reg = 0x2c08,
2942                 .enable_mask = BIT(7),
2943                 .hw.init = &(struct clk_init_data){
2944                         .name = "sata_clk_src",
2945                         .parent_names = gcc_pxo_pll8_pll3,
2946                         .num_parents = 3,
2947                         .ops = &clk_rcg_ops,
2948                         .flags = CLK_SET_RATE_GATE,
2949                 },
2950         },
2951 };
2952
2953 static struct clk_branch sata_rxoob_clk = {
2954         .halt_reg = 0x2fdc,
2955         .halt_bit = 26,
2956         .clkr = {
2957                 .enable_reg = 0x2c0c,
2958                 .enable_mask = BIT(4),
2959                 .hw.init = &(struct clk_init_data){
2960                         .name = "sata_rxoob_clk",
2961                         .parent_names = (const char *[]){ "sata_clk_src" },
2962                         .num_parents = 1,
2963                         .ops = &clk_branch_ops,
2964                         .flags = CLK_SET_RATE_PARENT,
2965                 },
2966         },
2967 };
2968
2969 static struct clk_branch sata_pmalive_clk = {
2970         .halt_reg = 0x2fdc,
2971         .halt_bit = 25,
2972         .clkr = {
2973                 .enable_reg = 0x2c10,
2974                 .enable_mask = BIT(4),
2975                 .hw.init = &(struct clk_init_data){
2976                         .name = "sata_pmalive_clk",
2977                         .parent_names = (const char *[]){ "sata_clk_src" },
2978                         .num_parents = 1,
2979                         .ops = &clk_branch_ops,
2980                         .flags = CLK_SET_RATE_PARENT,
2981                 },
2982         },
2983 };
2984
2985 static struct clk_branch sata_phy_ref_clk = {
2986         .halt_reg = 0x2fdc,
2987         .halt_bit = 24,
2988         .clkr = {
2989                 .enable_reg = 0x2c14,
2990                 .enable_mask = BIT(4),
2991                 .hw.init = &(struct clk_init_data){
2992                         .name = "sata_phy_ref_clk",
2993                         .parent_names = (const char *[]){ "pxo" },
2994                         .num_parents = 1,
2995                         .ops = &clk_branch_ops,
2996                 },
2997         },
2998 };
2999
3000 static struct clk_branch sata_a_clk = {
3001         .halt_reg = 0x2fc0,
3002         .halt_bit = 12,
3003         .clkr = {
3004                 .enable_reg = 0x2c20,
3005                 .enable_mask = BIT(4),
3006                 .hw.init = &(struct clk_init_data){
3007                         .name = "sata_a_clk",
3008                         .ops = &clk_branch_ops,
3009                 },
3010         },
3011 };
3012
3013 static struct clk_branch sata_h_clk = {
3014         .halt_reg = 0x2fdc,
3015         .halt_bit = 27,
3016         .clkr = {
3017                 .enable_reg = 0x2c00,
3018                 .enable_mask = BIT(4),
3019                 .hw.init = &(struct clk_init_data){
3020                         .name = "sata_h_clk",
3021                         .ops = &clk_branch_ops,
3022                 },
3023         },
3024 };
3025
3026 static struct clk_branch sfab_sata_s_h_clk = {
3027         .halt_reg = 0x2fc4,
3028         .halt_bit = 14,
3029         .clkr = {
3030                 .enable_reg = 0x2480,
3031                 .enable_mask = BIT(4),
3032                 .hw.init = &(struct clk_init_data){
3033                         .name = "sfab_sata_s_h_clk",
3034                         .ops = &clk_branch_ops,
3035                 },
3036         },
3037 };
3038
3039 static struct clk_branch sata_phy_cfg_clk = {
3040         .halt_reg = 0x2fcc,
3041         .halt_bit = 12,
3042         .clkr = {
3043                 .enable_reg = 0x2c40,
3044                 .enable_mask = BIT(4),
3045                 .hw.init = &(struct clk_init_data){
3046                         .name = "sata_phy_cfg_clk",
3047                         .ops = &clk_branch_ops,
3048                 },
3049         },
3050 };
3051
3052 static struct clk_branch pcie_phy_ref_clk = {
3053         .halt_reg = 0x2fdc,
3054         .halt_bit = 29,
3055         .clkr = {
3056                 .enable_reg = 0x22d0,
3057                 .enable_mask = BIT(4),
3058                 .hw.init = &(struct clk_init_data){
3059                         .name = "pcie_phy_ref_clk",
3060                         .ops = &clk_branch_ops,
3061                 },
3062         },
3063 };
3064
3065 static struct clk_branch pcie_h_clk = {
3066         .halt_reg = 0x2fd4,
3067         .halt_bit = 8,
3068         .clkr = {
3069                 .enable_reg = 0x22cc,
3070                 .enable_mask = BIT(4),
3071                 .hw.init = &(struct clk_init_data){
3072                         .name = "pcie_h_clk",
3073                         .ops = &clk_branch_ops,
3074                 },
3075         },
3076 };
3077
3078 static struct clk_branch pcie_a_clk = {
3079         .halt_reg = 0x2fc0,
3080         .halt_bit = 13,
3081         .clkr = {
3082                 .enable_reg = 0x22c0,
3083                 .enable_mask = BIT(4),
3084                 .hw.init = &(struct clk_init_data){
3085                         .name = "pcie_a_clk",
3086                         .ops = &clk_branch_ops,
3087                 },
3088         },
3089 };
3090
3091 static struct clk_branch pmic_arb0_h_clk = {
3092         .halt_reg = 0x2fd8,
3093         .halt_check = BRANCH_HALT_VOTED,
3094         .halt_bit = 22,
3095         .clkr = {
3096                 .enable_reg = 0x3080,
3097                 .enable_mask = BIT(8),
3098                 .hw.init = &(struct clk_init_data){
3099                         .name = "pmic_arb0_h_clk",
3100                         .ops = &clk_branch_ops,
3101                 },
3102         },
3103 };
3104
3105 static struct clk_branch pmic_arb1_h_clk = {
3106         .halt_reg = 0x2fd8,
3107         .halt_check = BRANCH_HALT_VOTED,
3108         .halt_bit = 21,
3109         .clkr = {
3110                 .enable_reg = 0x3080,
3111                 .enable_mask = BIT(9),
3112                 .hw.init = &(struct clk_init_data){
3113                         .name = "pmic_arb1_h_clk",
3114                         .ops = &clk_branch_ops,
3115                 },
3116         },
3117 };
3118
3119 static struct clk_branch pmic_ssbi2_clk = {
3120         .halt_reg = 0x2fd8,
3121         .halt_check = BRANCH_HALT_VOTED,
3122         .halt_bit = 23,
3123         .clkr = {
3124                 .enable_reg = 0x3080,
3125                 .enable_mask = BIT(7),
3126                 .hw.init = &(struct clk_init_data){
3127                         .name = "pmic_ssbi2_clk",
3128                         .ops = &clk_branch_ops,
3129                 },
3130         },
3131 };
3132
3133 static struct clk_branch rpm_msg_ram_h_clk = {
3134         .hwcg_reg = 0x27e0,
3135         .hwcg_bit = 6,
3136         .halt_reg = 0x2fd8,
3137         .halt_check = BRANCH_HALT_VOTED,
3138         .halt_bit = 12,
3139         .clkr = {
3140                 .enable_reg = 0x3080,
3141                 .enable_mask = BIT(6),
3142                 .hw.init = &(struct clk_init_data){
3143                         .name = "rpm_msg_ram_h_clk",
3144                         .ops = &clk_branch_ops,
3145                 },
3146         },
3147 };
3148
3149 static struct clk_regmap *gcc_msm8960_clks[] = {
3150         [PLL3] = &pll3.clkr,
3151         [PLL4_VOTE] = &pll4_vote,
3152         [PLL8] = &pll8.clkr,
3153         [PLL8_VOTE] = &pll8_vote,
3154         [PLL14] = &pll14.clkr,
3155         [PLL14_VOTE] = &pll14_vote,
3156         [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3157         [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3158         [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3159         [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3160         [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3161         [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3162         [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3163         [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3164         [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3165         [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3166         [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3167         [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3168         [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3169         [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3170         [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
3171         [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
3172         [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
3173         [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
3174         [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
3175         [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
3176         [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
3177         [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
3178         [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
3179         [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
3180         [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3181         [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3182         [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3183         [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3184         [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3185         [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3186         [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3187         [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3188         [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3189         [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3190         [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3191         [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3192         [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3193         [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3194         [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
3195         [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
3196         [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
3197         [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
3198         [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
3199         [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
3200         [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
3201         [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
3202         [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
3203         [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
3204         [GP0_SRC] = &gp0_src.clkr,
3205         [GP0_CLK] = &gp0_clk.clkr,
3206         [GP1_SRC] = &gp1_src.clkr,
3207         [GP1_CLK] = &gp1_clk.clkr,
3208         [GP2_SRC] = &gp2_src.clkr,
3209         [GP2_CLK] = &gp2_clk.clkr,
3210         [PMEM_A_CLK] = &pmem_clk.clkr,
3211         [PRNG_SRC] = &prng_src.clkr,
3212         [PRNG_CLK] = &prng_clk.clkr,
3213         [SDC1_SRC] = &sdc1_src.clkr,
3214         [SDC1_CLK] = &sdc1_clk.clkr,
3215         [SDC2_SRC] = &sdc2_src.clkr,
3216         [SDC2_CLK] = &sdc2_clk.clkr,
3217         [SDC3_SRC] = &sdc3_src.clkr,
3218         [SDC3_CLK] = &sdc3_clk.clkr,
3219         [SDC4_SRC] = &sdc4_src.clkr,
3220         [SDC4_CLK] = &sdc4_clk.clkr,
3221         [SDC5_SRC] = &sdc5_src.clkr,
3222         [SDC5_CLK] = &sdc5_clk.clkr,
3223         [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3224         [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3225         [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3226         [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3227         [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3228         [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3229         [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3230         [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3231         [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3232         [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3233         [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3234         [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3235         [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
3236         [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
3237         [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
3238         [CE1_CORE_CLK] = &ce1_core_clk.clkr,
3239         [CE1_H_CLK] = &ce1_h_clk.clkr,
3240         [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3241         [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3242         [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3243         [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3244         [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3245         [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3246         [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3247         [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3248         [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
3249         [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
3250         [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
3251         [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
3252         [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
3253         [TSIF_H_CLK] = &tsif_h_clk.clkr,
3254         [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3255         [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
3256         [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3257         [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3258         [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3259         [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3260         [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3261         [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3262         [SDC5_H_CLK] = &sdc5_h_clk.clkr,
3263         [ADM0_CLK] = &adm0_clk.clkr,
3264         [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3265         [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3266         [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3267         [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3268         [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3269         [PLL9] = &hfpll0.clkr,
3270         [PLL10] = &hfpll1.clkr,
3271         [PLL12] = &hfpll_l2.clkr,
3272 };
3273
3274 static const struct qcom_reset_map gcc_msm8960_resets[] = {
3275         [SFAB_MSS_Q6_SW_RESET] = { 0x2040, 7 },
3276         [SFAB_MSS_Q6_FW_RESET] = { 0x2044, 7 },
3277         [QDSS_STM_RESET] = { 0x2060, 6 },
3278         [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3279         [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3280         [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3281         [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3282         [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3283         [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3284         [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3285         [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3286         [ADM0_C2_RESET] = { 0x220c, 4},
3287         [ADM0_C1_RESET] = { 0x220c, 3},
3288         [ADM0_C0_RESET] = { 0x220c, 2},
3289         [ADM0_PBUS_RESET] = { 0x220c, 1 },
3290         [ADM0_RESET] = { 0x220c },
3291         [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3292         [QDSS_POR_RESET] = { 0x2260, 4 },
3293         [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3294         [QDSS_HRESET_RESET] = { 0x2260, 2 },
3295         [QDSS_AXI_RESET] = { 0x2260, 1 },
3296         [QDSS_DBG_RESET] = { 0x2260 },
3297         [PCIE_A_RESET] = { 0x22c0, 7 },
3298         [PCIE_AUX_RESET] = { 0x22c8, 7 },
3299         [PCIE_H_RESET] = { 0x22d0, 7 },
3300         [SFAB_PCIE_M_RESET] = { 0x22d4, 1 },
3301         [SFAB_PCIE_S_RESET] = { 0x22d4 },
3302         [SFAB_MSS_M_RESET] = { 0x2340, 7 },
3303         [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3304         [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3305         [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3306         [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3307         [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3308         [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3309         [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3310         [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3311         [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3312         [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3313         [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3314         [DFAB_ARB0_RESET] = { 0x2560, 7 },
3315         [DFAB_ARB1_RESET] = { 0x2564, 7 },
3316         [PPSS_PROC_RESET] = { 0x2594, 1 },
3317         [PPSS_RESET] = { 0x2594},
3318         [DMA_BAM_RESET] = { 0x25c0, 7 },
3319         [SPS_TIC_H_RESET] = { 0x2600, 7 },
3320         [SLIMBUS_H_RESET] = { 0x2620, 7 },
3321         [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3322         [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3323         [TSIF_H_RESET] = { 0x2700, 7 },
3324         [CE1_H_RESET] = { 0x2720, 7 },
3325         [CE1_CORE_RESET] = { 0x2724, 7 },
3326         [CE1_SLEEP_RESET] = { 0x2728, 7 },
3327         [CE2_H_RESET] = { 0x2740, 7 },
3328         [CE2_CORE_RESET] = { 0x2744, 7 },
3329         [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3330         [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3331         [RPM_PROC_RESET] = { 0x27c0, 7 },
3332         [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3333         [SDC1_RESET] = { 0x2830 },
3334         [SDC2_RESET] = { 0x2850 },
3335         [SDC3_RESET] = { 0x2870 },
3336         [SDC4_RESET] = { 0x2890 },
3337         [SDC5_RESET] = { 0x28b0 },
3338         [DFAB_A2_RESET] = { 0x28c0, 7 },
3339         [USB_HS1_RESET] = { 0x2910 },
3340         [USB_HSIC_RESET] = { 0x2934 },
3341         [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3342         [USB_FS1_RESET] = { 0x2974 },
3343         [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
3344         [USB_FS2_RESET] = { 0x2994 },
3345         [GSBI1_RESET] = { 0x29dc },
3346         [GSBI2_RESET] = { 0x29fc },
3347         [GSBI3_RESET] = { 0x2a1c },
3348         [GSBI4_RESET] = { 0x2a3c },
3349         [GSBI5_RESET] = { 0x2a5c },
3350         [GSBI6_RESET] = { 0x2a7c },
3351         [GSBI7_RESET] = { 0x2a9c },
3352         [GSBI8_RESET] = { 0x2abc },
3353         [GSBI9_RESET] = { 0x2adc },
3354         [GSBI10_RESET] = { 0x2afc },
3355         [GSBI11_RESET] = { 0x2b1c },
3356         [GSBI12_RESET] = { 0x2b3c },
3357         [SPDM_RESET] = { 0x2b6c },
3358         [TLMM_H_RESET] = { 0x2ba0, 7 },
3359         [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
3360         [MSS_SLP_RESET] = { 0x2c60, 7 },
3361         [MSS_Q6SW_JTAG_RESET] = { 0x2c68, 7 },
3362         [MSS_Q6FW_JTAG_RESET] = { 0x2c6c, 7 },
3363         [MSS_RESET] = { 0x2c64 },
3364         [SATA_H_RESET] = { 0x2c80, 7 },
3365         [SATA_RXOOB_RESE] = { 0x2c8c, 7 },
3366         [SATA_PMALIVE_RESET] = { 0x2c90, 7 },
3367         [SATA_SFAB_M_RESET] = { 0x2c98, 7 },
3368         [TSSC_RESET] = { 0x2ca0, 7 },
3369         [PDM_RESET] = { 0x2cc0, 12 },
3370         [MPM_H_RESET] = { 0x2da0, 7 },
3371         [MPM_RESET] = { 0x2da4 },
3372         [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3373         [PRNG_RESET] = { 0x2e80, 12 },
3374         [RIVA_RESET] = { 0x35e0 },
3375 };
3376
3377 static struct clk_regmap *gcc_apq8064_clks[] = {
3378         [PLL3] = &pll3.clkr,
3379         [PLL4_VOTE] = &pll4_vote,
3380         [PLL8] = &pll8.clkr,
3381         [PLL8_VOTE] = &pll8_vote,
3382         [PLL14] = &pll14.clkr,
3383         [PLL14_VOTE] = &pll14_vote,
3384         [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3385         [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3386         [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3387         [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3388         [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3389         [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3390         [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3391         [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3392         [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3393         [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3394         [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3395         [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3396         [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3397         [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3398         [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3399         [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3400         [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3401         [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3402         [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3403         [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3404         [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3405         [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3406         [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3407         [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3408         [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3409         [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3410         [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3411         [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3412         [GP0_SRC] = &gp0_src.clkr,
3413         [GP0_CLK] = &gp0_clk.clkr,
3414         [GP1_SRC] = &gp1_src.clkr,
3415         [GP1_CLK] = &gp1_clk.clkr,
3416         [GP2_SRC] = &gp2_src.clkr,
3417         [GP2_CLK] = &gp2_clk.clkr,
3418         [PMEM_A_CLK] = &pmem_clk.clkr,
3419         [PRNG_SRC] = &prng_src.clkr,
3420         [PRNG_CLK] = &prng_clk.clkr,
3421         [SDC1_SRC] = &sdc1_src.clkr,
3422         [SDC1_CLK] = &sdc1_clk.clkr,
3423         [SDC2_SRC] = &sdc2_src.clkr,
3424         [SDC2_CLK] = &sdc2_clk.clkr,
3425         [SDC3_SRC] = &sdc3_src.clkr,
3426         [SDC3_CLK] = &sdc3_clk.clkr,
3427         [SDC4_SRC] = &sdc4_src.clkr,
3428         [SDC4_CLK] = &sdc4_clk.clkr,
3429         [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3430         [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3431         [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3432         [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3433         [USB_HS3_XCVR_SRC] = &usb_hs3_xcvr_src.clkr,
3434         [USB_HS3_XCVR_CLK] = &usb_hs3_xcvr_clk.clkr,
3435         [USB_HS4_XCVR_SRC] = &usb_hs4_xcvr_src.clkr,
3436         [USB_HS4_XCVR_CLK] = &usb_hs4_xcvr_clk.clkr,
3437         [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3438         [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3439         [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3440         [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3441         [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3442         [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3443         [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3444         [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3445         [SATA_H_CLK] = &sata_h_clk.clkr,
3446         [SATA_CLK_SRC] = &sata_clk_src.clkr,
3447         [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
3448         [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
3449         [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
3450         [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
3451         [SATA_A_CLK] = &sata_a_clk.clkr,
3452         [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
3453         [CE3_SRC] = &ce3_src.clkr,
3454         [CE3_CORE_CLK] = &ce3_core_clk.clkr,
3455         [CE3_H_CLK] = &ce3_h_clk.clkr,
3456         [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3457         [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3458         [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3459         [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3460         [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3461         [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3462         [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3463         [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3464         [TSIF_H_CLK] = &tsif_h_clk.clkr,
3465         [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3466         [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3467         [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3468         [USB_HS3_H_CLK] = &usb_hs3_h_clk.clkr,
3469         [USB_HS4_H_CLK] = &usb_hs4_h_clk.clkr,
3470         [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3471         [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3472         [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3473         [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3474         [ADM0_CLK] = &adm0_clk.clkr,
3475         [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3476         [PCIE_A_CLK] = &pcie_a_clk.clkr,
3477         [PCIE_PHY_REF_CLK] = &pcie_phy_ref_clk.clkr,
3478         [PCIE_H_CLK] = &pcie_h_clk.clkr,
3479         [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3480         [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3481         [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3482         [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3483         [PLL9] = &hfpll0.clkr,
3484         [PLL10] = &hfpll1.clkr,
3485         [PLL12] = &hfpll_l2.clkr,
3486         [PLL16] = &hfpll2.clkr,
3487         [PLL17] = &hfpll3.clkr,
3488 };
3489
3490 static const struct qcom_reset_map gcc_apq8064_resets[] = {
3491         [QDSS_STM_RESET] = { 0x2060, 6 },
3492         [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3493         [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3494         [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3495         [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3496         [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3497         [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3498         [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3499         [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3500         [ADM0_C2_RESET] = { 0x220c, 4},
3501         [ADM0_C1_RESET] = { 0x220c, 3},
3502         [ADM0_C0_RESET] = { 0x220c, 2},
3503         [ADM0_PBUS_RESET] = { 0x220c, 1 },
3504         [ADM0_RESET] = { 0x220c },
3505         [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3506         [QDSS_POR_RESET] = { 0x2260, 4 },
3507         [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3508         [QDSS_HRESET_RESET] = { 0x2260, 2 },
3509         [QDSS_AXI_RESET] = { 0x2260, 1 },
3510         [QDSS_DBG_RESET] = { 0x2260 },
3511         [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
3512         [SFAB_PCIE_S_RESET] = { 0x22d8 },
3513         [PCIE_EXT_PCI_RESET] = { 0x22dc, 6 },
3514         [PCIE_PHY_RESET] = { 0x22dc, 5 },
3515         [PCIE_PCI_RESET] = { 0x22dc, 4 },
3516         [PCIE_POR_RESET] = { 0x22dc, 3 },
3517         [PCIE_HCLK_RESET] = { 0x22dc, 2 },
3518         [PCIE_ACLK_RESET] = { 0x22dc },
3519         [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3520         [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3521         [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3522         [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3523         [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3524         [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3525         [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3526         [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3527         [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3528         [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3529         [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3530         [DFAB_ARB0_RESET] = { 0x2560, 7 },
3531         [DFAB_ARB1_RESET] = { 0x2564, 7 },
3532         [PPSS_PROC_RESET] = { 0x2594, 1 },
3533         [PPSS_RESET] = { 0x2594},
3534         [DMA_BAM_RESET] = { 0x25c0, 7 },
3535         [SPS_TIC_H_RESET] = { 0x2600, 7 },
3536         [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3537         [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3538         [TSIF_H_RESET] = { 0x2700, 7 },
3539         [CE1_H_RESET] = { 0x2720, 7 },
3540         [CE1_CORE_RESET] = { 0x2724, 7 },
3541         [CE1_SLEEP_RESET] = { 0x2728, 7 },
3542         [CE2_H_RESET] = { 0x2740, 7 },
3543         [CE2_CORE_RESET] = { 0x2744, 7 },
3544         [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3545         [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3546         [RPM_PROC_RESET] = { 0x27c0, 7 },
3547         [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3548         [SDC1_RESET] = { 0x2830 },
3549         [SDC2_RESET] = { 0x2850 },
3550         [SDC3_RESET] = { 0x2870 },
3551         [SDC4_RESET] = { 0x2890 },
3552         [USB_HS1_RESET] = { 0x2910 },
3553         [USB_HSIC_RESET] = { 0x2934 },
3554         [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3555         [USB_FS1_RESET] = { 0x2974 },
3556         [GSBI1_RESET] = { 0x29dc },
3557         [GSBI2_RESET] = { 0x29fc },
3558         [GSBI3_RESET] = { 0x2a1c },
3559         [GSBI4_RESET] = { 0x2a3c },
3560         [GSBI5_RESET] = { 0x2a5c },
3561         [GSBI6_RESET] = { 0x2a7c },
3562         [GSBI7_RESET] = { 0x2a9c },
3563         [SPDM_RESET] = { 0x2b6c },
3564         [TLMM_H_RESET] = { 0x2ba0, 7 },
3565         [SATA_SFAB_M_RESET] = { 0x2c18 },
3566         [SATA_RESET] = { 0x2c1c },
3567         [GSS_SLP_RESET] = { 0x2c60, 7 },
3568         [GSS_RESET] = { 0x2c64 },
3569         [TSSC_RESET] = { 0x2ca0, 7 },
3570         [PDM_RESET] = { 0x2cc0, 12 },
3571         [MPM_H_RESET] = { 0x2da0, 7 },
3572         [MPM_RESET] = { 0x2da4 },
3573         [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3574         [PRNG_RESET] = { 0x2e80, 12 },
3575         [RIVA_RESET] = { 0x35e0 },
3576         [CE3_H_RESET] = { 0x36c4, 7 },
3577         [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
3578         [SFAB_CE3_S_RESET] = { 0x36c8 },
3579         [CE3_RESET] = { 0x36cc, 7 },
3580         [CE3_SLEEP_RESET] = { 0x36d0, 7 },
3581         [USB_HS3_RESET] = { 0x3710 },
3582         [USB_HS4_RESET] = { 0x3730 },
3583 };
3584
3585 static const struct regmap_config gcc_msm8960_regmap_config = {
3586         .reg_bits       = 32,
3587         .reg_stride     = 4,
3588         .val_bits       = 32,
3589         .max_register   = 0x3660,
3590         .fast_io        = true,
3591 };
3592
3593 static const struct regmap_config gcc_apq8064_regmap_config = {
3594         .reg_bits       = 32,
3595         .reg_stride     = 4,
3596         .val_bits       = 32,
3597         .max_register   = 0x3880,
3598         .fast_io        = true,
3599 };
3600
3601 static const struct qcom_cc_desc gcc_msm8960_desc = {
3602         .config = &gcc_msm8960_regmap_config,
3603         .clks = gcc_msm8960_clks,
3604         .num_clks = ARRAY_SIZE(gcc_msm8960_clks),
3605         .resets = gcc_msm8960_resets,
3606         .num_resets = ARRAY_SIZE(gcc_msm8960_resets),
3607 };
3608
3609 static const struct qcom_cc_desc gcc_apq8064_desc = {
3610         .config = &gcc_apq8064_regmap_config,
3611         .clks = gcc_apq8064_clks,
3612         .num_clks = ARRAY_SIZE(gcc_apq8064_clks),
3613         .resets = gcc_apq8064_resets,
3614         .num_resets = ARRAY_SIZE(gcc_apq8064_resets),
3615 };
3616
3617 static const struct of_device_id gcc_msm8960_match_table[] = {
3618         { .compatible = "qcom,gcc-msm8960", .data = &gcc_msm8960_desc },
3619         { .compatible = "qcom,gcc-apq8064", .data = &gcc_apq8064_desc },
3620         { }
3621 };
3622 MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table);
3623
3624 static int gcc_msm8960_probe(struct platform_device *pdev)
3625 {
3626         struct device *dev = &pdev->dev;
3627         const struct of_device_id *match;
3628         struct platform_device *tsens;
3629         int ret;
3630
3631         match = of_match_device(gcc_msm8960_match_table, &pdev->dev);
3632         if (!match)
3633                 return -EINVAL;
3634
3635         ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000);
3636         if (ret)
3637                 return ret;
3638
3639         ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000);
3640         if (ret)
3641                 return ret;
3642
3643         ret = qcom_cc_probe(pdev, match->data);
3644         if (ret)
3645                 return ret;
3646
3647         if (match->data == &gcc_apq8064_desc) {
3648                 hfpll1.d = &hfpll1_8064_data;
3649                 hfpll_l2.d = &hfpll_l2_8064_data;
3650         }
3651
3652         tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1,
3653                                               NULL, 0);
3654         if (IS_ERR(tsens))
3655                 return PTR_ERR(tsens);
3656
3657         platform_set_drvdata(pdev, tsens);
3658
3659         return 0;
3660 }
3661
3662 static int gcc_msm8960_remove(struct platform_device *pdev)
3663 {
3664         struct platform_device *tsens = platform_get_drvdata(pdev);
3665
3666         platform_device_unregister(tsens);
3667
3668         return 0;
3669 }
3670
3671 static struct platform_driver gcc_msm8960_driver = {
3672         .probe          = gcc_msm8960_probe,
3673         .remove         = gcc_msm8960_remove,
3674         .driver         = {
3675                 .name   = "gcc-msm8960",
3676                 .of_match_table = gcc_msm8960_match_table,
3677         },
3678 };
3679
3680 static int __init gcc_msm8960_init(void)
3681 {
3682         return platform_driver_register(&gcc_msm8960_driver);
3683 }
3684 core_initcall(gcc_msm8960_init);
3685
3686 static void __exit gcc_msm8960_exit(void)
3687 {
3688         platform_driver_unregister(&gcc_msm8960_driver);
3689 }
3690 module_exit(gcc_msm8960_exit);
3691
3692 MODULE_DESCRIPTION("QCOM GCC MSM8960 Driver");
3693 MODULE_LICENSE("GPL v2");
3694 MODULE_ALIAS("platform:gcc-msm8960");