2 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
26 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
29 #include "clk-regmap.h"
32 #include "clk-branch.h"
33 #include "clk-hfpll.h"
36 static struct clk_pll pll3 = {
44 .clkr.hw.init = &(struct clk_init_data){
46 .parent_names = (const char *[]){ "pxo" },
52 static struct clk_regmap pll4_vote = {
54 .enable_mask = BIT(4),
55 .hw.init = &(struct clk_init_data){
57 .parent_names = (const char *[]){ "pll4" },
59 .ops = &clk_pll_vote_ops,
63 static struct clk_pll pll8 = {
71 .clkr.hw.init = &(struct clk_init_data){
73 .parent_names = (const char *[]){ "pxo" },
79 static struct clk_regmap pll8_vote = {
81 .enable_mask = BIT(8),
82 .hw.init = &(struct clk_init_data){
84 .parent_names = (const char *[]){ "pll8" },
86 .ops = &clk_pll_vote_ops,
90 static struct hfpll_data hfpll0_data = {
97 .config_val = 0x7845c665,
99 .droop_val = 0x0108c000,
100 .min_rate = 600000000UL,
101 .max_rate = 1800000000UL,
104 static struct clk_hfpll hfpll0 = {
106 .clkr.hw.init = &(struct clk_init_data){
107 .parent_names = (const char *[]){ "pxo" },
110 .ops = &clk_ops_hfpll,
111 .flags = CLK_IGNORE_UNUSED,
113 .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
116 static struct hfpll_data hfpll1_8064_data = {
121 .config_reg = 0x3244,
122 .status_reg = 0x325c,
123 .config_val = 0x7845c665,
125 .droop_val = 0x0108c000,
126 .min_rate = 600000000UL,
127 .max_rate = 1800000000UL,
130 static struct hfpll_data hfpll1_data = {
135 .config_reg = 0x3304,
136 .status_reg = 0x331c,
137 .config_val = 0x7845c665,
139 .droop_val = 0x0108c000,
140 .min_rate = 600000000UL,
141 .max_rate = 1800000000UL,
144 static struct clk_hfpll hfpll1 = {
146 .clkr.hw.init = &(struct clk_init_data){
147 .parent_names = (const char *[]){ "pxo" },
150 .ops = &clk_ops_hfpll,
151 .flags = CLK_IGNORE_UNUSED,
153 .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
156 static struct hfpll_data hfpll2_data = {
161 .config_reg = 0x3284,
162 .status_reg = 0x329c,
163 .config_val = 0x7845c665,
165 .droop_val = 0x0108c000,
166 .min_rate = 600000000UL,
167 .max_rate = 1800000000UL,
170 static struct clk_hfpll hfpll2 = {
172 .clkr.hw.init = &(struct clk_init_data){
173 .parent_names = (const char *[]){ "pxo" },
176 .ops = &clk_ops_hfpll,
177 .flags = CLK_IGNORE_UNUSED,
179 .lock = __SPIN_LOCK_UNLOCKED(hfpll2.lock),
182 static struct hfpll_data hfpll3_data = {
187 .config_reg = 0x32c4,
188 .status_reg = 0x32dc,
189 .config_val = 0x7845c665,
191 .droop_val = 0x0108c000,
192 .min_rate = 600000000UL,
193 .max_rate = 1800000000UL,
196 static struct clk_hfpll hfpll3 = {
198 .clkr.hw.init = &(struct clk_init_data){
199 .parent_names = (const char *[]){ "pxo" },
202 .ops = &clk_ops_hfpll,
203 .flags = CLK_IGNORE_UNUSED,
205 .lock = __SPIN_LOCK_UNLOCKED(hfpll3.lock),
208 static struct hfpll_data hfpll_l2_8064_data = {
213 .config_reg = 0x3304,
214 .status_reg = 0x331c,
215 .config_val = 0x7845c665,
217 .droop_val = 0x0108c000,
218 .min_rate = 600000000UL,
219 .max_rate = 1800000000UL,
222 static struct hfpll_data hfpll_l2_data = {
227 .config_reg = 0x3404,
228 .status_reg = 0x341c,
229 .config_val = 0x7845c665,
231 .droop_val = 0x0108c000,
232 .min_rate = 600000000UL,
233 .max_rate = 1800000000UL,
236 static struct clk_hfpll hfpll_l2 = {
238 .clkr.hw.init = &(struct clk_init_data){
239 .parent_names = (const char *[]){ "pxo" },
242 .ops = &clk_ops_hfpll,
243 .flags = CLK_IGNORE_UNUSED,
245 .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
248 static struct clk_pll pll14 = {
252 .config_reg = 0x31d4,
254 .status_reg = 0x31d8,
256 .clkr.hw.init = &(struct clk_init_data){
258 .parent_names = (const char *[]){ "pxo" },
264 static struct clk_regmap pll14_vote = {
265 .enable_reg = 0x34c0,
266 .enable_mask = BIT(14),
267 .hw.init = &(struct clk_init_data){
268 .name = "pll14_vote",
269 .parent_names = (const char *[]){ "pll14" },
271 .ops = &clk_pll_vote_ops,
282 static const struct parent_map gcc_pxo_pll8_map[] = {
287 static const char * const gcc_pxo_pll8[] = {
292 static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
298 static const char * const gcc_pxo_pll8_cxo[] = {
304 static const struct parent_map gcc_pxo_pll8_pll3_map[] = {
310 static const char * const gcc_pxo_pll8_pll3[] = {
316 static struct freq_tbl clk_tbl_gsbi_uart[] = {
317 { 1843200, P_PLL8, 2, 6, 625 },
318 { 3686400, P_PLL8, 2, 12, 625 },
319 { 7372800, P_PLL8, 2, 24, 625 },
320 { 14745600, P_PLL8, 2, 48, 625 },
321 { 16000000, P_PLL8, 4, 1, 6 },
322 { 24000000, P_PLL8, 4, 1, 4 },
323 { 32000000, P_PLL8, 4, 1, 3 },
324 { 40000000, P_PLL8, 1, 5, 48 },
325 { 46400000, P_PLL8, 1, 29, 240 },
326 { 48000000, P_PLL8, 4, 1, 2 },
327 { 51200000, P_PLL8, 1, 2, 15 },
328 { 56000000, P_PLL8, 1, 7, 48 },
329 { 58982400, P_PLL8, 1, 96, 625 },
330 { 64000000, P_PLL8, 2, 1, 3 },
334 static struct clk_rcg gsbi1_uart_src = {
339 .mnctr_reset_bit = 7,
340 .mnctr_mode_shift = 5,
351 .parent_map = gcc_pxo_pll8_map,
353 .freq_tbl = clk_tbl_gsbi_uart,
355 .enable_reg = 0x29d4,
356 .enable_mask = BIT(11),
357 .hw.init = &(struct clk_init_data){
358 .name = "gsbi1_uart_src",
359 .parent_names = gcc_pxo_pll8,
362 .flags = CLK_SET_PARENT_GATE,
367 static struct clk_branch gsbi1_uart_clk = {
371 .enable_reg = 0x29d4,
372 .enable_mask = BIT(9),
373 .hw.init = &(struct clk_init_data){
374 .name = "gsbi1_uart_clk",
375 .parent_names = (const char *[]){
379 .ops = &clk_branch_ops,
380 .flags = CLK_SET_RATE_PARENT,
385 static struct clk_rcg gsbi2_uart_src = {
390 .mnctr_reset_bit = 7,
391 .mnctr_mode_shift = 5,
402 .parent_map = gcc_pxo_pll8_map,
404 .freq_tbl = clk_tbl_gsbi_uart,
406 .enable_reg = 0x29f4,
407 .enable_mask = BIT(11),
408 .hw.init = &(struct clk_init_data){
409 .name = "gsbi2_uart_src",
410 .parent_names = gcc_pxo_pll8,
413 .flags = CLK_SET_PARENT_GATE,
418 static struct clk_branch gsbi2_uart_clk = {
422 .enable_reg = 0x29f4,
423 .enable_mask = BIT(9),
424 .hw.init = &(struct clk_init_data){
425 .name = "gsbi2_uart_clk",
426 .parent_names = (const char *[]){
430 .ops = &clk_branch_ops,
431 .flags = CLK_SET_RATE_PARENT,
436 static struct clk_rcg gsbi3_uart_src = {
441 .mnctr_reset_bit = 7,
442 .mnctr_mode_shift = 5,
453 .parent_map = gcc_pxo_pll8_map,
455 .freq_tbl = clk_tbl_gsbi_uart,
457 .enable_reg = 0x2a14,
458 .enable_mask = BIT(11),
459 .hw.init = &(struct clk_init_data){
460 .name = "gsbi3_uart_src",
461 .parent_names = gcc_pxo_pll8,
464 .flags = CLK_SET_PARENT_GATE,
469 static struct clk_branch gsbi3_uart_clk = {
473 .enable_reg = 0x2a14,
474 .enable_mask = BIT(9),
475 .hw.init = &(struct clk_init_data){
476 .name = "gsbi3_uart_clk",
477 .parent_names = (const char *[]){
481 .ops = &clk_branch_ops,
482 .flags = CLK_SET_RATE_PARENT,
487 static struct clk_rcg gsbi4_uart_src = {
492 .mnctr_reset_bit = 7,
493 .mnctr_mode_shift = 5,
504 .parent_map = gcc_pxo_pll8_map,
506 .freq_tbl = clk_tbl_gsbi_uart,
508 .enable_reg = 0x2a34,
509 .enable_mask = BIT(11),
510 .hw.init = &(struct clk_init_data){
511 .name = "gsbi4_uart_src",
512 .parent_names = gcc_pxo_pll8,
515 .flags = CLK_SET_PARENT_GATE,
520 static struct clk_branch gsbi4_uart_clk = {
524 .enable_reg = 0x2a34,
525 .enable_mask = BIT(9),
526 .hw.init = &(struct clk_init_data){
527 .name = "gsbi4_uart_clk",
528 .parent_names = (const char *[]){
532 .ops = &clk_branch_ops,
533 .flags = CLK_SET_RATE_PARENT,
538 static struct clk_rcg gsbi5_uart_src = {
543 .mnctr_reset_bit = 7,
544 .mnctr_mode_shift = 5,
555 .parent_map = gcc_pxo_pll8_map,
557 .freq_tbl = clk_tbl_gsbi_uart,
559 .enable_reg = 0x2a54,
560 .enable_mask = BIT(11),
561 .hw.init = &(struct clk_init_data){
562 .name = "gsbi5_uart_src",
563 .parent_names = gcc_pxo_pll8,
566 .flags = CLK_SET_PARENT_GATE,
571 static struct clk_branch gsbi5_uart_clk = {
575 .enable_reg = 0x2a54,
576 .enable_mask = BIT(9),
577 .hw.init = &(struct clk_init_data){
578 .name = "gsbi5_uart_clk",
579 .parent_names = (const char *[]){
583 .ops = &clk_branch_ops,
584 .flags = CLK_SET_RATE_PARENT,
589 static struct clk_rcg gsbi6_uart_src = {
594 .mnctr_reset_bit = 7,
595 .mnctr_mode_shift = 5,
606 .parent_map = gcc_pxo_pll8_map,
608 .freq_tbl = clk_tbl_gsbi_uart,
610 .enable_reg = 0x2a74,
611 .enable_mask = BIT(11),
612 .hw.init = &(struct clk_init_data){
613 .name = "gsbi6_uart_src",
614 .parent_names = gcc_pxo_pll8,
617 .flags = CLK_SET_PARENT_GATE,
622 static struct clk_branch gsbi6_uart_clk = {
626 .enable_reg = 0x2a74,
627 .enable_mask = BIT(9),
628 .hw.init = &(struct clk_init_data){
629 .name = "gsbi6_uart_clk",
630 .parent_names = (const char *[]){
634 .ops = &clk_branch_ops,
635 .flags = CLK_SET_RATE_PARENT,
640 static struct clk_rcg gsbi7_uart_src = {
645 .mnctr_reset_bit = 7,
646 .mnctr_mode_shift = 5,
657 .parent_map = gcc_pxo_pll8_map,
659 .freq_tbl = clk_tbl_gsbi_uart,
661 .enable_reg = 0x2a94,
662 .enable_mask = BIT(11),
663 .hw.init = &(struct clk_init_data){
664 .name = "gsbi7_uart_src",
665 .parent_names = gcc_pxo_pll8,
668 .flags = CLK_SET_PARENT_GATE,
673 static struct clk_branch gsbi7_uart_clk = {
677 .enable_reg = 0x2a94,
678 .enable_mask = BIT(9),
679 .hw.init = &(struct clk_init_data){
680 .name = "gsbi7_uart_clk",
681 .parent_names = (const char *[]){
685 .ops = &clk_branch_ops,
686 .flags = CLK_SET_RATE_PARENT,
691 static struct clk_rcg gsbi8_uart_src = {
696 .mnctr_reset_bit = 7,
697 .mnctr_mode_shift = 5,
708 .parent_map = gcc_pxo_pll8_map,
710 .freq_tbl = clk_tbl_gsbi_uart,
712 .enable_reg = 0x2ab4,
713 .enable_mask = BIT(11),
714 .hw.init = &(struct clk_init_data){
715 .name = "gsbi8_uart_src",
716 .parent_names = gcc_pxo_pll8,
719 .flags = CLK_SET_PARENT_GATE,
724 static struct clk_branch gsbi8_uart_clk = {
728 .enable_reg = 0x2ab4,
729 .enable_mask = BIT(9),
730 .hw.init = &(struct clk_init_data){
731 .name = "gsbi8_uart_clk",
732 .parent_names = (const char *[]){ "gsbi8_uart_src" },
734 .ops = &clk_branch_ops,
735 .flags = CLK_SET_RATE_PARENT,
740 static struct clk_rcg gsbi9_uart_src = {
745 .mnctr_reset_bit = 7,
746 .mnctr_mode_shift = 5,
757 .parent_map = gcc_pxo_pll8_map,
759 .freq_tbl = clk_tbl_gsbi_uart,
761 .enable_reg = 0x2ad4,
762 .enable_mask = BIT(11),
763 .hw.init = &(struct clk_init_data){
764 .name = "gsbi9_uart_src",
765 .parent_names = gcc_pxo_pll8,
768 .flags = CLK_SET_PARENT_GATE,
773 static struct clk_branch gsbi9_uart_clk = {
777 .enable_reg = 0x2ad4,
778 .enable_mask = BIT(9),
779 .hw.init = &(struct clk_init_data){
780 .name = "gsbi9_uart_clk",
781 .parent_names = (const char *[]){ "gsbi9_uart_src" },
783 .ops = &clk_branch_ops,
784 .flags = CLK_SET_RATE_PARENT,
789 static struct clk_rcg gsbi10_uart_src = {
794 .mnctr_reset_bit = 7,
795 .mnctr_mode_shift = 5,
806 .parent_map = gcc_pxo_pll8_map,
808 .freq_tbl = clk_tbl_gsbi_uart,
810 .enable_reg = 0x2af4,
811 .enable_mask = BIT(11),
812 .hw.init = &(struct clk_init_data){
813 .name = "gsbi10_uart_src",
814 .parent_names = gcc_pxo_pll8,
817 .flags = CLK_SET_PARENT_GATE,
822 static struct clk_branch gsbi10_uart_clk = {
826 .enable_reg = 0x2af4,
827 .enable_mask = BIT(9),
828 .hw.init = &(struct clk_init_data){
829 .name = "gsbi10_uart_clk",
830 .parent_names = (const char *[]){ "gsbi10_uart_src" },
832 .ops = &clk_branch_ops,
833 .flags = CLK_SET_RATE_PARENT,
838 static struct clk_rcg gsbi11_uart_src = {
843 .mnctr_reset_bit = 7,
844 .mnctr_mode_shift = 5,
855 .parent_map = gcc_pxo_pll8_map,
857 .freq_tbl = clk_tbl_gsbi_uart,
859 .enable_reg = 0x2b14,
860 .enable_mask = BIT(11),
861 .hw.init = &(struct clk_init_data){
862 .name = "gsbi11_uart_src",
863 .parent_names = gcc_pxo_pll8,
866 .flags = CLK_SET_PARENT_GATE,
871 static struct clk_branch gsbi11_uart_clk = {
875 .enable_reg = 0x2b14,
876 .enable_mask = BIT(9),
877 .hw.init = &(struct clk_init_data){
878 .name = "gsbi11_uart_clk",
879 .parent_names = (const char *[]){ "gsbi11_uart_src" },
881 .ops = &clk_branch_ops,
882 .flags = CLK_SET_RATE_PARENT,
887 static struct clk_rcg gsbi12_uart_src = {
892 .mnctr_reset_bit = 7,
893 .mnctr_mode_shift = 5,
904 .parent_map = gcc_pxo_pll8_map,
906 .freq_tbl = clk_tbl_gsbi_uart,
908 .enable_reg = 0x2b34,
909 .enable_mask = BIT(11),
910 .hw.init = &(struct clk_init_data){
911 .name = "gsbi12_uart_src",
912 .parent_names = gcc_pxo_pll8,
915 .flags = CLK_SET_PARENT_GATE,
920 static struct clk_branch gsbi12_uart_clk = {
924 .enable_reg = 0x2b34,
925 .enable_mask = BIT(9),
926 .hw.init = &(struct clk_init_data){
927 .name = "gsbi12_uart_clk",
928 .parent_names = (const char *[]){ "gsbi12_uart_src" },
930 .ops = &clk_branch_ops,
931 .flags = CLK_SET_RATE_PARENT,
936 static struct freq_tbl clk_tbl_gsbi_qup[] = {
937 { 1100000, P_PXO, 1, 2, 49 },
938 { 5400000, P_PXO, 1, 1, 5 },
939 { 10800000, P_PXO, 1, 2, 5 },
940 { 15060000, P_PLL8, 1, 2, 51 },
941 { 24000000, P_PLL8, 4, 1, 4 },
942 { 25600000, P_PLL8, 1, 1, 15 },
943 { 27000000, P_PXO, 1, 0, 0 },
944 { 48000000, P_PLL8, 4, 1, 2 },
945 { 51200000, P_PLL8, 1, 2, 15 },
949 static struct clk_rcg gsbi1_qup_src = {
954 .mnctr_reset_bit = 7,
955 .mnctr_mode_shift = 5,
966 .parent_map = gcc_pxo_pll8_map,
968 .freq_tbl = clk_tbl_gsbi_qup,
970 .enable_reg = 0x29cc,
971 .enable_mask = BIT(11),
972 .hw.init = &(struct clk_init_data){
973 .name = "gsbi1_qup_src",
974 .parent_names = gcc_pxo_pll8,
977 .flags = CLK_SET_PARENT_GATE,
982 static struct clk_branch gsbi1_qup_clk = {
986 .enable_reg = 0x29cc,
987 .enable_mask = BIT(9),
988 .hw.init = &(struct clk_init_data){
989 .name = "gsbi1_qup_clk",
990 .parent_names = (const char *[]){ "gsbi1_qup_src" },
992 .ops = &clk_branch_ops,
993 .flags = CLK_SET_RATE_PARENT,
998 static struct clk_rcg gsbi2_qup_src = {
1003 .mnctr_reset_bit = 7,
1004 .mnctr_mode_shift = 5,
1015 .parent_map = gcc_pxo_pll8_map,
1017 .freq_tbl = clk_tbl_gsbi_qup,
1019 .enable_reg = 0x29ec,
1020 .enable_mask = BIT(11),
1021 .hw.init = &(struct clk_init_data){
1022 .name = "gsbi2_qup_src",
1023 .parent_names = gcc_pxo_pll8,
1025 .ops = &clk_rcg_ops,
1026 .flags = CLK_SET_PARENT_GATE,
1031 static struct clk_branch gsbi2_qup_clk = {
1035 .enable_reg = 0x29ec,
1036 .enable_mask = BIT(9),
1037 .hw.init = &(struct clk_init_data){
1038 .name = "gsbi2_qup_clk",
1039 .parent_names = (const char *[]){ "gsbi2_qup_src" },
1041 .ops = &clk_branch_ops,
1042 .flags = CLK_SET_RATE_PARENT,
1047 static struct clk_rcg gsbi3_qup_src = {
1052 .mnctr_reset_bit = 7,
1053 .mnctr_mode_shift = 5,
1064 .parent_map = gcc_pxo_pll8_map,
1066 .freq_tbl = clk_tbl_gsbi_qup,
1068 .enable_reg = 0x2a0c,
1069 .enable_mask = BIT(11),
1070 .hw.init = &(struct clk_init_data){
1071 .name = "gsbi3_qup_src",
1072 .parent_names = gcc_pxo_pll8,
1074 .ops = &clk_rcg_ops,
1075 .flags = CLK_SET_PARENT_GATE,
1080 static struct clk_branch gsbi3_qup_clk = {
1084 .enable_reg = 0x2a0c,
1085 .enable_mask = BIT(9),
1086 .hw.init = &(struct clk_init_data){
1087 .name = "gsbi3_qup_clk",
1088 .parent_names = (const char *[]){ "gsbi3_qup_src" },
1090 .ops = &clk_branch_ops,
1091 .flags = CLK_SET_RATE_PARENT,
1096 static struct clk_rcg gsbi4_qup_src = {
1101 .mnctr_reset_bit = 7,
1102 .mnctr_mode_shift = 5,
1113 .parent_map = gcc_pxo_pll8_map,
1115 .freq_tbl = clk_tbl_gsbi_qup,
1117 .enable_reg = 0x2a2c,
1118 .enable_mask = BIT(11),
1119 .hw.init = &(struct clk_init_data){
1120 .name = "gsbi4_qup_src",
1121 .parent_names = gcc_pxo_pll8,
1123 .ops = &clk_rcg_ops,
1124 .flags = CLK_SET_PARENT_GATE,
1129 static struct clk_branch gsbi4_qup_clk = {
1133 .enable_reg = 0x2a2c,
1134 .enable_mask = BIT(9),
1135 .hw.init = &(struct clk_init_data){
1136 .name = "gsbi4_qup_clk",
1137 .parent_names = (const char *[]){ "gsbi4_qup_src" },
1139 .ops = &clk_branch_ops,
1140 .flags = CLK_SET_RATE_PARENT,
1145 static struct clk_rcg gsbi5_qup_src = {
1150 .mnctr_reset_bit = 7,
1151 .mnctr_mode_shift = 5,
1162 .parent_map = gcc_pxo_pll8_map,
1164 .freq_tbl = clk_tbl_gsbi_qup,
1166 .enable_reg = 0x2a4c,
1167 .enable_mask = BIT(11),
1168 .hw.init = &(struct clk_init_data){
1169 .name = "gsbi5_qup_src",
1170 .parent_names = gcc_pxo_pll8,
1172 .ops = &clk_rcg_ops,
1173 .flags = CLK_SET_PARENT_GATE,
1178 static struct clk_branch gsbi5_qup_clk = {
1182 .enable_reg = 0x2a4c,
1183 .enable_mask = BIT(9),
1184 .hw.init = &(struct clk_init_data){
1185 .name = "gsbi5_qup_clk",
1186 .parent_names = (const char *[]){ "gsbi5_qup_src" },
1188 .ops = &clk_branch_ops,
1189 .flags = CLK_SET_RATE_PARENT,
1194 static struct clk_rcg gsbi6_qup_src = {
1199 .mnctr_reset_bit = 7,
1200 .mnctr_mode_shift = 5,
1211 .parent_map = gcc_pxo_pll8_map,
1213 .freq_tbl = clk_tbl_gsbi_qup,
1215 .enable_reg = 0x2a6c,
1216 .enable_mask = BIT(11),
1217 .hw.init = &(struct clk_init_data){
1218 .name = "gsbi6_qup_src",
1219 .parent_names = gcc_pxo_pll8,
1221 .ops = &clk_rcg_ops,
1222 .flags = CLK_SET_PARENT_GATE,
1227 static struct clk_branch gsbi6_qup_clk = {
1231 .enable_reg = 0x2a6c,
1232 .enable_mask = BIT(9),
1233 .hw.init = &(struct clk_init_data){
1234 .name = "gsbi6_qup_clk",
1235 .parent_names = (const char *[]){ "gsbi6_qup_src" },
1237 .ops = &clk_branch_ops,
1238 .flags = CLK_SET_RATE_PARENT,
1243 static struct clk_rcg gsbi7_qup_src = {
1248 .mnctr_reset_bit = 7,
1249 .mnctr_mode_shift = 5,
1260 .parent_map = gcc_pxo_pll8_map,
1262 .freq_tbl = clk_tbl_gsbi_qup,
1264 .enable_reg = 0x2a8c,
1265 .enable_mask = BIT(11),
1266 .hw.init = &(struct clk_init_data){
1267 .name = "gsbi7_qup_src",
1268 .parent_names = gcc_pxo_pll8,
1270 .ops = &clk_rcg_ops,
1271 .flags = CLK_SET_PARENT_GATE,
1276 static struct clk_branch gsbi7_qup_clk = {
1280 .enable_reg = 0x2a8c,
1281 .enable_mask = BIT(9),
1282 .hw.init = &(struct clk_init_data){
1283 .name = "gsbi7_qup_clk",
1284 .parent_names = (const char *[]){ "gsbi7_qup_src" },
1286 .ops = &clk_branch_ops,
1287 .flags = CLK_SET_RATE_PARENT,
1292 static struct clk_rcg gsbi8_qup_src = {
1297 .mnctr_reset_bit = 7,
1298 .mnctr_mode_shift = 5,
1309 .parent_map = gcc_pxo_pll8_map,
1311 .freq_tbl = clk_tbl_gsbi_qup,
1313 .enable_reg = 0x2aac,
1314 .enable_mask = BIT(11),
1315 .hw.init = &(struct clk_init_data){
1316 .name = "gsbi8_qup_src",
1317 .parent_names = gcc_pxo_pll8,
1319 .ops = &clk_rcg_ops,
1320 .flags = CLK_SET_PARENT_GATE,
1325 static struct clk_branch gsbi8_qup_clk = {
1329 .enable_reg = 0x2aac,
1330 .enable_mask = BIT(9),
1331 .hw.init = &(struct clk_init_data){
1332 .name = "gsbi8_qup_clk",
1333 .parent_names = (const char *[]){ "gsbi8_qup_src" },
1335 .ops = &clk_branch_ops,
1336 .flags = CLK_SET_RATE_PARENT,
1341 static struct clk_rcg gsbi9_qup_src = {
1346 .mnctr_reset_bit = 7,
1347 .mnctr_mode_shift = 5,
1358 .parent_map = gcc_pxo_pll8_map,
1360 .freq_tbl = clk_tbl_gsbi_qup,
1362 .enable_reg = 0x2acc,
1363 .enable_mask = BIT(11),
1364 .hw.init = &(struct clk_init_data){
1365 .name = "gsbi9_qup_src",
1366 .parent_names = gcc_pxo_pll8,
1368 .ops = &clk_rcg_ops,
1369 .flags = CLK_SET_PARENT_GATE,
1374 static struct clk_branch gsbi9_qup_clk = {
1378 .enable_reg = 0x2acc,
1379 .enable_mask = BIT(9),
1380 .hw.init = &(struct clk_init_data){
1381 .name = "gsbi9_qup_clk",
1382 .parent_names = (const char *[]){ "gsbi9_qup_src" },
1384 .ops = &clk_branch_ops,
1385 .flags = CLK_SET_RATE_PARENT,
1390 static struct clk_rcg gsbi10_qup_src = {
1395 .mnctr_reset_bit = 7,
1396 .mnctr_mode_shift = 5,
1407 .parent_map = gcc_pxo_pll8_map,
1409 .freq_tbl = clk_tbl_gsbi_qup,
1411 .enable_reg = 0x2aec,
1412 .enable_mask = BIT(11),
1413 .hw.init = &(struct clk_init_data){
1414 .name = "gsbi10_qup_src",
1415 .parent_names = gcc_pxo_pll8,
1417 .ops = &clk_rcg_ops,
1418 .flags = CLK_SET_PARENT_GATE,
1423 static struct clk_branch gsbi10_qup_clk = {
1427 .enable_reg = 0x2aec,
1428 .enable_mask = BIT(9),
1429 .hw.init = &(struct clk_init_data){
1430 .name = "gsbi10_qup_clk",
1431 .parent_names = (const char *[]){ "gsbi10_qup_src" },
1433 .ops = &clk_branch_ops,
1434 .flags = CLK_SET_RATE_PARENT,
1439 static struct clk_rcg gsbi11_qup_src = {
1444 .mnctr_reset_bit = 7,
1445 .mnctr_mode_shift = 5,
1456 .parent_map = gcc_pxo_pll8_map,
1458 .freq_tbl = clk_tbl_gsbi_qup,
1460 .enable_reg = 0x2b0c,
1461 .enable_mask = BIT(11),
1462 .hw.init = &(struct clk_init_data){
1463 .name = "gsbi11_qup_src",
1464 .parent_names = gcc_pxo_pll8,
1466 .ops = &clk_rcg_ops,
1467 .flags = CLK_SET_PARENT_GATE,
1472 static struct clk_branch gsbi11_qup_clk = {
1476 .enable_reg = 0x2b0c,
1477 .enable_mask = BIT(9),
1478 .hw.init = &(struct clk_init_data){
1479 .name = "gsbi11_qup_clk",
1480 .parent_names = (const char *[]){ "gsbi11_qup_src" },
1482 .ops = &clk_branch_ops,
1483 .flags = CLK_SET_RATE_PARENT,
1488 static struct clk_rcg gsbi12_qup_src = {
1493 .mnctr_reset_bit = 7,
1494 .mnctr_mode_shift = 5,
1505 .parent_map = gcc_pxo_pll8_map,
1507 .freq_tbl = clk_tbl_gsbi_qup,
1509 .enable_reg = 0x2b2c,
1510 .enable_mask = BIT(11),
1511 .hw.init = &(struct clk_init_data){
1512 .name = "gsbi12_qup_src",
1513 .parent_names = gcc_pxo_pll8,
1515 .ops = &clk_rcg_ops,
1516 .flags = CLK_SET_PARENT_GATE,
1521 static struct clk_branch gsbi12_qup_clk = {
1525 .enable_reg = 0x2b2c,
1526 .enable_mask = BIT(9),
1527 .hw.init = &(struct clk_init_data){
1528 .name = "gsbi12_qup_clk",
1529 .parent_names = (const char *[]){ "gsbi12_qup_src" },
1531 .ops = &clk_branch_ops,
1532 .flags = CLK_SET_RATE_PARENT,
1537 static const struct freq_tbl clk_tbl_gp[] = {
1538 { 9600000, P_CXO, 2, 0, 0 },
1539 { 13500000, P_PXO, 2, 0, 0 },
1540 { 19200000, P_CXO, 1, 0, 0 },
1541 { 27000000, P_PXO, 1, 0, 0 },
1542 { 64000000, P_PLL8, 2, 1, 3 },
1543 { 76800000, P_PLL8, 1, 1, 5 },
1544 { 96000000, P_PLL8, 4, 0, 0 },
1545 { 128000000, P_PLL8, 3, 0, 0 },
1546 { 192000000, P_PLL8, 2, 0, 0 },
1550 static struct clk_rcg gp0_src = {
1555 .mnctr_reset_bit = 7,
1556 .mnctr_mode_shift = 5,
1567 .parent_map = gcc_pxo_pll8_cxo_map,
1569 .freq_tbl = clk_tbl_gp,
1571 .enable_reg = 0x2d24,
1572 .enable_mask = BIT(11),
1573 .hw.init = &(struct clk_init_data){
1575 .parent_names = gcc_pxo_pll8_cxo,
1577 .ops = &clk_rcg_ops,
1578 .flags = CLK_SET_PARENT_GATE,
1583 static struct clk_branch gp0_clk = {
1587 .enable_reg = 0x2d24,
1588 .enable_mask = BIT(9),
1589 .hw.init = &(struct clk_init_data){
1591 .parent_names = (const char *[]){ "gp0_src" },
1593 .ops = &clk_branch_ops,
1594 .flags = CLK_SET_RATE_PARENT,
1599 static struct clk_rcg gp1_src = {
1604 .mnctr_reset_bit = 7,
1605 .mnctr_mode_shift = 5,
1616 .parent_map = gcc_pxo_pll8_cxo_map,
1618 .freq_tbl = clk_tbl_gp,
1620 .enable_reg = 0x2d44,
1621 .enable_mask = BIT(11),
1622 .hw.init = &(struct clk_init_data){
1624 .parent_names = gcc_pxo_pll8_cxo,
1626 .ops = &clk_rcg_ops,
1627 .flags = CLK_SET_RATE_GATE,
1632 static struct clk_branch gp1_clk = {
1636 .enable_reg = 0x2d44,
1637 .enable_mask = BIT(9),
1638 .hw.init = &(struct clk_init_data){
1640 .parent_names = (const char *[]){ "gp1_src" },
1642 .ops = &clk_branch_ops,
1643 .flags = CLK_SET_RATE_PARENT,
1648 static struct clk_rcg gp2_src = {
1653 .mnctr_reset_bit = 7,
1654 .mnctr_mode_shift = 5,
1665 .parent_map = gcc_pxo_pll8_cxo_map,
1667 .freq_tbl = clk_tbl_gp,
1669 .enable_reg = 0x2d64,
1670 .enable_mask = BIT(11),
1671 .hw.init = &(struct clk_init_data){
1673 .parent_names = gcc_pxo_pll8_cxo,
1675 .ops = &clk_rcg_ops,
1676 .flags = CLK_SET_RATE_GATE,
1681 static struct clk_branch gp2_clk = {
1685 .enable_reg = 0x2d64,
1686 .enable_mask = BIT(9),
1687 .hw.init = &(struct clk_init_data){
1689 .parent_names = (const char *[]){ "gp2_src" },
1691 .ops = &clk_branch_ops,
1692 .flags = CLK_SET_RATE_PARENT,
1697 static struct clk_branch pmem_clk = {
1703 .enable_reg = 0x25a0,
1704 .enable_mask = BIT(4),
1705 .hw.init = &(struct clk_init_data){
1707 .ops = &clk_branch_ops,
1712 static struct clk_rcg prng_src = {
1720 .parent_map = gcc_pxo_pll8_map,
1723 .hw.init = &(struct clk_init_data){
1725 .parent_names = gcc_pxo_pll8,
1727 .ops = &clk_rcg_ops,
1732 static struct clk_branch prng_clk = {
1734 .halt_check = BRANCH_HALT_VOTED,
1737 .enable_reg = 0x3080,
1738 .enable_mask = BIT(10),
1739 .hw.init = &(struct clk_init_data){
1741 .parent_names = (const char *[]){ "prng_src" },
1743 .ops = &clk_branch_ops,
1748 static const struct freq_tbl clk_tbl_sdc[] = {
1749 { 144000, P_PXO, 3, 2, 125 },
1750 { 400000, P_PLL8, 4, 1, 240 },
1751 { 16000000, P_PLL8, 4, 1, 6 },
1752 { 17070000, P_PLL8, 1, 2, 45 },
1753 { 20210000, P_PLL8, 1, 1, 19 },
1754 { 24000000, P_PLL8, 4, 1, 4 },
1755 { 48000000, P_PLL8, 4, 1, 2 },
1756 { 64000000, P_PLL8, 3, 1, 2 },
1757 { 96000000, P_PLL8, 4, 0, 0 },
1758 { 192000000, P_PLL8, 2, 0, 0 },
1762 static struct clk_rcg sdc1_src = {
1767 .mnctr_reset_bit = 7,
1768 .mnctr_mode_shift = 5,
1779 .parent_map = gcc_pxo_pll8_map,
1781 .freq_tbl = clk_tbl_sdc,
1783 .enable_reg = 0x282c,
1784 .enable_mask = BIT(11),
1785 .hw.init = &(struct clk_init_data){
1787 .parent_names = gcc_pxo_pll8,
1789 .ops = &clk_rcg_ops,
1794 static struct clk_branch sdc1_clk = {
1798 .enable_reg = 0x282c,
1799 .enable_mask = BIT(9),
1800 .hw.init = &(struct clk_init_data){
1802 .parent_names = (const char *[]){ "sdc1_src" },
1804 .ops = &clk_branch_ops,
1805 .flags = CLK_SET_RATE_PARENT,
1810 static struct clk_rcg sdc2_src = {
1815 .mnctr_reset_bit = 7,
1816 .mnctr_mode_shift = 5,
1827 .parent_map = gcc_pxo_pll8_map,
1829 .freq_tbl = clk_tbl_sdc,
1831 .enable_reg = 0x284c,
1832 .enable_mask = BIT(11),
1833 .hw.init = &(struct clk_init_data){
1835 .parent_names = gcc_pxo_pll8,
1837 .ops = &clk_rcg_ops,
1842 static struct clk_branch sdc2_clk = {
1846 .enable_reg = 0x284c,
1847 .enable_mask = BIT(9),
1848 .hw.init = &(struct clk_init_data){
1850 .parent_names = (const char *[]){ "sdc2_src" },
1852 .ops = &clk_branch_ops,
1853 .flags = CLK_SET_RATE_PARENT,
1858 static struct clk_rcg sdc3_src = {
1863 .mnctr_reset_bit = 7,
1864 .mnctr_mode_shift = 5,
1875 .parent_map = gcc_pxo_pll8_map,
1877 .freq_tbl = clk_tbl_sdc,
1879 .enable_reg = 0x286c,
1880 .enable_mask = BIT(11),
1881 .hw.init = &(struct clk_init_data){
1883 .parent_names = gcc_pxo_pll8,
1885 .ops = &clk_rcg_ops,
1890 static struct clk_branch sdc3_clk = {
1894 .enable_reg = 0x286c,
1895 .enable_mask = BIT(9),
1896 .hw.init = &(struct clk_init_data){
1898 .parent_names = (const char *[]){ "sdc3_src" },
1900 .ops = &clk_branch_ops,
1901 .flags = CLK_SET_RATE_PARENT,
1906 static struct clk_rcg sdc4_src = {
1911 .mnctr_reset_bit = 7,
1912 .mnctr_mode_shift = 5,
1923 .parent_map = gcc_pxo_pll8_map,
1925 .freq_tbl = clk_tbl_sdc,
1927 .enable_reg = 0x288c,
1928 .enable_mask = BIT(11),
1929 .hw.init = &(struct clk_init_data){
1931 .parent_names = gcc_pxo_pll8,
1933 .ops = &clk_rcg_ops,
1938 static struct clk_branch sdc4_clk = {
1942 .enable_reg = 0x288c,
1943 .enable_mask = BIT(9),
1944 .hw.init = &(struct clk_init_data){
1946 .parent_names = (const char *[]){ "sdc4_src" },
1948 .ops = &clk_branch_ops,
1949 .flags = CLK_SET_RATE_PARENT,
1954 static struct clk_rcg sdc5_src = {
1959 .mnctr_reset_bit = 7,
1960 .mnctr_mode_shift = 5,
1971 .parent_map = gcc_pxo_pll8_map,
1973 .freq_tbl = clk_tbl_sdc,
1975 .enable_reg = 0x28ac,
1976 .enable_mask = BIT(11),
1977 .hw.init = &(struct clk_init_data){
1979 .parent_names = gcc_pxo_pll8,
1981 .ops = &clk_rcg_ops,
1986 static struct clk_branch sdc5_clk = {
1990 .enable_reg = 0x28ac,
1991 .enable_mask = BIT(9),
1992 .hw.init = &(struct clk_init_data){
1994 .parent_names = (const char *[]){ "sdc5_src" },
1996 .ops = &clk_branch_ops,
1997 .flags = CLK_SET_RATE_PARENT,
2002 static const struct freq_tbl clk_tbl_tsif_ref[] = {
2003 { 105000, P_PXO, 1, 1, 256 },
2007 static struct clk_rcg tsif_ref_src = {
2012 .mnctr_reset_bit = 7,
2013 .mnctr_mode_shift = 5,
2024 .parent_map = gcc_pxo_pll8_map,
2026 .freq_tbl = clk_tbl_tsif_ref,
2028 .enable_reg = 0x2710,
2029 .enable_mask = BIT(11),
2030 .hw.init = &(struct clk_init_data){
2031 .name = "tsif_ref_src",
2032 .parent_names = gcc_pxo_pll8,
2034 .ops = &clk_rcg_ops,
2035 .flags = CLK_SET_RATE_GATE,
2040 static struct clk_branch tsif_ref_clk = {
2044 .enable_reg = 0x2710,
2045 .enable_mask = BIT(9),
2046 .hw.init = &(struct clk_init_data){
2047 .name = "tsif_ref_clk",
2048 .parent_names = (const char *[]){ "tsif_ref_src" },
2050 .ops = &clk_branch_ops,
2051 .flags = CLK_SET_RATE_PARENT,
2056 static const struct freq_tbl clk_tbl_usb[] = {
2057 { 60000000, P_PLL8, 1, 5, 32 },
2061 static struct clk_rcg usb_hs1_xcvr_src = {
2066 .mnctr_reset_bit = 7,
2067 .mnctr_mode_shift = 5,
2078 .parent_map = gcc_pxo_pll8_map,
2080 .freq_tbl = clk_tbl_usb,
2082 .enable_reg = 0x290c,
2083 .enable_mask = BIT(11),
2084 .hw.init = &(struct clk_init_data){
2085 .name = "usb_hs1_xcvr_src",
2086 .parent_names = gcc_pxo_pll8,
2088 .ops = &clk_rcg_ops,
2089 .flags = CLK_SET_RATE_GATE,
2094 static struct clk_branch usb_hs1_xcvr_clk = {
2098 .enable_reg = 0x290c,
2099 .enable_mask = BIT(9),
2100 .hw.init = &(struct clk_init_data){
2101 .name = "usb_hs1_xcvr_clk",
2102 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
2104 .ops = &clk_branch_ops,
2105 .flags = CLK_SET_RATE_PARENT,
2110 static struct clk_rcg usb_hs3_xcvr_src = {
2115 .mnctr_reset_bit = 7,
2116 .mnctr_mode_shift = 5,
2127 .parent_map = gcc_pxo_pll8_map,
2129 .freq_tbl = clk_tbl_usb,
2131 .enable_reg = 0x370c,
2132 .enable_mask = BIT(11),
2133 .hw.init = &(struct clk_init_data){
2134 .name = "usb_hs3_xcvr_src",
2135 .parent_names = gcc_pxo_pll8,
2137 .ops = &clk_rcg_ops,
2138 .flags = CLK_SET_RATE_GATE,
2143 static struct clk_branch usb_hs3_xcvr_clk = {
2147 .enable_reg = 0x370c,
2148 .enable_mask = BIT(9),
2149 .hw.init = &(struct clk_init_data){
2150 .name = "usb_hs3_xcvr_clk",
2151 .parent_names = (const char *[]){ "usb_hs3_xcvr_src" },
2153 .ops = &clk_branch_ops,
2154 .flags = CLK_SET_RATE_PARENT,
2159 static struct clk_rcg usb_hs4_xcvr_src = {
2164 .mnctr_reset_bit = 7,
2165 .mnctr_mode_shift = 5,
2176 .parent_map = gcc_pxo_pll8_map,
2178 .freq_tbl = clk_tbl_usb,
2180 .enable_reg = 0x372c,
2181 .enable_mask = BIT(11),
2182 .hw.init = &(struct clk_init_data){
2183 .name = "usb_hs4_xcvr_src",
2184 .parent_names = gcc_pxo_pll8,
2186 .ops = &clk_rcg_ops,
2187 .flags = CLK_SET_RATE_GATE,
2192 static struct clk_branch usb_hs4_xcvr_clk = {
2196 .enable_reg = 0x372c,
2197 .enable_mask = BIT(9),
2198 .hw.init = &(struct clk_init_data){
2199 .name = "usb_hs4_xcvr_clk",
2200 .parent_names = (const char *[]){ "usb_hs4_xcvr_src" },
2202 .ops = &clk_branch_ops,
2203 .flags = CLK_SET_RATE_PARENT,
2208 static struct clk_rcg usb_hsic_xcvr_fs_src = {
2213 .mnctr_reset_bit = 7,
2214 .mnctr_mode_shift = 5,
2225 .parent_map = gcc_pxo_pll8_map,
2227 .freq_tbl = clk_tbl_usb,
2229 .enable_reg = 0x2928,
2230 .enable_mask = BIT(11),
2231 .hw.init = &(struct clk_init_data){
2232 .name = "usb_hsic_xcvr_fs_src",
2233 .parent_names = gcc_pxo_pll8,
2235 .ops = &clk_rcg_ops,
2236 .flags = CLK_SET_RATE_GATE,
2241 static const char * const usb_hsic_xcvr_fs_src_p[] = { "usb_hsic_xcvr_fs_src" };
2243 static struct clk_branch usb_hsic_xcvr_fs_clk = {
2247 .enable_reg = 0x2928,
2248 .enable_mask = BIT(9),
2249 .hw.init = &(struct clk_init_data){
2250 .name = "usb_hsic_xcvr_fs_clk",
2251 .parent_names = usb_hsic_xcvr_fs_src_p,
2253 .ops = &clk_branch_ops,
2254 .flags = CLK_SET_RATE_PARENT,
2259 static struct clk_branch usb_hsic_system_clk = {
2263 .enable_reg = 0x292c,
2264 .enable_mask = BIT(4),
2265 .hw.init = &(struct clk_init_data){
2266 .parent_names = usb_hsic_xcvr_fs_src_p,
2268 .name = "usb_hsic_system_clk",
2269 .ops = &clk_branch_ops,
2270 .flags = CLK_SET_RATE_PARENT,
2275 static struct clk_branch usb_hsic_hsic_clk = {
2279 .enable_reg = 0x2b44,
2280 .enable_mask = BIT(0),
2281 .hw.init = &(struct clk_init_data){
2282 .parent_names = (const char *[]){ "pll14_vote" },
2284 .name = "usb_hsic_hsic_clk",
2285 .ops = &clk_branch_ops,
2290 static struct clk_branch usb_hsic_hsio_cal_clk = {
2294 .enable_reg = 0x2b48,
2295 .enable_mask = BIT(0),
2296 .hw.init = &(struct clk_init_data){
2297 .name = "usb_hsic_hsio_cal_clk",
2298 .ops = &clk_branch_ops,
2303 static struct clk_rcg usb_fs1_xcvr_fs_src = {
2308 .mnctr_reset_bit = 7,
2309 .mnctr_mode_shift = 5,
2320 .parent_map = gcc_pxo_pll8_map,
2322 .freq_tbl = clk_tbl_usb,
2324 .enable_reg = 0x2968,
2325 .enable_mask = BIT(11),
2326 .hw.init = &(struct clk_init_data){
2327 .name = "usb_fs1_xcvr_fs_src",
2328 .parent_names = gcc_pxo_pll8,
2330 .ops = &clk_rcg_ops,
2331 .flags = CLK_SET_RATE_GATE,
2336 static const char * const usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" };
2338 static struct clk_branch usb_fs1_xcvr_fs_clk = {
2342 .enable_reg = 0x2968,
2343 .enable_mask = BIT(9),
2344 .hw.init = &(struct clk_init_data){
2345 .name = "usb_fs1_xcvr_fs_clk",
2346 .parent_names = usb_fs1_xcvr_fs_src_p,
2348 .ops = &clk_branch_ops,
2349 .flags = CLK_SET_RATE_PARENT,
2354 static struct clk_branch usb_fs1_system_clk = {
2358 .enable_reg = 0x296c,
2359 .enable_mask = BIT(4),
2360 .hw.init = &(struct clk_init_data){
2361 .parent_names = usb_fs1_xcvr_fs_src_p,
2363 .name = "usb_fs1_system_clk",
2364 .ops = &clk_branch_ops,
2365 .flags = CLK_SET_RATE_PARENT,
2370 static struct clk_rcg usb_fs2_xcvr_fs_src = {
2375 .mnctr_reset_bit = 7,
2376 .mnctr_mode_shift = 5,
2387 .parent_map = gcc_pxo_pll8_map,
2389 .freq_tbl = clk_tbl_usb,
2391 .enable_reg = 0x2988,
2392 .enable_mask = BIT(11),
2393 .hw.init = &(struct clk_init_data){
2394 .name = "usb_fs2_xcvr_fs_src",
2395 .parent_names = gcc_pxo_pll8,
2397 .ops = &clk_rcg_ops,
2398 .flags = CLK_SET_RATE_GATE,
2403 static const char * const usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" };
2405 static struct clk_branch usb_fs2_xcvr_fs_clk = {
2409 .enable_reg = 0x2988,
2410 .enable_mask = BIT(9),
2411 .hw.init = &(struct clk_init_data){
2412 .name = "usb_fs2_xcvr_fs_clk",
2413 .parent_names = usb_fs2_xcvr_fs_src_p,
2415 .ops = &clk_branch_ops,
2416 .flags = CLK_SET_RATE_PARENT,
2421 static struct clk_branch usb_fs2_system_clk = {
2425 .enable_reg = 0x298c,
2426 .enable_mask = BIT(4),
2427 .hw.init = &(struct clk_init_data){
2428 .name = "usb_fs2_system_clk",
2429 .parent_names = usb_fs2_xcvr_fs_src_p,
2431 .ops = &clk_branch_ops,
2432 .flags = CLK_SET_RATE_PARENT,
2437 static struct clk_branch ce1_core_clk = {
2443 .enable_reg = 0x2724,
2444 .enable_mask = BIT(4),
2445 .hw.init = &(struct clk_init_data){
2446 .name = "ce1_core_clk",
2447 .ops = &clk_branch_ops,
2452 static struct clk_branch ce1_h_clk = {
2456 .enable_reg = 0x2720,
2457 .enable_mask = BIT(4),
2458 .hw.init = &(struct clk_init_data){
2459 .name = "ce1_h_clk",
2460 .ops = &clk_branch_ops,
2465 static struct clk_branch dma_bam_h_clk = {
2471 .enable_reg = 0x25c0,
2472 .enable_mask = BIT(4),
2473 .hw.init = &(struct clk_init_data){
2474 .name = "dma_bam_h_clk",
2475 .ops = &clk_branch_ops,
2480 static struct clk_branch gsbi1_h_clk = {
2486 .enable_reg = 0x29c0,
2487 .enable_mask = BIT(4),
2488 .hw.init = &(struct clk_init_data){
2489 .name = "gsbi1_h_clk",
2490 .ops = &clk_branch_ops,
2495 static struct clk_branch gsbi2_h_clk = {
2501 .enable_reg = 0x29e0,
2502 .enable_mask = BIT(4),
2503 .hw.init = &(struct clk_init_data){
2504 .name = "gsbi2_h_clk",
2505 .ops = &clk_branch_ops,
2510 static struct clk_branch gsbi3_h_clk = {
2516 .enable_reg = 0x2a00,
2517 .enable_mask = BIT(4),
2518 .hw.init = &(struct clk_init_data){
2519 .name = "gsbi3_h_clk",
2520 .ops = &clk_branch_ops,
2525 static struct clk_branch gsbi4_h_clk = {
2531 .enable_reg = 0x2a20,
2532 .enable_mask = BIT(4),
2533 .hw.init = &(struct clk_init_data){
2534 .name = "gsbi4_h_clk",
2535 .ops = &clk_branch_ops,
2540 static struct clk_branch gsbi5_h_clk = {
2546 .enable_reg = 0x2a40,
2547 .enable_mask = BIT(4),
2548 .hw.init = &(struct clk_init_data){
2549 .name = "gsbi5_h_clk",
2550 .ops = &clk_branch_ops,
2555 static struct clk_branch gsbi6_h_clk = {
2561 .enable_reg = 0x2a60,
2562 .enable_mask = BIT(4),
2563 .hw.init = &(struct clk_init_data){
2564 .name = "gsbi6_h_clk",
2565 .ops = &clk_branch_ops,
2570 static struct clk_branch gsbi7_h_clk = {
2576 .enable_reg = 0x2a80,
2577 .enable_mask = BIT(4),
2578 .hw.init = &(struct clk_init_data){
2579 .name = "gsbi7_h_clk",
2580 .ops = &clk_branch_ops,
2585 static struct clk_branch gsbi8_h_clk = {
2591 .enable_reg = 0x2aa0,
2592 .enable_mask = BIT(4),
2593 .hw.init = &(struct clk_init_data){
2594 .name = "gsbi8_h_clk",
2595 .ops = &clk_branch_ops,
2600 static struct clk_branch gsbi9_h_clk = {
2606 .enable_reg = 0x2ac0,
2607 .enable_mask = BIT(4),
2608 .hw.init = &(struct clk_init_data){
2609 .name = "gsbi9_h_clk",
2610 .ops = &clk_branch_ops,
2615 static struct clk_branch gsbi10_h_clk = {
2621 .enable_reg = 0x2ae0,
2622 .enable_mask = BIT(4),
2623 .hw.init = &(struct clk_init_data){
2624 .name = "gsbi10_h_clk",
2625 .ops = &clk_branch_ops,
2630 static struct clk_branch gsbi11_h_clk = {
2636 .enable_reg = 0x2b00,
2637 .enable_mask = BIT(4),
2638 .hw.init = &(struct clk_init_data){
2639 .name = "gsbi11_h_clk",
2640 .ops = &clk_branch_ops,
2645 static struct clk_branch gsbi12_h_clk = {
2651 .enable_reg = 0x2b20,
2652 .enable_mask = BIT(4),
2653 .hw.init = &(struct clk_init_data){
2654 .name = "gsbi12_h_clk",
2655 .ops = &clk_branch_ops,
2660 static struct clk_branch tsif_h_clk = {
2666 .enable_reg = 0x2700,
2667 .enable_mask = BIT(4),
2668 .hw.init = &(struct clk_init_data){
2669 .name = "tsif_h_clk",
2670 .ops = &clk_branch_ops,
2675 static struct clk_branch usb_fs1_h_clk = {
2679 .enable_reg = 0x2960,
2680 .enable_mask = BIT(4),
2681 .hw.init = &(struct clk_init_data){
2682 .name = "usb_fs1_h_clk",
2683 .ops = &clk_branch_ops,
2688 static struct clk_branch usb_fs2_h_clk = {
2692 .enable_reg = 0x2980,
2693 .enable_mask = BIT(4),
2694 .hw.init = &(struct clk_init_data){
2695 .name = "usb_fs2_h_clk",
2696 .ops = &clk_branch_ops,
2701 static struct clk_branch usb_hs1_h_clk = {
2707 .enable_reg = 0x2900,
2708 .enable_mask = BIT(4),
2709 .hw.init = &(struct clk_init_data){
2710 .name = "usb_hs1_h_clk",
2711 .ops = &clk_branch_ops,
2716 static struct clk_branch usb_hs3_h_clk = {
2720 .enable_reg = 0x3700,
2721 .enable_mask = BIT(4),
2722 .hw.init = &(struct clk_init_data){
2723 .name = "usb_hs3_h_clk",
2724 .ops = &clk_branch_ops,
2729 static struct clk_branch usb_hs4_h_clk = {
2733 .enable_reg = 0x3720,
2734 .enable_mask = BIT(4),
2735 .hw.init = &(struct clk_init_data){
2736 .name = "usb_hs4_h_clk",
2737 .ops = &clk_branch_ops,
2742 static struct clk_branch usb_hsic_h_clk = {
2746 .enable_reg = 0x2920,
2747 .enable_mask = BIT(4),
2748 .hw.init = &(struct clk_init_data){
2749 .name = "usb_hsic_h_clk",
2750 .ops = &clk_branch_ops,
2755 static struct clk_branch sdc1_h_clk = {
2761 .enable_reg = 0x2820,
2762 .enable_mask = BIT(4),
2763 .hw.init = &(struct clk_init_data){
2764 .name = "sdc1_h_clk",
2765 .ops = &clk_branch_ops,
2770 static struct clk_branch sdc2_h_clk = {
2776 .enable_reg = 0x2840,
2777 .enable_mask = BIT(4),
2778 .hw.init = &(struct clk_init_data){
2779 .name = "sdc2_h_clk",
2780 .ops = &clk_branch_ops,
2785 static struct clk_branch sdc3_h_clk = {
2791 .enable_reg = 0x2860,
2792 .enable_mask = BIT(4),
2793 .hw.init = &(struct clk_init_data){
2794 .name = "sdc3_h_clk",
2795 .ops = &clk_branch_ops,
2800 static struct clk_branch sdc4_h_clk = {
2806 .enable_reg = 0x2880,
2807 .enable_mask = BIT(4),
2808 .hw.init = &(struct clk_init_data){
2809 .name = "sdc4_h_clk",
2810 .ops = &clk_branch_ops,
2815 static struct clk_branch sdc5_h_clk = {
2821 .enable_reg = 0x28a0,
2822 .enable_mask = BIT(4),
2823 .hw.init = &(struct clk_init_data){
2824 .name = "sdc5_h_clk",
2825 .ops = &clk_branch_ops,
2830 static struct clk_branch adm0_clk = {
2832 .halt_check = BRANCH_HALT_VOTED,
2835 .enable_reg = 0x3080,
2836 .enable_mask = BIT(2),
2837 .hw.init = &(struct clk_init_data){
2839 .ops = &clk_branch_ops,
2844 static struct clk_branch adm0_pbus_clk = {
2848 .halt_check = BRANCH_HALT_VOTED,
2851 .enable_reg = 0x3080,
2852 .enable_mask = BIT(3),
2853 .hw.init = &(struct clk_init_data){
2854 .name = "adm0_pbus_clk",
2855 .ops = &clk_branch_ops,
2860 static struct freq_tbl clk_tbl_ce3[] = {
2861 { 48000000, P_PLL8, 8 },
2862 { 100000000, P_PLL3, 12 },
2863 { 120000000, P_PLL3, 10 },
2867 static struct clk_rcg ce3_src = {
2875 .parent_map = gcc_pxo_pll8_pll3_map,
2877 .freq_tbl = clk_tbl_ce3,
2879 .enable_reg = 0x36c0,
2880 .enable_mask = BIT(7),
2881 .hw.init = &(struct clk_init_data){
2883 .parent_names = gcc_pxo_pll8_pll3,
2885 .ops = &clk_rcg_ops,
2886 .flags = CLK_SET_RATE_GATE,
2891 static struct clk_branch ce3_core_clk = {
2895 .enable_reg = 0x36cc,
2896 .enable_mask = BIT(4),
2897 .hw.init = &(struct clk_init_data){
2898 .name = "ce3_core_clk",
2899 .parent_names = (const char *[]){ "ce3_src" },
2901 .ops = &clk_branch_ops,
2902 .flags = CLK_SET_RATE_PARENT,
2907 static struct clk_branch ce3_h_clk = {
2911 .enable_reg = 0x36c4,
2912 .enable_mask = BIT(4),
2913 .hw.init = &(struct clk_init_data){
2914 .name = "ce3_h_clk",
2915 .parent_names = (const char *[]){ "ce3_src" },
2917 .ops = &clk_branch_ops,
2918 .flags = CLK_SET_RATE_PARENT,
2923 static const struct freq_tbl clk_tbl_sata_ref[] = {
2924 { 48000000, P_PLL8, 8, 0, 0 },
2925 { 100000000, P_PLL3, 12, 0, 0 },
2929 static struct clk_rcg sata_clk_src = {
2937 .parent_map = gcc_pxo_pll8_pll3_map,
2939 .freq_tbl = clk_tbl_sata_ref,
2941 .enable_reg = 0x2c08,
2942 .enable_mask = BIT(7),
2943 .hw.init = &(struct clk_init_data){
2944 .name = "sata_clk_src",
2945 .parent_names = gcc_pxo_pll8_pll3,
2947 .ops = &clk_rcg_ops,
2948 .flags = CLK_SET_RATE_GATE,
2953 static struct clk_branch sata_rxoob_clk = {
2957 .enable_reg = 0x2c0c,
2958 .enable_mask = BIT(4),
2959 .hw.init = &(struct clk_init_data){
2960 .name = "sata_rxoob_clk",
2961 .parent_names = (const char *[]){ "sata_clk_src" },
2963 .ops = &clk_branch_ops,
2964 .flags = CLK_SET_RATE_PARENT,
2969 static struct clk_branch sata_pmalive_clk = {
2973 .enable_reg = 0x2c10,
2974 .enable_mask = BIT(4),
2975 .hw.init = &(struct clk_init_data){
2976 .name = "sata_pmalive_clk",
2977 .parent_names = (const char *[]){ "sata_clk_src" },
2979 .ops = &clk_branch_ops,
2980 .flags = CLK_SET_RATE_PARENT,
2985 static struct clk_branch sata_phy_ref_clk = {
2989 .enable_reg = 0x2c14,
2990 .enable_mask = BIT(4),
2991 .hw.init = &(struct clk_init_data){
2992 .name = "sata_phy_ref_clk",
2993 .parent_names = (const char *[]){ "pxo" },
2995 .ops = &clk_branch_ops,
3000 static struct clk_branch sata_a_clk = {
3004 .enable_reg = 0x2c20,
3005 .enable_mask = BIT(4),
3006 .hw.init = &(struct clk_init_data){
3007 .name = "sata_a_clk",
3008 .ops = &clk_branch_ops,
3013 static struct clk_branch sata_h_clk = {
3017 .enable_reg = 0x2c00,
3018 .enable_mask = BIT(4),
3019 .hw.init = &(struct clk_init_data){
3020 .name = "sata_h_clk",
3021 .ops = &clk_branch_ops,
3026 static struct clk_branch sfab_sata_s_h_clk = {
3030 .enable_reg = 0x2480,
3031 .enable_mask = BIT(4),
3032 .hw.init = &(struct clk_init_data){
3033 .name = "sfab_sata_s_h_clk",
3034 .ops = &clk_branch_ops,
3039 static struct clk_branch sata_phy_cfg_clk = {
3043 .enable_reg = 0x2c40,
3044 .enable_mask = BIT(4),
3045 .hw.init = &(struct clk_init_data){
3046 .name = "sata_phy_cfg_clk",
3047 .ops = &clk_branch_ops,
3052 static struct clk_branch pcie_phy_ref_clk = {
3056 .enable_reg = 0x22d0,
3057 .enable_mask = BIT(4),
3058 .hw.init = &(struct clk_init_data){
3059 .name = "pcie_phy_ref_clk",
3060 .ops = &clk_branch_ops,
3065 static struct clk_branch pcie_h_clk = {
3069 .enable_reg = 0x22cc,
3070 .enable_mask = BIT(4),
3071 .hw.init = &(struct clk_init_data){
3072 .name = "pcie_h_clk",
3073 .ops = &clk_branch_ops,
3078 static struct clk_branch pcie_a_clk = {
3082 .enable_reg = 0x22c0,
3083 .enable_mask = BIT(4),
3084 .hw.init = &(struct clk_init_data){
3085 .name = "pcie_a_clk",
3086 .ops = &clk_branch_ops,
3091 static struct clk_branch pmic_arb0_h_clk = {
3093 .halt_check = BRANCH_HALT_VOTED,
3096 .enable_reg = 0x3080,
3097 .enable_mask = BIT(8),
3098 .hw.init = &(struct clk_init_data){
3099 .name = "pmic_arb0_h_clk",
3100 .ops = &clk_branch_ops,
3105 static struct clk_branch pmic_arb1_h_clk = {
3107 .halt_check = BRANCH_HALT_VOTED,
3110 .enable_reg = 0x3080,
3111 .enable_mask = BIT(9),
3112 .hw.init = &(struct clk_init_data){
3113 .name = "pmic_arb1_h_clk",
3114 .ops = &clk_branch_ops,
3119 static struct clk_branch pmic_ssbi2_clk = {
3121 .halt_check = BRANCH_HALT_VOTED,
3124 .enable_reg = 0x3080,
3125 .enable_mask = BIT(7),
3126 .hw.init = &(struct clk_init_data){
3127 .name = "pmic_ssbi2_clk",
3128 .ops = &clk_branch_ops,
3133 static struct clk_branch rpm_msg_ram_h_clk = {
3137 .halt_check = BRANCH_HALT_VOTED,
3140 .enable_reg = 0x3080,
3141 .enable_mask = BIT(6),
3142 .hw.init = &(struct clk_init_data){
3143 .name = "rpm_msg_ram_h_clk",
3144 .ops = &clk_branch_ops,
3149 static struct clk_regmap *gcc_msm8960_clks[] = {
3150 [PLL3] = &pll3.clkr,
3151 [PLL4_VOTE] = &pll4_vote,
3152 [PLL8] = &pll8.clkr,
3153 [PLL8_VOTE] = &pll8_vote,
3154 [PLL14] = &pll14.clkr,
3155 [PLL14_VOTE] = &pll14_vote,
3156 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3157 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3158 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3159 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3160 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3161 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3162 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3163 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3164 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3165 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3166 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3167 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3168 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3169 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3170 [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
3171 [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
3172 [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
3173 [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
3174 [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
3175 [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
3176 [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
3177 [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
3178 [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
3179 [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
3180 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3181 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3182 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3183 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3184 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3185 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3186 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3187 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3188 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3189 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3190 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3191 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3192 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3193 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3194 [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
3195 [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
3196 [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
3197 [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
3198 [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
3199 [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
3200 [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
3201 [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
3202 [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
3203 [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
3204 [GP0_SRC] = &gp0_src.clkr,
3205 [GP0_CLK] = &gp0_clk.clkr,
3206 [GP1_SRC] = &gp1_src.clkr,
3207 [GP1_CLK] = &gp1_clk.clkr,
3208 [GP2_SRC] = &gp2_src.clkr,
3209 [GP2_CLK] = &gp2_clk.clkr,
3210 [PMEM_A_CLK] = &pmem_clk.clkr,
3211 [PRNG_SRC] = &prng_src.clkr,
3212 [PRNG_CLK] = &prng_clk.clkr,
3213 [SDC1_SRC] = &sdc1_src.clkr,
3214 [SDC1_CLK] = &sdc1_clk.clkr,
3215 [SDC2_SRC] = &sdc2_src.clkr,
3216 [SDC2_CLK] = &sdc2_clk.clkr,
3217 [SDC3_SRC] = &sdc3_src.clkr,
3218 [SDC3_CLK] = &sdc3_clk.clkr,
3219 [SDC4_SRC] = &sdc4_src.clkr,
3220 [SDC4_CLK] = &sdc4_clk.clkr,
3221 [SDC5_SRC] = &sdc5_src.clkr,
3222 [SDC5_CLK] = &sdc5_clk.clkr,
3223 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3224 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3225 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3226 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3227 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3228 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3229 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3230 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3231 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3232 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3233 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3234 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3235 [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
3236 [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
3237 [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
3238 [CE1_CORE_CLK] = &ce1_core_clk.clkr,
3239 [CE1_H_CLK] = &ce1_h_clk.clkr,
3240 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3241 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3242 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3243 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3244 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3245 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3246 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3247 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3248 [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
3249 [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
3250 [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
3251 [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
3252 [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
3253 [TSIF_H_CLK] = &tsif_h_clk.clkr,
3254 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3255 [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
3256 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3257 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3258 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3259 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3260 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3261 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3262 [SDC5_H_CLK] = &sdc5_h_clk.clkr,
3263 [ADM0_CLK] = &adm0_clk.clkr,
3264 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3265 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3266 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3267 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3268 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3269 [PLL9] = &hfpll0.clkr,
3270 [PLL10] = &hfpll1.clkr,
3271 [PLL12] = &hfpll_l2.clkr,
3274 static const struct qcom_reset_map gcc_msm8960_resets[] = {
3275 [SFAB_MSS_Q6_SW_RESET] = { 0x2040, 7 },
3276 [SFAB_MSS_Q6_FW_RESET] = { 0x2044, 7 },
3277 [QDSS_STM_RESET] = { 0x2060, 6 },
3278 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3279 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3280 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3281 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3282 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3283 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3284 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3285 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3286 [ADM0_C2_RESET] = { 0x220c, 4},
3287 [ADM0_C1_RESET] = { 0x220c, 3},
3288 [ADM0_C0_RESET] = { 0x220c, 2},
3289 [ADM0_PBUS_RESET] = { 0x220c, 1 },
3290 [ADM0_RESET] = { 0x220c },
3291 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3292 [QDSS_POR_RESET] = { 0x2260, 4 },
3293 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3294 [QDSS_HRESET_RESET] = { 0x2260, 2 },
3295 [QDSS_AXI_RESET] = { 0x2260, 1 },
3296 [QDSS_DBG_RESET] = { 0x2260 },
3297 [PCIE_A_RESET] = { 0x22c0, 7 },
3298 [PCIE_AUX_RESET] = { 0x22c8, 7 },
3299 [PCIE_H_RESET] = { 0x22d0, 7 },
3300 [SFAB_PCIE_M_RESET] = { 0x22d4, 1 },
3301 [SFAB_PCIE_S_RESET] = { 0x22d4 },
3302 [SFAB_MSS_M_RESET] = { 0x2340, 7 },
3303 [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3304 [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3305 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3306 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3307 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3308 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3309 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3310 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3311 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3312 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3313 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3314 [DFAB_ARB0_RESET] = { 0x2560, 7 },
3315 [DFAB_ARB1_RESET] = { 0x2564, 7 },
3316 [PPSS_PROC_RESET] = { 0x2594, 1 },
3317 [PPSS_RESET] = { 0x2594},
3318 [DMA_BAM_RESET] = { 0x25c0, 7 },
3319 [SPS_TIC_H_RESET] = { 0x2600, 7 },
3320 [SLIMBUS_H_RESET] = { 0x2620, 7 },
3321 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3322 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3323 [TSIF_H_RESET] = { 0x2700, 7 },
3324 [CE1_H_RESET] = { 0x2720, 7 },
3325 [CE1_CORE_RESET] = { 0x2724, 7 },
3326 [CE1_SLEEP_RESET] = { 0x2728, 7 },
3327 [CE2_H_RESET] = { 0x2740, 7 },
3328 [CE2_CORE_RESET] = { 0x2744, 7 },
3329 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3330 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3331 [RPM_PROC_RESET] = { 0x27c0, 7 },
3332 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3333 [SDC1_RESET] = { 0x2830 },
3334 [SDC2_RESET] = { 0x2850 },
3335 [SDC3_RESET] = { 0x2870 },
3336 [SDC4_RESET] = { 0x2890 },
3337 [SDC5_RESET] = { 0x28b0 },
3338 [DFAB_A2_RESET] = { 0x28c0, 7 },
3339 [USB_HS1_RESET] = { 0x2910 },
3340 [USB_HSIC_RESET] = { 0x2934 },
3341 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3342 [USB_FS1_RESET] = { 0x2974 },
3343 [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
3344 [USB_FS2_RESET] = { 0x2994 },
3345 [GSBI1_RESET] = { 0x29dc },
3346 [GSBI2_RESET] = { 0x29fc },
3347 [GSBI3_RESET] = { 0x2a1c },
3348 [GSBI4_RESET] = { 0x2a3c },
3349 [GSBI5_RESET] = { 0x2a5c },
3350 [GSBI6_RESET] = { 0x2a7c },
3351 [GSBI7_RESET] = { 0x2a9c },
3352 [GSBI8_RESET] = { 0x2abc },
3353 [GSBI9_RESET] = { 0x2adc },
3354 [GSBI10_RESET] = { 0x2afc },
3355 [GSBI11_RESET] = { 0x2b1c },
3356 [GSBI12_RESET] = { 0x2b3c },
3357 [SPDM_RESET] = { 0x2b6c },
3358 [TLMM_H_RESET] = { 0x2ba0, 7 },
3359 [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
3360 [MSS_SLP_RESET] = { 0x2c60, 7 },
3361 [MSS_Q6SW_JTAG_RESET] = { 0x2c68, 7 },
3362 [MSS_Q6FW_JTAG_RESET] = { 0x2c6c, 7 },
3363 [MSS_RESET] = { 0x2c64 },
3364 [SATA_H_RESET] = { 0x2c80, 7 },
3365 [SATA_RXOOB_RESE] = { 0x2c8c, 7 },
3366 [SATA_PMALIVE_RESET] = { 0x2c90, 7 },
3367 [SATA_SFAB_M_RESET] = { 0x2c98, 7 },
3368 [TSSC_RESET] = { 0x2ca0, 7 },
3369 [PDM_RESET] = { 0x2cc0, 12 },
3370 [MPM_H_RESET] = { 0x2da0, 7 },
3371 [MPM_RESET] = { 0x2da4 },
3372 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3373 [PRNG_RESET] = { 0x2e80, 12 },
3374 [RIVA_RESET] = { 0x35e0 },
3377 static struct clk_regmap *gcc_apq8064_clks[] = {
3378 [PLL3] = &pll3.clkr,
3379 [PLL4_VOTE] = &pll4_vote,
3380 [PLL8] = &pll8.clkr,
3381 [PLL8_VOTE] = &pll8_vote,
3382 [PLL14] = &pll14.clkr,
3383 [PLL14_VOTE] = &pll14_vote,
3384 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3385 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3386 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3387 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3388 [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3389 [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3390 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3391 [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3392 [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3393 [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3394 [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3395 [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3396 [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3397 [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3398 [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3399 [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3400 [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3401 [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3402 [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3403 [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3404 [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3405 [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3406 [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3407 [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3408 [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3409 [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3410 [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3411 [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3412 [GP0_SRC] = &gp0_src.clkr,
3413 [GP0_CLK] = &gp0_clk.clkr,
3414 [GP1_SRC] = &gp1_src.clkr,
3415 [GP1_CLK] = &gp1_clk.clkr,
3416 [GP2_SRC] = &gp2_src.clkr,
3417 [GP2_CLK] = &gp2_clk.clkr,
3418 [PMEM_A_CLK] = &pmem_clk.clkr,
3419 [PRNG_SRC] = &prng_src.clkr,
3420 [PRNG_CLK] = &prng_clk.clkr,
3421 [SDC1_SRC] = &sdc1_src.clkr,
3422 [SDC1_CLK] = &sdc1_clk.clkr,
3423 [SDC2_SRC] = &sdc2_src.clkr,
3424 [SDC2_CLK] = &sdc2_clk.clkr,
3425 [SDC3_SRC] = &sdc3_src.clkr,
3426 [SDC3_CLK] = &sdc3_clk.clkr,
3427 [SDC4_SRC] = &sdc4_src.clkr,
3428 [SDC4_CLK] = &sdc4_clk.clkr,
3429 [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3430 [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3431 [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3432 [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3433 [USB_HS3_XCVR_SRC] = &usb_hs3_xcvr_src.clkr,
3434 [USB_HS3_XCVR_CLK] = &usb_hs3_xcvr_clk.clkr,
3435 [USB_HS4_XCVR_SRC] = &usb_hs4_xcvr_src.clkr,
3436 [USB_HS4_XCVR_CLK] = &usb_hs4_xcvr_clk.clkr,
3437 [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3438 [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3439 [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3440 [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3441 [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3442 [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3443 [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3444 [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3445 [SATA_H_CLK] = &sata_h_clk.clkr,
3446 [SATA_CLK_SRC] = &sata_clk_src.clkr,
3447 [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
3448 [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
3449 [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
3450 [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
3451 [SATA_A_CLK] = &sata_a_clk.clkr,
3452 [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
3453 [CE3_SRC] = &ce3_src.clkr,
3454 [CE3_CORE_CLK] = &ce3_core_clk.clkr,
3455 [CE3_H_CLK] = &ce3_h_clk.clkr,
3456 [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3457 [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3458 [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3459 [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3460 [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3461 [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3462 [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3463 [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3464 [TSIF_H_CLK] = &tsif_h_clk.clkr,
3465 [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3466 [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3467 [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3468 [USB_HS3_H_CLK] = &usb_hs3_h_clk.clkr,
3469 [USB_HS4_H_CLK] = &usb_hs4_h_clk.clkr,
3470 [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3471 [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3472 [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3473 [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3474 [ADM0_CLK] = &adm0_clk.clkr,
3475 [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3476 [PCIE_A_CLK] = &pcie_a_clk.clkr,
3477 [PCIE_PHY_REF_CLK] = &pcie_phy_ref_clk.clkr,
3478 [PCIE_H_CLK] = &pcie_h_clk.clkr,
3479 [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3480 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3481 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3482 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3483 [PLL9] = &hfpll0.clkr,
3484 [PLL10] = &hfpll1.clkr,
3485 [PLL12] = &hfpll_l2.clkr,
3486 [PLL16] = &hfpll2.clkr,
3487 [PLL17] = &hfpll3.clkr,
3490 static const struct qcom_reset_map gcc_apq8064_resets[] = {
3491 [QDSS_STM_RESET] = { 0x2060, 6 },
3492 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3493 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3494 [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3495 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3496 [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3497 [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3498 [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3499 [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3500 [ADM0_C2_RESET] = { 0x220c, 4},
3501 [ADM0_C1_RESET] = { 0x220c, 3},
3502 [ADM0_C0_RESET] = { 0x220c, 2},
3503 [ADM0_PBUS_RESET] = { 0x220c, 1 },
3504 [ADM0_RESET] = { 0x220c },
3505 [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3506 [QDSS_POR_RESET] = { 0x2260, 4 },
3507 [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3508 [QDSS_HRESET_RESET] = { 0x2260, 2 },
3509 [QDSS_AXI_RESET] = { 0x2260, 1 },
3510 [QDSS_DBG_RESET] = { 0x2260 },
3511 [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
3512 [SFAB_PCIE_S_RESET] = { 0x22d8 },
3513 [PCIE_EXT_PCI_RESET] = { 0x22dc, 6 },
3514 [PCIE_PHY_RESET] = { 0x22dc, 5 },
3515 [PCIE_PCI_RESET] = { 0x22dc, 4 },
3516 [PCIE_POR_RESET] = { 0x22dc, 3 },
3517 [PCIE_HCLK_RESET] = { 0x22dc, 2 },
3518 [PCIE_ACLK_RESET] = { 0x22dc },
3519 [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3520 [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3521 [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3522 [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3523 [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3524 [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3525 [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3526 [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3527 [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3528 [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3529 [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3530 [DFAB_ARB0_RESET] = { 0x2560, 7 },
3531 [DFAB_ARB1_RESET] = { 0x2564, 7 },
3532 [PPSS_PROC_RESET] = { 0x2594, 1 },
3533 [PPSS_RESET] = { 0x2594},
3534 [DMA_BAM_RESET] = { 0x25c0, 7 },
3535 [SPS_TIC_H_RESET] = { 0x2600, 7 },
3536 [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3537 [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3538 [TSIF_H_RESET] = { 0x2700, 7 },
3539 [CE1_H_RESET] = { 0x2720, 7 },
3540 [CE1_CORE_RESET] = { 0x2724, 7 },
3541 [CE1_SLEEP_RESET] = { 0x2728, 7 },
3542 [CE2_H_RESET] = { 0x2740, 7 },
3543 [CE2_CORE_RESET] = { 0x2744, 7 },
3544 [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3545 [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3546 [RPM_PROC_RESET] = { 0x27c0, 7 },
3547 [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3548 [SDC1_RESET] = { 0x2830 },
3549 [SDC2_RESET] = { 0x2850 },
3550 [SDC3_RESET] = { 0x2870 },
3551 [SDC4_RESET] = { 0x2890 },
3552 [USB_HS1_RESET] = { 0x2910 },
3553 [USB_HSIC_RESET] = { 0x2934 },
3554 [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3555 [USB_FS1_RESET] = { 0x2974 },
3556 [GSBI1_RESET] = { 0x29dc },
3557 [GSBI2_RESET] = { 0x29fc },
3558 [GSBI3_RESET] = { 0x2a1c },
3559 [GSBI4_RESET] = { 0x2a3c },
3560 [GSBI5_RESET] = { 0x2a5c },
3561 [GSBI6_RESET] = { 0x2a7c },
3562 [GSBI7_RESET] = { 0x2a9c },
3563 [SPDM_RESET] = { 0x2b6c },
3564 [TLMM_H_RESET] = { 0x2ba0, 7 },
3565 [SATA_SFAB_M_RESET] = { 0x2c18 },
3566 [SATA_RESET] = { 0x2c1c },
3567 [GSS_SLP_RESET] = { 0x2c60, 7 },
3568 [GSS_RESET] = { 0x2c64 },
3569 [TSSC_RESET] = { 0x2ca0, 7 },
3570 [PDM_RESET] = { 0x2cc0, 12 },
3571 [MPM_H_RESET] = { 0x2da0, 7 },
3572 [MPM_RESET] = { 0x2da4 },
3573 [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3574 [PRNG_RESET] = { 0x2e80, 12 },
3575 [RIVA_RESET] = { 0x35e0 },
3576 [CE3_H_RESET] = { 0x36c4, 7 },
3577 [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
3578 [SFAB_CE3_S_RESET] = { 0x36c8 },
3579 [CE3_RESET] = { 0x36cc, 7 },
3580 [CE3_SLEEP_RESET] = { 0x36d0, 7 },
3581 [USB_HS3_RESET] = { 0x3710 },
3582 [USB_HS4_RESET] = { 0x3730 },
3585 static const struct regmap_config gcc_msm8960_regmap_config = {
3589 .max_register = 0x3660,
3593 static const struct regmap_config gcc_apq8064_regmap_config = {
3597 .max_register = 0x3880,
3601 static const struct qcom_cc_desc gcc_msm8960_desc = {
3602 .config = &gcc_msm8960_regmap_config,
3603 .clks = gcc_msm8960_clks,
3604 .num_clks = ARRAY_SIZE(gcc_msm8960_clks),
3605 .resets = gcc_msm8960_resets,
3606 .num_resets = ARRAY_SIZE(gcc_msm8960_resets),
3609 static const struct qcom_cc_desc gcc_apq8064_desc = {
3610 .config = &gcc_apq8064_regmap_config,
3611 .clks = gcc_apq8064_clks,
3612 .num_clks = ARRAY_SIZE(gcc_apq8064_clks),
3613 .resets = gcc_apq8064_resets,
3614 .num_resets = ARRAY_SIZE(gcc_apq8064_resets),
3617 static const struct of_device_id gcc_msm8960_match_table[] = {
3618 { .compatible = "qcom,gcc-msm8960", .data = &gcc_msm8960_desc },
3619 { .compatible = "qcom,gcc-apq8064", .data = &gcc_apq8064_desc },
3622 MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table);
3624 static int gcc_msm8960_probe(struct platform_device *pdev)
3626 struct device *dev = &pdev->dev;
3627 const struct of_device_id *match;
3628 struct platform_device *tsens;
3631 match = of_match_device(gcc_msm8960_match_table, &pdev->dev);
3635 ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000);
3639 ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000);
3643 ret = qcom_cc_probe(pdev, match->data);
3647 if (match->data == &gcc_apq8064_desc) {
3648 hfpll1.d = &hfpll1_8064_data;
3649 hfpll_l2.d = &hfpll_l2_8064_data;
3652 tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1,
3655 return PTR_ERR(tsens);
3657 platform_set_drvdata(pdev, tsens);
3662 static int gcc_msm8960_remove(struct platform_device *pdev)
3664 struct platform_device *tsens = platform_get_drvdata(pdev);
3666 platform_device_unregister(tsens);
3671 static struct platform_driver gcc_msm8960_driver = {
3672 .probe = gcc_msm8960_probe,
3673 .remove = gcc_msm8960_remove,
3675 .name = "gcc-msm8960",
3676 .of_match_table = gcc_msm8960_match_table,
3680 static int __init gcc_msm8960_init(void)
3682 return platform_driver_register(&gcc_msm8960_driver);
3684 core_initcall(gcc_msm8960_init);
3686 static void __exit gcc_msm8960_exit(void)
3688 platform_driver_unregister(&gcc_msm8960_driver);
3690 module_exit(gcc_msm8960_exit);
3692 MODULE_DESCRIPTION("QCOM GCC MSM8960 Driver");
3693 MODULE_LICENSE("GPL v2");
3694 MODULE_ALIAS("platform:gcc-msm8960");